OpenTitan Roadmap

New Top Level “Earl Grey 2”

OpenTitan is addressing the new security challenges introduced by Artificial Intelligence and future quantum computers with a new top level design.

✪ Hardware memory safety through the addition of Capability Hardware Enhanced RISC Instructions (CHERI)

✪ Security-hardened and optimized Post-Quantum Cryptography (PQC) compatible with CNSA 2.0, through extensions to its crypto accelerators

✪ Advanced control plane I/O with the addition of an I3C controller and target to address peripheral bottlenecks

✪ Greater efficiency, reducing area and power consumption through process node updates, compressed instructions, IP block optimizations and power domain splitting

Support for CHERI and legacy modes

CHERI technology brings a revolutionary, preventive approach to silicon security by enabling fine-grained memory protection and highly scalable software compartmentalization.

OpenTitan will implement CHERIoT, a specific derivative tailored for highly constrained embedded devices. Existing users who already have certified software relying on traditional PMP can take advantage of the other features in Earl Grey 2 without software changes, while new users can benefit from CHERI’s advantages from the start.

Post Quantum Cryptography (PQC) with Side-Channel Analysis and Fault Injection Resistance

To support modern Post-Quantum Cryptography (PQC) standards with the side-channel analysis and fault injection resistance required for security certification (for example under Common Criteria), OpenTitan’s cryptographic subsystem gets native hardware support for algorithms including ML-KEM and ML-DSA. This includes significant extensions to the OpenTitan Big Number (OTBN) programmable accelerator, with new datapath components for mask conversion, new instructions, expanded data and instruction memories, and a direct interface to the KMAC hardware IP block.

On-chip non-volatile on-memory (NVM)

To support recent silicon nodes and improve performance of on-chip non-volatile memory (NVM), OpenTitan supports Resistive RAM (RRAM) in addition to embedded flash (eFlash) .

Low-power optimizations

To further reduce the power consumption in deep sleep, OpenTitan will minimize the amount of logic that needs to remain always on, and the module hierarchy of OpenTitan Earl Grey will be clearly split into an always-on and a power-gateable part.

Ibex Processor

The Ibex core processor is optimized to target higher operating frequencies while maintaining the existing security-hardened and formally-verified microarchitecture.

The Ibex core additionally gets support for the Zcb and Zcmp compressed instruction set extensions to achieve an estimated 10% reduction in code size.

I3C Controller and Target

Since I3C is gaining popularity in communication between chip(let)s, OpenTitan introduces an I3C Controller + Target hardware IP block alongside its existing I/O communication blocks. This I3C IP will support SDR and HDR-DDR modes, in-band interrupts, programmed I/O mode implementation of HCI, and hot-join of targets and secondary controllers, among other features.

AES accelerator

Updated to include native support for AES-GCM mode including side-channel hardening.

HMAC accelerator

Like the AES and KMAC accelerators, the HMAC accelerator is extended with a key sideload interface from Key Manager which allows shielding HMAC keys from software.

KMAC accelerator

Like the HMAC accelerator, the KMAC accelerator is extended with a context switching feature to enable software interleaving long-running hashing operations.

Entropy complex

The EDN, CSRNG and ENTROPY_SRC hardware IP blocks get various usability improvements. CSRNG and ENTROPY_SRC get optimized for substantially reduced silicon area footprint without reducing functionality and flexibility.

Key manager

OpenTitan’s key manager gets extended to support PQC key generation, and the DICE Protection Environment (DPE) extension gets harmonized for all top-level designs.