14void isr_testutils_ac_range_check_isr(
17 dif_ac_range_check_irq_t *irq_serviced) {
22 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
26 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
29 dif_ac_range_check_irq_t irq =
30 (dif_ac_range_check_irq_t)(plic_irq_id -
32 .plic_ac_range_check_start_irq_id);
38 CHECK_DIF_OK(dif_ac_range_check_irq_get_state(
41 "Only ac_range_check IRQ %d expected to fire. Actual IRQ state = %x",
47 CHECK_DIF_OK(dif_ac_range_check_irq_get_type(
50 CHECK_DIF_OK(dif_ac_range_check_irq_acknowledge(
55 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
59void isr_testutils_alert_handler_isr(
62 dif_alert_handler_irq_t *irq_serviced) {
67 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
71 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
74 dif_alert_handler_irq_t irq =
75 (dif_alert_handler_irq_t)(plic_irq_id -
77 .plic_alert_handler_start_irq_id);
83 CHECK_DIF_OK(dif_alert_handler_irq_get_state(
86 "Only alert_handler IRQ %d expected to fire. Actual IRQ state = %x",
92 CHECK_DIF_OK(dif_alert_handler_irq_get_type(alert_handler_ctx.
alert_handler,
95 CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(
100 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
104void isr_testutils_aon_timer_isr(
107 dif_aon_timer_irq_t *irq_serviced) {
112 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
116 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
119 dif_aon_timer_irq_t irq =
120 (dif_aon_timer_irq_t)(plic_irq_id -
128 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
130 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
136 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
138 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
142 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
146void isr_testutils_csrng_isr(
149 dif_csrng_irq_t *irq_serviced) {
154 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
158 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
161 dif_csrng_irq_t irq =
168 CHECK_DIF_OK(dif_csrng_irq_get_state(csrng_ctx.
csrng, &snapshot));
170 "Only csrng IRQ %d expected to fire. Actual IRQ state = %x", irq,
176 CHECK_DIF_OK(dif_csrng_irq_get_type(csrng_ctx.
csrng, irq, &type));
178 CHECK_DIF_OK(dif_csrng_irq_acknowledge(csrng_ctx.
csrng, irq));
182 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
186void isr_testutils_dma_isr(
189 dif_dma_irq_t *irq_serviced) {
194 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
198 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
208 CHECK_DIF_OK(dif_dma_irq_get_state(dma_ctx.
dma, &snapshot));
210 "Only dma IRQ %d expected to fire. Actual IRQ state = %x", irq,
216 CHECK_DIF_OK(dif_dma_irq_get_type(dma_ctx.
dma, irq, &type));
218 CHECK_DIF_OK(dif_dma_irq_acknowledge(dma_ctx.
dma, irq));
219 }
else if (mute_status_irq) {
224 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
228void isr_testutils_edn_isr(
231 dif_edn_irq_t *irq_serviced) {
236 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
240 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
250 CHECK_DIF_OK(dif_edn_irq_get_state(edn_ctx.
edn, &snapshot));
252 "Only edn IRQ %d expected to fire. Actual IRQ state = %x", irq,
258 CHECK_DIF_OK(dif_edn_irq_get_type(edn_ctx.
edn, irq, &type));
260 CHECK_DIF_OK(dif_edn_irq_acknowledge(edn_ctx.
edn, irq));
264 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
268void isr_testutils_gpio_isr(
271 dif_gpio_irq_t *irq_serviced) {
276 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
280 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
290 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
292 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
298 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
300 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
304 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
308void isr_testutils_hmac_isr(
311 dif_hmac_irq_t *irq_serviced) {
316 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
320 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
330 CHECK_DIF_OK(dif_hmac_irq_get_state(hmac_ctx.
hmac, &snapshot));
332 "Only hmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
338 CHECK_DIF_OK(dif_hmac_irq_get_type(hmac_ctx.
hmac, irq, &type));
340 CHECK_DIF_OK(dif_hmac_irq_acknowledge(hmac_ctx.
hmac, irq));
341 }
else if (mute_status_irq) {
347 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
351void isr_testutils_i2c_isr(
354 dif_i2c_irq_t *irq_serviced) {
359 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
363 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
373 CHECK_DIF_OK(dif_i2c_irq_get_state(i2c_ctx.
i2c, &snapshot));
375 "Only i2c IRQ %d expected to fire. Actual IRQ state = %x", irq,
381 CHECK_DIF_OK(dif_i2c_irq_get_type(i2c_ctx.
i2c, irq, &type));
383 CHECK_DIF_OK(dif_i2c_irq_acknowledge(i2c_ctx.
i2c, irq));
384 }
else if (mute_status_irq) {
389 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
393void isr_testutils_keymgr_dpe_isr(
396 dif_keymgr_dpe_irq_t *irq_serviced) {
401 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
405 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
408 dif_keymgr_dpe_irq_t irq =
409 (dif_keymgr_dpe_irq_t)(plic_irq_id -
417 dif_keymgr_dpe_irq_get_state(keymgr_dpe_ctx.
keymgr_dpe, &snapshot));
419 "Only keymgr_dpe IRQ %d expected to fire. Actual IRQ state = %x", irq,
426 dif_keymgr_dpe_irq_get_type(keymgr_dpe_ctx.
keymgr_dpe, irq, &type));
429 dif_keymgr_dpe_irq_acknowledge(keymgr_dpe_ctx.
keymgr_dpe, irq));
433 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
437void isr_testutils_kmac_isr(
440 dif_kmac_irq_t *irq_serviced) {
445 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
449 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
459 CHECK_DIF_OK(dif_kmac_irq_get_state(kmac_ctx.
kmac, &snapshot));
461 "Only kmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
467 CHECK_DIF_OK(dif_kmac_irq_get_type(kmac_ctx.
kmac, irq, &type));
469 CHECK_DIF_OK(dif_kmac_irq_acknowledge(kmac_ctx.
kmac, irq));
470 }
else if (mute_status_irq) {
476 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
480void isr_testutils_mbx_isr(
483 dif_mbx_irq_t *irq_serviced) {
488 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
492 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
502 CHECK_DIF_OK(dif_mbx_irq_get_state(mbx_ctx.
mbx, &snapshot));
504 "Only mbx IRQ %d expected to fire. Actual IRQ state = %x", irq,
510 CHECK_DIF_OK(dif_mbx_irq_get_type(mbx_ctx.
mbx, irq, &type));
512 CHECK_DIF_OK(dif_mbx_irq_acknowledge(mbx_ctx.
mbx, irq));
516 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
520void isr_testutils_otbn_isr(
523 dif_otbn_irq_t *irq_serviced) {
528 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
532 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
542 CHECK_DIF_OK(dif_otbn_irq_get_state(otbn_ctx.
otbn, &snapshot));
544 "Only otbn IRQ %d expected to fire. Actual IRQ state = %x", irq,
550 CHECK_DIF_OK(dif_otbn_irq_get_type(otbn_ctx.
otbn, irq, &type));
552 CHECK_DIF_OK(dif_otbn_irq_acknowledge(otbn_ctx.
otbn, irq));
556 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
560void isr_testutils_otp_ctrl_isr(
563 dif_otp_ctrl_irq_t *irq_serviced) {
568 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
572 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
575 dif_otp_ctrl_irq_t irq =
576 (dif_otp_ctrl_irq_t)(plic_irq_id -
583 CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(otp_ctrl_ctx.
otp_ctrl, &snapshot));
585 "Only otp_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
591 CHECK_DIF_OK(dif_otp_ctrl_irq_get_type(otp_ctrl_ctx.
otp_ctrl, irq, &type));
593 CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(otp_ctrl_ctx.
otp_ctrl, irq));
597 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
601void isr_testutils_pwrmgr_isr(
604 dif_pwrmgr_irq_t *irq_serviced) {
609 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
613 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
616 dif_pwrmgr_irq_t irq =
623 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
625 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
631 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
633 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
637 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
641void isr_testutils_racl_ctrl_isr(
644 dif_racl_ctrl_irq_t *irq_serviced) {
649 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
653 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
656 dif_racl_ctrl_irq_t irq =
657 (dif_racl_ctrl_irq_t)(plic_irq_id -
665 dif_racl_ctrl_irq_get_state(racl_ctrl_ctx.
racl_ctrl, &snapshot));
667 "Only racl_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
673 CHECK_DIF_OK(dif_racl_ctrl_irq_get_type(racl_ctrl_ctx.
racl_ctrl, irq, &type));
675 CHECK_DIF_OK(dif_racl_ctrl_irq_acknowledge(racl_ctrl_ctx.
racl_ctrl, irq));
676 }
else if (mute_status_irq) {
677 CHECK_DIF_OK(dif_racl_ctrl_irq_set_enabled(racl_ctrl_ctx.
racl_ctrl, irq,
682 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
686void isr_testutils_rv_timer_isr(
689 dif_rv_timer_irq_t *irq_serviced) {
694 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
698 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
701 dif_rv_timer_irq_t irq =
702 (dif_rv_timer_irq_t)(plic_irq_id -
709 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
712 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
718 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
720 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
724 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
728void isr_testutils_soc_proxy_isr(
731 dif_soc_proxy_irq_t *irq_serviced) {
736 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
740 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
743 dif_soc_proxy_irq_t irq =
744 (dif_soc_proxy_irq_t)(plic_irq_id -
752 dif_soc_proxy_irq_get_state(soc_proxy_ctx.
soc_proxy, &snapshot));
754 "Only soc_proxy IRQ %d expected to fire. Actual IRQ state = %x", irq,
760 CHECK_DIF_OK(dif_soc_proxy_irq_get_type(soc_proxy_ctx.
soc_proxy, irq, &type));
762 CHECK_DIF_OK(dif_soc_proxy_irq_acknowledge(soc_proxy_ctx.
soc_proxy, irq));
766 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
770void isr_testutils_spi_device_isr(
773 dif_spi_device_irq_t *irq_serviced) {
778 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
782 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
785 dif_spi_device_irq_t irq =
786 (dif_spi_device_irq_t)(plic_irq_id -
794 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
796 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
803 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
806 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
807 }
else if (mute_status_irq) {
808 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
813 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
817void isr_testutils_spi_host_isr(
820 dif_spi_host_irq_t *irq_serviced) {
825 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
829 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
832 dif_spi_host_irq_t irq =
833 (dif_spi_host_irq_t)(plic_irq_id -
840 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
842 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
848 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
850 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
851 }
else if (mute_status_irq) {
852 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
857 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
861void isr_testutils_uart_isr(
864 dif_uart_irq_t *irq_serviced) {
869 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
873 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
883 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
885 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
891 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
893 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
894 }
else if (mute_status_irq) {
900 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,