14void isr_testutils_ac_range_check_isr(
17 dif_ac_range_check_irq_t *irq_serviced) {
22 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
26 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
29 dif_ac_range_check_irq_t irq =
30 (dif_ac_range_check_irq_t)(plic_irq_id -
32 .plic_ac_range_check_start_irq_id);
38 CHECK_DIF_OK(dif_ac_range_check_irq_get_state(
41 "Only ac_range_check IRQ %d expected to fire. Actual IRQ state = %x",
47 CHECK_DIF_OK(dif_ac_range_check_irq_get_type(
50 CHECK_DIF_OK(dif_ac_range_check_irq_acknowledge(
52 }
else if (mute_status_irq) {
53 CHECK_DIF_OK(dif_ac_range_check_irq_set_enabled(
58 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
62void isr_testutils_alert_handler_isr(
65 dif_alert_handler_irq_t *irq_serviced) {
70 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
74 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
77 dif_alert_handler_irq_t irq =
78 (dif_alert_handler_irq_t)(plic_irq_id -
80 .plic_alert_handler_start_irq_id);
86 CHECK_DIF_OK(dif_alert_handler_irq_get_state(
89 "Only alert_handler IRQ %d expected to fire. Actual IRQ state = %x",
95 CHECK_DIF_OK(dif_alert_handler_irq_get_type(alert_handler_ctx.
alert_handler,
98 CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(
103 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
107void isr_testutils_aon_timer_isr(
110 dif_aon_timer_irq_t *irq_serviced) {
115 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
119 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
122 dif_aon_timer_irq_t irq =
123 (dif_aon_timer_irq_t)(plic_irq_id -
131 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
133 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
139 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
141 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
145 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
149void isr_testutils_csrng_isr(
152 dif_csrng_irq_t *irq_serviced) {
157 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
161 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
164 dif_csrng_irq_t irq =
171 CHECK_DIF_OK(dif_csrng_irq_get_state(csrng_ctx.
csrng, &snapshot));
173 "Only csrng IRQ %d expected to fire. Actual IRQ state = %x", irq,
179 CHECK_DIF_OK(dif_csrng_irq_get_type(csrng_ctx.
csrng, irq, &type));
181 CHECK_DIF_OK(dif_csrng_irq_acknowledge(csrng_ctx.
csrng, irq));
185 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
189void isr_testutils_dma_isr(
192 dif_dma_irq_t *irq_serviced) {
197 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
201 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
211 CHECK_DIF_OK(dif_dma_irq_get_state(dma_ctx.
dma, &snapshot));
213 "Only dma IRQ %d expected to fire. Actual IRQ state = %x", irq,
219 CHECK_DIF_OK(dif_dma_irq_get_type(dma_ctx.
dma, irq, &type));
221 CHECK_DIF_OK(dif_dma_irq_acknowledge(dma_ctx.
dma, irq));
222 }
else if (mute_status_irq) {
227 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
231void isr_testutils_edn_isr(
234 dif_edn_irq_t *irq_serviced) {
239 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
243 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
253 CHECK_DIF_OK(dif_edn_irq_get_state(edn_ctx.
edn, &snapshot));
255 "Only edn IRQ %d expected to fire. Actual IRQ state = %x", irq,
261 CHECK_DIF_OK(dif_edn_irq_get_type(edn_ctx.
edn, irq, &type));
263 CHECK_DIF_OK(dif_edn_irq_acknowledge(edn_ctx.
edn, irq));
267 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
271void isr_testutils_entropy_src_isr(
274 dif_entropy_src_irq_t *irq_serviced) {
279 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
283 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
286 dif_entropy_src_irq_t irq =
287 (dif_entropy_src_irq_t)(plic_irq_id -
295 dif_entropy_src_irq_get_state(entropy_src_ctx.
entropy_src, &snapshot));
297 "Only entropy_src IRQ %d expected to fire. Actual IRQ state = %x",
304 dif_entropy_src_irq_get_type(entropy_src_ctx.
entropy_src, irq, &type));
307 dif_entropy_src_irq_acknowledge(entropy_src_ctx.
entropy_src, irq));
311 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
315void isr_testutils_gpio_isr(
318 dif_gpio_irq_t *irq_serviced) {
323 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
327 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
337 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
339 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
345 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
347 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
351 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
355void isr_testutils_hmac_isr(
358 dif_hmac_irq_t *irq_serviced) {
363 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
367 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
377 CHECK_DIF_OK(dif_hmac_irq_get_state(hmac_ctx.
hmac, &snapshot));
379 "Only hmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
385 CHECK_DIF_OK(dif_hmac_irq_get_type(hmac_ctx.
hmac, irq, &type));
387 CHECK_DIF_OK(dif_hmac_irq_acknowledge(hmac_ctx.
hmac, irq));
388 }
else if (mute_status_irq) {
394 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
398void isr_testutils_i2c_isr(
401 dif_i2c_irq_t *irq_serviced) {
406 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
410 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
420 CHECK_DIF_OK(dif_i2c_irq_get_state(i2c_ctx.
i2c, &snapshot));
422 "Only i2c IRQ %d expected to fire. Actual IRQ state = %x", irq,
428 CHECK_DIF_OK(dif_i2c_irq_get_type(i2c_ctx.
i2c, irq, &type));
430 CHECK_DIF_OK(dif_i2c_irq_acknowledge(i2c_ctx.
i2c, irq));
431 }
else if (mute_status_irq) {
436 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
440void isr_testutils_keymgr_dpe_isr(
443 dif_keymgr_dpe_irq_t *irq_serviced) {
448 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
452 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
455 dif_keymgr_dpe_irq_t irq =
456 (dif_keymgr_dpe_irq_t)(plic_irq_id -
464 dif_keymgr_dpe_irq_get_state(keymgr_dpe_ctx.
keymgr_dpe, &snapshot));
466 "Only keymgr_dpe IRQ %d expected to fire. Actual IRQ state = %x", irq,
473 dif_keymgr_dpe_irq_get_type(keymgr_dpe_ctx.
keymgr_dpe, irq, &type));
476 dif_keymgr_dpe_irq_acknowledge(keymgr_dpe_ctx.
keymgr_dpe, irq));
480 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
484void isr_testutils_kmac_isr(
487 dif_kmac_irq_t *irq_serviced) {
492 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
496 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
506 CHECK_DIF_OK(dif_kmac_irq_get_state(kmac_ctx.
kmac, &snapshot));
508 "Only kmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
514 CHECK_DIF_OK(dif_kmac_irq_get_type(kmac_ctx.
kmac, irq, &type));
516 CHECK_DIF_OK(dif_kmac_irq_acknowledge(kmac_ctx.
kmac, irq));
517 }
else if (mute_status_irq) {
523 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
527void isr_testutils_mbx_isr(
530 dif_mbx_irq_t *irq_serviced) {
535 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
539 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
549 CHECK_DIF_OK(dif_mbx_irq_get_state(mbx_ctx.
mbx, &snapshot));
551 "Only mbx IRQ %d expected to fire. Actual IRQ state = %x", irq,
557 CHECK_DIF_OK(dif_mbx_irq_get_type(mbx_ctx.
mbx, irq, &type));
559 CHECK_DIF_OK(dif_mbx_irq_acknowledge(mbx_ctx.
mbx, irq));
563 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
567void isr_testutils_otbn_isr(
570 dif_otbn_irq_t *irq_serviced) {
575 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
579 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
589 CHECK_DIF_OK(dif_otbn_irq_get_state(otbn_ctx.
otbn, &snapshot));
591 "Only otbn IRQ %d expected to fire. Actual IRQ state = %x", irq,
597 CHECK_DIF_OK(dif_otbn_irq_get_type(otbn_ctx.
otbn, irq, &type));
599 CHECK_DIF_OK(dif_otbn_irq_acknowledge(otbn_ctx.
otbn, irq));
603 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
607void isr_testutils_otp_ctrl_isr(
610 dif_otp_ctrl_irq_t *irq_serviced) {
615 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
619 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
622 dif_otp_ctrl_irq_t irq =
623 (dif_otp_ctrl_irq_t)(plic_irq_id -
630 CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(otp_ctrl_ctx.
otp_ctrl, &snapshot));
632 "Only otp_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
638 CHECK_DIF_OK(dif_otp_ctrl_irq_get_type(otp_ctrl_ctx.
otp_ctrl, irq, &type));
640 CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(otp_ctrl_ctx.
otp_ctrl, irq));
644 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
648void isr_testutils_pwrmgr_isr(
651 dif_pwrmgr_irq_t *irq_serviced) {
656 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
660 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
663 dif_pwrmgr_irq_t irq =
670 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
672 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
678 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
680 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
684 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
688void isr_testutils_racl_ctrl_isr(
691 dif_racl_ctrl_irq_t *irq_serviced) {
696 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
700 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
703 dif_racl_ctrl_irq_t irq =
704 (dif_racl_ctrl_irq_t)(plic_irq_id -
712 dif_racl_ctrl_irq_get_state(racl_ctrl_ctx.
racl_ctrl, &snapshot));
714 "Only racl_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
720 CHECK_DIF_OK(dif_racl_ctrl_irq_get_type(racl_ctrl_ctx.
racl_ctrl, irq, &type));
722 CHECK_DIF_OK(dif_racl_ctrl_irq_acknowledge(racl_ctrl_ctx.
racl_ctrl, irq));
723 }
else if (mute_status_irq) {
724 CHECK_DIF_OK(dif_racl_ctrl_irq_set_enabled(racl_ctrl_ctx.
racl_ctrl, irq,
729 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
733void isr_testutils_rv_timer_isr(
736 dif_rv_timer_irq_t *irq_serviced) {
741 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
745 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
748 dif_rv_timer_irq_t irq =
749 (dif_rv_timer_irq_t)(plic_irq_id -
756 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
759 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
765 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
767 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
771 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
775void isr_testutils_soc_proxy_isr(
778 dif_soc_proxy_irq_t *irq_serviced) {
783 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
787 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
790 dif_soc_proxy_irq_t irq =
791 (dif_soc_proxy_irq_t)(plic_irq_id -
799 dif_soc_proxy_irq_get_state(soc_proxy_ctx.
soc_proxy, &snapshot));
801 "Only soc_proxy IRQ %d expected to fire. Actual IRQ state = %x", irq,
807 CHECK_DIF_OK(dif_soc_proxy_irq_get_type(soc_proxy_ctx.
soc_proxy, irq, &type));
809 CHECK_DIF_OK(dif_soc_proxy_irq_acknowledge(soc_proxy_ctx.
soc_proxy, irq));
813 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
817void isr_testutils_spi_device_isr(
820 dif_spi_device_irq_t *irq_serviced) {
825 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
829 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
832 dif_spi_device_irq_t irq =
833 (dif_spi_device_irq_t)(plic_irq_id -
841 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
843 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
850 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
853 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
854 }
else if (mute_status_irq) {
855 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
860 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
864void isr_testutils_spi_host_isr(
867 dif_spi_host_irq_t *irq_serviced) {
872 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
876 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
879 dif_spi_host_irq_t irq =
880 (dif_spi_host_irq_t)(plic_irq_id -
887 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
889 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
895 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
897 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
898 }
else if (mute_status_irq) {
899 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
904 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
908void isr_testutils_uart_isr(
911 dif_uart_irq_t *irq_serviced) {
916 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
920 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
930 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
932 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
938 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
940 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
941 }
else if (mute_status_irq) {
947 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,