14void isr_testutils_ac_range_check_isr(
17 dif_ac_range_check_irq_t *irq_serviced) {
22 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
26 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
29 dif_ac_range_check_irq_t irq =
30 (dif_ac_range_check_irq_t)(plic_irq_id -
32 .plic_ac_range_check_start_irq_id);
38 CHECK_DIF_OK(dif_ac_range_check_irq_get_state(
41 "Only ac_range_check IRQ %d expected to fire. Actual IRQ state = %x",
47 CHECK_DIF_OK(dif_ac_range_check_irq_get_type(
50 CHECK_DIF_OK(dif_ac_range_check_irq_acknowledge(
52 }
else if (mute_status_irq) {
53 CHECK_DIF_OK(dif_ac_range_check_irq_set_enabled(
58 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
62void isr_testutils_alert_handler_isr(
65 dif_alert_handler_irq_t *irq_serviced) {
70 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
74 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
77 dif_alert_handler_irq_t irq =
78 (dif_alert_handler_irq_t)(plic_irq_id -
80 .plic_alert_handler_start_irq_id);
86 CHECK_DIF_OK(dif_alert_handler_irq_get_state(
89 "Only alert_handler IRQ %d expected to fire. Actual IRQ state = %x",
95 CHECK_DIF_OK(dif_alert_handler_irq_get_type(alert_handler_ctx.
alert_handler,
98 CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(
103 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
107void isr_testutils_aon_timer_isr(
110 dif_aon_timer_irq_t *irq_serviced) {
115 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
119 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
122 dif_aon_timer_irq_t irq =
123 (dif_aon_timer_irq_t)(plic_irq_id -
131 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
133 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
139 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
141 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
145 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
149void isr_testutils_csrng_isr(
152 dif_csrng_irq_t *irq_serviced) {
157 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
161 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
164 dif_csrng_irq_t irq =
171 CHECK_DIF_OK(dif_csrng_irq_get_state(csrng_ctx.
csrng, &snapshot));
173 "Only csrng IRQ %d expected to fire. Actual IRQ state = %x", irq,
179 CHECK_DIF_OK(dif_csrng_irq_get_type(csrng_ctx.
csrng, irq, &type));
181 CHECK_DIF_OK(dif_csrng_irq_acknowledge(csrng_ctx.
csrng, irq));
185 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
189void isr_testutils_dma_isr(
192 dif_dma_irq_t *irq_serviced) {
197 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
201 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
211 CHECK_DIF_OK(dif_dma_irq_get_state(dma_ctx.
dma, &snapshot));
213 "Only dma IRQ %d expected to fire. Actual IRQ state = %x", irq,
219 CHECK_DIF_OK(dif_dma_irq_get_type(dma_ctx.
dma, irq, &type));
221 CHECK_DIF_OK(dif_dma_irq_acknowledge(dma_ctx.
dma, irq));
222 }
else if (mute_status_irq) {
227 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
231void isr_testutils_edn_isr(
234 dif_edn_irq_t *irq_serviced) {
239 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
243 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
253 CHECK_DIF_OK(dif_edn_irq_get_state(edn_ctx.
edn, &snapshot));
255 "Only edn IRQ %d expected to fire. Actual IRQ state = %x", irq,
261 CHECK_DIF_OK(dif_edn_irq_get_type(edn_ctx.
edn, irq, &type));
263 CHECK_DIF_OK(dif_edn_irq_acknowledge(edn_ctx.
edn, irq));
267 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
271void isr_testutils_gpio_isr(
274 dif_gpio_irq_t *irq_serviced) {
279 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
283 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
293 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
295 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
301 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
303 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
307 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
311void isr_testutils_hmac_isr(
314 dif_hmac_irq_t *irq_serviced) {
319 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
323 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
333 CHECK_DIF_OK(dif_hmac_irq_get_state(hmac_ctx.
hmac, &snapshot));
335 "Only hmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
341 CHECK_DIF_OK(dif_hmac_irq_get_type(hmac_ctx.
hmac, irq, &type));
343 CHECK_DIF_OK(dif_hmac_irq_acknowledge(hmac_ctx.
hmac, irq));
344 }
else if (mute_status_irq) {
350 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
354void isr_testutils_i2c_isr(
357 dif_i2c_irq_t *irq_serviced) {
362 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
366 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
376 CHECK_DIF_OK(dif_i2c_irq_get_state(i2c_ctx.
i2c, &snapshot));
378 "Only i2c IRQ %d expected to fire. Actual IRQ state = %x", irq,
384 CHECK_DIF_OK(dif_i2c_irq_get_type(i2c_ctx.
i2c, irq, &type));
386 CHECK_DIF_OK(dif_i2c_irq_acknowledge(i2c_ctx.
i2c, irq));
387 }
else if (mute_status_irq) {
392 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
396void isr_testutils_keymgr_dpe_isr(
399 dif_keymgr_dpe_irq_t *irq_serviced) {
404 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
408 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
411 dif_keymgr_dpe_irq_t irq =
412 (dif_keymgr_dpe_irq_t)(plic_irq_id -
420 dif_keymgr_dpe_irq_get_state(keymgr_dpe_ctx.
keymgr_dpe, &snapshot));
422 "Only keymgr_dpe IRQ %d expected to fire. Actual IRQ state = %x", irq,
429 dif_keymgr_dpe_irq_get_type(keymgr_dpe_ctx.
keymgr_dpe, irq, &type));
432 dif_keymgr_dpe_irq_acknowledge(keymgr_dpe_ctx.
keymgr_dpe, irq));
436 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
440void isr_testutils_kmac_isr(
443 dif_kmac_irq_t *irq_serviced) {
448 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
452 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
462 CHECK_DIF_OK(dif_kmac_irq_get_state(kmac_ctx.
kmac, &snapshot));
464 "Only kmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
470 CHECK_DIF_OK(dif_kmac_irq_get_type(kmac_ctx.
kmac, irq, &type));
472 CHECK_DIF_OK(dif_kmac_irq_acknowledge(kmac_ctx.
kmac, irq));
473 }
else if (mute_status_irq) {
479 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
483void isr_testutils_mbx_isr(
486 dif_mbx_irq_t *irq_serviced) {
491 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
495 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
505 CHECK_DIF_OK(dif_mbx_irq_get_state(mbx_ctx.
mbx, &snapshot));
507 "Only mbx IRQ %d expected to fire. Actual IRQ state = %x", irq,
513 CHECK_DIF_OK(dif_mbx_irq_get_type(mbx_ctx.
mbx, irq, &type));
515 CHECK_DIF_OK(dif_mbx_irq_acknowledge(mbx_ctx.
mbx, irq));
519 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
523void isr_testutils_otbn_isr(
526 dif_otbn_irq_t *irq_serviced) {
531 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
535 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
545 CHECK_DIF_OK(dif_otbn_irq_get_state(otbn_ctx.
otbn, &snapshot));
547 "Only otbn IRQ %d expected to fire. Actual IRQ state = %x", irq,
553 CHECK_DIF_OK(dif_otbn_irq_get_type(otbn_ctx.
otbn, irq, &type));
555 CHECK_DIF_OK(dif_otbn_irq_acknowledge(otbn_ctx.
otbn, irq));
559 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
563void isr_testutils_otp_ctrl_isr(
566 dif_otp_ctrl_irq_t *irq_serviced) {
571 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
575 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
578 dif_otp_ctrl_irq_t irq =
579 (dif_otp_ctrl_irq_t)(plic_irq_id -
586 CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(otp_ctrl_ctx.
otp_ctrl, &snapshot));
588 "Only otp_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
594 CHECK_DIF_OK(dif_otp_ctrl_irq_get_type(otp_ctrl_ctx.
otp_ctrl, irq, &type));
596 CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(otp_ctrl_ctx.
otp_ctrl, irq));
600 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
604void isr_testutils_pwrmgr_isr(
607 dif_pwrmgr_irq_t *irq_serviced) {
612 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
616 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
619 dif_pwrmgr_irq_t irq =
626 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
628 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
634 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
636 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
640 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
644void isr_testutils_racl_ctrl_isr(
647 dif_racl_ctrl_irq_t *irq_serviced) {
652 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
656 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
659 dif_racl_ctrl_irq_t irq =
660 (dif_racl_ctrl_irq_t)(plic_irq_id -
668 dif_racl_ctrl_irq_get_state(racl_ctrl_ctx.
racl_ctrl, &snapshot));
670 "Only racl_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
676 CHECK_DIF_OK(dif_racl_ctrl_irq_get_type(racl_ctrl_ctx.
racl_ctrl, irq, &type));
678 CHECK_DIF_OK(dif_racl_ctrl_irq_acknowledge(racl_ctrl_ctx.
racl_ctrl, irq));
679 }
else if (mute_status_irq) {
680 CHECK_DIF_OK(dif_racl_ctrl_irq_set_enabled(racl_ctrl_ctx.
racl_ctrl, irq,
685 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
689void isr_testutils_rv_timer_isr(
692 dif_rv_timer_irq_t *irq_serviced) {
697 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
701 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
704 dif_rv_timer_irq_t irq =
705 (dif_rv_timer_irq_t)(plic_irq_id -
712 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
715 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
721 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
723 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
727 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
731void isr_testutils_soc_proxy_isr(
734 dif_soc_proxy_irq_t *irq_serviced) {
739 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
743 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
746 dif_soc_proxy_irq_t irq =
747 (dif_soc_proxy_irq_t)(plic_irq_id -
755 dif_soc_proxy_irq_get_state(soc_proxy_ctx.
soc_proxy, &snapshot));
757 "Only soc_proxy IRQ %d expected to fire. Actual IRQ state = %x", irq,
763 CHECK_DIF_OK(dif_soc_proxy_irq_get_type(soc_proxy_ctx.
soc_proxy, irq, &type));
765 CHECK_DIF_OK(dif_soc_proxy_irq_acknowledge(soc_proxy_ctx.
soc_proxy, irq));
769 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
773void isr_testutils_spi_device_isr(
776 dif_spi_device_irq_t *irq_serviced) {
781 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
785 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
788 dif_spi_device_irq_t irq =
789 (dif_spi_device_irq_t)(plic_irq_id -
797 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
799 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
806 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
809 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
810 }
else if (mute_status_irq) {
811 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
816 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
820void isr_testutils_spi_host_isr(
823 dif_spi_host_irq_t *irq_serviced) {
828 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
832 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
835 dif_spi_host_irq_t irq =
836 (dif_spi_host_irq_t)(plic_irq_id -
843 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
845 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
851 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
853 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
854 }
else if (mute_status_irq) {
855 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
860 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
864void isr_testutils_uart_isr(
867 dif_uart_irq_t *irq_serviced) {
872 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
876 top_darjeeling_plic_interrupt_for_peripheral[plic_irq_id];
886 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
888 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
894 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
896 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
897 }
else if (mute_status_irq) {
903 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,