Top-specific Definitions. More...

Macros
#define	TOP_DARJEELING_UART0_BASE_ADDR 0x30010000u
	Peripheral base address for uart0 in top darjeeling.

#define	TOP_DARJEELING_UART0_SIZE_BYTES 0x40u
	Peripheral size for uart0 in top darjeeling.

#define	TOP_DARJEELING_GPIO_BASE_ADDR 0x30000000u
	Peripheral base address for gpio in top darjeeling.

#define	TOP_DARJEELING_GPIO_SIZE_BYTES 0x100u
	Peripheral size for gpio in top darjeeling.

#define	TOP_DARJEELING_SPI_DEVICE_BASE_ADDR 0x30310000u
	Peripheral base address for spi_device in top darjeeling.

#define	TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES 0x2000u
	Peripheral size for spi_device in top darjeeling.

#define	TOP_DARJEELING_I2C0_BASE_ADDR 0x30080000u
	Peripheral base address for i2c0 in top darjeeling.

#define	TOP_DARJEELING_I2C0_SIZE_BYTES 0x80u
	Peripheral size for i2c0 in top darjeeling.

#define	TOP_DARJEELING_RV_TIMER_BASE_ADDR 0x30100000u
	Peripheral base address for rv_timer in top darjeeling.

#define	TOP_DARJEELING_RV_TIMER_SIZE_BYTES 0x200u
	Peripheral size for rv_timer in top darjeeling.

#define	TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR 0x30130000u
	Peripheral base address for core device on otp_ctrl in top darjeeling.

#define	TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES 0x8000u
	Peripheral size for core device on otp_ctrl in top darjeeling.

#define	TOP_DARJEELING_OTP_MACRO_BASE_ADDR 0x30140000u
	Peripheral base address for otp_macro in top darjeeling.

#define	TOP_DARJEELING_OTP_MACRO_SIZE_BYTES 0x20u
	Peripheral size for otp_macro in top darjeeling.

#define	TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR 0x30150000u
	Peripheral base address for regs device on lc_ctrl in top darjeeling.

#define	TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES 0x100u
	Peripheral size for regs device on lc_ctrl in top darjeeling.

#define	TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR 0x30160000u
	Peripheral base address for alert_handler in top darjeeling.

#define	TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES 0x800u
	Peripheral size for alert_handler in top darjeeling.

#define	TOP_DARJEELING_SPI_HOST0_BASE_ADDR 0x30300000u
	Peripheral base address for spi_host0 in top darjeeling.

#define	TOP_DARJEELING_SPI_HOST0_SIZE_BYTES 0x40u
	Peripheral size for spi_host0 in top darjeeling.

#define	TOP_DARJEELING_PWRMGR_AON_BASE_ADDR 0x30400000u
	Peripheral base address for pwrmgr_aon in top darjeeling.

#define	TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for pwrmgr_aon in top darjeeling.

#define	TOP_DARJEELING_RSTMGR_AON_BASE_ADDR 0x30410000u
	Peripheral base address for rstmgr_aon in top darjeeling.

#define	TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for rstmgr_aon in top darjeeling.

#define	TOP_DARJEELING_CLKMGR_AON_BASE_ADDR 0x30420000u
	Peripheral base address for clkmgr_aon in top darjeeling.

#define	TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES 0x40u
	Peripheral size for clkmgr_aon in top darjeeling.

#define	TOP_DARJEELING_PINMUX_AON_BASE_ADDR 0x30460000u
	Peripheral base address for pinmux_aon in top darjeeling.

#define	TOP_DARJEELING_PINMUX_AON_SIZE_BYTES 0x800u
	Peripheral size for pinmux_aon in top darjeeling.

#define	TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR 0x30470000u
	Peripheral base address for aon_timer_aon in top darjeeling.

#define	TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES 0x40u
	Peripheral size for aon_timer_aon in top darjeeling.

#define	TOP_DARJEELING_AST_BASE_ADDR 0x30480000u
	Peripheral base address for ast in top darjeeling.

#define	TOP_DARJEELING_AST_SIZE_BYTES 0x400u
	Peripheral size for ast in top darjeeling.

#define	TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR 0x22030000u
	Peripheral base address for core device on soc_proxy in top darjeeling.

#define	TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES 0x10u
	Peripheral size for core device on soc_proxy in top darjeeling.

#define	TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR 0x40000000u
	Peripheral base address for ctn device on soc_proxy in top darjeeling.

#define	TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x40000000u
	Peripheral size for ctn device on soc_proxy in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x30500000u
	Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u
	Peripheral size for regs device on sram_ctrl_ret_aon in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x30600000u
	Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
	Peripheral size for ram device on sram_ctrl_ret_aon in top darjeeling.

#define	TOP_DARJEELING_RV_DM_REGS_BASE_ADDR 0x21200000u
	Peripheral base address for regs device on rv_dm in top darjeeling.

#define	TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES 0x10u
	Peripheral size for regs device on rv_dm in top darjeeling.

#define	TOP_DARJEELING_RV_DM_MEM_BASE_ADDR 0x40000u
	Peripheral base address for mem device on rv_dm in top darjeeling.

#define	TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES 0x1000u
	Peripheral size for mem device on rv_dm in top darjeeling.

#define	TOP_DARJEELING_RV_PLIC_BASE_ADDR 0x28000000u
	Peripheral base address for rv_plic in top darjeeling.

#define	TOP_DARJEELING_RV_PLIC_SIZE_BYTES 0x8000000u
	Peripheral size for rv_plic in top darjeeling.

#define	TOP_DARJEELING_AES_BASE_ADDR 0x21100000u
	Peripheral base address for aes in top darjeeling.

#define	TOP_DARJEELING_AES_SIZE_BYTES 0x100u
	Peripheral size for aes in top darjeeling.

#define	TOP_DARJEELING_HMAC_BASE_ADDR 0x21110000u
	Peripheral base address for hmac in top darjeeling.

#define	TOP_DARJEELING_HMAC_SIZE_BYTES 0x2000u
	Peripheral size for hmac in top darjeeling.

#define	TOP_DARJEELING_KMAC_BASE_ADDR 0x21120000u
	Peripheral base address for kmac in top darjeeling.

#define	TOP_DARJEELING_KMAC_SIZE_BYTES 0x1000u
	Peripheral size for kmac in top darjeeling.

#define	TOP_DARJEELING_OTBN_BASE_ADDR 0x21130000u
	Peripheral base address for otbn in top darjeeling.

#define	TOP_DARJEELING_OTBN_SIZE_BYTES 0x10000u
	Peripheral size for otbn in top darjeeling.

#define	TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR 0x21140000u
	Peripheral base address for keymgr_dpe in top darjeeling.

#define	TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES 0x100u
	Peripheral size for keymgr_dpe in top darjeeling.

#define	TOP_DARJEELING_CSRNG_BASE_ADDR 0x21150000u
	Peripheral base address for csrng in top darjeeling.

#define	TOP_DARJEELING_CSRNG_SIZE_BYTES 0x80u
	Peripheral size for csrng in top darjeeling.

#define	TOP_DARJEELING_EDN0_BASE_ADDR 0x21170000u
	Peripheral base address for edn0 in top darjeeling.

#define	TOP_DARJEELING_EDN0_SIZE_BYTES 0x80u
	Peripheral size for edn0 in top darjeeling.

#define	TOP_DARJEELING_EDN1_BASE_ADDR 0x21180000u
	Peripheral base address for edn1 in top darjeeling.

#define	TOP_DARJEELING_EDN1_SIZE_BYTES 0x80u
	Peripheral size for edn1 in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x211C0000u
	Peripheral base address for regs device on sram_ctrl_main in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
	Peripheral size for regs device on sram_ctrl_main in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
	Peripheral base address for ram device on sram_ctrl_main in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x10000u
	Peripheral size for ram device on sram_ctrl_main in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR 0x211D0000u
	Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES 0x40u
	Peripheral size for regs device on sram_ctrl_mbox in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR 0x11000000u
	Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling.

#define	TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES 0x1000u
	Peripheral size for ram device on sram_ctrl_mbox in top darjeeling.

#define	TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR 0x211E0000u
	Peripheral base address for regs device on rom_ctrl0 in top darjeeling.

#define	TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES 0x80u
	Peripheral size for regs device on rom_ctrl0 in top darjeeling.

#define	TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR 0x8000u
	Peripheral base address for rom device on rom_ctrl0 in top darjeeling.

#define	TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES 0x8000u
	Peripheral size for rom device on rom_ctrl0 in top darjeeling.

#define	TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR 0x211E1000u
	Peripheral base address for regs device on rom_ctrl1 in top darjeeling.

#define	TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES 0x80u
	Peripheral size for regs device on rom_ctrl1 in top darjeeling.

#define	TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR 0x20000u
	Peripheral base address for rom device on rom_ctrl1 in top darjeeling.

#define	TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES 0x10000u
	Peripheral size for rom device on rom_ctrl1 in top darjeeling.

#define	TOP_DARJEELING_DMA_BASE_ADDR 0x22010000u
	Peripheral base address for dma in top darjeeling.

#define	TOP_DARJEELING_DMA_SIZE_BYTES 0x200u
	Peripheral size for dma in top darjeeling.

#define	TOP_DARJEELING_MBX0_CORE_BASE_ADDR 0x22000000u
	Peripheral base address for core device on mbx0 in top darjeeling.

#define	TOP_DARJEELING_MBX0_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx0 in top darjeeling.

#define	TOP_DARJEELING_MBX1_CORE_BASE_ADDR 0x22000100u
	Peripheral base address for core device on mbx1 in top darjeeling.

#define	TOP_DARJEELING_MBX1_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx1 in top darjeeling.

#define	TOP_DARJEELING_MBX2_CORE_BASE_ADDR 0x22000200u
	Peripheral base address for core device on mbx2 in top darjeeling.

#define	TOP_DARJEELING_MBX2_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx2 in top darjeeling.

#define	TOP_DARJEELING_MBX3_CORE_BASE_ADDR 0x22000300u
	Peripheral base address for core device on mbx3 in top darjeeling.

#define	TOP_DARJEELING_MBX3_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx3 in top darjeeling.

#define	TOP_DARJEELING_MBX4_CORE_BASE_ADDR 0x22000400u
	Peripheral base address for core device on mbx4 in top darjeeling.

#define	TOP_DARJEELING_MBX4_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx4 in top darjeeling.

#define	TOP_DARJEELING_MBX5_CORE_BASE_ADDR 0x22000500u
	Peripheral base address for core device on mbx5 in top darjeeling.

#define	TOP_DARJEELING_MBX5_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx5 in top darjeeling.

#define	TOP_DARJEELING_MBX6_CORE_BASE_ADDR 0x22000600u
	Peripheral base address for core device on mbx6 in top darjeeling.

#define	TOP_DARJEELING_MBX6_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx6 in top darjeeling.

#define	TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR 0x22000800u
	Peripheral base address for core device on mbx_jtag in top darjeeling.

#define	TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx_jtag in top darjeeling.

#define	TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR 0x22040000u
	Peripheral base address for core device on mbx_pcie0 in top darjeeling.

#define	TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx_pcie0 in top darjeeling.

#define	TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR 0x22040100u
	Peripheral base address for core device on mbx_pcie1 in top darjeeling.

#define	TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES 0x80u
	Peripheral size for core device on mbx_pcie1 in top darjeeling.

#define	TOP_DARJEELING_SOC_DBG_CTRL_CORE_BASE_ADDR 0x30170000u
	Peripheral base address for core device on soc_dbg_ctrl in top darjeeling.

#define	TOP_DARJEELING_SOC_DBG_CTRL_CORE_SIZE_BYTES 0x20u
	Peripheral size for core device on soc_dbg_ctrl in top darjeeling.

#define	TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR 0x211F0000u
	Peripheral base address for cfg device on rv_core_ibex in top darjeeling.

#define	TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES 0x800u
	Peripheral size for cfg device on rv_core_ibex in top darjeeling.

#define	TOP_DARJEELING_CTN_BASE_ADDR 0x40000000u
	Memory base address for ctn in top darjeeling.

#define	TOP_DARJEELING_CTN_SIZE_BYTES 0x40000000u
	Memory size for ctn in top darjeeling.

#define	TOP_DARJEELING_RAM_RET_AON_BASE_ADDR 0x30600000u
	Memory base address for ram_ret_aon in top darjeeling.

#define	TOP_DARJEELING_RAM_RET_AON_SIZE_BYTES 0x1000u
	Memory size for ram_ret_aon in top darjeeling.

#define	TOP_DARJEELING_RAM_MAIN_BASE_ADDR 0x10000000u
	Memory base address for ram_main in top darjeeling.

#define	TOP_DARJEELING_RAM_MAIN_SIZE_BYTES 0x10000u
	Memory size for ram_main in top darjeeling.

#define	TOP_DARJEELING_RAM_MBOX_BASE_ADDR 0x11000000u
	Memory base address for ram_mbox in top darjeeling.

#define	TOP_DARJEELING_RAM_MBOX_SIZE_BYTES 0x1000u
	Memory size for ram_mbox in top darjeeling.

#define	TOP_DARJEELING_ROM0_BASE_ADDR 0x8000u
	Memory base address for rom0 in top darjeeling.

#define	TOP_DARJEELING_ROM0_SIZE_BYTES 0x8000u
	Memory size for rom0 in top darjeeling.

#define	TOP_DARJEELING_ROM1_BASE_ADDR 0x20000u
	Memory base address for rom1 in top darjeeling.

#define	TOP_DARJEELING_ROM1_SIZE_BYTES 0x10000u
	Memory size for rom1 in top darjeeling.

#define	PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2

#define	NUM_MIO_PADS 12

#define	NUM_DIO_PADS 73

#define	PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3

#define	TOP_DARJEELING_MMIO_BASE_ADDR 0x21100000u
	MMIO Region.

#define	TOP_DARJEELING_MMIO_SIZE_BYTES 0xF501000u

Typedefs
typedef enum top_darjeeling_plic_peripheral	top_darjeeling_plic_peripheral_t
	PLIC Interrupt Source Peripheral.

typedef enum top_darjeeling_plic_irq_id	top_darjeeling_plic_irq_id_t
	PLIC Interrupt Source.

typedef enum top_darjeeling_plic_target	top_darjeeling_plic_target_t
	PLIC Interrupt Target.

typedef enum top_darjeeling_alert_peripheral	top_darjeeling_alert_peripheral_t
	Alert Handler Source Peripheral.

typedef enum top_darjeeling_alert_id	top_darjeeling_alert_id_t
	Alert Handler Alert Source.

typedef enum top_darjeeling_pinmux_peripheral_in	top_darjeeling_pinmux_peripheral_in_t
	Pinmux Peripheral Input.

typedef enum top_darjeeling_pinmux_insel	top_darjeeling_pinmux_insel_t
	Pinmux MIO Input Selector.

typedef enum top_darjeeling_pinmux_mio_out	top_darjeeling_pinmux_mio_out_t
	Pinmux MIO Output.

typedef enum top_darjeeling_pinmux_outsel	top_darjeeling_pinmux_outsel_t
	Pinmux Peripheral Output Selector.

typedef enum top_darjeeling_direct_pads	top_darjeeling_direct_pads_t
	Dedicated Pad Selects.

typedef enum top_darjeeling_muxed_pads	top_darjeeling_muxed_pads_t
	Muxed Pad Selects.

typedef enum top_darjeeling_power_manager_wake_ups	top_darjeeling_power_manager_wake_ups_t
	Power Manager Wakeup Signals.

typedef enum top_darjeeling_reset_manager_sw_resets	top_darjeeling_reset_manager_sw_resets_t
	Reset Manager Software Controlled Resets.

typedef enum top_darjeeling_power_manager_reset_requests	top_darjeeling_power_manager_reset_requests_t
	Power Manager Reset Request Signals.

typedef enum top_darjeeling_gateable_clocks	top_darjeeling_gateable_clocks_t
	Clock Manager Software-Controlled ("Gated") Clocks.

typedef enum top_darjeeling_hintable_clocks	top_darjeeling_hintable_clocks_t
	Clock Manager Software-Hinted Clocks.

Enumerations
enum	top_darjeeling_plic_peripheral { kTopDarjeelingPlicPeripheralUnknown = 0 , kTopDarjeelingPlicPeripheralUart0 = 1 , kTopDarjeelingPlicPeripheralGpio = 2 , kTopDarjeelingPlicPeripheralSpiDevice = 3 , kTopDarjeelingPlicPeripheralI2c0 = 4 , kTopDarjeelingPlicPeripheralRvTimer = 5 , kTopDarjeelingPlicPeripheralOtpCtrl = 6 , kTopDarjeelingPlicPeripheralAlertHandler = 7 , kTopDarjeelingPlicPeripheralSpiHost0 = 8 , kTopDarjeelingPlicPeripheralPwrmgrAon = 9 , kTopDarjeelingPlicPeripheralAonTimerAon = 10 , kTopDarjeelingPlicPeripheralSocProxy = 11 , kTopDarjeelingPlicPeripheralHmac = 12 , kTopDarjeelingPlicPeripheralKmac = 13 , kTopDarjeelingPlicPeripheralOtbn = 14 , kTopDarjeelingPlicPeripheralKeymgrDpe = 15 , kTopDarjeelingPlicPeripheralCsrng = 16 , kTopDarjeelingPlicPeripheralEdn0 = 17 , kTopDarjeelingPlicPeripheralEdn1 = 18 , kTopDarjeelingPlicPeripheralDma = 19 , kTopDarjeelingPlicPeripheralMbx0 = 20 , kTopDarjeelingPlicPeripheralMbx1 = 21 , kTopDarjeelingPlicPeripheralMbx2 = 22 , kTopDarjeelingPlicPeripheralMbx3 = 23 , kTopDarjeelingPlicPeripheralMbx4 = 24 , kTopDarjeelingPlicPeripheralMbx5 = 25 , kTopDarjeelingPlicPeripheralMbx6 = 26 , kTopDarjeelingPlicPeripheralMbxJtag = 27 , kTopDarjeelingPlicPeripheralMbxPcie0 = 28 , kTopDarjeelingPlicPeripheralMbxPcie1 = 29 , kTopDarjeelingPlicPeripheralRaclCtrl = 30 , kTopDarjeelingPlicPeripheralAcRangeCheck = 31 , kTopDarjeelingPlicPeripheralLast = 31 }
	PLIC Interrupt Source Peripheral. More...

enum	top_darjeeling_plic_irq_id { kTopDarjeelingPlicIrqIdNone = 0 , kTopDarjeelingPlicIrqIdUart0TxWatermark = 1 , kTopDarjeelingPlicIrqIdUart0RxWatermark = 2 , kTopDarjeelingPlicIrqIdUart0TxDone = 3 , kTopDarjeelingPlicIrqIdUart0RxOverflow = 4 , kTopDarjeelingPlicIrqIdUart0RxFrameErr = 5 , kTopDarjeelingPlicIrqIdUart0RxBreakErr = 6 , kTopDarjeelingPlicIrqIdUart0RxTimeout = 7 , kTopDarjeelingPlicIrqIdUart0RxParityErr = 8 , kTopDarjeelingPlicIrqIdUart0TxEmpty = 9 , kTopDarjeelingPlicIrqIdGpioGpio0 = 10 , kTopDarjeelingPlicIrqIdGpioGpio1 = 11 , kTopDarjeelingPlicIrqIdGpioGpio2 = 12 , kTopDarjeelingPlicIrqIdGpioGpio3 = 13 , kTopDarjeelingPlicIrqIdGpioGpio4 = 14 , kTopDarjeelingPlicIrqIdGpioGpio5 = 15 , kTopDarjeelingPlicIrqIdGpioGpio6 = 16 , kTopDarjeelingPlicIrqIdGpioGpio7 = 17 , kTopDarjeelingPlicIrqIdGpioGpio8 = 18 , kTopDarjeelingPlicIrqIdGpioGpio9 = 19 , kTopDarjeelingPlicIrqIdGpioGpio10 = 20 , kTopDarjeelingPlicIrqIdGpioGpio11 = 21 , kTopDarjeelingPlicIrqIdGpioGpio12 = 22 , kTopDarjeelingPlicIrqIdGpioGpio13 = 23 , kTopDarjeelingPlicIrqIdGpioGpio14 = 24 , kTopDarjeelingPlicIrqIdGpioGpio15 = 25 , kTopDarjeelingPlicIrqIdGpioGpio16 = 26 , kTopDarjeelingPlicIrqIdGpioGpio17 = 27 , kTopDarjeelingPlicIrqIdGpioGpio18 = 28 , kTopDarjeelingPlicIrqIdGpioGpio19 = 29 , kTopDarjeelingPlicIrqIdGpioGpio20 = 30 , kTopDarjeelingPlicIrqIdGpioGpio21 = 31 , kTopDarjeelingPlicIrqIdGpioGpio22 = 32 , kTopDarjeelingPlicIrqIdGpioGpio23 = 33 , kTopDarjeelingPlicIrqIdGpioGpio24 = 34 , kTopDarjeelingPlicIrqIdGpioGpio25 = 35 , kTopDarjeelingPlicIrqIdGpioGpio26 = 36 , kTopDarjeelingPlicIrqIdGpioGpio27 = 37 , kTopDarjeelingPlicIrqIdGpioGpio28 = 38 , kTopDarjeelingPlicIrqIdGpioGpio29 = 39 , kTopDarjeelingPlicIrqIdGpioGpio30 = 40 , kTopDarjeelingPlicIrqIdGpioGpio31 = 41 , kTopDarjeelingPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 42 , kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 43 , kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadOverflow = 44 , kTopDarjeelingPlicIrqIdSpiDeviceReadbufWatermark = 45 , kTopDarjeelingPlicIrqIdSpiDeviceReadbufFlip = 46 , kTopDarjeelingPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 47 , kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 48 , kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoDrop = 49 , kTopDarjeelingPlicIrqIdI2c0FmtThreshold = 50 , kTopDarjeelingPlicIrqIdI2c0RxThreshold = 51 , kTopDarjeelingPlicIrqIdI2c0AcqThreshold = 52 , kTopDarjeelingPlicIrqIdI2c0RxOverflow = 53 , kTopDarjeelingPlicIrqIdI2c0ControllerHalt = 54 , kTopDarjeelingPlicIrqIdI2c0SclInterference = 55 , kTopDarjeelingPlicIrqIdI2c0SdaInterference = 56 , kTopDarjeelingPlicIrqIdI2c0StretchTimeout = 57 , kTopDarjeelingPlicIrqIdI2c0SdaUnstable = 58 , kTopDarjeelingPlicIrqIdI2c0CmdComplete = 59 , kTopDarjeelingPlicIrqIdI2c0TxStretch = 60 , kTopDarjeelingPlicIrqIdI2c0TxThreshold = 61 , kTopDarjeelingPlicIrqIdI2c0AcqStretch = 62 , kTopDarjeelingPlicIrqIdI2c0UnexpStop = 63 , kTopDarjeelingPlicIrqIdI2c0HostTimeout = 64 , kTopDarjeelingPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 65 , kTopDarjeelingPlicIrqIdOtpCtrlOtpOperationDone = 66 , kTopDarjeelingPlicIrqIdOtpCtrlOtpError = 67 , kTopDarjeelingPlicIrqIdAlertHandlerClassa = 68 , kTopDarjeelingPlicIrqIdAlertHandlerClassb = 69 , kTopDarjeelingPlicIrqIdAlertHandlerClassc = 70 , kTopDarjeelingPlicIrqIdAlertHandlerClassd = 71 , kTopDarjeelingPlicIrqIdSpiHost0Error = 72 , kTopDarjeelingPlicIrqIdSpiHost0SpiEvent = 73 , kTopDarjeelingPlicIrqIdPwrmgrAonWakeup = 74 , kTopDarjeelingPlicIrqIdAonTimerAonWkupTimerExpired = 75 , kTopDarjeelingPlicIrqIdAonTimerAonWdogTimerBark = 76 , kTopDarjeelingPlicIrqIdSocProxyExternal0 = 77 , kTopDarjeelingPlicIrqIdSocProxyExternal1 = 78 , kTopDarjeelingPlicIrqIdSocProxyExternal2 = 79 , kTopDarjeelingPlicIrqIdSocProxyExternal3 = 80 , kTopDarjeelingPlicIrqIdSocProxyExternal4 = 81 , kTopDarjeelingPlicIrqIdSocProxyExternal5 = 82 , kTopDarjeelingPlicIrqIdSocProxyExternal6 = 83 , kTopDarjeelingPlicIrqIdSocProxyExternal7 = 84 , kTopDarjeelingPlicIrqIdSocProxyExternal8 = 85 , kTopDarjeelingPlicIrqIdSocProxyExternal9 = 86 , kTopDarjeelingPlicIrqIdSocProxyExternal10 = 87 , kTopDarjeelingPlicIrqIdSocProxyExternal11 = 88 , kTopDarjeelingPlicIrqIdSocProxyExternal12 = 89 , kTopDarjeelingPlicIrqIdSocProxyExternal13 = 90 , kTopDarjeelingPlicIrqIdSocProxyExternal14 = 91 , kTopDarjeelingPlicIrqIdSocProxyExternal15 = 92 , kTopDarjeelingPlicIrqIdSocProxyExternal16 = 93 , kTopDarjeelingPlicIrqIdSocProxyExternal17 = 94 , kTopDarjeelingPlicIrqIdSocProxyExternal18 = 95 , kTopDarjeelingPlicIrqIdSocProxyExternal19 = 96 , kTopDarjeelingPlicIrqIdSocProxyExternal20 = 97 , kTopDarjeelingPlicIrqIdSocProxyExternal21 = 98 , kTopDarjeelingPlicIrqIdSocProxyExternal22 = 99 , kTopDarjeelingPlicIrqIdSocProxyExternal23 = 100 , kTopDarjeelingPlicIrqIdSocProxyExternal24 = 101 , kTopDarjeelingPlicIrqIdSocProxyExternal25 = 102 , kTopDarjeelingPlicIrqIdSocProxyExternal26 = 103 , kTopDarjeelingPlicIrqIdSocProxyExternal27 = 104 , kTopDarjeelingPlicIrqIdSocProxyExternal28 = 105 , kTopDarjeelingPlicIrqIdSocProxyExternal29 = 106 , kTopDarjeelingPlicIrqIdSocProxyExternal30 = 107 , kTopDarjeelingPlicIrqIdSocProxyExternal31 = 108 , kTopDarjeelingPlicIrqIdHmacHmacDone = 109 , kTopDarjeelingPlicIrqIdHmacFifoEmpty = 110 , kTopDarjeelingPlicIrqIdHmacHmacErr = 111 , kTopDarjeelingPlicIrqIdKmacKmacDone = 112 , kTopDarjeelingPlicIrqIdKmacFifoEmpty = 113 , kTopDarjeelingPlicIrqIdKmacKmacErr = 114 , kTopDarjeelingPlicIrqIdOtbnDone = 115 , kTopDarjeelingPlicIrqIdKeymgrDpeOpDone = 116 , kTopDarjeelingPlicIrqIdCsrngCsCmdReqDone = 117 , kTopDarjeelingPlicIrqIdCsrngCsEntropyReq = 118 , kTopDarjeelingPlicIrqIdCsrngCsHwInstExc = 119 , kTopDarjeelingPlicIrqIdCsrngCsFatalErr = 120 , kTopDarjeelingPlicIrqIdEdn0EdnCmdReqDone = 121 , kTopDarjeelingPlicIrqIdEdn0EdnFatalErr = 122 , kTopDarjeelingPlicIrqIdEdn1EdnCmdReqDone = 123 , kTopDarjeelingPlicIrqIdEdn1EdnFatalErr = 124 , kTopDarjeelingPlicIrqIdDmaDmaDone = 125 , kTopDarjeelingPlicIrqIdDmaDmaChunkDone = 126 , kTopDarjeelingPlicIrqIdDmaDmaError = 127 , kTopDarjeelingPlicIrqIdMbx0MbxReady = 128 , kTopDarjeelingPlicIrqIdMbx0MbxAbort = 129 , kTopDarjeelingPlicIrqIdMbx0MbxError = 130 , kTopDarjeelingPlicIrqIdMbx1MbxReady = 131 , kTopDarjeelingPlicIrqIdMbx1MbxAbort = 132 , kTopDarjeelingPlicIrqIdMbx1MbxError = 133 , kTopDarjeelingPlicIrqIdMbx2MbxReady = 134 , kTopDarjeelingPlicIrqIdMbx2MbxAbort = 135 , kTopDarjeelingPlicIrqIdMbx2MbxError = 136 , kTopDarjeelingPlicIrqIdMbx3MbxReady = 137 , kTopDarjeelingPlicIrqIdMbx3MbxAbort = 138 , kTopDarjeelingPlicIrqIdMbx3MbxError = 139 , kTopDarjeelingPlicIrqIdMbx4MbxReady = 140 , kTopDarjeelingPlicIrqIdMbx4MbxAbort = 141 , kTopDarjeelingPlicIrqIdMbx4MbxError = 142 , kTopDarjeelingPlicIrqIdMbx5MbxReady = 143 , kTopDarjeelingPlicIrqIdMbx5MbxAbort = 144 , kTopDarjeelingPlicIrqIdMbx5MbxError = 145 , kTopDarjeelingPlicIrqIdMbx6MbxReady = 146 , kTopDarjeelingPlicIrqIdMbx6MbxAbort = 147 , kTopDarjeelingPlicIrqIdMbx6MbxError = 148 , kTopDarjeelingPlicIrqIdMbxJtagMbxReady = 149 , kTopDarjeelingPlicIrqIdMbxJtagMbxAbort = 150 , kTopDarjeelingPlicIrqIdMbxJtagMbxError = 151 , kTopDarjeelingPlicIrqIdMbxPcie0MbxReady = 152 , kTopDarjeelingPlicIrqIdMbxPcie0MbxAbort = 153 , kTopDarjeelingPlicIrqIdMbxPcie0MbxError = 154 , kTopDarjeelingPlicIrqIdMbxPcie1MbxReady = 155 , kTopDarjeelingPlicIrqIdMbxPcie1MbxAbort = 156 , kTopDarjeelingPlicIrqIdMbxPcie1MbxError = 157 , kTopDarjeelingPlicIrqIdRaclCtrlRaclError = 158 , kTopDarjeelingPlicIrqIdAcRangeCheckDenyCntReached = 159 , kTopDarjeelingPlicIrqIdLast = 159 }
	PLIC Interrupt Source. More...

enum	top_darjeeling_plic_target { kTopDarjeelingPlicTargetIbex0 = 0 , kTopDarjeelingPlicTargetLast = 0 }
	PLIC Interrupt Target. More...

enum	top_darjeeling_alert_peripheral { kTopDarjeelingAlertPeripheralExternal = 0 , kTopDarjeelingAlertPeripheralUart0 = 1 , kTopDarjeelingAlertPeripheralGpio = 2 , kTopDarjeelingAlertPeripheralSpiDevice = 3 , kTopDarjeelingAlertPeripheralI2c0 = 4 , kTopDarjeelingAlertPeripheralRvTimer = 5 , kTopDarjeelingAlertPeripheralOtpCtrl = 6 , kTopDarjeelingAlertPeripheralLcCtrl = 7 , kTopDarjeelingAlertPeripheralSpiHost0 = 8 , kTopDarjeelingAlertPeripheralPwrmgrAon = 9 , kTopDarjeelingAlertPeripheralRstmgrAon = 10 , kTopDarjeelingAlertPeripheralClkmgrAon = 11 , kTopDarjeelingAlertPeripheralPinmuxAon = 12 , kTopDarjeelingAlertPeripheralAonTimerAon = 13 , kTopDarjeelingAlertPeripheralSocProxy = 14 , kTopDarjeelingAlertPeripheralSramCtrlRetAon = 15 , kTopDarjeelingAlertPeripheralRvDm = 16 , kTopDarjeelingAlertPeripheralRvPlic = 17 , kTopDarjeelingAlertPeripheralAes = 18 , kTopDarjeelingAlertPeripheralHmac = 19 , kTopDarjeelingAlertPeripheralKmac = 20 , kTopDarjeelingAlertPeripheralOtbn = 21 , kTopDarjeelingAlertPeripheralKeymgrDpe = 22 , kTopDarjeelingAlertPeripheralCsrng = 23 , kTopDarjeelingAlertPeripheralEdn0 = 24 , kTopDarjeelingAlertPeripheralEdn1 = 25 , kTopDarjeelingAlertPeripheralSramCtrlMain = 26 , kTopDarjeelingAlertPeripheralSramCtrlMbox = 27 , kTopDarjeelingAlertPeripheralRomCtrl0 = 28 , kTopDarjeelingAlertPeripheralRomCtrl1 = 29 , kTopDarjeelingAlertPeripheralDma = 30 , kTopDarjeelingAlertPeripheralMbx0 = 31 , kTopDarjeelingAlertPeripheralMbx1 = 32 , kTopDarjeelingAlertPeripheralMbx2 = 33 , kTopDarjeelingAlertPeripheralMbx3 = 34 , kTopDarjeelingAlertPeripheralMbx4 = 35 , kTopDarjeelingAlertPeripheralMbx5 = 36 , kTopDarjeelingAlertPeripheralMbx6 = 37 , kTopDarjeelingAlertPeripheralMbxJtag = 38 , kTopDarjeelingAlertPeripheralMbxPcie0 = 39 , kTopDarjeelingAlertPeripheralMbxPcie1 = 40 , kTopDarjeelingAlertPeripheralSocDbgCtrl = 41 , kTopDarjeelingAlertPeripheralRaclCtrl = 42 , kTopDarjeelingAlertPeripheralAcRangeCheck = 43 , kTopDarjeelingAlertPeripheralRvCoreIbex = 44 , kTopDarjeelingAlertPeripheralLast = 44 }
	Alert Handler Source Peripheral. More...

enum	top_darjeeling_alert_id { kTopDarjeelingAlertIdUart0FatalFault = 0 , kTopDarjeelingAlertIdGpioFatalFault = 1 , kTopDarjeelingAlertIdSpiDeviceFatalFault = 2 , kTopDarjeelingAlertIdI2c0FatalFault = 3 , kTopDarjeelingAlertIdRvTimerFatalFault = 4 , kTopDarjeelingAlertIdOtpCtrlFatalMacroError = 5 , kTopDarjeelingAlertIdOtpCtrlFatalCheckError = 6 , kTopDarjeelingAlertIdOtpCtrlFatalBusIntegError = 7 , kTopDarjeelingAlertIdOtpCtrlFatalPrimOtpAlert = 8 , kTopDarjeelingAlertIdOtpCtrlRecovPrimOtpAlert = 9 , kTopDarjeelingAlertIdLcCtrlFatalProgError = 10 , kTopDarjeelingAlertIdLcCtrlFatalStateError = 11 , kTopDarjeelingAlertIdLcCtrlFatalBusIntegError = 12 , kTopDarjeelingAlertIdSpiHost0FatalFault = 13 , kTopDarjeelingAlertIdPwrmgrAonFatalFault = 14 , kTopDarjeelingAlertIdRstmgrAonFatalFault = 15 , kTopDarjeelingAlertIdRstmgrAonFatalCnstyFault = 16 , kTopDarjeelingAlertIdClkmgrAonRecovFault = 17 , kTopDarjeelingAlertIdClkmgrAonFatalFault = 18 , kTopDarjeelingAlertIdPinmuxAonFatalFault = 19 , kTopDarjeelingAlertIdAonTimerAonFatalFault = 20 , kTopDarjeelingAlertIdSocProxyFatalAlertIntg = 21 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal0 = 22 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal1 = 23 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal2 = 24 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal3 = 25 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal4 = 26 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal5 = 27 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal6 = 28 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal7 = 29 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal8 = 30 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal9 = 31 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal10 = 32 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal11 = 33 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal12 = 34 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal13 = 35 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal14 = 36 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal15 = 37 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal16 = 38 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal17 = 39 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal18 = 40 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal19 = 41 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal20 = 42 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal21 = 43 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal22 = 44 , kTopDarjeelingAlertIdSocProxyFatalAlertExternal23 = 45 , kTopDarjeelingAlertIdSocProxyRecovAlertExternal0 = 46 , kTopDarjeelingAlertIdSocProxyRecovAlertExternal1 = 47 , kTopDarjeelingAlertIdSocProxyRecovAlertExternal2 = 48 , kTopDarjeelingAlertIdSocProxyRecovAlertExternal3 = 49 , kTopDarjeelingAlertIdSramCtrlRetAonFatalError = 50 , kTopDarjeelingAlertIdRvDmFatalFault = 51 , kTopDarjeelingAlertIdRvPlicFatalFault = 52 , kTopDarjeelingAlertIdAesRecovCtrlUpdateErr = 53 , kTopDarjeelingAlertIdAesFatalFault = 54 , kTopDarjeelingAlertIdHmacFatalFault = 55 , kTopDarjeelingAlertIdKmacRecovOperationErr = 56 , kTopDarjeelingAlertIdKmacFatalFaultErr = 57 , kTopDarjeelingAlertIdOtbnFatal = 58 , kTopDarjeelingAlertIdOtbnRecov = 59 , kTopDarjeelingAlertIdKeymgrDpeRecovOperationErr = 60 , kTopDarjeelingAlertIdKeymgrDpeFatalFaultErr = 61 , kTopDarjeelingAlertIdCsrngRecovAlert = 62 , kTopDarjeelingAlertIdCsrngFatalAlert = 63 , kTopDarjeelingAlertIdEdn0RecovAlert = 64 , kTopDarjeelingAlertIdEdn0FatalAlert = 65 , kTopDarjeelingAlertIdEdn1RecovAlert = 66 , kTopDarjeelingAlertIdEdn1FatalAlert = 67 , kTopDarjeelingAlertIdSramCtrlMainFatalError = 68 , kTopDarjeelingAlertIdSramCtrlMboxFatalError = 69 , kTopDarjeelingAlertIdRomCtrl0Fatal = 70 , kTopDarjeelingAlertIdRomCtrl1Fatal = 71 , kTopDarjeelingAlertIdDmaFatalFault = 72 , kTopDarjeelingAlertIdMbx0FatalFault = 73 , kTopDarjeelingAlertIdMbx0RecovFault = 74 , kTopDarjeelingAlertIdMbx1FatalFault = 75 , kTopDarjeelingAlertIdMbx1RecovFault = 76 , kTopDarjeelingAlertIdMbx2FatalFault = 77 , kTopDarjeelingAlertIdMbx2RecovFault = 78 , kTopDarjeelingAlertIdMbx3FatalFault = 79 , kTopDarjeelingAlertIdMbx3RecovFault = 80 , kTopDarjeelingAlertIdMbx4FatalFault = 81 , kTopDarjeelingAlertIdMbx4RecovFault = 82 , kTopDarjeelingAlertIdMbx5FatalFault = 83 , kTopDarjeelingAlertIdMbx5RecovFault = 84 , kTopDarjeelingAlertIdMbx6FatalFault = 85 , kTopDarjeelingAlertIdMbx6RecovFault = 86 , kTopDarjeelingAlertIdMbxJtagFatalFault = 87 , kTopDarjeelingAlertIdMbxJtagRecovFault = 88 , kTopDarjeelingAlertIdMbxPcie0FatalFault = 89 , kTopDarjeelingAlertIdMbxPcie0RecovFault = 90 , kTopDarjeelingAlertIdMbxPcie1FatalFault = 91 , kTopDarjeelingAlertIdMbxPcie1RecovFault = 92 , kTopDarjeelingAlertIdSocDbgCtrlFatalFault = 93 , kTopDarjeelingAlertIdSocDbgCtrlRecovCtrlUpdateErr = 94 , kTopDarjeelingAlertIdRaclCtrlFatalFault = 95 , kTopDarjeelingAlertIdRaclCtrlRecovCtrlUpdateErr = 96 , kTopDarjeelingAlertIdAcRangeCheckRecovCtrlUpdateErr = 97 , kTopDarjeelingAlertIdAcRangeCheckFatalFault = 98 , kTopDarjeelingAlertIdRvCoreIbexFatalSwErr = 99 , kTopDarjeelingAlertIdRvCoreIbexRecovSwErr = 100 , kTopDarjeelingAlertIdRvCoreIbexFatalHwErr = 101 , kTopDarjeelingAlertIdRvCoreIbexRecovHwErr = 102 , kTopDarjeelingAlertIdLast = 102 }
	Alert Handler Alert Source. More...

enum	top_darjeeling_pinmux_peripheral_in { kTopDarjeelingPinmuxPeripheralInSocProxySocGpi12 = 0 , kTopDarjeelingPinmuxPeripheralInSocProxySocGpi13 = 1 , kTopDarjeelingPinmuxPeripheralInSocProxySocGpi14 = 2 , kTopDarjeelingPinmuxPeripheralInSocProxySocGpi15 = 3 , kTopDarjeelingPinmuxPeripheralInLast = 3 }
	Pinmux Peripheral Input. More...

enum	top_darjeeling_pinmux_insel { kTopDarjeelingPinmuxInselConstantZero = 0 , kTopDarjeelingPinmuxInselConstantOne = 1 , kTopDarjeelingPinmuxInselMio0 = 2 , kTopDarjeelingPinmuxInselMio1 = 3 , kTopDarjeelingPinmuxInselMio2 = 4 , kTopDarjeelingPinmuxInselMio3 = 5 , kTopDarjeelingPinmuxInselMio4 = 6 , kTopDarjeelingPinmuxInselMio5 = 7 , kTopDarjeelingPinmuxInselMio6 = 8 , kTopDarjeelingPinmuxInselMio7 = 9 , kTopDarjeelingPinmuxInselMio8 = 10 , kTopDarjeelingPinmuxInselMio9 = 11 , kTopDarjeelingPinmuxInselMio10 = 12 , kTopDarjeelingPinmuxInselMio11 = 13 , kTopDarjeelingPinmuxInselLast = 13 }
	Pinmux MIO Input Selector. More...

enum	top_darjeeling_pinmux_mio_out { kTopDarjeelingPinmuxMioOutMio0 = 0 , kTopDarjeelingPinmuxMioOutMio1 = 1 , kTopDarjeelingPinmuxMioOutMio2 = 2 , kTopDarjeelingPinmuxMioOutMio3 = 3 , kTopDarjeelingPinmuxMioOutMio4 = 4 , kTopDarjeelingPinmuxMioOutMio5 = 5 , kTopDarjeelingPinmuxMioOutMio6 = 6 , kTopDarjeelingPinmuxMioOutMio7 = 7 , kTopDarjeelingPinmuxMioOutMio8 = 8 , kTopDarjeelingPinmuxMioOutMio9 = 9 , kTopDarjeelingPinmuxMioOutMio10 = 10 , kTopDarjeelingPinmuxMioOutMio11 = 11 , kTopDarjeelingPinmuxMioOutLast = 11 }
	Pinmux MIO Output. More...

enum	top_darjeeling_pinmux_outsel { kTopDarjeelingPinmuxOutselConstantZero = 0 , kTopDarjeelingPinmuxOutselConstantOne = 1 , kTopDarjeelingPinmuxOutselConstantHighZ = 2 , kTopDarjeelingPinmuxOutselSocProxySocGpo12 = 3 , kTopDarjeelingPinmuxOutselSocProxySocGpo13 = 4 , kTopDarjeelingPinmuxOutselSocProxySocGpo14 = 5 , kTopDarjeelingPinmuxOutselSocProxySocGpo15 = 6 , kTopDarjeelingPinmuxOutselOtpMacroTest0 = 7 , kTopDarjeelingPinmuxOutselLast = 7 }
	Pinmux Peripheral Output Selector. More...

enum	top_darjeeling_direct_pads { kTopDarjeelingDirectPadsSpiHost0Sd0 = 0 , kTopDarjeelingDirectPadsSpiHost0Sd1 = 1 , kTopDarjeelingDirectPadsSpiHost0Sd2 = 2 , kTopDarjeelingDirectPadsSpiHost0Sd3 = 3 , kTopDarjeelingDirectPadsSpiDeviceSd0 = 4 , kTopDarjeelingDirectPadsSpiDeviceSd1 = 5 , kTopDarjeelingDirectPadsSpiDeviceSd2 = 6 , kTopDarjeelingDirectPadsSpiDeviceSd3 = 7 , kTopDarjeelingDirectPadsI2c0Scl = 8 , kTopDarjeelingDirectPadsI2c0Sda = 9 , kTopDarjeelingDirectPadsGpioGpio0 = 10 , kTopDarjeelingDirectPadsGpioGpio1 = 11 , kTopDarjeelingDirectPadsGpioGpio2 = 12 , kTopDarjeelingDirectPadsGpioGpio3 = 13 , kTopDarjeelingDirectPadsGpioGpio4 = 14 , kTopDarjeelingDirectPadsGpioGpio5 = 15 , kTopDarjeelingDirectPadsGpioGpio6 = 16 , kTopDarjeelingDirectPadsGpioGpio7 = 17 , kTopDarjeelingDirectPadsGpioGpio8 = 18 , kTopDarjeelingDirectPadsGpioGpio9 = 19 , kTopDarjeelingDirectPadsGpioGpio10 = 20 , kTopDarjeelingDirectPadsGpioGpio11 = 21 , kTopDarjeelingDirectPadsGpioGpio12 = 22 , kTopDarjeelingDirectPadsGpioGpio13 = 23 , kTopDarjeelingDirectPadsGpioGpio14 = 24 , kTopDarjeelingDirectPadsGpioGpio15 = 25 , kTopDarjeelingDirectPadsGpioGpio16 = 26 , kTopDarjeelingDirectPadsGpioGpio17 = 27 , kTopDarjeelingDirectPadsGpioGpio18 = 28 , kTopDarjeelingDirectPadsGpioGpio19 = 29 , kTopDarjeelingDirectPadsGpioGpio20 = 30 , kTopDarjeelingDirectPadsGpioGpio21 = 31 , kTopDarjeelingDirectPadsGpioGpio22 = 32 , kTopDarjeelingDirectPadsGpioGpio23 = 33 , kTopDarjeelingDirectPadsGpioGpio24 = 34 , kTopDarjeelingDirectPadsGpioGpio25 = 35 , kTopDarjeelingDirectPadsGpioGpio26 = 36 , kTopDarjeelingDirectPadsGpioGpio27 = 37 , kTopDarjeelingDirectPadsGpioGpio28 = 38 , kTopDarjeelingDirectPadsGpioGpio29 = 39 , kTopDarjeelingDirectPadsGpioGpio30 = 40 , kTopDarjeelingDirectPadsGpioGpio31 = 41 , kTopDarjeelingDirectPadsSpiDeviceSck = 42 , kTopDarjeelingDirectPadsSpiDeviceCsb = 43 , kTopDarjeelingDirectPadsSpiDeviceTpmCsb = 44 , kTopDarjeelingDirectPadsUart0Rx = 45 , kTopDarjeelingDirectPadsSocProxySocGpi0 = 46 , kTopDarjeelingDirectPadsSocProxySocGpi1 = 47 , kTopDarjeelingDirectPadsSocProxySocGpi2 = 48 , kTopDarjeelingDirectPadsSocProxySocGpi3 = 49 , kTopDarjeelingDirectPadsSocProxySocGpi4 = 50 , kTopDarjeelingDirectPadsSocProxySocGpi5 = 51 , kTopDarjeelingDirectPadsSocProxySocGpi6 = 52 , kTopDarjeelingDirectPadsSocProxySocGpi7 = 53 , kTopDarjeelingDirectPadsSocProxySocGpi8 = 54 , kTopDarjeelingDirectPadsSocProxySocGpi9 = 55 , kTopDarjeelingDirectPadsSocProxySocGpi10 = 56 , kTopDarjeelingDirectPadsSocProxySocGpi11 = 57 , kTopDarjeelingDirectPadsSpiHost0Sck = 58 , kTopDarjeelingDirectPadsSpiHost0Csb = 59 , kTopDarjeelingDirectPadsUart0Tx = 60 , kTopDarjeelingDirectPadsSocProxySocGpo0 = 61 , kTopDarjeelingDirectPadsSocProxySocGpo1 = 62 , kTopDarjeelingDirectPadsSocProxySocGpo2 = 63 , kTopDarjeelingDirectPadsSocProxySocGpo3 = 64 , kTopDarjeelingDirectPadsSocProxySocGpo4 = 65 , kTopDarjeelingDirectPadsSocProxySocGpo5 = 66 , kTopDarjeelingDirectPadsSocProxySocGpo6 = 67 , kTopDarjeelingDirectPadsSocProxySocGpo7 = 68 , kTopDarjeelingDirectPadsSocProxySocGpo8 = 69 , kTopDarjeelingDirectPadsSocProxySocGpo9 = 70 , kTopDarjeelingDirectPadsSocProxySocGpo10 = 71 , kTopDarjeelingDirectPadsSocProxySocGpo11 = 72 , kTopDarjeelingDirectPadsLast = 72 }
	Dedicated Pad Selects. More...

enum	top_darjeeling_muxed_pads { kTopDarjeelingMuxedPadsMio0 = 0 , kTopDarjeelingMuxedPadsMio1 = 1 , kTopDarjeelingMuxedPadsMio2 = 2 , kTopDarjeelingMuxedPadsMio3 = 3 , kTopDarjeelingMuxedPadsMio4 = 4 , kTopDarjeelingMuxedPadsMio5 = 5 , kTopDarjeelingMuxedPadsMio6 = 6 , kTopDarjeelingMuxedPadsMio7 = 7 , kTopDarjeelingMuxedPadsMio8 = 8 , kTopDarjeelingMuxedPadsMio9 = 9 , kTopDarjeelingMuxedPadsMio10 = 10 , kTopDarjeelingMuxedPadsMio11 = 11 , kTopDarjeelingMuxedPadsLast = 11 }
	Muxed Pad Selects. More...

enum	top_darjeeling_power_manager_wake_ups { kTopDarjeelingPowerManagerWakeUpsPinmuxAonPinWkupReq = 0 , kTopDarjeelingPowerManagerWakeUpsAonTimerAonWkupReq = 1 , kTopDarjeelingPowerManagerWakeUpsSocProxyWkupInternalReq = 2 , kTopDarjeelingPowerManagerWakeUpsSocProxyWkupExternalReq = 3 , kTopDarjeelingPowerManagerWakeUpsLast = 3 }
	Power Manager Wakeup Signals. More...

enum	top_darjeeling_reset_manager_sw_resets { kTopDarjeelingResetManagerSwResetsSpiDevice = 0 , kTopDarjeelingResetManagerSwResetsSpiHost0 = 1 , kTopDarjeelingResetManagerSwResetsI2c0 = 2 , kTopDarjeelingResetManagerSwResetsLast = 2 }
	Reset Manager Software Controlled Resets. More...

enum	top_darjeeling_power_manager_reset_requests { kTopDarjeelingPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 0 , kTopDarjeelingPowerManagerResetRequestsSocProxyRstReqExternal = 1 , kTopDarjeelingPowerManagerResetRequestsLast = 1 }
	Power Manager Reset Request Signals. More...

enum	top_darjeeling_gateable_clocks { kTopDarjeelingGateableClocksIoDiv4Peri = 0 , kTopDarjeelingGateableClocksIoDiv2Peri = 1 , kTopDarjeelingGateableClocksLast = 1 }
	Clock Manager Software-Controlled ("Gated") Clocks. More...

enum	top_darjeeling_hintable_clocks { kTopDarjeelingHintableClocksMainAes = 0 , kTopDarjeelingHintableClocksMainHmac = 1 , kTopDarjeelingHintableClocksMainKmac = 2 , kTopDarjeelingHintableClocksMainOtbn = 3 , kTopDarjeelingHintableClocksLast = 3 }
	Clock Manager Software-Hinted Clocks. More...

Variables
const top_darjeeling_plic_peripheral_t	top_darjeeling_plic_interrupt_for_peripheral [160]
	PLIC Interrupt Source to Peripheral Map.

const top_darjeeling_alert_peripheral_t	top_darjeeling_alert_for_peripheral [103]
	Alert Handler Alert Source to Peripheral Map.

Detailed Description

Top-specific Definitions.

This file contains preprocessor and type definitions for use within the device C/C++ codebase.

These definitions are for information that depends on the top-specific chip configuration, which includes:

Device Memory Information (for Peripherals and Memory)
PLIC Interrupt ID Names and Source Mappings
Alert ID Names and Source Mappings
Pinmux Pin/Select Names
Power Manager Wakeups

Definition in file top_darjeeling.h.

Macro Definition Documentation

◆ NUM_DIO_PADS

#define NUM_DIO_PADS 73

Definition at line 1445 of file top_darjeeling.h.

◆ NUM_MIO_PADS

#define NUM_MIO_PADS 12

Definition at line 1444 of file top_darjeeling.h.

◆ PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2

Definition at line 1440 of file top_darjeeling.h.

◆ PINMUX_PERIPH_OUTSEL_IDX_OFFSET

#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3

Definition at line 1447 of file top_darjeeling.h.

◆ TOP_DARJEELING_AES_BASE_ADDR

#define TOP_DARJEELING_AES_BASE_ADDR 0x21100000u

Peripheral base address for aes in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 453 of file top_darjeeling.h.

◆ TOP_DARJEELING_AES_SIZE_BYTES

#define TOP_DARJEELING_AES_SIZE_BYTES 0x100u

Peripheral size for aes in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_AES_BASE_ADDR and TOP_DARJEELING_AES_BASE_ADDR + TOP_DARJEELING_AES_SIZE_BYTES.

Definition at line 463 of file top_darjeeling.h.

◆ TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR

#define TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR 0x30160000u

Peripheral base address for alert_handler in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 183 of file top_darjeeling.h.

◆ TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES

#define TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES 0x800u

Peripheral size for alert_handler in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR and TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR + TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES.

Definition at line 193 of file top_darjeeling.h.

◆ TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR

#define TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR 0x30470000u

Peripheral base address for aon_timer_aon in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 291 of file top_darjeeling.h.

◆ TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES

#define TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES 0x40u

Peripheral size for aon_timer_aon in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR and TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR + TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES.

Definition at line 301 of file top_darjeeling.h.

◆ TOP_DARJEELING_AST_BASE_ADDR

#define TOP_DARJEELING_AST_BASE_ADDR 0x30480000u

Peripheral base address for ast in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 309 of file top_darjeeling.h.

◆ TOP_DARJEELING_AST_SIZE_BYTES

#define TOP_DARJEELING_AST_SIZE_BYTES 0x400u

Peripheral size for ast in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_AST_BASE_ADDR and TOP_DARJEELING_AST_BASE_ADDR + TOP_DARJEELING_AST_SIZE_BYTES.

Definition at line 319 of file top_darjeeling.h.

◆ TOP_DARJEELING_CLKMGR_AON_BASE_ADDR

#define TOP_DARJEELING_CLKMGR_AON_BASE_ADDR 0x30420000u

Peripheral base address for clkmgr_aon in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 255 of file top_darjeeling.h.

◆ TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES

#define TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES 0x40u

Peripheral size for clkmgr_aon in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_CLKMGR_AON_BASE_ADDR and TOP_DARJEELING_CLKMGR_AON_BASE_ADDR + TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES.

Definition at line 265 of file top_darjeeling.h.

◆ TOP_DARJEELING_CSRNG_BASE_ADDR

#define TOP_DARJEELING_CSRNG_BASE_ADDR 0x21150000u

Peripheral base address for csrng in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 543 of file top_darjeeling.h.

◆ TOP_DARJEELING_CSRNG_SIZE_BYTES

#define TOP_DARJEELING_CSRNG_SIZE_BYTES 0x80u

Peripheral size for csrng in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_CSRNG_BASE_ADDR and TOP_DARJEELING_CSRNG_BASE_ADDR + TOP_DARJEELING_CSRNG_SIZE_BYTES.

Definition at line 553 of file top_darjeeling.h.

◆ TOP_DARJEELING_CTN_BASE_ADDR

#define TOP_DARJEELING_CTN_BASE_ADDR 0x40000000u

Memory base address for ctn in top darjeeling.

Definition at line 973 of file top_darjeeling.h.

◆ TOP_DARJEELING_CTN_SIZE_BYTES

#define TOP_DARJEELING_CTN_SIZE_BYTES 0x40000000u

Memory size for ctn in top darjeeling.

Definition at line 978 of file top_darjeeling.h.

◆ TOP_DARJEELING_DMA_BASE_ADDR

#define TOP_DARJEELING_DMA_BASE_ADDR 0x22010000u

Peripheral base address for dma in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 741 of file top_darjeeling.h.

◆ TOP_DARJEELING_DMA_SIZE_BYTES

#define TOP_DARJEELING_DMA_SIZE_BYTES 0x200u

Peripheral size for dma in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_DMA_BASE_ADDR and TOP_DARJEELING_DMA_BASE_ADDR + TOP_DARJEELING_DMA_SIZE_BYTES.

Definition at line 751 of file top_darjeeling.h.

◆ TOP_DARJEELING_EDN0_BASE_ADDR

#define TOP_DARJEELING_EDN0_BASE_ADDR 0x21170000u

Peripheral base address for edn0 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 561 of file top_darjeeling.h.

◆ TOP_DARJEELING_EDN0_SIZE_BYTES

#define TOP_DARJEELING_EDN0_SIZE_BYTES 0x80u

Peripheral size for edn0 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_EDN0_BASE_ADDR and TOP_DARJEELING_EDN0_BASE_ADDR + TOP_DARJEELING_EDN0_SIZE_BYTES.

Definition at line 571 of file top_darjeeling.h.

◆ TOP_DARJEELING_EDN1_BASE_ADDR

#define TOP_DARJEELING_EDN1_BASE_ADDR 0x21180000u

Peripheral base address for edn1 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 579 of file top_darjeeling.h.

◆ TOP_DARJEELING_EDN1_SIZE_BYTES

#define TOP_DARJEELING_EDN1_SIZE_BYTES 0x80u

Peripheral size for edn1 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_EDN1_BASE_ADDR and TOP_DARJEELING_EDN1_BASE_ADDR + TOP_DARJEELING_EDN1_SIZE_BYTES.

Definition at line 589 of file top_darjeeling.h.

◆ TOP_DARJEELING_GPIO_BASE_ADDR

#define TOP_DARJEELING_GPIO_BASE_ADDR 0x30000000u

Peripheral base address for gpio in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 57 of file top_darjeeling.h.

◆ TOP_DARJEELING_GPIO_SIZE_BYTES

#define TOP_DARJEELING_GPIO_SIZE_BYTES 0x100u

Peripheral size for gpio in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_GPIO_BASE_ADDR and TOP_DARJEELING_GPIO_BASE_ADDR + TOP_DARJEELING_GPIO_SIZE_BYTES.

Definition at line 67 of file top_darjeeling.h.

◆ TOP_DARJEELING_HMAC_BASE_ADDR

#define TOP_DARJEELING_HMAC_BASE_ADDR 0x21110000u

Peripheral base address for hmac in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 471 of file top_darjeeling.h.

◆ TOP_DARJEELING_HMAC_SIZE_BYTES

#define TOP_DARJEELING_HMAC_SIZE_BYTES 0x2000u

Peripheral size for hmac in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_HMAC_BASE_ADDR and TOP_DARJEELING_HMAC_BASE_ADDR + TOP_DARJEELING_HMAC_SIZE_BYTES.

Definition at line 481 of file top_darjeeling.h.

◆ TOP_DARJEELING_I2C0_BASE_ADDR

#define TOP_DARJEELING_I2C0_BASE_ADDR 0x30080000u

Peripheral base address for i2c0 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 93 of file top_darjeeling.h.

◆ TOP_DARJEELING_I2C0_SIZE_BYTES

#define TOP_DARJEELING_I2C0_SIZE_BYTES 0x80u

Peripheral size for i2c0 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_I2C0_BASE_ADDR and TOP_DARJEELING_I2C0_BASE_ADDR + TOP_DARJEELING_I2C0_SIZE_BYTES.

Definition at line 103 of file top_darjeeling.h.

◆ TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR

#define TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR 0x21140000u

Peripheral base address for keymgr_dpe in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 525 of file top_darjeeling.h.

◆ TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES

#define TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES 0x100u

Peripheral size for keymgr_dpe in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR and TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR + TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES.

Definition at line 535 of file top_darjeeling.h.

◆ TOP_DARJEELING_KMAC_BASE_ADDR

#define TOP_DARJEELING_KMAC_BASE_ADDR 0x21120000u

Peripheral base address for kmac in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 489 of file top_darjeeling.h.

◆ TOP_DARJEELING_KMAC_SIZE_BYTES

#define TOP_DARJEELING_KMAC_SIZE_BYTES 0x1000u

Peripheral size for kmac in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_KMAC_BASE_ADDR and TOP_DARJEELING_KMAC_BASE_ADDR + TOP_DARJEELING_KMAC_SIZE_BYTES.

Definition at line 499 of file top_darjeeling.h.

◆ TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR

#define TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR 0x30150000u

Peripheral base address for regs device on lc_ctrl in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 165 of file top_darjeeling.h.

◆ TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES

#define TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES 0x100u

Peripheral size for regs device on lc_ctrl in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR and TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR + TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES.

Definition at line 175 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX0_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX0_CORE_BASE_ADDR 0x22000000u

Peripheral base address for core device on mbx0 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 759 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX0_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX0_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx0 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX0_CORE_BASE_ADDR and TOP_DARJEELING_MBX0_CORE_BASE_ADDR + TOP_DARJEELING_MBX0_CORE_SIZE_BYTES.

Definition at line 769 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX1_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX1_CORE_BASE_ADDR 0x22000100u

Peripheral base address for core device on mbx1 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 777 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX1_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX1_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx1 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX1_CORE_BASE_ADDR and TOP_DARJEELING_MBX1_CORE_BASE_ADDR + TOP_DARJEELING_MBX1_CORE_SIZE_BYTES.

Definition at line 787 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX2_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX2_CORE_BASE_ADDR 0x22000200u

Peripheral base address for core device on mbx2 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 795 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX2_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX2_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx2 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX2_CORE_BASE_ADDR and TOP_DARJEELING_MBX2_CORE_BASE_ADDR + TOP_DARJEELING_MBX2_CORE_SIZE_BYTES.

Definition at line 805 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX3_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX3_CORE_BASE_ADDR 0x22000300u

Peripheral base address for core device on mbx3 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 813 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX3_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX3_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx3 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX3_CORE_BASE_ADDR and TOP_DARJEELING_MBX3_CORE_BASE_ADDR + TOP_DARJEELING_MBX3_CORE_SIZE_BYTES.

Definition at line 823 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX4_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX4_CORE_BASE_ADDR 0x22000400u

Peripheral base address for core device on mbx4 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 831 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX4_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX4_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx4 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX4_CORE_BASE_ADDR and TOP_DARJEELING_MBX4_CORE_BASE_ADDR + TOP_DARJEELING_MBX4_CORE_SIZE_BYTES.

Definition at line 841 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX5_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX5_CORE_BASE_ADDR 0x22000500u

Peripheral base address for core device on mbx5 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 849 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX5_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX5_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx5 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX5_CORE_BASE_ADDR and TOP_DARJEELING_MBX5_CORE_BASE_ADDR + TOP_DARJEELING_MBX5_CORE_SIZE_BYTES.

Definition at line 859 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX6_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX6_CORE_BASE_ADDR 0x22000600u

Peripheral base address for core device on mbx6 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 867 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX6_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX6_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx6 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX6_CORE_BASE_ADDR and TOP_DARJEELING_MBX6_CORE_BASE_ADDR + TOP_DARJEELING_MBX6_CORE_SIZE_BYTES.

Definition at line 877 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR 0x22000800u

Peripheral base address for core device on mbx_jtag in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 885 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx_jtag in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR and TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES.

Definition at line 895 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR 0x22040000u

Peripheral base address for core device on mbx_pcie0 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 903 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx_pcie0 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR and TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES.

Definition at line 913 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR

#define TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR 0x22040100u

Peripheral base address for core device on mbx_pcie1 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 921 of file top_darjeeling.h.

◆ TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES

#define TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES 0x80u

Peripheral size for core device on mbx_pcie1 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR and TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES.

Definition at line 931 of file top_darjeeling.h.

◆ TOP_DARJEELING_MMIO_BASE_ADDR

#define TOP_DARJEELING_MMIO_BASE_ADDR 0x21100000u

MMIO Region.

MMIO region excludes any memory that is separate from the module configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but retention SRAM or spi_device are included.

Definition at line 1676 of file top_darjeeling.h.

◆ TOP_DARJEELING_MMIO_SIZE_BYTES

#define TOP_DARJEELING_MMIO_SIZE_BYTES 0xF501000u

Definition at line 1677 of file top_darjeeling.h.

◆ TOP_DARJEELING_OTBN_BASE_ADDR

#define TOP_DARJEELING_OTBN_BASE_ADDR 0x21130000u

Peripheral base address for otbn in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 507 of file top_darjeeling.h.

◆ TOP_DARJEELING_OTBN_SIZE_BYTES

#define TOP_DARJEELING_OTBN_SIZE_BYTES 0x10000u

Peripheral size for otbn in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_OTBN_BASE_ADDR and TOP_DARJEELING_OTBN_BASE_ADDR + TOP_DARJEELING_OTBN_SIZE_BYTES.

Definition at line 517 of file top_darjeeling.h.

◆ TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR

#define TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR 0x30130000u

Peripheral base address for core device on otp_ctrl in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 129 of file top_darjeeling.h.

◆ TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES

#define TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES 0x8000u

Peripheral size for core device on otp_ctrl in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR and TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES.

Definition at line 139 of file top_darjeeling.h.

◆ TOP_DARJEELING_OTP_MACRO_BASE_ADDR

#define TOP_DARJEELING_OTP_MACRO_BASE_ADDR 0x30140000u

Peripheral base address for otp_macro in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 147 of file top_darjeeling.h.

◆ TOP_DARJEELING_OTP_MACRO_SIZE_BYTES

#define TOP_DARJEELING_OTP_MACRO_SIZE_BYTES 0x20u

Peripheral size for otp_macro in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_OTP_MACRO_BASE_ADDR and TOP_DARJEELING_OTP_MACRO_BASE_ADDR + TOP_DARJEELING_OTP_MACRO_SIZE_BYTES.

Definition at line 157 of file top_darjeeling.h.

◆ TOP_DARJEELING_PINMUX_AON_BASE_ADDR

#define TOP_DARJEELING_PINMUX_AON_BASE_ADDR 0x30460000u

Peripheral base address for pinmux_aon in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 273 of file top_darjeeling.h.

◆ TOP_DARJEELING_PINMUX_AON_SIZE_BYTES

#define TOP_DARJEELING_PINMUX_AON_SIZE_BYTES 0x800u

Peripheral size for pinmux_aon in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_PINMUX_AON_BASE_ADDR and TOP_DARJEELING_PINMUX_AON_BASE_ADDR + TOP_DARJEELING_PINMUX_AON_SIZE_BYTES.

Definition at line 283 of file top_darjeeling.h.

◆ TOP_DARJEELING_PWRMGR_AON_BASE_ADDR

#define TOP_DARJEELING_PWRMGR_AON_BASE_ADDR 0x30400000u

Peripheral base address for pwrmgr_aon in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 219 of file top_darjeeling.h.

◆ TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES

#define TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES 0x80u

Peripheral size for pwrmgr_aon in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_PWRMGR_AON_BASE_ADDR and TOP_DARJEELING_PWRMGR_AON_BASE_ADDR + TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES.

Definition at line 229 of file top_darjeeling.h.

◆ TOP_DARJEELING_RAM_MAIN_BASE_ADDR

#define TOP_DARJEELING_RAM_MAIN_BASE_ADDR 0x10000000u

Memory base address for ram_main in top darjeeling.

Definition at line 993 of file top_darjeeling.h.

◆ TOP_DARJEELING_RAM_MAIN_SIZE_BYTES

#define TOP_DARJEELING_RAM_MAIN_SIZE_BYTES 0x10000u

Memory size for ram_main in top darjeeling.

Definition at line 998 of file top_darjeeling.h.

◆ TOP_DARJEELING_RAM_MBOX_BASE_ADDR

#define TOP_DARJEELING_RAM_MBOX_BASE_ADDR 0x11000000u

Memory base address for ram_mbox in top darjeeling.

Definition at line 1003 of file top_darjeeling.h.

◆ TOP_DARJEELING_RAM_MBOX_SIZE_BYTES

#define TOP_DARJEELING_RAM_MBOX_SIZE_BYTES 0x1000u

Memory size for ram_mbox in top darjeeling.

Definition at line 1008 of file top_darjeeling.h.

◆ TOP_DARJEELING_RAM_RET_AON_BASE_ADDR

#define TOP_DARJEELING_RAM_RET_AON_BASE_ADDR 0x30600000u

Memory base address for ram_ret_aon in top darjeeling.

Definition at line 983 of file top_darjeeling.h.

◆ TOP_DARJEELING_RAM_RET_AON_SIZE_BYTES

#define TOP_DARJEELING_RAM_RET_AON_SIZE_BYTES 0x1000u

Memory size for ram_ret_aon in top darjeeling.

Definition at line 988 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM0_BASE_ADDR

#define TOP_DARJEELING_ROM0_BASE_ADDR 0x8000u

Memory base address for rom0 in top darjeeling.

Definition at line 1013 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM0_SIZE_BYTES

#define TOP_DARJEELING_ROM0_SIZE_BYTES 0x8000u

Memory size for rom0 in top darjeeling.

Definition at line 1018 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM1_BASE_ADDR

#define TOP_DARJEELING_ROM1_BASE_ADDR 0x20000u

Memory base address for rom1 in top darjeeling.

Definition at line 1023 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM1_SIZE_BYTES

#define TOP_DARJEELING_ROM1_SIZE_BYTES 0x10000u

Memory size for rom1 in top darjeeling.

Definition at line 1028 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR

#define TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR 0x211E0000u

Peripheral base address for regs device on rom_ctrl0 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 669 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES

#define TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES 0x80u

Peripheral size for regs device on rom_ctrl0 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR and TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR + TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES.

Definition at line 679 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR

#define TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR 0x8000u

Peripheral base address for rom device on rom_ctrl0 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 687 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES

#define TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES 0x8000u

Peripheral size for rom device on rom_ctrl0 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR and TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR + TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES.

Definition at line 697 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR

#define TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR 0x211E1000u

Peripheral base address for regs device on rom_ctrl1 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 705 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES

#define TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES 0x80u

Peripheral size for regs device on rom_ctrl1 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR and TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR + TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES.

Definition at line 715 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR

#define TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR 0x20000u

Peripheral base address for rom device on rom_ctrl1 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 723 of file top_darjeeling.h.

◆ TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES

#define TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES 0x10000u

Peripheral size for rom device on rom_ctrl1 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR and TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR + TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES.

Definition at line 733 of file top_darjeeling.h.

◆ TOP_DARJEELING_RSTMGR_AON_BASE_ADDR

#define TOP_DARJEELING_RSTMGR_AON_BASE_ADDR 0x30410000u

Peripheral base address for rstmgr_aon in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 237 of file top_darjeeling.h.

◆ TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES

#define TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES 0x80u

Peripheral size for rstmgr_aon in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_RSTMGR_AON_BASE_ADDR and TOP_DARJEELING_RSTMGR_AON_BASE_ADDR + TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES.

Definition at line 247 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR

#define TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR 0x211F0000u

Peripheral base address for cfg device on rv_core_ibex in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 957 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES

#define TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES 0x800u

Peripheral size for cfg device on rv_core_ibex in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR and TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES.

Definition at line 967 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_DM_MEM_BASE_ADDR

#define TOP_DARJEELING_RV_DM_MEM_BASE_ADDR 0x40000u

Peripheral base address for mem device on rv_dm in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 417 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES

#define TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES 0x1000u

Peripheral size for mem device on rv_dm in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_RV_DM_MEM_BASE_ADDR and TOP_DARJEELING_RV_DM_MEM_BASE_ADDR + TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES.

Definition at line 427 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_DM_REGS_BASE_ADDR

#define TOP_DARJEELING_RV_DM_REGS_BASE_ADDR 0x21200000u

Peripheral base address for regs device on rv_dm in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 399 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES

#define TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES 0x10u

Peripheral size for regs device on rv_dm in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_RV_DM_REGS_BASE_ADDR and TOP_DARJEELING_RV_DM_REGS_BASE_ADDR + TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES.

Definition at line 409 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_PLIC_BASE_ADDR

#define TOP_DARJEELING_RV_PLIC_BASE_ADDR 0x28000000u

Peripheral base address for rv_plic in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 435 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_PLIC_SIZE_BYTES

#define TOP_DARJEELING_RV_PLIC_SIZE_BYTES 0x8000000u

Peripheral size for rv_plic in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_RV_PLIC_BASE_ADDR and TOP_DARJEELING_RV_PLIC_BASE_ADDR + TOP_DARJEELING_RV_PLIC_SIZE_BYTES.

Definition at line 445 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_TIMER_BASE_ADDR

#define TOP_DARJEELING_RV_TIMER_BASE_ADDR 0x30100000u

Peripheral base address for rv_timer in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 111 of file top_darjeeling.h.

◆ TOP_DARJEELING_RV_TIMER_SIZE_BYTES

#define TOP_DARJEELING_RV_TIMER_SIZE_BYTES 0x200u

Peripheral size for rv_timer in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_RV_TIMER_BASE_ADDR and TOP_DARJEELING_RV_TIMER_BASE_ADDR + TOP_DARJEELING_RV_TIMER_SIZE_BYTES.

Definition at line 121 of file top_darjeeling.h.

◆ TOP_DARJEELING_SOC_DBG_CTRL_CORE_BASE_ADDR

#define TOP_DARJEELING_SOC_DBG_CTRL_CORE_BASE_ADDR 0x30170000u

Peripheral base address for core device on soc_dbg_ctrl in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 939 of file top_darjeeling.h.

◆ TOP_DARJEELING_SOC_DBG_CTRL_CORE_SIZE_BYTES

#define TOP_DARJEELING_SOC_DBG_CTRL_CORE_SIZE_BYTES 0x20u

Peripheral size for core device on soc_dbg_ctrl in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SOC_DBG_CTRL_CORE_BASE_ADDR and TOP_DARJEELING_SOC_DBG_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_SOC_DBG_CTRL_CORE_SIZE_BYTES.

Definition at line 949 of file top_darjeeling.h.

◆ TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR

#define TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR 0x22030000u

Peripheral base address for core device on soc_proxy in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 327 of file top_darjeeling.h.

◆ TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES

#define TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES 0x10u

Peripheral size for core device on soc_proxy in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR and TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES.

Definition at line 337 of file top_darjeeling.h.

◆ TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR

#define TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR 0x40000000u

Peripheral base address for ctn device on soc_proxy in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 345 of file top_darjeeling.h.

◆ TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES

#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x40000000u

Peripheral size for ctn device on soc_proxy in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR and TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES.

Definition at line 355 of file top_darjeeling.h.

◆ TOP_DARJEELING_SPI_DEVICE_BASE_ADDR

#define TOP_DARJEELING_SPI_DEVICE_BASE_ADDR 0x30310000u

Peripheral base address for spi_device in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 75 of file top_darjeeling.h.

◆ TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES

#define TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES 0x2000u

Peripheral size for spi_device in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SPI_DEVICE_BASE_ADDR and TOP_DARJEELING_SPI_DEVICE_BASE_ADDR + TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES.

Definition at line 85 of file top_darjeeling.h.

◆ TOP_DARJEELING_SPI_HOST0_BASE_ADDR

#define TOP_DARJEELING_SPI_HOST0_BASE_ADDR 0x30300000u

Peripheral base address for spi_host0 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 201 of file top_darjeeling.h.

◆ TOP_DARJEELING_SPI_HOST0_SIZE_BYTES

#define TOP_DARJEELING_SPI_HOST0_SIZE_BYTES 0x40u

Peripheral size for spi_host0 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SPI_HOST0_BASE_ADDR and TOP_DARJEELING_SPI_HOST0_BASE_ADDR + TOP_DARJEELING_SPI_HOST0_SIZE_BYTES.

Definition at line 211 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR

#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u

Peripheral base address for ram device on sram_ctrl_main in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 615 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES

#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x10000u

Peripheral size for ram device on sram_ctrl_main in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR and TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES.

Definition at line 625 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR

#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x211C0000u

Peripheral base address for regs device on sram_ctrl_main in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 597 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES

#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u

Peripheral size for regs device on sram_ctrl_main in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR and TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES.

Definition at line 607 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR

#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR 0x11000000u

Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 651 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES

#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES 0x1000u

Peripheral size for ram device on sram_ctrl_mbox in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR and TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES.

Definition at line 661 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR

#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR 0x211D0000u

Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 633 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES

#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES 0x40u

Peripheral size for regs device on sram_ctrl_mbox in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR and TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES.

Definition at line 643 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR

#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x30600000u

Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 381 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES

#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u

Peripheral size for ram device on sram_ctrl_ret_aon in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES.

Definition at line 391 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR

#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x30500000u

Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 363 of file top_darjeeling.h.

◆ TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES

#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u

Peripheral size for regs device on sram_ctrl_ret_aon in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES.

Definition at line 373 of file top_darjeeling.h.

◆ TOP_DARJEELING_UART0_BASE_ADDR

#define TOP_DARJEELING_UART0_BASE_ADDR 0x30010000u

Peripheral base address for uart0 in top darjeeling.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 39 of file top_darjeeling.h.

◆ TOP_DARJEELING_UART0_SIZE_BYTES

#define TOP_DARJEELING_UART0_SIZE_BYTES 0x40u

Peripheral size for uart0 in top darjeeling.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_DARJEELING_UART0_BASE_ADDR and TOP_DARJEELING_UART0_BASE_ADDR + TOP_DARJEELING_UART0_SIZE_BYTES.

Definition at line 49 of file top_darjeeling.h.

Typedef Documentation

◆ top_darjeeling_alert_id_t

typedef enum top_darjeeling_alert_id top_darjeeling_alert_id_t

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

◆ top_darjeeling_alert_peripheral_t

typedef enum top_darjeeling_alert_peripheral top_darjeeling_alert_peripheral_t

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

◆ top_darjeeling_gateable_clocks_t

typedef enum top_darjeeling_gateable_clocks top_darjeeling_gateable_clocks_t

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

◆ top_darjeeling_hintable_clocks_t

typedef enum top_darjeeling_hintable_clocks top_darjeeling_hintable_clocks_t

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

◆ top_darjeeling_plic_irq_id_t

typedef enum top_darjeeling_plic_irq_id top_darjeeling_plic_irq_id_t

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

◆ top_darjeeling_plic_peripheral_t

typedef enum top_darjeeling_plic_peripheral top_darjeeling_plic_peripheral_t

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

◆ top_darjeeling_plic_target_t

typedef enum top_darjeeling_plic_target top_darjeeling_plic_target_t

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumeration Type Documentation

◆ top_darjeeling_alert_id

enum top_darjeeling_alert_id

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopDarjeelingAlertIdUart0FatalFault	uart0_fatal_fault
kTopDarjeelingAlertIdGpioFatalFault	gpio_fatal_fault
kTopDarjeelingAlertIdSpiDeviceFatalFault	spi_device_fatal_fault
kTopDarjeelingAlertIdI2c0FatalFault	i2c0_fatal_fault
kTopDarjeelingAlertIdRvTimerFatalFault	rv_timer_fatal_fault
kTopDarjeelingAlertIdOtpCtrlFatalMacroError	otp_ctrl_fatal_macro_error
kTopDarjeelingAlertIdOtpCtrlFatalCheckError	otp_ctrl_fatal_check_error
kTopDarjeelingAlertIdOtpCtrlFatalBusIntegError	otp_ctrl_fatal_bus_integ_error
kTopDarjeelingAlertIdOtpCtrlFatalPrimOtpAlert	otp_ctrl_fatal_prim_otp_alert
kTopDarjeelingAlertIdOtpCtrlRecovPrimOtpAlert	otp_ctrl_recov_prim_otp_alert
kTopDarjeelingAlertIdLcCtrlFatalProgError	lc_ctrl_fatal_prog_error
kTopDarjeelingAlertIdLcCtrlFatalStateError	lc_ctrl_fatal_state_error
kTopDarjeelingAlertIdLcCtrlFatalBusIntegError	lc_ctrl_fatal_bus_integ_error
kTopDarjeelingAlertIdSpiHost0FatalFault	spi_host0_fatal_fault
kTopDarjeelingAlertIdPwrmgrAonFatalFault	pwrmgr_aon_fatal_fault
kTopDarjeelingAlertIdRstmgrAonFatalFault	rstmgr_aon_fatal_fault
kTopDarjeelingAlertIdRstmgrAonFatalCnstyFault	rstmgr_aon_fatal_cnsty_fault
kTopDarjeelingAlertIdClkmgrAonRecovFault	clkmgr_aon_recov_fault
kTopDarjeelingAlertIdClkmgrAonFatalFault	clkmgr_aon_fatal_fault
kTopDarjeelingAlertIdPinmuxAonFatalFault	pinmux_aon_fatal_fault
kTopDarjeelingAlertIdAonTimerAonFatalFault	aon_timer_aon_fatal_fault
kTopDarjeelingAlertIdSocProxyFatalAlertIntg	soc_proxy_fatal_alert_intg
kTopDarjeelingAlertIdSocProxyFatalAlertExternal0	soc_proxy_fatal_alert_external_0
kTopDarjeelingAlertIdSocProxyFatalAlertExternal1	soc_proxy_fatal_alert_external_1
kTopDarjeelingAlertIdSocProxyFatalAlertExternal2	soc_proxy_fatal_alert_external_2
kTopDarjeelingAlertIdSocProxyFatalAlertExternal3	soc_proxy_fatal_alert_external_3
kTopDarjeelingAlertIdSocProxyFatalAlertExternal4	soc_proxy_fatal_alert_external_4
kTopDarjeelingAlertIdSocProxyFatalAlertExternal5	soc_proxy_fatal_alert_external_5
kTopDarjeelingAlertIdSocProxyFatalAlertExternal6	soc_proxy_fatal_alert_external_6
kTopDarjeelingAlertIdSocProxyFatalAlertExternal7	soc_proxy_fatal_alert_external_7
kTopDarjeelingAlertIdSocProxyFatalAlertExternal8	soc_proxy_fatal_alert_external_8
kTopDarjeelingAlertIdSocProxyFatalAlertExternal9	soc_proxy_fatal_alert_external_9
kTopDarjeelingAlertIdSocProxyFatalAlertExternal10	soc_proxy_fatal_alert_external_10
kTopDarjeelingAlertIdSocProxyFatalAlertExternal11	soc_proxy_fatal_alert_external_11
kTopDarjeelingAlertIdSocProxyFatalAlertExternal12	soc_proxy_fatal_alert_external_12
kTopDarjeelingAlertIdSocProxyFatalAlertExternal13	soc_proxy_fatal_alert_external_13
kTopDarjeelingAlertIdSocProxyFatalAlertExternal14	soc_proxy_fatal_alert_external_14
kTopDarjeelingAlertIdSocProxyFatalAlertExternal15	soc_proxy_fatal_alert_external_15
kTopDarjeelingAlertIdSocProxyFatalAlertExternal16	soc_proxy_fatal_alert_external_16
kTopDarjeelingAlertIdSocProxyFatalAlertExternal17	soc_proxy_fatal_alert_external_17
kTopDarjeelingAlertIdSocProxyFatalAlertExternal18	soc_proxy_fatal_alert_external_18
kTopDarjeelingAlertIdSocProxyFatalAlertExternal19	soc_proxy_fatal_alert_external_19
kTopDarjeelingAlertIdSocProxyFatalAlertExternal20	soc_proxy_fatal_alert_external_20
kTopDarjeelingAlertIdSocProxyFatalAlertExternal21	soc_proxy_fatal_alert_external_21
kTopDarjeelingAlertIdSocProxyFatalAlertExternal22	soc_proxy_fatal_alert_external_22
kTopDarjeelingAlertIdSocProxyFatalAlertExternal23	soc_proxy_fatal_alert_external_23
kTopDarjeelingAlertIdSocProxyRecovAlertExternal0	soc_proxy_recov_alert_external_0
kTopDarjeelingAlertIdSocProxyRecovAlertExternal1	soc_proxy_recov_alert_external_1
kTopDarjeelingAlertIdSocProxyRecovAlertExternal2	soc_proxy_recov_alert_external_2
kTopDarjeelingAlertIdSocProxyRecovAlertExternal3	soc_proxy_recov_alert_external_3
kTopDarjeelingAlertIdSramCtrlRetAonFatalError	sram_ctrl_ret_aon_fatal_error
kTopDarjeelingAlertIdRvDmFatalFault	rv_dm_fatal_fault
kTopDarjeelingAlertIdRvPlicFatalFault	rv_plic_fatal_fault
kTopDarjeelingAlertIdAesRecovCtrlUpdateErr	aes_recov_ctrl_update_err
kTopDarjeelingAlertIdAesFatalFault	aes_fatal_fault
kTopDarjeelingAlertIdHmacFatalFault	hmac_fatal_fault
kTopDarjeelingAlertIdKmacRecovOperationErr	kmac_recov_operation_err
kTopDarjeelingAlertIdKmacFatalFaultErr	kmac_fatal_fault_err
kTopDarjeelingAlertIdOtbnFatal	otbn_fatal
kTopDarjeelingAlertIdOtbnRecov	otbn_recov
kTopDarjeelingAlertIdKeymgrDpeRecovOperationErr	keymgr_dpe_recov_operation_err
kTopDarjeelingAlertIdKeymgrDpeFatalFaultErr	keymgr_dpe_fatal_fault_err
kTopDarjeelingAlertIdCsrngRecovAlert	csrng_recov_alert
kTopDarjeelingAlertIdCsrngFatalAlert	csrng_fatal_alert
kTopDarjeelingAlertIdEdn0RecovAlert	edn0_recov_alert
kTopDarjeelingAlertIdEdn0FatalAlert	edn0_fatal_alert
kTopDarjeelingAlertIdEdn1RecovAlert	edn1_recov_alert
kTopDarjeelingAlertIdEdn1FatalAlert	edn1_fatal_alert
kTopDarjeelingAlertIdSramCtrlMainFatalError	sram_ctrl_main_fatal_error
kTopDarjeelingAlertIdSramCtrlMboxFatalError	sram_ctrl_mbox_fatal_error
kTopDarjeelingAlertIdRomCtrl0Fatal	rom_ctrl0_fatal
kTopDarjeelingAlertIdRomCtrl1Fatal	rom_ctrl1_fatal
kTopDarjeelingAlertIdDmaFatalFault	dma_fatal_fault
kTopDarjeelingAlertIdMbx0FatalFault	mbx0_fatal_fault
kTopDarjeelingAlertIdMbx0RecovFault	mbx0_recov_fault
kTopDarjeelingAlertIdMbx1FatalFault	mbx1_fatal_fault
kTopDarjeelingAlertIdMbx1RecovFault	mbx1_recov_fault
kTopDarjeelingAlertIdMbx2FatalFault	mbx2_fatal_fault
kTopDarjeelingAlertIdMbx2RecovFault	mbx2_recov_fault
kTopDarjeelingAlertIdMbx3FatalFault	mbx3_fatal_fault
kTopDarjeelingAlertIdMbx3RecovFault	mbx3_recov_fault
kTopDarjeelingAlertIdMbx4FatalFault	mbx4_fatal_fault
kTopDarjeelingAlertIdMbx4RecovFault	mbx4_recov_fault
kTopDarjeelingAlertIdMbx5FatalFault	mbx5_fatal_fault
kTopDarjeelingAlertIdMbx5RecovFault	mbx5_recov_fault
kTopDarjeelingAlertIdMbx6FatalFault	mbx6_fatal_fault
kTopDarjeelingAlertIdMbx6RecovFault	mbx6_recov_fault
kTopDarjeelingAlertIdMbxJtagFatalFault	mbx_jtag_fatal_fault
kTopDarjeelingAlertIdMbxJtagRecovFault	mbx_jtag_recov_fault
kTopDarjeelingAlertIdMbxPcie0FatalFault	mbx_pcie0_fatal_fault
kTopDarjeelingAlertIdMbxPcie0RecovFault	mbx_pcie0_recov_fault
kTopDarjeelingAlertIdMbxPcie1FatalFault	mbx_pcie1_fatal_fault
kTopDarjeelingAlertIdMbxPcie1RecovFault	mbx_pcie1_recov_fault
kTopDarjeelingAlertIdSocDbgCtrlFatalFault	soc_dbg_ctrl_fatal_fault
kTopDarjeelingAlertIdSocDbgCtrlRecovCtrlUpdateErr	soc_dbg_ctrl_recov_ctrl_update_err
kTopDarjeelingAlertIdRaclCtrlFatalFault	racl_ctrl_fatal_fault
kTopDarjeelingAlertIdRaclCtrlRecovCtrlUpdateErr	racl_ctrl_recov_ctrl_update_err
kTopDarjeelingAlertIdAcRangeCheckRecovCtrlUpdateErr	ac_range_check_recov_ctrl_update_err
kTopDarjeelingAlertIdAcRangeCheckFatalFault	ac_range_check_fatal_fault
kTopDarjeelingAlertIdRvCoreIbexFatalSwErr	rv_core_ibex_fatal_sw_err
kTopDarjeelingAlertIdRvCoreIbexRecovSwErr	rv_core_ibex_recov_sw_err
kTopDarjeelingAlertIdRvCoreIbexFatalHwErr	rv_core_ibex_fatal_hw_err
kTopDarjeelingAlertIdRvCoreIbexRecovHwErr	rv_core_ibex_recov_hw_err

Definition at line 1324 of file top_darjeeling.h.

◆ top_darjeeling_alert_peripheral

enum top_darjeeling_alert_peripheral

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

Enumerator
kTopDarjeelingAlertPeripheralExternal	External Peripheral.
kTopDarjeelingAlertPeripheralUart0	uart0
kTopDarjeelingAlertPeripheralGpio	gpio
kTopDarjeelingAlertPeripheralSpiDevice	spi_device
kTopDarjeelingAlertPeripheralI2c0	i2c0
kTopDarjeelingAlertPeripheralRvTimer	rv_timer
kTopDarjeelingAlertPeripheralOtpCtrl	otp_ctrl
kTopDarjeelingAlertPeripheralLcCtrl	lc_ctrl
kTopDarjeelingAlertPeripheralSpiHost0	spi_host0
kTopDarjeelingAlertPeripheralPwrmgrAon	pwrmgr_aon
kTopDarjeelingAlertPeripheralRstmgrAon	rstmgr_aon
kTopDarjeelingAlertPeripheralClkmgrAon	clkmgr_aon
kTopDarjeelingAlertPeripheralPinmuxAon	pinmux_aon
kTopDarjeelingAlertPeripheralAonTimerAon	aon_timer_aon
kTopDarjeelingAlertPeripheralSocProxy	soc_proxy
kTopDarjeelingAlertPeripheralSramCtrlRetAon	sram_ctrl_ret_aon
kTopDarjeelingAlertPeripheralRvDm	rv_dm
kTopDarjeelingAlertPeripheralRvPlic	rv_plic
kTopDarjeelingAlertPeripheralAes	aes
kTopDarjeelingAlertPeripheralHmac	hmac
kTopDarjeelingAlertPeripheralKmac	kmac
kTopDarjeelingAlertPeripheralOtbn	otbn
kTopDarjeelingAlertPeripheralKeymgrDpe	keymgr_dpe
kTopDarjeelingAlertPeripheralCsrng	csrng
kTopDarjeelingAlertPeripheralEdn0	edn0
kTopDarjeelingAlertPeripheralEdn1	edn1
kTopDarjeelingAlertPeripheralSramCtrlMain	sram_ctrl_main
kTopDarjeelingAlertPeripheralSramCtrlMbox	sram_ctrl_mbox
kTopDarjeelingAlertPeripheralRomCtrl0	rom_ctrl0
kTopDarjeelingAlertPeripheralRomCtrl1	rom_ctrl1
kTopDarjeelingAlertPeripheralDma	dma
kTopDarjeelingAlertPeripheralMbx0	mbx0
kTopDarjeelingAlertPeripheralMbx1	mbx1
kTopDarjeelingAlertPeripheralMbx2	mbx2
kTopDarjeelingAlertPeripheralMbx3	mbx3
kTopDarjeelingAlertPeripheralMbx4	mbx4
kTopDarjeelingAlertPeripheralMbx5	mbx5
kTopDarjeelingAlertPeripheralMbx6	mbx6
kTopDarjeelingAlertPeripheralMbxJtag	mbx_jtag
kTopDarjeelingAlertPeripheralMbxPcie0	mbx_pcie0
kTopDarjeelingAlertPeripheralMbxPcie1	mbx_pcie1
kTopDarjeelingAlertPeripheralSocDbgCtrl	soc_dbg_ctrl
kTopDarjeelingAlertPeripheralRaclCtrl	racl_ctrl
kTopDarjeelingAlertPeripheralAcRangeCheck	ac_range_check
kTopDarjeelingAlertPeripheralRvCoreIbex	rv_core_ibex

Definition at line 1269 of file top_darjeeling.h.

◆ top_darjeeling_direct_pads

enum top_darjeeling_direct_pads

Dedicated Pad Selects.

Definition at line 1518 of file top_darjeeling.h.

◆ top_darjeeling_gateable_clocks

enum top_darjeeling_gateable_clocks

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

Enumerator
kTopDarjeelingGateableClocksIoDiv4Peri	Clock clk_io_div4_peri in group peri.
kTopDarjeelingGateableClocksIoDiv2Peri	Clock clk_io_div2_peri in group peri.

Definition at line 1649 of file top_darjeeling.h.

◆ top_darjeeling_hintable_clocks

enum top_darjeeling_hintable_clocks

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

Enumerator
kTopDarjeelingHintableClocksMainAes	Clock clk_main_aes in group trans.
kTopDarjeelingHintableClocksMainHmac	Clock clk_main_hmac in group trans.
kTopDarjeelingHintableClocksMainKmac	Clock clk_main_kmac in group trans.
kTopDarjeelingHintableClocksMainOtbn	Clock clk_main_otbn in group trans.

Definition at line 1661 of file top_darjeeling.h.

◆ top_darjeeling_muxed_pads

enum top_darjeeling_muxed_pads

Muxed Pad Selects.

Definition at line 1598 of file top_darjeeling.h.

◆ top_darjeeling_pinmux_insel

enum top_darjeeling_pinmux_insel

Pinmux MIO Input Selector.

Enumerator
kTopDarjeelingPinmuxInselConstantZero	Tie constantly to zero.
kTopDarjeelingPinmuxInselConstantOne	Tie constantly to one.
kTopDarjeelingPinmuxInselMio0	MIO Pad 0.
kTopDarjeelingPinmuxInselMio1	MIO Pad 1.
kTopDarjeelingPinmuxInselMio2	MIO Pad 2.
kTopDarjeelingPinmuxInselMio3	MIO Pad 3.
kTopDarjeelingPinmuxInselMio4	MIO Pad 4.
kTopDarjeelingPinmuxInselMio5	MIO Pad 5.
kTopDarjeelingPinmuxInselMio6	MIO Pad 6.
kTopDarjeelingPinmuxInselMio7	MIO Pad 7.
kTopDarjeelingPinmuxInselMio8	MIO Pad 8.
kTopDarjeelingPinmuxInselMio9	MIO Pad 9.
kTopDarjeelingPinmuxInselMio10	MIO Pad 10.
kTopDarjeelingPinmuxInselMio11	MIO Pad 11.

Definition at line 1463 of file top_darjeeling.h.

◆ top_darjeeling_pinmux_mio_out

enum top_darjeeling_pinmux_mio_out

Pinmux MIO Output.

Enumerator
kTopDarjeelingPinmuxMioOutMio0	MIO Pad 0.
kTopDarjeelingPinmuxMioOutMio1	MIO Pad 1.
kTopDarjeelingPinmuxMioOutMio2	MIO Pad 2.
kTopDarjeelingPinmuxMioOutMio3	MIO Pad 3.
kTopDarjeelingPinmuxMioOutMio4	MIO Pad 4.
kTopDarjeelingPinmuxMioOutMio5	MIO Pad 5.
kTopDarjeelingPinmuxMioOutMio6	MIO Pad 6.
kTopDarjeelingPinmuxMioOutMio7	MIO Pad 7.
kTopDarjeelingPinmuxMioOutMio8	MIO Pad 8.
kTopDarjeelingPinmuxMioOutMio9	MIO Pad 9.
kTopDarjeelingPinmuxMioOutMio10	MIO Pad 10.
kTopDarjeelingPinmuxMioOutMio11	MIO Pad 11.

Definition at line 1484 of file top_darjeeling.h.

◆ top_darjeeling_pinmux_outsel

enum top_darjeeling_pinmux_outsel

Pinmux Peripheral Output Selector.

Enumerator
kTopDarjeelingPinmuxOutselConstantZero	Tie constantly to zero.
kTopDarjeelingPinmuxOutselConstantOne	Tie constantly to one.
kTopDarjeelingPinmuxOutselConstantHighZ	Tie constantly to high-Z.
kTopDarjeelingPinmuxOutselSocProxySocGpo12	Peripheral Output 0.
kTopDarjeelingPinmuxOutselSocProxySocGpo13	Peripheral Output 1.
kTopDarjeelingPinmuxOutselSocProxySocGpo14	Peripheral Output 2.
kTopDarjeelingPinmuxOutselSocProxySocGpo15	Peripheral Output 3.
kTopDarjeelingPinmuxOutselOtpMacroTest0	Peripheral Output 4.

Definition at line 1503 of file top_darjeeling.h.

◆ top_darjeeling_pinmux_peripheral_in

enum top_darjeeling_pinmux_peripheral_in

Pinmux Peripheral Input.

Enumerator
kTopDarjeelingPinmuxPeripheralInSocProxySocGpi12	Peripheral Input 0.
kTopDarjeelingPinmuxPeripheralInSocProxySocGpi13	Peripheral Input 1.
kTopDarjeelingPinmuxPeripheralInSocProxySocGpi14	Peripheral Input 2.
kTopDarjeelingPinmuxPeripheralInSocProxySocGpi15	Peripheral Input 3.

Definition at line 1452 of file top_darjeeling.h.

◆ top_darjeeling_plic_irq_id

enum top_darjeeling_plic_irq_id

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopDarjeelingPlicIrqIdNone	No Interrupt.
kTopDarjeelingPlicIrqIdUart0TxWatermark	uart0_tx_watermark
kTopDarjeelingPlicIrqIdUart0RxWatermark	uart0_rx_watermark
kTopDarjeelingPlicIrqIdUart0TxDone	uart0_tx_done
kTopDarjeelingPlicIrqIdUart0RxOverflow	uart0_rx_overflow
kTopDarjeelingPlicIrqIdUart0RxFrameErr	uart0_rx_frame_err
kTopDarjeelingPlicIrqIdUart0RxBreakErr	uart0_rx_break_err
kTopDarjeelingPlicIrqIdUart0RxTimeout	uart0_rx_timeout
kTopDarjeelingPlicIrqIdUart0RxParityErr	uart0_rx_parity_err
kTopDarjeelingPlicIrqIdUart0TxEmpty	uart0_tx_empty
kTopDarjeelingPlicIrqIdGpioGpio0	gpio_gpio 0
kTopDarjeelingPlicIrqIdGpioGpio1	gpio_gpio 1
kTopDarjeelingPlicIrqIdGpioGpio2	gpio_gpio 2
kTopDarjeelingPlicIrqIdGpioGpio3	gpio_gpio 3
kTopDarjeelingPlicIrqIdGpioGpio4	gpio_gpio 4
kTopDarjeelingPlicIrqIdGpioGpio5	gpio_gpio 5
kTopDarjeelingPlicIrqIdGpioGpio6	gpio_gpio 6
kTopDarjeelingPlicIrqIdGpioGpio7	gpio_gpio 7
kTopDarjeelingPlicIrqIdGpioGpio8	gpio_gpio 8
kTopDarjeelingPlicIrqIdGpioGpio9	gpio_gpio 9
kTopDarjeelingPlicIrqIdGpioGpio10	gpio_gpio 10
kTopDarjeelingPlicIrqIdGpioGpio11	gpio_gpio 11
kTopDarjeelingPlicIrqIdGpioGpio12	gpio_gpio 12
kTopDarjeelingPlicIrqIdGpioGpio13	gpio_gpio 13
kTopDarjeelingPlicIrqIdGpioGpio14	gpio_gpio 14
kTopDarjeelingPlicIrqIdGpioGpio15	gpio_gpio 15
kTopDarjeelingPlicIrqIdGpioGpio16	gpio_gpio 16
kTopDarjeelingPlicIrqIdGpioGpio17	gpio_gpio 17
kTopDarjeelingPlicIrqIdGpioGpio18	gpio_gpio 18
kTopDarjeelingPlicIrqIdGpioGpio19	gpio_gpio 19
kTopDarjeelingPlicIrqIdGpioGpio20	gpio_gpio 20
kTopDarjeelingPlicIrqIdGpioGpio21	gpio_gpio 21
kTopDarjeelingPlicIrqIdGpioGpio22	gpio_gpio 22
kTopDarjeelingPlicIrqIdGpioGpio23	gpio_gpio 23
kTopDarjeelingPlicIrqIdGpioGpio24	gpio_gpio 24
kTopDarjeelingPlicIrqIdGpioGpio25	gpio_gpio 25
kTopDarjeelingPlicIrqIdGpioGpio26	gpio_gpio 26
kTopDarjeelingPlicIrqIdGpioGpio27	gpio_gpio 27
kTopDarjeelingPlicIrqIdGpioGpio28	gpio_gpio 28
kTopDarjeelingPlicIrqIdGpioGpio29	gpio_gpio 29
kTopDarjeelingPlicIrqIdGpioGpio30	gpio_gpio 30
kTopDarjeelingPlicIrqIdGpioGpio31	gpio_gpio 31
kTopDarjeelingPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty	spi_device_upload_cmdfifo_not_empty
kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadNotEmpty	spi_device_upload_payload_not_empty
kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadOverflow	spi_device_upload_payload_overflow
kTopDarjeelingPlicIrqIdSpiDeviceReadbufWatermark	spi_device_readbuf_watermark
kTopDarjeelingPlicIrqIdSpiDeviceReadbufFlip	spi_device_readbuf_flip
kTopDarjeelingPlicIrqIdSpiDeviceTpmHeaderNotEmpty	spi_device_tpm_header_not_empty
kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoCmdEnd	spi_device_tpm_rdfifo_cmd_end
kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoDrop	spi_device_tpm_rdfifo_drop
kTopDarjeelingPlicIrqIdI2c0FmtThreshold	i2c0_fmt_threshold
kTopDarjeelingPlicIrqIdI2c0RxThreshold	i2c0_rx_threshold
kTopDarjeelingPlicIrqIdI2c0AcqThreshold	i2c0_acq_threshold
kTopDarjeelingPlicIrqIdI2c0RxOverflow	i2c0_rx_overflow
kTopDarjeelingPlicIrqIdI2c0ControllerHalt	i2c0_controller_halt
kTopDarjeelingPlicIrqIdI2c0SclInterference	i2c0_scl_interference
kTopDarjeelingPlicIrqIdI2c0SdaInterference	i2c0_sda_interference
kTopDarjeelingPlicIrqIdI2c0StretchTimeout	i2c0_stretch_timeout
kTopDarjeelingPlicIrqIdI2c0SdaUnstable	i2c0_sda_unstable
kTopDarjeelingPlicIrqIdI2c0CmdComplete	i2c0_cmd_complete
kTopDarjeelingPlicIrqIdI2c0TxStretch	i2c0_tx_stretch
kTopDarjeelingPlicIrqIdI2c0TxThreshold	i2c0_tx_threshold
kTopDarjeelingPlicIrqIdI2c0AcqStretch	i2c0_acq_stretch
kTopDarjeelingPlicIrqIdI2c0UnexpStop	i2c0_unexp_stop
kTopDarjeelingPlicIrqIdI2c0HostTimeout	i2c0_host_timeout
kTopDarjeelingPlicIrqIdRvTimerTimerExpiredHart0Timer0	rv_timer_timer_expired_hart0_timer0
kTopDarjeelingPlicIrqIdOtpCtrlOtpOperationDone	otp_ctrl_otp_operation_done
kTopDarjeelingPlicIrqIdOtpCtrlOtpError	otp_ctrl_otp_error
kTopDarjeelingPlicIrqIdAlertHandlerClassa	alert_handler_classa
kTopDarjeelingPlicIrqIdAlertHandlerClassb	alert_handler_classb
kTopDarjeelingPlicIrqIdAlertHandlerClassc	alert_handler_classc
kTopDarjeelingPlicIrqIdAlertHandlerClassd	alert_handler_classd
kTopDarjeelingPlicIrqIdSpiHost0Error	spi_host0_error
kTopDarjeelingPlicIrqIdSpiHost0SpiEvent	spi_host0_spi_event
kTopDarjeelingPlicIrqIdPwrmgrAonWakeup	pwrmgr_aon_wakeup
kTopDarjeelingPlicIrqIdAonTimerAonWkupTimerExpired	aon_timer_aon_wkup_timer_expired
kTopDarjeelingPlicIrqIdAonTimerAonWdogTimerBark	aon_timer_aon_wdog_timer_bark
kTopDarjeelingPlicIrqIdSocProxyExternal0	soc_proxy_external 0
kTopDarjeelingPlicIrqIdSocProxyExternal1	soc_proxy_external 1
kTopDarjeelingPlicIrqIdSocProxyExternal2	soc_proxy_external 2
kTopDarjeelingPlicIrqIdSocProxyExternal3	soc_proxy_external 3
kTopDarjeelingPlicIrqIdSocProxyExternal4	soc_proxy_external 4
kTopDarjeelingPlicIrqIdSocProxyExternal5	soc_proxy_external 5
kTopDarjeelingPlicIrqIdSocProxyExternal6	soc_proxy_external 6
kTopDarjeelingPlicIrqIdSocProxyExternal7	soc_proxy_external 7
kTopDarjeelingPlicIrqIdSocProxyExternal8	soc_proxy_external 8
kTopDarjeelingPlicIrqIdSocProxyExternal9	soc_proxy_external 9
kTopDarjeelingPlicIrqIdSocProxyExternal10	soc_proxy_external 10
kTopDarjeelingPlicIrqIdSocProxyExternal11	soc_proxy_external 11
kTopDarjeelingPlicIrqIdSocProxyExternal12	soc_proxy_external 12
kTopDarjeelingPlicIrqIdSocProxyExternal13	soc_proxy_external 13
kTopDarjeelingPlicIrqIdSocProxyExternal14	soc_proxy_external 14
kTopDarjeelingPlicIrqIdSocProxyExternal15	soc_proxy_external 15
kTopDarjeelingPlicIrqIdSocProxyExternal16	soc_proxy_external 16
kTopDarjeelingPlicIrqIdSocProxyExternal17	soc_proxy_external 17
kTopDarjeelingPlicIrqIdSocProxyExternal18	soc_proxy_external 18
kTopDarjeelingPlicIrqIdSocProxyExternal19	soc_proxy_external 19
kTopDarjeelingPlicIrqIdSocProxyExternal20	soc_proxy_external 20
kTopDarjeelingPlicIrqIdSocProxyExternal21	soc_proxy_external 21
kTopDarjeelingPlicIrqIdSocProxyExternal22	soc_proxy_external 22
kTopDarjeelingPlicIrqIdSocProxyExternal23	soc_proxy_external 23
kTopDarjeelingPlicIrqIdSocProxyExternal24	soc_proxy_external 24
kTopDarjeelingPlicIrqIdSocProxyExternal25	soc_proxy_external 25
kTopDarjeelingPlicIrqIdSocProxyExternal26	soc_proxy_external 26
kTopDarjeelingPlicIrqIdSocProxyExternal27	soc_proxy_external 27
kTopDarjeelingPlicIrqIdSocProxyExternal28	soc_proxy_external 28
kTopDarjeelingPlicIrqIdSocProxyExternal29	soc_proxy_external 29
kTopDarjeelingPlicIrqIdSocProxyExternal30	soc_proxy_external 30
kTopDarjeelingPlicIrqIdSocProxyExternal31	soc_proxy_external 31
kTopDarjeelingPlicIrqIdHmacHmacDone	hmac_hmac_done
kTopDarjeelingPlicIrqIdHmacFifoEmpty	hmac_fifo_empty
kTopDarjeelingPlicIrqIdHmacHmacErr	hmac_hmac_err
kTopDarjeelingPlicIrqIdKmacKmacDone	kmac_kmac_done
kTopDarjeelingPlicIrqIdKmacFifoEmpty	kmac_fifo_empty
kTopDarjeelingPlicIrqIdKmacKmacErr	kmac_kmac_err
kTopDarjeelingPlicIrqIdOtbnDone	otbn_done
kTopDarjeelingPlicIrqIdKeymgrDpeOpDone	keymgr_dpe_op_done
kTopDarjeelingPlicIrqIdCsrngCsCmdReqDone	csrng_cs_cmd_req_done
kTopDarjeelingPlicIrqIdCsrngCsEntropyReq	csrng_cs_entropy_req
kTopDarjeelingPlicIrqIdCsrngCsHwInstExc	csrng_cs_hw_inst_exc
kTopDarjeelingPlicIrqIdCsrngCsFatalErr	csrng_cs_fatal_err
kTopDarjeelingPlicIrqIdEdn0EdnCmdReqDone	edn0_edn_cmd_req_done
kTopDarjeelingPlicIrqIdEdn0EdnFatalErr	edn0_edn_fatal_err
kTopDarjeelingPlicIrqIdEdn1EdnCmdReqDone	edn1_edn_cmd_req_done
kTopDarjeelingPlicIrqIdEdn1EdnFatalErr	edn1_edn_fatal_err
kTopDarjeelingPlicIrqIdDmaDmaDone	dma_dma_done
kTopDarjeelingPlicIrqIdDmaDmaChunkDone	dma_dma_chunk_done
kTopDarjeelingPlicIrqIdDmaDmaError	dma_dma_error
kTopDarjeelingPlicIrqIdMbx0MbxReady	mbx0_mbx_ready
kTopDarjeelingPlicIrqIdMbx0MbxAbort	mbx0_mbx_abort
kTopDarjeelingPlicIrqIdMbx0MbxError	mbx0_mbx_error
kTopDarjeelingPlicIrqIdMbx1MbxReady	mbx1_mbx_ready
kTopDarjeelingPlicIrqIdMbx1MbxAbort	mbx1_mbx_abort
kTopDarjeelingPlicIrqIdMbx1MbxError	mbx1_mbx_error
kTopDarjeelingPlicIrqIdMbx2MbxReady	mbx2_mbx_ready
kTopDarjeelingPlicIrqIdMbx2MbxAbort	mbx2_mbx_abort
kTopDarjeelingPlicIrqIdMbx2MbxError	mbx2_mbx_error
kTopDarjeelingPlicIrqIdMbx3MbxReady	mbx3_mbx_ready
kTopDarjeelingPlicIrqIdMbx3MbxAbort	mbx3_mbx_abort
kTopDarjeelingPlicIrqIdMbx3MbxError	mbx3_mbx_error
kTopDarjeelingPlicIrqIdMbx4MbxReady	mbx4_mbx_ready
kTopDarjeelingPlicIrqIdMbx4MbxAbort	mbx4_mbx_abort
kTopDarjeelingPlicIrqIdMbx4MbxError	mbx4_mbx_error
kTopDarjeelingPlicIrqIdMbx5MbxReady	mbx5_mbx_ready
kTopDarjeelingPlicIrqIdMbx5MbxAbort	mbx5_mbx_abort
kTopDarjeelingPlicIrqIdMbx5MbxError	mbx5_mbx_error
kTopDarjeelingPlicIrqIdMbx6MbxReady	mbx6_mbx_ready
kTopDarjeelingPlicIrqIdMbx6MbxAbort	mbx6_mbx_abort
kTopDarjeelingPlicIrqIdMbx6MbxError	mbx6_mbx_error
kTopDarjeelingPlicIrqIdMbxJtagMbxReady	mbx_jtag_mbx_ready
kTopDarjeelingPlicIrqIdMbxJtagMbxAbort	mbx_jtag_mbx_abort
kTopDarjeelingPlicIrqIdMbxJtagMbxError	mbx_jtag_mbx_error
kTopDarjeelingPlicIrqIdMbxPcie0MbxReady	mbx_pcie0_mbx_ready
kTopDarjeelingPlicIrqIdMbxPcie0MbxAbort	mbx_pcie0_mbx_abort
kTopDarjeelingPlicIrqIdMbxPcie0MbxError	mbx_pcie0_mbx_error
kTopDarjeelingPlicIrqIdMbxPcie1MbxReady	mbx_pcie1_mbx_ready
kTopDarjeelingPlicIrqIdMbxPcie1MbxAbort	mbx_pcie1_mbx_abort
kTopDarjeelingPlicIrqIdMbxPcie1MbxError	mbx_pcie1_mbx_error
kTopDarjeelingPlicIrqIdRaclCtrlRaclError	racl_ctrl_racl_error
kTopDarjeelingPlicIrqIdAcRangeCheckDenyCntReached	ac_range_check_deny_cnt_reached

Definition at line 1079 of file top_darjeeling.h.

◆ top_darjeeling_plic_peripheral

enum top_darjeeling_plic_peripheral

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

Enumerator
kTopDarjeelingPlicPeripheralUnknown	Unknown Peripheral.
kTopDarjeelingPlicPeripheralUart0	uart0
kTopDarjeelingPlicPeripheralGpio	gpio
kTopDarjeelingPlicPeripheralSpiDevice	spi_device
kTopDarjeelingPlicPeripheralI2c0	i2c0
kTopDarjeelingPlicPeripheralRvTimer	rv_timer
kTopDarjeelingPlicPeripheralOtpCtrl	otp_ctrl
kTopDarjeelingPlicPeripheralAlertHandler	alert_handler
kTopDarjeelingPlicPeripheralSpiHost0	spi_host0
kTopDarjeelingPlicPeripheralPwrmgrAon	pwrmgr_aon
kTopDarjeelingPlicPeripheralAonTimerAon	aon_timer_aon
kTopDarjeelingPlicPeripheralSocProxy	soc_proxy
kTopDarjeelingPlicPeripheralHmac	hmac
kTopDarjeelingPlicPeripheralKmac	kmac
kTopDarjeelingPlicPeripheralOtbn	otbn
kTopDarjeelingPlicPeripheralKeymgrDpe	keymgr_dpe
kTopDarjeelingPlicPeripheralCsrng	csrng
kTopDarjeelingPlicPeripheralEdn0	edn0
kTopDarjeelingPlicPeripheralEdn1	edn1
kTopDarjeelingPlicPeripheralDma	dma
kTopDarjeelingPlicPeripheralMbx0	mbx0
kTopDarjeelingPlicPeripheralMbx1	mbx1
kTopDarjeelingPlicPeripheralMbx2	mbx2
kTopDarjeelingPlicPeripheralMbx3	mbx3
kTopDarjeelingPlicPeripheralMbx4	mbx4
kTopDarjeelingPlicPeripheralMbx5	mbx5
kTopDarjeelingPlicPeripheralMbx6	mbx6
kTopDarjeelingPlicPeripheralMbxJtag	mbx_jtag
kTopDarjeelingPlicPeripheralMbxPcie0	mbx_pcie0
kTopDarjeelingPlicPeripheralMbxPcie1	mbx_pcie1
kTopDarjeelingPlicPeripheralRaclCtrl	racl_ctrl
kTopDarjeelingPlicPeripheralAcRangeCheck	ac_range_check

Definition at line 1037 of file top_darjeeling.h.

◆ top_darjeeling_plic_target

enum top_darjeeling_plic_target

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumerator
kTopDarjeelingPlicTargetIbex0	Ibex Core 0.

Definition at line 1258 of file top_darjeeling.h.

◆ top_darjeeling_power_manager_reset_requests

enum top_darjeeling_power_manager_reset_requests

Power Manager Reset Request Signals.

Definition at line 1638 of file top_darjeeling.h.

◆ top_darjeeling_power_manager_wake_ups

enum top_darjeeling_power_manager_wake_ups

Power Manager Wakeup Signals.

Definition at line 1617 of file top_darjeeling.h.

◆ top_darjeeling_reset_manager_sw_resets

enum top_darjeeling_reset_manager_sw_resets

Reset Manager Software Controlled Resets.

Definition at line 1628 of file top_darjeeling.h.

Variable Documentation

◆ top_darjeeling_alert_for_peripheral

const top_darjeeling_alert_peripheral_t top_darjeeling_alert_for_peripheral[103]

extern

Alert Handler Alert Source to Peripheral Map.

This array is a mapping from top_darjeeling_alert_id_t to top_darjeeling_alert_peripheral_t.

Definition at line 19 of file top_darjeeling.c.

◆ top_darjeeling_plic_interrupt_for_peripheral

const top_darjeeling_plic_peripheral_t top_darjeeling_plic_interrupt_for_peripheral[160]

extern

PLIC Interrupt Source to Peripheral Map.

This array is a mapping from top_darjeeling_plic_irq_id_t to top_darjeeling_plic_peripheral_t.

Definition at line 132 of file top_darjeeling.c.

Macros

Typedefs

Enumerations

Variables

Detailed Description

Macro Definition Documentation

◆ NUM_DIO_PADS

◆ NUM_MIO_PADS

◆ PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET

◆ PINMUX_PERIPH_OUTSEL_IDX_OFFSET

◆ TOP_DARJEELING_AES_BASE_ADDR

◆ TOP_DARJEELING_AES_SIZE_BYTES

◆ TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR

◆ TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES

◆ TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR

◆ TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES

◆ TOP_DARJEELING_AST_BASE_ADDR

◆ TOP_DARJEELING_AST_SIZE_BYTES

◆ TOP_DARJEELING_CLKMGR_AON_BASE_ADDR

◆ TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES

◆ TOP_DARJEELING_CSRNG_BASE_ADDR

◆ TOP_DARJEELING_CSRNG_SIZE_BYTES

◆ TOP_DARJEELING_CTN_BASE_ADDR

◆ TOP_DARJEELING_CTN_SIZE_BYTES

◆ TOP_DARJEELING_DMA_BASE_ADDR

◆ TOP_DARJEELING_DMA_SIZE_BYTES

◆ TOP_DARJEELING_EDN0_BASE_ADDR

◆ TOP_DARJEELING_EDN0_SIZE_BYTES

◆ TOP_DARJEELING_EDN1_BASE_ADDR

◆ TOP_DARJEELING_EDN1_SIZE_BYTES

◆ TOP_DARJEELING_GPIO_BASE_ADDR

◆ TOP_DARJEELING_GPIO_SIZE_BYTES

◆ TOP_DARJEELING_HMAC_BASE_ADDR

◆ TOP_DARJEELING_HMAC_SIZE_BYTES

◆ TOP_DARJEELING_I2C0_BASE_ADDR

◆ TOP_DARJEELING_I2C0_SIZE_BYTES

◆ TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR

◆ TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES

◆ TOP_DARJEELING_KMAC_BASE_ADDR

◆ TOP_DARJEELING_KMAC_SIZE_BYTES

◆ TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR

◆ TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES

◆ TOP_DARJEELING_MBX0_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX0_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MBX1_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX1_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MBX2_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX2_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MBX3_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX3_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MBX4_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX4_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MBX5_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX5_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MBX6_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX6_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR

◆ TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES

◆ TOP_DARJEELING_MMIO_BASE_ADDR

◆ TOP_DARJEELING_MMIO_SIZE_BYTES

◆ TOP_DARJEELING_OTBN_BASE_ADDR

◆ TOP_DARJEELING_OTBN_SIZE_BYTES

◆ TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR

◆ TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES

◆ TOP_DARJEELING_OTP_MACRO_BASE_ADDR

◆ TOP_DARJEELING_OTP_MACRO_SIZE_BYTES

◆ TOP_DARJEELING_PINMUX_AON_BASE_ADDR

◆ TOP_DARJEELING_PINMUX_AON_SIZE_BYTES

◆ TOP_DARJEELING_PWRMGR_AON_BASE_ADDR

◆ TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES

◆ TOP_DARJEELING_RAM_MAIN_BASE_ADDR

◆ TOP_DARJEELING_RAM_MAIN_SIZE_BYTES

◆ TOP_DARJEELING_RAM_MBOX_BASE_ADDR

◆ TOP_DARJEELING_RAM_MBOX_SIZE_BYTES

◆ TOP_DARJEELING_RAM_RET_AON_BASE_ADDR

◆ TOP_DARJEELING_RAM_RET_AON_SIZE_BYTES