Documentation

HW SW Security Tooling Governance Use-Cases

Introduction to OpenTitan

OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. This repository exists to enable collaboration across partners participating in the OpenTitan project.

OpenTitan Earl Grey (Standalone Chip)
📋 Datasheet

High speed domain

DUAL LOCKSTEP Ibex Core (RV32IMCB) Interrupt Controller ROM Debug Module Main
SRAM TL-UL
Crossbar Key Manager KMAC EDN SPI
Host 0 OTBN HMAC CSRNG SPI
Host 1 AES Flash Entropy Source USB

Peripheral domain

TL-UL Crossbar OTP (Fuse) Controller Life
Cycle Alert Handler 4 x UART Timers GPIO 3 x I2C SPI
Device Pattern Generators
Padring (only wire and pad instances) Analog Sensor Top
~100 MHz
96 MHz
48 MHz
24 MHz
200 kHz
Logic Only
OpenTitan Darjeeling (Integrated Admissible Architecture)
📋 Datasheet Darjeeling Block Diagram

Getting Started

To get started with OpenTitan, see the Getting Started page. For additional resources when working with OpenTitan, see the contribution guide and the tools guide. Lastly, the Hardware book contains technical documentation on the SoC, the Ibex processor core, and the individual IP blocks. For questions about how the project is organized, see the project landing spot for more information.

Understanding OpenTitan

Datasheets

Documentation

Development