Earl Grey Top-Level Checklist

This checklist is for Hardware Stage transitions for the Earl Grey top-level design. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneDatasheet and detailed spec describe Earl Grey 2.
DocumentationCSR_DEFINEDDoneNo top-level CSRs; per-IP register files listed in Memory Map.
RTLCLKRST_CONNECTEDDoneChecked generated earlgrey_pd_{main,aon}.sv: all clk/rst ports driven by clkmgr/rstmgr, reset domains match their clocks.
RTLIP_TOPDoneTop RTL generated by topgen from top_earlgrey.hjson and checked in CI; all instantiated IPs have IP_TOP Done except ast and rram_macro, for which the open-source code is only a behavioral model (the actual implementation is closed-source and signed off separately).
RTLIP_INSTANTIABLEDoneChip TB and generated RAL in place; JTAG CSR/mem tests pass in nightly regression; chip CSR tests in stub-CPU mode fail on a TB artefact (#31728).
RTLPHYSICAL_MACROS_DEFINED_80DoneAll memories macros and RRAM instantiated (behavioral models in the open-source repo); AST and pads behavioral.
RTLFUNC_IMPLEMENTEDDoneAll smoke tests pass; every block except I3C has a passing chip-level test.
RTLASSERT_KNOWN_ADDEDDoneTop-level outputs are pass-throughs of IP outputs, which carry ASSERT_KNOWN in their IPs; scanmode_o asserted in earlgrey_pd_aon.
Code QualityLINT_SETUPDoneRTL/DV/FPV lint cfgs in hw/top_earlgrey/lint; AscentLint, Verible, and slang run in CI.
SecuritySEC_CM_SCOPEDDoneCountermeasures are implemented in the IPs, all of which have SEC_CM_SCOPED Done.

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESNot Started
DocumentationBLOCK_DIAGRAMNot Started
DocumentationDOC_INTERFACENot Started
DocumentationDOC_INTEGRATION_D2Not Started
DocumentationMISSING_FUNCNot Started
DocumentationFEATURE_FROZENNot Started
RTLFEATURE_COMPLETENot Started
RTLPORT_FROZENNot Started
RTLARCHITECTURE_FROZENNot Started
RTLREVIEW_TODONot Started
RTLSTYLE_XNot Started
RTLCDC_SYNCMACRONot Started
Code QualityLINT_PASSNot Started
Code QualityCDC_SETUPNot Started
Code QualityRDC_SETUPNot Started
Code QualityAREA_CHECKNot Started
Code QualityTIMING_CHECKNot Started
SecuritySEC_CM_DOCUMENTEDNot Started

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDNot Started
SecuritySEC_CM_IMPLEMENTEDNot Started
SecuritySEC_CM_RND_CNSTNot Started
SecuritySEC_CM_NON_RESET_FLOPSNot Started
SecuritySEC_CM_SHADOW_REGSNot Started
SecuritySEC_CM_RTL_REVIEWEDNot Started
SecuritySEC_CM_COUNCIL_REVIEWEDNot Started

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Not Started
DocumentationDOC_INTEGRATION_D3Not Started
RTLTODO_COMPLETENot Started
Code QualityLINT_COMPLETENot Started
Code QualityCDC_COMPLETENot Started
Code QualityRDC_COMPLETENot Started
ReviewREVIEW_RTLNot Started
ReviewREVIEW_DELETED_FFNot Started
ReviewREVIEW_SW_CHANGENot Started
ReviewREVIEW_SW_ERRATANot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDNot StartedEarl Grey DV document
DocumentationTESTPLAN_COMPLETEDNot StartedChip Testplan
TestbenchTB_TOP_CREATEDNot Started
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDNot Started
TestbenchSIM_TB_ENV_CREATEDNot Started
TestbenchSIM_RAL_MODEL_GEN_AUTOMATEDNot Started
TestbenchCSR_CHECK_GEN_AUTOMATEDNot Started
TestbenchTB_GEN_AUTOMATEDNot Started
TestsSIM_SMOKE_TEST_PASSINGNot Started
TestsSIM_CSR_MEM_TEST_SUITE_PASSINGNot Started
TestsFPV_MAIN_ASSERTIONS_PROVENNot Started
Tool SetupSIM_ALT_TOOL_SETUPNot Started
RegressionSIM_SMOKE_REGRESSION_SETUPNot Started
RegressionSIM_NIGHTLY_REGRESSION_SETUPNot Started
RegressionFPV_REGRESSION_SETUPNot Started
CoverageSIM_COVERAGE_MODEL_ADDEDNot Started
Code QualityTB_LINT_SETUPNot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V1Not Started
ReviewDESIGN_SPEC_REVIEWEDNot Started
ReviewTESTPLAN_REVIEWEDNot Started
ReviewSTD_TEST_CATEGORIES_PLANNEDNot StartedException (?)
ReviewV2_CHECKLIST_SCOPEDNot Started

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2Not Started
DocumentationDV_DOC_COMPLETEDNot Started
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDNot Started
TestbenchALL_INTERFACES_EXERCISEDNot Started
TestbenchALL_ASSERTION_CHECKS_ADDEDNot Started
TestbenchSIM_TB_ENV_COMPLETEDNot Started
TestsSIM_ALL_TESTS_PASSINGNot Started
TestsFPV_ALL_ASSERTIONS_WRITTENNot Started
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDNot Started
TestsSIM_FW_SIMULATEDNot Started
RegressionSIM_NIGHTLY_REGRESSION_V2Not Started
CoverageSIM_CODE_COVERAGE_V2Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_V2Not Started
CoverageFPV_CODE_COVERAGE_V2Not Started
CoverageFPV_COI_COVERAGE_V2Not Started
IntegrationPRE_VERIFIED_SUB_MODULES_V2Not Started
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGNot Started
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDNot Started
ReviewDV_DOC_TESTPLAN_REVIEWEDNot Started
ReviewV2S_CHECKLIST_SCOPEDNot Started
ReviewV3_FUNCTIONAL_CHECKLIST_SCOPEDNot Started

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDNot Started
TestsFPV_SEC_CM_VERIFIEDNot Started
TestsSIM_SEC_CM_VERIFIEDNot Started
CoverageSIM_COVERAGE_REVIEWEDNot Started
ReviewSEC_CM_DV_REVIEWEDNot Started
ReviewV3_CHECKLIST_SCOPEDNot Started

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3Not Started
TestsX_PROP_ANALYSIS_COMPLETEDNot Started
TestsFPV_ASSERTIONS_PROVEN_AT_V3Not Started
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Not Started
CoverageSIM_CODE_COVERAGE_AT_100Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Not Started
CoverageFPV_CODE_COVERAGE_AT_100Not Started
CoverageFPV_COI_COVERAGE_AT_100Not Started
Code QualityALL_TODOS_RESOLVEDNot Started
Code QualityNO_TOOL_WARNINGS_THROWNNot Started
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Not Started
IssuesNO_ISSUES_PENDINGNot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started