CHERIoT Checklist

This checklist is for Hardware Stage transitions for the CHERIoT peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDoneCHERIoT Design Spec
DocumentationCSR_DEFINEDDoneCHERIoT Registers.
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDoneElaborates cleanly in Earl Grey; chip_sw_cheriot_smoketest and chip_sw_cheriot_epmp_smoketest pass.
RTLPHYSICAL_MACROS_DEFINED_80N/A
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDone
Code QualityLINT_SETUPDoneLinted in pre-merge CI with Verible, slang and AscentLint via top_earlgrey_lint_cfgs.hjson.
SecuritySEC_CM_SCOPEDDoneSecurity countermeasures, reviewed in the HW WG meeting (successor of the Security WG meeting) on 2026-09-15, see #31707.

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESNot Started
DocumentationBLOCK_DIAGRAMDoneBlock diagram
DocumentationDOC_INTERFACEDoneHardware Interfaces
DocumentationDOC_INTEGRATION_GUIDENot Started
DocumentationMISSING_FUNCNot Started
DocumentationFEATURE_FROZENNot Started
RTLFEATURE_COMPLETENot Started
RTLPORT_FROZENNot Started
RTLARCHITECTURE_FROZENNot Started
RTLREVIEW_TODONot Started
RTLSTYLE_XNot Started
RTLCDC_SYNCMACRON/A
Code QualityLINT_PASSNot Started
Code QualityCDC_SETUPNot Started
Code QualityRDC_SETUPNot Started
Code QualityAREA_CHECKNot Started
Code QualityTIMING_CHECKNot Started
SecuritySEC_CM_DOCUMENTEDNot Started

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDonecheriot_mem_sys.hjson
SecuritySEC_CM_IMPLEMENTEDNot StartedLOGIC.SHADOW (#30572) and CORED_TAG.INTERSIG.MUBI (#31066) are not implemented yet, and BUS.INTEGRITY relies on LOGIC.SHADOW. MEM.SW_NOACCESS and INTERSIG.MUBI are implemented.
SecuritySEC_CM_RND_CNSTN/A
SecuritySEC_CM_NON_RESET_FLOPSNot Started
SecuritySEC_CM_SHADOW_REGSNot Started
SecuritySEC_CM_RTL_REVIEWEDNot Started
SecuritySEC_CM_COUNCIL_REVIEWEDNot Started

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Not Started
RTLTODO_COMPLETENot Started
Code QualityLINT_COMPLETENot Started
Code QualityCDC_COMPLETENot Started
Code QualityRDC_COMPLETENot Started
ReviewREVIEW_RTLNot Started
ReviewREVIEW_DELETED_FFNot Started
ReviewREVIEW_SW_CHANGENot Started
ReviewREVIEW_SW_ERRATANot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDNot StartedTemplate present CHERIoT Memory Subsystem DV document
DocumentationTESTPLAN_COMPLETEDNot StartedTemplate present Testplan
TestbenchTB_TOP_CREATEDDonetb.sv
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDNot Started
TestbenchSIM_TB_ENV_CREATEDNot Started
TestbenchSIM_RAL_MODEL_GEN_AUTOMATEDDone
TestbenchCSR_CHECK_GEN_AUTOMATEDDone
TestbenchTB_GEN_AUTOMATEDNot Started
TestsSIM_SMOKE_TEST_PASSINGNot Started
TestsSIM_CSR_MEM_TEST_SUITE_PASSINGDoneThe CSR tests run in the nightly regression. No mem walk: the subsystem has no memories, and revbm is a window into sram_ctrl_meta, to be walked at chip level (#31708).
TestsFPV_MAIN_ASSERTIONS_PROVENNot Started
Tool SetupSIM_ALT_TOOL_SETUPNot Started
RegressionSIM_SMOKE_REGRESSION_SETUPNot Started
RegressionSIM_NIGHTLY_REGRESSION_SETUPNot Started
RegressionFPV_REGRESSION_SETUPNot Started
CoverageSIM_COVERAGE_MODEL_ADDEDNot Started
Code QualityTB_LINT_SETUPNot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V1Not Started
ReviewDESIGN_SPEC_REVIEWEDNot Started
ReviewTESTPLAN_REVIEWEDNot Started
ReviewSTD_TEST_CATEGORIES_PLANNEDNot Started
ReviewV2_CHECKLIST_SCOPEDNot Started

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2Not Started
DocumentationDV_DOC_COMPLETEDNot Started
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDNot Started
TestbenchALL_INTERFACES_EXERCISEDNot Started
TestbenchALL_ASSERTION_CHECKS_ADDEDNot Started
TestbenchSIM_TB_ENV_COMPLETEDNot Started
TestsSIM_ALL_TESTS_PASSINGNot Started
TestsFPV_ALL_ASSERTIONS_WRITTENNot Started
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDNot Started
TestsSIM_FW_SIMULATEDN/A
RegressionSIM_NIGHTLY_REGRESSION_V2Not Started
CoverageSIM_CODE_COVERAGE_V2Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_V2Not Started
CoverageFPV_CODE_COVERAGE_V2Not Started
CoverageFPV_COI_COVERAGE_V2Not Started
IntegrationPRE_VERIFIED_SUB_MODULES_V2Not Started
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGNot Started
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDNot Started
ReviewDV_DOC_TESTPLAN_REVIEWEDNot Started
ReviewV3_CHECKLIST_SCOPEDNot Started

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDNot Started
TestsFPV_SEC_CM_VERIFIEDNot Started
TestsSIM_SEC_CM_VERIFIEDNot Started
CoverageSIM_COVERAGE_REVIEWEDNot Started
ReviewSEC_CM_DV_REVIEWEDNot Started

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3Not Started
TestsX_PROP_ANALYSIS_COMPLETEDNot Started
TestsFPV_ASSERTIONS_PROVEN_AT_V3Not Started
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Not Started
CoverageSIM_CODE_COVERAGE_AT_100Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Not Started
CoverageFPV_CODE_COVERAGE_AT_100Not Started
CoverageFPV_COI_COVERAGE_AT_100Not Started
Code QualityALL_TODOS_RESOLVEDNot Started
Code QualityNO_TOOL_WARNINGS_THROWNNot Started
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Not Started
IssuesNO_ISSUES_PENDINGNot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started