CHERIoT Memory Subsystem DV document

Goals

• Verify the CHERIoT memory subsystem with a SV/UVM testbench based on the CIP testbench architecture.
• Run the tests in the testplan towards closing code and functional coverage.

Current status

• Design & verification stage
  • HW development stages

Design features

See the CHERIoT Memory Subsystem HWIP technical specification.

Testbench

hw/ip/cheriot_mem_sys/dv/tb.sv instantiates hw/ip/cheriot_mem_sys/rtl/cheriot_mem_sys.sv with:

• Clock and reset interface
• TileLink host interface on the regs CSR port
• Alert interface for fatal_fault
• Interrupt pins interface for intr_tbre_done_o

Building and running tests

The dvsim tool is used for building and running our tests and regressions.

To run a smoke test, use:

$ dvsim hw/ip/cheriot_mem_sys/dv/cheriot_mem_sys_sim_cfg.hjson -i cheriot_mem_sys_smoke

To run the CSR, alert, interrupt and TL-UL suites, use:

$ dvsim hw/ip/cheriot_mem_sys/dv/cheriot_mem_sys_sim_cfg.hjson

Testplan

Testplan