Struct OpenOcdJtagTap

pub struct OpenOcdJtagTap { /* private fields */ }

An JTAG interface driver over OpenOCD.

Trait Implementations

impl Jtag for OpenOcdJtagTap

fn into_raw(self: Box<Self>) -> Result<OpenOcd>

Stop further operation and returns raw OpenOCD instance.

fn as_raw(&mut self) -> Result<&mut OpenOcd>

Returns the underlying OpenOCD instance.

fn disconnect(self: Box<Self>) -> Result<()>

Disconnect from the TAP.

fn tap(&self) -> JtagTap

Get TAP we are currently connected too.

fn read_lc_ctrl_reg(&mut self, reg: &LcCtrlReg) -> Result<u32>

Read a lifecycle controller register.

fn write_lc_ctrl_reg(&mut self, reg: &LcCtrlReg, value: u32) -> Result<()>

Write a value to a lifecycle controller register.

fn read_memory(&mut self, addr: u32, buf: &mut [u8]) -> Result<usize>

Read bytes/words from memory into the provided buffer. When reading bytes, each memory access is 8 bits. When reading words, each memory access is 32 bit. If the hardware does not support unaligned memory accesses, this function will fail.

fn read_memory32(&mut self, addr: u32, buf: &mut [u32]) -> Result<usize>

fn write_memory(&mut self, addr: u32, buf: &[u8]) -> Result<()>

Write bytes/words to memory.

fn write_memory32(&mut self, addr: u32, buf: &[u32]) -> Result<()>

fn halt(&mut self) -> Result<()>

Halt execution.

fn wait_halt(&mut self, timeout: Duration) -> Result<()>

Wait until the target halt. This does NOT halt the target on timeout.

fn resume(&mut self) -> Result<()>

Resume execution at its current code position.

fn resume_at(&mut self, addr: u32) -> Result<()>

Resume execution at the specified address.

fn reset(&mut self, run: bool) -> Result<()>

Reset the target as hard as possible. If run is true, the target will start running code immediately after reset, otherwise it will be halted immediately.

fn step(&mut self) -> Result<()>

Single-step the target at its current code position.

fn step_at(&mut self, addr: u32) -> Result<()>

Single-step the target at the specified address.

fn read_riscv_reg(&mut self, reg: &RiscvReg) -> Result<u32>

Read/write a RISC-V register

fn write_riscv_reg(&mut self, reg: &RiscvReg, val: u32) -> Result<()>

fn set_breakpoint(&mut self, address: u32, hw: bool) -> Result<()>

Set a breakpoint at the given address.

fn remove_breakpoint(&mut self, addr: u32) -> Result<()>

fn remove_all_breakpoints(&mut self) -> Result<()>