Top-specific Definitions. More...

Macros
#define	TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR 0x40000000u
	Peripheral base address for uart0 in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_UART0_SIZE_BYTES 0x40u
	Peripheral size for uart0 in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR 0x40010000u
	Peripheral base address for uart1 in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_UART1_SIZE_BYTES 0x40u
	Peripheral size for uart1 in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR 0x40040000u
	Peripheral base address for gpio in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_GPIO_SIZE_BYTES 0x80u
	Peripheral size for gpio in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR 0x40050000u
	Peripheral base address for spi_device in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_SPI_DEVICE_SIZE_BYTES 0x2000u
	Peripheral size for spi_device in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR 0x40060000u
	Peripheral base address for spi_host0 in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_SPI_HOST0_SIZE_BYTES 0x40u
	Peripheral size for spi_host0 in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR 0x40100000u
	Peripheral base address for rv_timer in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RV_TIMER_SIZE_BYTES 0x200u
	Peripheral size for rv_timer in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR 0x40320000u
	Peripheral base address for usbdev in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_USBDEV_SIZE_BYTES 0x1000u
	Peripheral size for usbdev in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR 0x40400000u
	Peripheral base address for pwrmgr_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_PWRMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for pwrmgr_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR 0x40410000u
	Peripheral base address for rstmgr_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for rstmgr_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR 0x40420000u
	Peripheral base address for clkmgr_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_CLKMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for clkmgr_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR 0x40460000u
	Peripheral base address for pinmux_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_PINMUX_AON_SIZE_BYTES 0x1000u
	Peripheral size for pinmux_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR 0x40470000u
	Peripheral base address for aon_timer_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_AON_TIMER_AON_SIZE_BYTES 0x40u
	Peripheral size for aon_timer_aon in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_AST_BASE_ADDR 0x40480000u
	Peripheral base address for ast in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_AST_SIZE_BYTES 0x400u
	Peripheral size for ast in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
	Peripheral base address for core device on flash_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
	Peripheral size for core device on flash_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u
	Peripheral base address for prim device on flash_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u
	Peripheral size for prim device on flash_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
	Peripheral base address for mem device on flash_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_SIZE_BYTES 0x10000u
	Peripheral size for mem device on flash_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR 0x48000000u
	Peripheral base address for rv_plic in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RV_PLIC_SIZE_BYTES 0x8000000u
	Peripheral size for rv_plic in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_AES_BASE_ADDR 0x41100000u
	Peripheral base address for aes in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_AES_SIZE_BYTES 0x100u
	Peripheral size for aes in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
	Peripheral base address for regs device on sram_ctrl_main in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
	Peripheral size for regs device on sram_ctrl_main in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
	Peripheral base address for ram device on sram_ctrl_main in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
	Peripheral size for ram device on sram_ctrl_main in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
	Peripheral base address for regs device on rom_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_SIZE_BYTES 0x80u
	Peripheral size for regs device on rom_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR 0x8000u
	Peripheral base address for rom device on rom_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
	Peripheral size for rom device on rom_ctrl in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u
	Peripheral base address for cfg device on rv_core_ibex in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u
	Peripheral size for cfg device on rv_core_ibex in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_EFLASH_BASE_ADDR 0x20000000u
	Memory base address for eflash in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_EFLASH_SIZE_BYTES 0x10000u
	Memory size for eflash in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RAM_MAIN_BASE_ADDR 0x10000000u
	Memory base address for ram_main in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_RAM_MAIN_SIZE_BYTES 0x20000u
	Memory size for ram_main in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_ROM_BASE_ADDR 0x8000u
	Memory base address for rom in top englishbreakfast.

#define	TOP_ENGLISHBREAKFAST_ROM_SIZE_BYTES 0x8000u
	Memory size for rom in top englishbreakfast.

#define	PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2

#define	NUM_MIO_PADS 47

#define	NUM_DIO_PADS 14

#define	PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3

#define	TOP_ENGLISHBREAKFAST_MMIO_BASE_ADDR 0x40000000u
	MMIO Region.

#define	TOP_ENGLISHBREAKFAST_MMIO_SIZE_BYTES 0x10000000u

Typedefs
typedef enum top_englishbreakfast_plic_peripheral	top_englishbreakfast_plic_peripheral_t
	PLIC Interrupt Source Peripheral.

typedef enum top_englishbreakfast_plic_irq_id	top_englishbreakfast_plic_irq_id_t
	PLIC Interrupt Source.

typedef enum top_englishbreakfast_plic_target	top_englishbreakfast_plic_target_t
	PLIC Interrupt Target.

typedef enum top_englishbreakfast_pinmux_peripheral_in	top_englishbreakfast_pinmux_peripheral_in_t
	Pinmux Peripheral Input.

typedef enum top_englishbreakfast_pinmux_insel	top_englishbreakfast_pinmux_insel_t
	Pinmux MIO Input Selector.

typedef enum top_englishbreakfast_pinmux_mio_out	top_englishbreakfast_pinmux_mio_out_t
	Pinmux MIO Output.

typedef enum top_englishbreakfast_pinmux_outsel	top_englishbreakfast_pinmux_outsel_t
	Pinmux Peripheral Output Selector.

typedef enum top_englishbreakfast_direct_pads	top_englishbreakfast_direct_pads_t
	Dedicated Pad Selects.

typedef enum top_englishbreakfast_muxed_pads	top_englishbreakfast_muxed_pads_t
	Muxed Pad Selects.

typedef enum top_englishbreakfast_power_manager_wake_ups	top_englishbreakfast_power_manager_wake_ups_t
	Power Manager Wakeup Signals.

typedef enum top_englishbreakfast_reset_manager_sw_resets	top_englishbreakfast_reset_manager_sw_resets_t
	Reset Manager Software Controlled Resets.

typedef enum top_englishbreakfast_power_manager_reset_requests	top_englishbreakfast_power_manager_reset_requests_t
	Power Manager Reset Request Signals.

typedef enum top_englishbreakfast_gateable_clocks	top_englishbreakfast_gateable_clocks_t
	Clock Manager Software-Controlled ("Gated") Clocks.

typedef enum top_englishbreakfast_hintable_clocks	top_englishbreakfast_hintable_clocks_t
	Clock Manager Software-Hinted Clocks.

Enumerations
enum	top_englishbreakfast_plic_peripheral { kTopEnglishbreakfastPlicPeripheralUnknown = 0 , kTopEnglishbreakfastPlicPeripheralUart0 = 1 , kTopEnglishbreakfastPlicPeripheralUart1 = 2 , kTopEnglishbreakfastPlicPeripheralGpio = 3 , kTopEnglishbreakfastPlicPeripheralSpiDevice = 4 , kTopEnglishbreakfastPlicPeripheralSpiHost0 = 5 , kTopEnglishbreakfastPlicPeripheralUsbdev = 6 , kTopEnglishbreakfastPlicPeripheralPwrmgrAon = 7 , kTopEnglishbreakfastPlicPeripheralAonTimerAon = 8 , kTopEnglishbreakfastPlicPeripheralFlashCtrl = 9 , kTopEnglishbreakfastPlicPeripheralLast = 9 }
	PLIC Interrupt Source Peripheral. More...

enum	top_englishbreakfast_plic_irq_id { kTopEnglishbreakfastPlicIrqIdNone = 0 , kTopEnglishbreakfastPlicIrqIdUart0TxWatermark = 1 , kTopEnglishbreakfastPlicIrqIdUart0RxWatermark = 2 , kTopEnglishbreakfastPlicIrqIdUart0TxDone = 3 , kTopEnglishbreakfastPlicIrqIdUart0RxOverflow = 4 , kTopEnglishbreakfastPlicIrqIdUart0RxFrameErr = 5 , kTopEnglishbreakfastPlicIrqIdUart0RxBreakErr = 6 , kTopEnglishbreakfastPlicIrqIdUart0RxTimeout = 7 , kTopEnglishbreakfastPlicIrqIdUart0RxParityErr = 8 , kTopEnglishbreakfastPlicIrqIdUart0TxEmpty = 9 , kTopEnglishbreakfastPlicIrqIdUart1TxWatermark = 10 , kTopEnglishbreakfastPlicIrqIdUart1RxWatermark = 11 , kTopEnglishbreakfastPlicIrqIdUart1TxDone = 12 , kTopEnglishbreakfastPlicIrqIdUart1RxOverflow = 13 , kTopEnglishbreakfastPlicIrqIdUart1RxFrameErr = 14 , kTopEnglishbreakfastPlicIrqIdUart1RxBreakErr = 15 , kTopEnglishbreakfastPlicIrqIdUart1RxTimeout = 16 , kTopEnglishbreakfastPlicIrqIdUart1RxParityErr = 17 , kTopEnglishbreakfastPlicIrqIdUart1TxEmpty = 18 , kTopEnglishbreakfastPlicIrqIdGpioGpio0 = 19 , kTopEnglishbreakfastPlicIrqIdGpioGpio1 = 20 , kTopEnglishbreakfastPlicIrqIdGpioGpio2 = 21 , kTopEnglishbreakfastPlicIrqIdGpioGpio3 = 22 , kTopEnglishbreakfastPlicIrqIdGpioGpio4 = 23 , kTopEnglishbreakfastPlicIrqIdGpioGpio5 = 24 , kTopEnglishbreakfastPlicIrqIdGpioGpio6 = 25 , kTopEnglishbreakfastPlicIrqIdGpioGpio7 = 26 , kTopEnglishbreakfastPlicIrqIdGpioGpio8 = 27 , kTopEnglishbreakfastPlicIrqIdGpioGpio9 = 28 , kTopEnglishbreakfastPlicIrqIdGpioGpio10 = 29 , kTopEnglishbreakfastPlicIrqIdGpioGpio11 = 30 , kTopEnglishbreakfastPlicIrqIdGpioGpio12 = 31 , kTopEnglishbreakfastPlicIrqIdGpioGpio13 = 32 , kTopEnglishbreakfastPlicIrqIdGpioGpio14 = 33 , kTopEnglishbreakfastPlicIrqIdGpioGpio15 = 34 , kTopEnglishbreakfastPlicIrqIdGpioGpio16 = 35 , kTopEnglishbreakfastPlicIrqIdGpioGpio17 = 36 , kTopEnglishbreakfastPlicIrqIdGpioGpio18 = 37 , kTopEnglishbreakfastPlicIrqIdGpioGpio19 = 38 , kTopEnglishbreakfastPlicIrqIdGpioGpio20 = 39 , kTopEnglishbreakfastPlicIrqIdGpioGpio21 = 40 , kTopEnglishbreakfastPlicIrqIdGpioGpio22 = 41 , kTopEnglishbreakfastPlicIrqIdGpioGpio23 = 42 , kTopEnglishbreakfastPlicIrqIdGpioGpio24 = 43 , kTopEnglishbreakfastPlicIrqIdGpioGpio25 = 44 , kTopEnglishbreakfastPlicIrqIdGpioGpio26 = 45 , kTopEnglishbreakfastPlicIrqIdGpioGpio27 = 46 , kTopEnglishbreakfastPlicIrqIdGpioGpio28 = 47 , kTopEnglishbreakfastPlicIrqIdGpioGpio29 = 48 , kTopEnglishbreakfastPlicIrqIdGpioGpio30 = 49 , kTopEnglishbreakfastPlicIrqIdGpioGpio31 = 50 , kTopEnglishbreakfastPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 51 , kTopEnglishbreakfastPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 52 , kTopEnglishbreakfastPlicIrqIdSpiDeviceUploadPayloadOverflow = 53 , kTopEnglishbreakfastPlicIrqIdSpiDeviceReadbufWatermark = 54 , kTopEnglishbreakfastPlicIrqIdSpiDeviceReadbufFlip = 55 , kTopEnglishbreakfastPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 56 , kTopEnglishbreakfastPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 57 , kTopEnglishbreakfastPlicIrqIdSpiDeviceTpmRdfifoDrop = 58 , kTopEnglishbreakfastPlicIrqIdSpiHost0Error = 59 , kTopEnglishbreakfastPlicIrqIdSpiHost0SpiEvent = 60 , kTopEnglishbreakfastPlicIrqIdUsbdevPktReceived = 61 , kTopEnglishbreakfastPlicIrqIdUsbdevPktSent = 62 , kTopEnglishbreakfastPlicIrqIdUsbdevDisconnected = 63 , kTopEnglishbreakfastPlicIrqIdUsbdevHostLost = 64 , kTopEnglishbreakfastPlicIrqIdUsbdevLinkReset = 65 , kTopEnglishbreakfastPlicIrqIdUsbdevLinkSuspend = 66 , kTopEnglishbreakfastPlicIrqIdUsbdevLinkResume = 67 , kTopEnglishbreakfastPlicIrqIdUsbdevAvOutEmpty = 68 , kTopEnglishbreakfastPlicIrqIdUsbdevRxFull = 69 , kTopEnglishbreakfastPlicIrqIdUsbdevAvOverflow = 70 , kTopEnglishbreakfastPlicIrqIdUsbdevLinkInErr = 71 , kTopEnglishbreakfastPlicIrqIdUsbdevRxCrcErr = 72 , kTopEnglishbreakfastPlicIrqIdUsbdevRxPidErr = 73 , kTopEnglishbreakfastPlicIrqIdUsbdevRxBitstuffErr = 74 , kTopEnglishbreakfastPlicIrqIdUsbdevFrame = 75 , kTopEnglishbreakfastPlicIrqIdUsbdevPowered = 76 , kTopEnglishbreakfastPlicIrqIdUsbdevLinkOutErr = 77 , kTopEnglishbreakfastPlicIrqIdUsbdevAvSetupEmpty = 78 , kTopEnglishbreakfastPlicIrqIdPwrmgrAonWakeup = 79 , kTopEnglishbreakfastPlicIrqIdAonTimerAonWkupTimerExpired = 80 , kTopEnglishbreakfastPlicIrqIdAonTimerAonWdogTimerBark = 81 , kTopEnglishbreakfastPlicIrqIdFlashCtrlProgEmpty = 82 , kTopEnglishbreakfastPlicIrqIdFlashCtrlProgLvl = 83 , kTopEnglishbreakfastPlicIrqIdFlashCtrlRdFull = 84 , kTopEnglishbreakfastPlicIrqIdFlashCtrlRdLvl = 85 , kTopEnglishbreakfastPlicIrqIdFlashCtrlOpDone = 86 , kTopEnglishbreakfastPlicIrqIdFlashCtrlCorrErr = 87 , kTopEnglishbreakfastPlicIrqIdLast = 87 }
	PLIC Interrupt Source. More...

enum	top_englishbreakfast_plic_target { kTopEnglishbreakfastPlicTargetIbex0 = 0 , kTopEnglishbreakfastPlicTargetLast = 0 }
	PLIC Interrupt Target. More...

enum	top_englishbreakfast_pinmux_peripheral_in { kTopEnglishbreakfastPinmuxPeripheralInGpioGpio0 = 0 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio1 = 1 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio2 = 2 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio3 = 3 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio4 = 4 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio5 = 5 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio6 = 6 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio7 = 7 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio8 = 8 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio9 = 9 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio10 = 10 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio11 = 11 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio12 = 12 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio13 = 13 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio14 = 14 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio15 = 15 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio16 = 16 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio17 = 17 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio18 = 18 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio19 = 19 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio20 = 20 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio21 = 21 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio22 = 22 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio23 = 23 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio24 = 24 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio25 = 25 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio26 = 26 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio27 = 27 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio28 = 28 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio29 = 29 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio30 = 30 , kTopEnglishbreakfastPinmuxPeripheralInGpioGpio31 = 31 , kTopEnglishbreakfastPinmuxPeripheralInUart0Rx = 32 , kTopEnglishbreakfastPinmuxPeripheralInUart1Rx = 33 , kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTck = 34 , kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTms = 35 , kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTdi = 36 , kTopEnglishbreakfastPinmuxPeripheralInUsbdevSense = 37 , kTopEnglishbreakfastPinmuxPeripheralInLast = 37 }
	Pinmux Peripheral Input. More...

enum	top_englishbreakfast_pinmux_insel { kTopEnglishbreakfastPinmuxInselConstantZero = 0 , kTopEnglishbreakfastPinmuxInselConstantOne = 1 , kTopEnglishbreakfastPinmuxInselIoa0 = 2 , kTopEnglishbreakfastPinmuxInselIoa1 = 3 , kTopEnglishbreakfastPinmuxInselIoa2 = 4 , kTopEnglishbreakfastPinmuxInselIoa3 = 5 , kTopEnglishbreakfastPinmuxInselIoa4 = 6 , kTopEnglishbreakfastPinmuxInselIoa5 = 7 , kTopEnglishbreakfastPinmuxInselIoa6 = 8 , kTopEnglishbreakfastPinmuxInselIoa7 = 9 , kTopEnglishbreakfastPinmuxInselIoa8 = 10 , kTopEnglishbreakfastPinmuxInselIob0 = 11 , kTopEnglishbreakfastPinmuxInselIob1 = 12 , kTopEnglishbreakfastPinmuxInselIob2 = 13 , kTopEnglishbreakfastPinmuxInselIob3 = 14 , kTopEnglishbreakfastPinmuxInselIob4 = 15 , kTopEnglishbreakfastPinmuxInselIob5 = 16 , kTopEnglishbreakfastPinmuxInselIob6 = 17 , kTopEnglishbreakfastPinmuxInselIob7 = 18 , kTopEnglishbreakfastPinmuxInselIob8 = 19 , kTopEnglishbreakfastPinmuxInselIob9 = 20 , kTopEnglishbreakfastPinmuxInselIob10 = 21 , kTopEnglishbreakfastPinmuxInselIob11 = 22 , kTopEnglishbreakfastPinmuxInselIob12 = 23 , kTopEnglishbreakfastPinmuxInselIoc0 = 24 , kTopEnglishbreakfastPinmuxInselIoc1 = 25 , kTopEnglishbreakfastPinmuxInselIoc2 = 26 , kTopEnglishbreakfastPinmuxInselIoc3 = 27 , kTopEnglishbreakfastPinmuxInselIoc4 = 28 , kTopEnglishbreakfastPinmuxInselIoc5 = 29 , kTopEnglishbreakfastPinmuxInselIoc6 = 30 , kTopEnglishbreakfastPinmuxInselIoc7 = 31 , kTopEnglishbreakfastPinmuxInselIoc8 = 32 , kTopEnglishbreakfastPinmuxInselIoc9 = 33 , kTopEnglishbreakfastPinmuxInselIoc10 = 34 , kTopEnglishbreakfastPinmuxInselIoc11 = 35 , kTopEnglishbreakfastPinmuxInselIoc12 = 36 , kTopEnglishbreakfastPinmuxInselIor0 = 37 , kTopEnglishbreakfastPinmuxInselIor1 = 38 , kTopEnglishbreakfastPinmuxInselIor2 = 39 , kTopEnglishbreakfastPinmuxInselIor3 = 40 , kTopEnglishbreakfastPinmuxInselIor4 = 41 , kTopEnglishbreakfastPinmuxInselIor5 = 42 , kTopEnglishbreakfastPinmuxInselIor6 = 43 , kTopEnglishbreakfastPinmuxInselIor7 = 44 , kTopEnglishbreakfastPinmuxInselIor10 = 45 , kTopEnglishbreakfastPinmuxInselIor11 = 46 , kTopEnglishbreakfastPinmuxInselIor12 = 47 , kTopEnglishbreakfastPinmuxInselIor13 = 48 , kTopEnglishbreakfastPinmuxInselLast = 48 }
	Pinmux MIO Input Selector. More...

enum	top_englishbreakfast_pinmux_mio_out { kTopEnglishbreakfastPinmuxMioOutIoa0 = 0 , kTopEnglishbreakfastPinmuxMioOutIoa1 = 1 , kTopEnglishbreakfastPinmuxMioOutIoa2 = 2 , kTopEnglishbreakfastPinmuxMioOutIoa3 = 3 , kTopEnglishbreakfastPinmuxMioOutIoa4 = 4 , kTopEnglishbreakfastPinmuxMioOutIoa5 = 5 , kTopEnglishbreakfastPinmuxMioOutIoa6 = 6 , kTopEnglishbreakfastPinmuxMioOutIoa7 = 7 , kTopEnglishbreakfastPinmuxMioOutIoa8 = 8 , kTopEnglishbreakfastPinmuxMioOutIob0 = 9 , kTopEnglishbreakfastPinmuxMioOutIob1 = 10 , kTopEnglishbreakfastPinmuxMioOutIob2 = 11 , kTopEnglishbreakfastPinmuxMioOutIob3 = 12 , kTopEnglishbreakfastPinmuxMioOutIob4 = 13 , kTopEnglishbreakfastPinmuxMioOutIob5 = 14 , kTopEnglishbreakfastPinmuxMioOutIob6 = 15 , kTopEnglishbreakfastPinmuxMioOutIob7 = 16 , kTopEnglishbreakfastPinmuxMioOutIob8 = 17 , kTopEnglishbreakfastPinmuxMioOutIob9 = 18 , kTopEnglishbreakfastPinmuxMioOutIob10 = 19 , kTopEnglishbreakfastPinmuxMioOutIob11 = 20 , kTopEnglishbreakfastPinmuxMioOutIob12 = 21 , kTopEnglishbreakfastPinmuxMioOutIoc0 = 22 , kTopEnglishbreakfastPinmuxMioOutIoc1 = 23 , kTopEnglishbreakfastPinmuxMioOutIoc2 = 24 , kTopEnglishbreakfastPinmuxMioOutIoc3 = 25 , kTopEnglishbreakfastPinmuxMioOutIoc4 = 26 , kTopEnglishbreakfastPinmuxMioOutIoc5 = 27 , kTopEnglishbreakfastPinmuxMioOutIoc6 = 28 , kTopEnglishbreakfastPinmuxMioOutIoc7 = 29 , kTopEnglishbreakfastPinmuxMioOutIoc8 = 30 , kTopEnglishbreakfastPinmuxMioOutIoc9 = 31 , kTopEnglishbreakfastPinmuxMioOutIoc10 = 32 , kTopEnglishbreakfastPinmuxMioOutIoc11 = 33 , kTopEnglishbreakfastPinmuxMioOutIoc12 = 34 , kTopEnglishbreakfastPinmuxMioOutIor0 = 35 , kTopEnglishbreakfastPinmuxMioOutIor1 = 36 , kTopEnglishbreakfastPinmuxMioOutIor2 = 37 , kTopEnglishbreakfastPinmuxMioOutIor3 = 38 , kTopEnglishbreakfastPinmuxMioOutIor4 = 39 , kTopEnglishbreakfastPinmuxMioOutIor5 = 40 , kTopEnglishbreakfastPinmuxMioOutIor6 = 41 , kTopEnglishbreakfastPinmuxMioOutIor7 = 42 , kTopEnglishbreakfastPinmuxMioOutIor10 = 43 , kTopEnglishbreakfastPinmuxMioOutIor11 = 44 , kTopEnglishbreakfastPinmuxMioOutIor12 = 45 , kTopEnglishbreakfastPinmuxMioOutIor13 = 46 , kTopEnglishbreakfastPinmuxMioOutLast = 46 }
	Pinmux MIO Output. More...

enum	top_englishbreakfast_pinmux_outsel { kTopEnglishbreakfastPinmuxOutselConstantZero = 0 , kTopEnglishbreakfastPinmuxOutselConstantOne = 1 , kTopEnglishbreakfastPinmuxOutselConstantHighZ = 2 , kTopEnglishbreakfastPinmuxOutselGpioGpio0 = 3 , kTopEnglishbreakfastPinmuxOutselGpioGpio1 = 4 , kTopEnglishbreakfastPinmuxOutselGpioGpio2 = 5 , kTopEnglishbreakfastPinmuxOutselGpioGpio3 = 6 , kTopEnglishbreakfastPinmuxOutselGpioGpio4 = 7 , kTopEnglishbreakfastPinmuxOutselGpioGpio5 = 8 , kTopEnglishbreakfastPinmuxOutselGpioGpio6 = 9 , kTopEnglishbreakfastPinmuxOutselGpioGpio7 = 10 , kTopEnglishbreakfastPinmuxOutselGpioGpio8 = 11 , kTopEnglishbreakfastPinmuxOutselGpioGpio9 = 12 , kTopEnglishbreakfastPinmuxOutselGpioGpio10 = 13 , kTopEnglishbreakfastPinmuxOutselGpioGpio11 = 14 , kTopEnglishbreakfastPinmuxOutselGpioGpio12 = 15 , kTopEnglishbreakfastPinmuxOutselGpioGpio13 = 16 , kTopEnglishbreakfastPinmuxOutselGpioGpio14 = 17 , kTopEnglishbreakfastPinmuxOutselGpioGpio15 = 18 , kTopEnglishbreakfastPinmuxOutselGpioGpio16 = 19 , kTopEnglishbreakfastPinmuxOutselGpioGpio17 = 20 , kTopEnglishbreakfastPinmuxOutselGpioGpio18 = 21 , kTopEnglishbreakfastPinmuxOutselGpioGpio19 = 22 , kTopEnglishbreakfastPinmuxOutselGpioGpio20 = 23 , kTopEnglishbreakfastPinmuxOutselGpioGpio21 = 24 , kTopEnglishbreakfastPinmuxOutselGpioGpio22 = 25 , kTopEnglishbreakfastPinmuxOutselGpioGpio23 = 26 , kTopEnglishbreakfastPinmuxOutselGpioGpio24 = 27 , kTopEnglishbreakfastPinmuxOutselGpioGpio25 = 28 , kTopEnglishbreakfastPinmuxOutselGpioGpio26 = 29 , kTopEnglishbreakfastPinmuxOutselGpioGpio27 = 30 , kTopEnglishbreakfastPinmuxOutselGpioGpio28 = 31 , kTopEnglishbreakfastPinmuxOutselGpioGpio29 = 32 , kTopEnglishbreakfastPinmuxOutselGpioGpio30 = 33 , kTopEnglishbreakfastPinmuxOutselGpioGpio31 = 34 , kTopEnglishbreakfastPinmuxOutselUart0Tx = 35 , kTopEnglishbreakfastPinmuxOutselUart1Tx = 36 , kTopEnglishbreakfastPinmuxOutselFlashCtrlTdo = 37 , kTopEnglishbreakfastPinmuxOutselLast = 37 }
	Pinmux Peripheral Output Selector. More...

enum	top_englishbreakfast_direct_pads { kTopEnglishbreakfastDirectPadsSpiHost0Sd0 = 0 , kTopEnglishbreakfastDirectPadsSpiHost0Sd1 = 1 , kTopEnglishbreakfastDirectPadsSpiHost0Sd2 = 2 , kTopEnglishbreakfastDirectPadsSpiHost0Sd3 = 3 , kTopEnglishbreakfastDirectPadsSpiDeviceSd0 = 4 , kTopEnglishbreakfastDirectPadsSpiDeviceSd1 = 5 , kTopEnglishbreakfastDirectPadsSpiDeviceSd2 = 6 , kTopEnglishbreakfastDirectPadsSpiDeviceSd3 = 7 , kTopEnglishbreakfastDirectPadsUsbdevUsbDp = 8 , kTopEnglishbreakfastDirectPadsUsbdevUsbDn = 9 , kTopEnglishbreakfastDirectPadsSpiDeviceSck = 10 , kTopEnglishbreakfastDirectPadsSpiDeviceCsb = 11 , kTopEnglishbreakfastDirectPadsSpiHost0Sck = 12 , kTopEnglishbreakfastDirectPadsSpiHost0Csb = 13 , kTopEnglishbreakfastDirectPadsLast = 13 }
	Dedicated Pad Selects. More...

enum	top_englishbreakfast_muxed_pads { kTopEnglishbreakfastMuxedPadsIoa0 = 0 , kTopEnglishbreakfastMuxedPadsIoa1 = 1 , kTopEnglishbreakfastMuxedPadsIoa2 = 2 , kTopEnglishbreakfastMuxedPadsIoa3 = 3 , kTopEnglishbreakfastMuxedPadsIoa4 = 4 , kTopEnglishbreakfastMuxedPadsIoa5 = 5 , kTopEnglishbreakfastMuxedPadsIoa6 = 6 , kTopEnglishbreakfastMuxedPadsIoa7 = 7 , kTopEnglishbreakfastMuxedPadsIoa8 = 8 , kTopEnglishbreakfastMuxedPadsIob0 = 9 , kTopEnglishbreakfastMuxedPadsIob1 = 10 , kTopEnglishbreakfastMuxedPadsIob2 = 11 , kTopEnglishbreakfastMuxedPadsIob3 = 12 , kTopEnglishbreakfastMuxedPadsIob4 = 13 , kTopEnglishbreakfastMuxedPadsIob5 = 14 , kTopEnglishbreakfastMuxedPadsIob6 = 15 , kTopEnglishbreakfastMuxedPadsIob7 = 16 , kTopEnglishbreakfastMuxedPadsIob8 = 17 , kTopEnglishbreakfastMuxedPadsIob9 = 18 , kTopEnglishbreakfastMuxedPadsIob10 = 19 , kTopEnglishbreakfastMuxedPadsIob11 = 20 , kTopEnglishbreakfastMuxedPadsIob12 = 21 , kTopEnglishbreakfastMuxedPadsIoc0 = 22 , kTopEnglishbreakfastMuxedPadsIoc1 = 23 , kTopEnglishbreakfastMuxedPadsIoc2 = 24 , kTopEnglishbreakfastMuxedPadsIoc3 = 25 , kTopEnglishbreakfastMuxedPadsIoc4 = 26 , kTopEnglishbreakfastMuxedPadsIoc5 = 27 , kTopEnglishbreakfastMuxedPadsIoc6 = 28 , kTopEnglishbreakfastMuxedPadsIoc7 = 29 , kTopEnglishbreakfastMuxedPadsIoc8 = 30 , kTopEnglishbreakfastMuxedPadsIoc9 = 31 , kTopEnglishbreakfastMuxedPadsIoc10 = 32 , kTopEnglishbreakfastMuxedPadsIoc11 = 33 , kTopEnglishbreakfastMuxedPadsIoc12 = 34 , kTopEnglishbreakfastMuxedPadsIor0 = 35 , kTopEnglishbreakfastMuxedPadsIor1 = 36 , kTopEnglishbreakfastMuxedPadsIor2 = 37 , kTopEnglishbreakfastMuxedPadsIor3 = 38 , kTopEnglishbreakfastMuxedPadsIor4 = 39 , kTopEnglishbreakfastMuxedPadsIor5 = 40 , kTopEnglishbreakfastMuxedPadsIor6 = 41 , kTopEnglishbreakfastMuxedPadsIor7 = 42 , kTopEnglishbreakfastMuxedPadsIor10 = 43 , kTopEnglishbreakfastMuxedPadsIor11 = 44 , kTopEnglishbreakfastMuxedPadsIor12 = 45 , kTopEnglishbreakfastMuxedPadsIor13 = 46 , kTopEnglishbreakfastMuxedPadsLast = 46 }
	Muxed Pad Selects. More...

enum	top_englishbreakfast_power_manager_wake_ups { kTopEnglishbreakfastPowerManagerWakeUpsPinmuxAonPinWkupReq = 0 , kTopEnglishbreakfastPowerManagerWakeUpsPinmuxAonUsbWkupReq = 1 , kTopEnglishbreakfastPowerManagerWakeUpsAonTimerAonWkupReq = 2 , kTopEnglishbreakfastPowerManagerWakeUpsLast = 2 }
	Power Manager Wakeup Signals. More...

enum	top_englishbreakfast_reset_manager_sw_resets { kTopEnglishbreakfastResetManagerSwResetsSpiDevice = 0 , kTopEnglishbreakfastResetManagerSwResetsSpiHost0 = 1 , kTopEnglishbreakfastResetManagerSwResetsUsb = 2 , kTopEnglishbreakfastResetManagerSwResetsLast = 2 }
	Reset Manager Software Controlled Resets. More...

enum	top_englishbreakfast_power_manager_reset_requests { kTopEnglishbreakfastPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 0 , kTopEnglishbreakfastPowerManagerResetRequestsLast = 0 }
	Power Manager Reset Request Signals. More...

enum	top_englishbreakfast_gateable_clocks { kTopEnglishbreakfastGateableClocksIoDiv4Peri = 0 , kTopEnglishbreakfastGateableClocksIoDiv2Peri = 1 , kTopEnglishbreakfastGateableClocksIoPeri = 2 , kTopEnglishbreakfastGateableClocksUsbPeri = 3 , kTopEnglishbreakfastGateableClocksLast = 3 }
	Clock Manager Software-Controlled ("Gated") Clocks. More...

enum	top_englishbreakfast_hintable_clocks { kTopEnglishbreakfastHintableClocksMainAes = 0 , kTopEnglishbreakfastHintableClocksLast = 0 }
	Clock Manager Software-Hinted Clocks. More...

Variables
const top_englishbreakfast_plic_peripheral_t	top_englishbreakfast_plic_interrupt_for_peripheral [88]
	PLIC Interrupt Source to Peripheral Map.

Detailed Description

Top-specific Definitions.

This file contains preprocessor and type definitions for use within the device C/C++ codebase.

These definitions are for information that depends on the top-specific chip configuration, which includes:

Device Memory Information (for Peripherals and Memory)
PLIC Interrupt ID Names and Source Mappings
Pinmux Pin/Select Names
Power Manager Wakeups

Definition in file top_englishbreakfast.h.

Macro Definition Documentation

◆ NUM_DIO_PADS

#define NUM_DIO_PADS 14

Definition at line 621 of file top_englishbreakfast.h.

◆ NUM_MIO_PADS

#define NUM_MIO_PADS 47

Definition at line 620 of file top_englishbreakfast.h.

◆ PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2

Definition at line 616 of file top_englishbreakfast.h.

◆ PINMUX_PERIPH_OUTSEL_IDX_OFFSET

#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3

Definition at line 623 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_AES_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_AES_BASE_ADDR 0x41100000u

Peripheral base address for aes in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 344 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_AES_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_AES_SIZE_BYTES 0x100u

Peripheral size for aes in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_AES_BASE_ADDR and TOP_ENGLISHBREAKFAST_AES_BASE_ADDR + TOP_ENGLISHBREAKFAST_AES_SIZE_BYTES.

Definition at line 354 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR 0x40470000u

Peripheral base address for aon_timer_aon in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 236 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_AON_TIMER_AON_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_AON_TIMER_AON_SIZE_BYTES 0x40u

Peripheral size for aon_timer_aon in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR and TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_AON_TIMER_AON_SIZE_BYTES.

Definition at line 246 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_AST_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_AST_BASE_ADDR 0x40480000u

Peripheral base address for ast in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 254 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_AST_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_AST_SIZE_BYTES 0x400u

Peripheral size for ast in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_AST_BASE_ADDR and TOP_ENGLISHBREAKFAST_AST_BASE_ADDR + TOP_ENGLISHBREAKFAST_AST_SIZE_BYTES.

Definition at line 264 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR 0x40420000u

Peripheral base address for clkmgr_aon in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 200 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_CLKMGR_AON_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_CLKMGR_AON_SIZE_BYTES 0x80u

Peripheral size for clkmgr_aon in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR and TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_CLKMGR_AON_SIZE_BYTES.

Definition at line 210 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_EFLASH_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_EFLASH_BASE_ADDR 0x20000000u

Memory base address for eflash in top englishbreakfast.

Definition at line 450 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_EFLASH_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_EFLASH_SIZE_BYTES 0x10000u

Memory size for eflash in top englishbreakfast.

Definition at line 455 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u

Peripheral base address for core device on flash_ctrl in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 272 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES 0x200u

Peripheral size for core device on flash_ctrl in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR and TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES.

Definition at line 282 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u

Peripheral base address for mem device on flash_ctrl in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 308 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_SIZE_BYTES 0x10000u

Peripheral size for mem device on flash_ctrl in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR and TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_SIZE_BYTES.

Definition at line 318 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u

Peripheral base address for prim device on flash_ctrl in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 290 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u

Peripheral size for prim device on flash_ctrl in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR and TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES.

Definition at line 300 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR 0x40040000u

Peripheral base address for gpio in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 74 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_GPIO_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_GPIO_SIZE_BYTES 0x80u

Peripheral size for gpio in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR and TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR + TOP_ENGLISHBREAKFAST_GPIO_SIZE_BYTES.

Definition at line 84 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_MMIO_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_MMIO_BASE_ADDR 0x40000000u

MMIO Region.

MMIO region excludes any memory that is separate from the module configuration space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM, spi_device memory, or usbdev memory are included.

Definition at line 959 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_MMIO_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_MMIO_SIZE_BYTES 0x10000000u

Definition at line 960 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR 0x40460000u

Peripheral base address for pinmux_aon in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 218 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_PINMUX_AON_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_PINMUX_AON_SIZE_BYTES 0x1000u

Peripheral size for pinmux_aon in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR and TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_PINMUX_AON_SIZE_BYTES.

Definition at line 228 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR 0x40400000u

Peripheral base address for pwrmgr_aon in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 164 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_PWRMGR_AON_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_PWRMGR_AON_SIZE_BYTES 0x80u

Peripheral size for pwrmgr_aon in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR and TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_PWRMGR_AON_SIZE_BYTES.

Definition at line 174 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RAM_MAIN_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_RAM_MAIN_BASE_ADDR 0x10000000u

Memory base address for ram_main in top englishbreakfast.

Definition at line 460 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RAM_MAIN_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_RAM_MAIN_SIZE_BYTES 0x20000u

Memory size for ram_main in top englishbreakfast.

Definition at line 465 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_ROM_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_ROM_BASE_ADDR 0x8000u

Memory base address for rom in top englishbreakfast.

Definition at line 470 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u

Peripheral base address for regs device on rom_ctrl in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 398 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_SIZE_BYTES 0x80u

Peripheral size for regs device on rom_ctrl in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR and TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR + TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_SIZE_BYTES.

Definition at line 408 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR 0x8000u

Peripheral base address for rom device on rom_ctrl in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 416 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_SIZE_BYTES 0x8000u

Peripheral size for rom device on rom_ctrl in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR and TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR + TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_SIZE_BYTES.

Definition at line 426 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_ROM_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_ROM_SIZE_BYTES 0x8000u

Memory size for rom in top englishbreakfast.

Definition at line 475 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR 0x40410000u

Peripheral base address for rstmgr_aon in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 182 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES 0x80u

Peripheral size for rstmgr_aon in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR and TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES.

Definition at line 192 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u

Peripheral base address for cfg device on rv_core_ibex in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 434 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u

Peripheral size for cfg device on rv_core_ibex in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR and TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_SIZE_BYTES.

Definition at line 444 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR 0x48000000u

Peripheral base address for rv_plic in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 326 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RV_PLIC_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_RV_PLIC_SIZE_BYTES 0x8000000u

Peripheral size for rv_plic in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR and TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR + TOP_ENGLISHBREAKFAST_RV_PLIC_SIZE_BYTES.

Definition at line 336 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR 0x40100000u

Peripheral base address for rv_timer in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 128 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_RV_TIMER_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_RV_TIMER_SIZE_BYTES 0x200u

Peripheral size for rv_timer in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR and TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR + TOP_ENGLISHBREAKFAST_RV_TIMER_SIZE_BYTES.

Definition at line 138 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR 0x40050000u

Peripheral base address for spi_device in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 92 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_SPI_DEVICE_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_SPI_DEVICE_SIZE_BYTES 0x2000u

Peripheral size for spi_device in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR and TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR + TOP_ENGLISHBREAKFAST_SPI_DEVICE_SIZE_BYTES.

Definition at line 102 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR 0x40060000u

Peripheral base address for spi_host0 in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 110 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_SPI_HOST0_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_SPI_HOST0_SIZE_BYTES 0x40u

Peripheral size for spi_host0 in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR and TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR + TOP_ENGLISHBREAKFAST_SPI_HOST0_SIZE_BYTES.

Definition at line 120 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u

Peripheral base address for ram device on sram_ctrl_main in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 380 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u

Peripheral size for ram device on sram_ctrl_main in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR and TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_SIZE_BYTES.

Definition at line 390 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u

Peripheral base address for regs device on sram_ctrl_main in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 362 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u

Peripheral size for regs device on sram_ctrl_main in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR and TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_SIZE_BYTES.

Definition at line 372 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR 0x40000000u

Peripheral base address for uart0 in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 38 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_UART0_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_UART0_SIZE_BYTES 0x40u

Peripheral size for uart0 in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR and TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR + TOP_ENGLISHBREAKFAST_UART0_SIZE_BYTES.

Definition at line 48 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR 0x40010000u

Peripheral base address for uart1 in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 56 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_UART1_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_UART1_SIZE_BYTES 0x40u

Peripheral size for uart1 in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR and TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR + TOP_ENGLISHBREAKFAST_UART1_SIZE_BYTES.

Definition at line 66 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR

#define TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR 0x40320000u

Peripheral base address for usbdev in top englishbreakfast.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 146 of file top_englishbreakfast.h.

◆ TOP_ENGLISHBREAKFAST_USBDEV_SIZE_BYTES

#define TOP_ENGLISHBREAKFAST_USBDEV_SIZE_BYTES 0x1000u

Peripheral size for usbdev in top englishbreakfast.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR and TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR + TOP_ENGLISHBREAKFAST_USBDEV_SIZE_BYTES.

Definition at line 156 of file top_englishbreakfast.h.

Typedef Documentation

◆ top_englishbreakfast_gateable_clocks_t

typedef enum top_englishbreakfast_gateable_clocks top_englishbreakfast_gateable_clocks_t

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

◆ top_englishbreakfast_hintable_clocks_t

typedef enum top_englishbreakfast_hintable_clocks top_englishbreakfast_hintable_clocks_t

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

◆ top_englishbreakfast_plic_irq_id_t

typedef enum top_englishbreakfast_plic_irq_id top_englishbreakfast_plic_irq_id_t

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

◆ top_englishbreakfast_plic_peripheral_t

typedef enum top_englishbreakfast_plic_peripheral top_englishbreakfast_plic_peripheral_t

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

◆ top_englishbreakfast_plic_target_t

typedef enum top_englishbreakfast_plic_target top_englishbreakfast_plic_target_t

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumeration Type Documentation

◆ top_englishbreakfast_direct_pads

enum top_englishbreakfast_direct_pads

Dedicated Pad Selects.

Definition at line 828 of file top_englishbreakfast.h.

◆ top_englishbreakfast_gateable_clocks

enum top_englishbreakfast_gateable_clocks

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

Enumerator
kTopEnglishbreakfastGateableClocksIoDiv4Peri	Clock clk_io_div4_peri in group peri.
kTopEnglishbreakfastGateableClocksIoDiv2Peri	Clock clk_io_div2_peri in group peri.
kTopEnglishbreakfastGateableClocksIoPeri	Clock clk_io_peri in group peri.
kTopEnglishbreakfastGateableClocksUsbPeri	Clock clk_usb_peri in group peri.

Definition at line 933 of file top_englishbreakfast.h.

◆ top_englishbreakfast_hintable_clocks

enum top_englishbreakfast_hintable_clocks

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

Enumerator
kTopEnglishbreakfastHintableClocksMainAes	Clock clk_main_aes in group trans.

Definition at line 947 of file top_englishbreakfast.h.

◆ top_englishbreakfast_muxed_pads

enum top_englishbreakfast_muxed_pads

Muxed Pad Selects.

Definition at line 849 of file top_englishbreakfast.h.

◆ top_englishbreakfast_pinmux_insel

enum top_englishbreakfast_pinmux_insel

Pinmux MIO Input Selector.

Enumerator
kTopEnglishbreakfastPinmuxInselConstantZero	Tie constantly to zero.
kTopEnglishbreakfastPinmuxInselConstantOne	Tie constantly to one.
kTopEnglishbreakfastPinmuxInselIoa0	MIO Pad 0.
kTopEnglishbreakfastPinmuxInselIoa1	MIO Pad 1.
kTopEnglishbreakfastPinmuxInselIoa2	MIO Pad 2.
kTopEnglishbreakfastPinmuxInselIoa3	MIO Pad 3.
kTopEnglishbreakfastPinmuxInselIoa4	MIO Pad 4.
kTopEnglishbreakfastPinmuxInselIoa5	MIO Pad 5.
kTopEnglishbreakfastPinmuxInselIoa6	MIO Pad 6.
kTopEnglishbreakfastPinmuxInselIoa7	MIO Pad 7.
kTopEnglishbreakfastPinmuxInselIoa8	MIO Pad 8.
kTopEnglishbreakfastPinmuxInselIob0	MIO Pad 9.
kTopEnglishbreakfastPinmuxInselIob1	MIO Pad 10.
kTopEnglishbreakfastPinmuxInselIob2	MIO Pad 11.
kTopEnglishbreakfastPinmuxInselIob3	MIO Pad 12.
kTopEnglishbreakfastPinmuxInselIob4	MIO Pad 13.
kTopEnglishbreakfastPinmuxInselIob5	MIO Pad 14.
kTopEnglishbreakfastPinmuxInselIob6	MIO Pad 15.
kTopEnglishbreakfastPinmuxInselIob7	MIO Pad 16.
kTopEnglishbreakfastPinmuxInselIob8	MIO Pad 17.
kTopEnglishbreakfastPinmuxInselIob9	MIO Pad 18.
kTopEnglishbreakfastPinmuxInselIob10	MIO Pad 19.
kTopEnglishbreakfastPinmuxInselIob11	MIO Pad 20.
kTopEnglishbreakfastPinmuxInselIob12	MIO Pad 21.
kTopEnglishbreakfastPinmuxInselIoc0	MIO Pad 22.
kTopEnglishbreakfastPinmuxInselIoc1	MIO Pad 23.
kTopEnglishbreakfastPinmuxInselIoc2	MIO Pad 24.
kTopEnglishbreakfastPinmuxInselIoc3	MIO Pad 25.
kTopEnglishbreakfastPinmuxInselIoc4	MIO Pad 26.
kTopEnglishbreakfastPinmuxInselIoc5	MIO Pad 27.
kTopEnglishbreakfastPinmuxInselIoc6	MIO Pad 28.
kTopEnglishbreakfastPinmuxInselIoc7	MIO Pad 29.
kTopEnglishbreakfastPinmuxInselIoc8	MIO Pad 30.
kTopEnglishbreakfastPinmuxInselIoc9	MIO Pad 31.
kTopEnglishbreakfastPinmuxInselIoc10	MIO Pad 32.
kTopEnglishbreakfastPinmuxInselIoc11	MIO Pad 33.
kTopEnglishbreakfastPinmuxInselIoc12	MIO Pad 34.
kTopEnglishbreakfastPinmuxInselIor0	MIO Pad 35.
kTopEnglishbreakfastPinmuxInselIor1	MIO Pad 36.
kTopEnglishbreakfastPinmuxInselIor2	MIO Pad 37.
kTopEnglishbreakfastPinmuxInselIor3	MIO Pad 38.
kTopEnglishbreakfastPinmuxInselIor4	MIO Pad 39.
kTopEnglishbreakfastPinmuxInselIor5	MIO Pad 40.
kTopEnglishbreakfastPinmuxInselIor6	MIO Pad 41.
kTopEnglishbreakfastPinmuxInselIor7	MIO Pad 42.
kTopEnglishbreakfastPinmuxInselIor10	MIO Pad 43.
kTopEnglishbreakfastPinmuxInselIor11	MIO Pad 44.
kTopEnglishbreakfastPinmuxInselIor12	MIO Pad 45.
kTopEnglishbreakfastPinmuxInselIor13	MIO Pad 46.

Definition at line 673 of file top_englishbreakfast.h.

◆ top_englishbreakfast_pinmux_mio_out

enum top_englishbreakfast_pinmux_mio_out

Pinmux MIO Output.

Enumerator
kTopEnglishbreakfastPinmuxMioOutIoa0	MIO Pad 0.
kTopEnglishbreakfastPinmuxMioOutIoa1	MIO Pad 1.
kTopEnglishbreakfastPinmuxMioOutIoa2	MIO Pad 2.
kTopEnglishbreakfastPinmuxMioOutIoa3	MIO Pad 3.
kTopEnglishbreakfastPinmuxMioOutIoa4	MIO Pad 4.
kTopEnglishbreakfastPinmuxMioOutIoa5	MIO Pad 5.
kTopEnglishbreakfastPinmuxMioOutIoa6	MIO Pad 6.
kTopEnglishbreakfastPinmuxMioOutIoa7	MIO Pad 7.
kTopEnglishbreakfastPinmuxMioOutIoa8	MIO Pad 8.
kTopEnglishbreakfastPinmuxMioOutIob0	MIO Pad 9.
kTopEnglishbreakfastPinmuxMioOutIob1	MIO Pad 10.
kTopEnglishbreakfastPinmuxMioOutIob2	MIO Pad 11.
kTopEnglishbreakfastPinmuxMioOutIob3	MIO Pad 12.
kTopEnglishbreakfastPinmuxMioOutIob4	MIO Pad 13.
kTopEnglishbreakfastPinmuxMioOutIob5	MIO Pad 14.
kTopEnglishbreakfastPinmuxMioOutIob6	MIO Pad 15.
kTopEnglishbreakfastPinmuxMioOutIob7	MIO Pad 16.
kTopEnglishbreakfastPinmuxMioOutIob8	MIO Pad 17.
kTopEnglishbreakfastPinmuxMioOutIob9	MIO Pad 18.
kTopEnglishbreakfastPinmuxMioOutIob10	MIO Pad 19.
kTopEnglishbreakfastPinmuxMioOutIob11	MIO Pad 20.
kTopEnglishbreakfastPinmuxMioOutIob12	MIO Pad 21.
kTopEnglishbreakfastPinmuxMioOutIoc0	MIO Pad 22.
kTopEnglishbreakfastPinmuxMioOutIoc1	MIO Pad 23.
kTopEnglishbreakfastPinmuxMioOutIoc2	MIO Pad 24.
kTopEnglishbreakfastPinmuxMioOutIoc3	MIO Pad 25.
kTopEnglishbreakfastPinmuxMioOutIoc4	MIO Pad 26.
kTopEnglishbreakfastPinmuxMioOutIoc5	MIO Pad 27.
kTopEnglishbreakfastPinmuxMioOutIoc6	MIO Pad 28.
kTopEnglishbreakfastPinmuxMioOutIoc7	MIO Pad 29.
kTopEnglishbreakfastPinmuxMioOutIoc8	MIO Pad 30.
kTopEnglishbreakfastPinmuxMioOutIoc9	MIO Pad 31.
kTopEnglishbreakfastPinmuxMioOutIoc10	MIO Pad 32.
kTopEnglishbreakfastPinmuxMioOutIoc11	MIO Pad 33.
kTopEnglishbreakfastPinmuxMioOutIoc12	MIO Pad 34.
kTopEnglishbreakfastPinmuxMioOutIor0	MIO Pad 35.
kTopEnglishbreakfastPinmuxMioOutIor1	MIO Pad 36.
kTopEnglishbreakfastPinmuxMioOutIor2	MIO Pad 37.
kTopEnglishbreakfastPinmuxMioOutIor3	MIO Pad 38.
kTopEnglishbreakfastPinmuxMioOutIor4	MIO Pad 39.
kTopEnglishbreakfastPinmuxMioOutIor5	MIO Pad 40.
kTopEnglishbreakfastPinmuxMioOutIor6	MIO Pad 41.
kTopEnglishbreakfastPinmuxMioOutIor7	MIO Pad 42.
kTopEnglishbreakfastPinmuxMioOutIor10	MIO Pad 43.
kTopEnglishbreakfastPinmuxMioOutIor11	MIO Pad 44.
kTopEnglishbreakfastPinmuxMioOutIor12	MIO Pad 45.
kTopEnglishbreakfastPinmuxMioOutIor13	MIO Pad 46.

Definition at line 729 of file top_englishbreakfast.h.

◆ top_englishbreakfast_pinmux_outsel

enum top_englishbreakfast_pinmux_outsel

Pinmux Peripheral Output Selector.

Enumerator
kTopEnglishbreakfastPinmuxOutselConstantZero	Tie constantly to zero.
kTopEnglishbreakfastPinmuxOutselConstantOne	Tie constantly to one.
kTopEnglishbreakfastPinmuxOutselConstantHighZ	Tie constantly to high-Z.
kTopEnglishbreakfastPinmuxOutselGpioGpio0	Peripheral Output 0.
kTopEnglishbreakfastPinmuxOutselGpioGpio1	Peripheral Output 1.
kTopEnglishbreakfastPinmuxOutselGpioGpio2	Peripheral Output 2.
kTopEnglishbreakfastPinmuxOutselGpioGpio3	Peripheral Output 3.
kTopEnglishbreakfastPinmuxOutselGpioGpio4	Peripheral Output 4.
kTopEnglishbreakfastPinmuxOutselGpioGpio5	Peripheral Output 5.
kTopEnglishbreakfastPinmuxOutselGpioGpio6	Peripheral Output 6.
kTopEnglishbreakfastPinmuxOutselGpioGpio7	Peripheral Output 7.
kTopEnglishbreakfastPinmuxOutselGpioGpio8	Peripheral Output 8.
kTopEnglishbreakfastPinmuxOutselGpioGpio9	Peripheral Output 9.
kTopEnglishbreakfastPinmuxOutselGpioGpio10	Peripheral Output 10.
kTopEnglishbreakfastPinmuxOutselGpioGpio11	Peripheral Output 11.
kTopEnglishbreakfastPinmuxOutselGpioGpio12	Peripheral Output 12.
kTopEnglishbreakfastPinmuxOutselGpioGpio13	Peripheral Output 13.
kTopEnglishbreakfastPinmuxOutselGpioGpio14	Peripheral Output 14.
kTopEnglishbreakfastPinmuxOutselGpioGpio15	Peripheral Output 15.
kTopEnglishbreakfastPinmuxOutselGpioGpio16	Peripheral Output 16.
kTopEnglishbreakfastPinmuxOutselGpioGpio17	Peripheral Output 17.
kTopEnglishbreakfastPinmuxOutselGpioGpio18	Peripheral Output 18.
kTopEnglishbreakfastPinmuxOutselGpioGpio19	Peripheral Output 19.
kTopEnglishbreakfastPinmuxOutselGpioGpio20	Peripheral Output 20.
kTopEnglishbreakfastPinmuxOutselGpioGpio21	Peripheral Output 21.
kTopEnglishbreakfastPinmuxOutselGpioGpio22	Peripheral Output 22.
kTopEnglishbreakfastPinmuxOutselGpioGpio23	Peripheral Output 23.
kTopEnglishbreakfastPinmuxOutselGpioGpio24	Peripheral Output 24.
kTopEnglishbreakfastPinmuxOutselGpioGpio25	Peripheral Output 25.
kTopEnglishbreakfastPinmuxOutselGpioGpio26	Peripheral Output 26.
kTopEnglishbreakfastPinmuxOutselGpioGpio27	Peripheral Output 27.
kTopEnglishbreakfastPinmuxOutselGpioGpio28	Peripheral Output 28.
kTopEnglishbreakfastPinmuxOutselGpioGpio29	Peripheral Output 29.
kTopEnglishbreakfastPinmuxOutselGpioGpio30	Peripheral Output 30.
kTopEnglishbreakfastPinmuxOutselGpioGpio31	Peripheral Output 31.
kTopEnglishbreakfastPinmuxOutselUart0Tx	Peripheral Output 32.
kTopEnglishbreakfastPinmuxOutselUart1Tx	Peripheral Output 33.
kTopEnglishbreakfastPinmuxOutselFlashCtrlTdo	Peripheral Output 34.

Definition at line 783 of file top_englishbreakfast.h.

◆ top_englishbreakfast_pinmux_peripheral_in

enum top_englishbreakfast_pinmux_peripheral_in

Pinmux Peripheral Input.

Enumerator
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio0	Peripheral Input 0.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio1	Peripheral Input 1.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio2	Peripheral Input 2.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio3	Peripheral Input 3.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio4	Peripheral Input 4.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio5	Peripheral Input 5.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio6	Peripheral Input 6.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio7	Peripheral Input 7.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio8	Peripheral Input 8.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio9	Peripheral Input 9.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio10	Peripheral Input 10.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio11	Peripheral Input 11.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio12	Peripheral Input 12.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio13	Peripheral Input 13.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio14	Peripheral Input 14.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio15	Peripheral Input 15.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio16	Peripheral Input 16.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio17	Peripheral Input 17.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio18	Peripheral Input 18.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio19	Peripheral Input 19.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio20	Peripheral Input 20.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio21	Peripheral Input 21.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio22	Peripheral Input 22.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio23	Peripheral Input 23.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio24	Peripheral Input 24.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio25	Peripheral Input 25.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio26	Peripheral Input 26.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio27	Peripheral Input 27.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio28	Peripheral Input 28.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio29	Peripheral Input 29.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio30	Peripheral Input 30.
kTopEnglishbreakfastPinmuxPeripheralInGpioGpio31	Peripheral Input 31.
kTopEnglishbreakfastPinmuxPeripheralInUart0Rx	Peripheral Input 32.
kTopEnglishbreakfastPinmuxPeripheralInUart1Rx	Peripheral Input 33.
kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTck	Peripheral Input 34.
kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTms	Peripheral Input 35.
kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTdi	Peripheral Input 36.
kTopEnglishbreakfastPinmuxPeripheralInUsbdevSense	Peripheral Input 37.

Definition at line 628 of file top_englishbreakfast.h.

◆ top_englishbreakfast_plic_irq_id

enum top_englishbreakfast_plic_irq_id

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopEnglishbreakfastPlicIrqIdNone	No Interrupt.
kTopEnglishbreakfastPlicIrqIdUart0TxWatermark	uart0_tx_watermark
kTopEnglishbreakfastPlicIrqIdUart0RxWatermark	uart0_rx_watermark
kTopEnglishbreakfastPlicIrqIdUart0TxDone	uart0_tx_done
kTopEnglishbreakfastPlicIrqIdUart0RxOverflow	uart0_rx_overflow
kTopEnglishbreakfastPlicIrqIdUart0RxFrameErr	uart0_rx_frame_err
kTopEnglishbreakfastPlicIrqIdUart0RxBreakErr	uart0_rx_break_err
kTopEnglishbreakfastPlicIrqIdUart0RxTimeout	uart0_rx_timeout
kTopEnglishbreakfastPlicIrqIdUart0RxParityErr	uart0_rx_parity_err
kTopEnglishbreakfastPlicIrqIdUart0TxEmpty	uart0_tx_empty
kTopEnglishbreakfastPlicIrqIdUart1TxWatermark	uart1_tx_watermark
kTopEnglishbreakfastPlicIrqIdUart1RxWatermark	uart1_rx_watermark
kTopEnglishbreakfastPlicIrqIdUart1TxDone	uart1_tx_done
kTopEnglishbreakfastPlicIrqIdUart1RxOverflow	uart1_rx_overflow
kTopEnglishbreakfastPlicIrqIdUart1RxFrameErr	uart1_rx_frame_err
kTopEnglishbreakfastPlicIrqIdUart1RxBreakErr	uart1_rx_break_err
kTopEnglishbreakfastPlicIrqIdUart1RxTimeout	uart1_rx_timeout
kTopEnglishbreakfastPlicIrqIdUart1RxParityErr	uart1_rx_parity_err
kTopEnglishbreakfastPlicIrqIdUart1TxEmpty	uart1_tx_empty
kTopEnglishbreakfastPlicIrqIdGpioGpio0	gpio_gpio 0
kTopEnglishbreakfastPlicIrqIdGpioGpio1	gpio_gpio 1
kTopEnglishbreakfastPlicIrqIdGpioGpio2	gpio_gpio 2
kTopEnglishbreakfastPlicIrqIdGpioGpio3	gpio_gpio 3
kTopEnglishbreakfastPlicIrqIdGpioGpio4	gpio_gpio 4
kTopEnglishbreakfastPlicIrqIdGpioGpio5	gpio_gpio 5
kTopEnglishbreakfastPlicIrqIdGpioGpio6	gpio_gpio 6
kTopEnglishbreakfastPlicIrqIdGpioGpio7	gpio_gpio 7
kTopEnglishbreakfastPlicIrqIdGpioGpio8	gpio_gpio 8
kTopEnglishbreakfastPlicIrqIdGpioGpio9	gpio_gpio 9
kTopEnglishbreakfastPlicIrqIdGpioGpio10	gpio_gpio 10
kTopEnglishbreakfastPlicIrqIdGpioGpio11	gpio_gpio 11
kTopEnglishbreakfastPlicIrqIdGpioGpio12	gpio_gpio 12
kTopEnglishbreakfastPlicIrqIdGpioGpio13	gpio_gpio 13
kTopEnglishbreakfastPlicIrqIdGpioGpio14	gpio_gpio 14
kTopEnglishbreakfastPlicIrqIdGpioGpio15	gpio_gpio 15
kTopEnglishbreakfastPlicIrqIdGpioGpio16	gpio_gpio 16
kTopEnglishbreakfastPlicIrqIdGpioGpio17	gpio_gpio 17
kTopEnglishbreakfastPlicIrqIdGpioGpio18	gpio_gpio 18
kTopEnglishbreakfastPlicIrqIdGpioGpio19	gpio_gpio 19
kTopEnglishbreakfastPlicIrqIdGpioGpio20	gpio_gpio 20
kTopEnglishbreakfastPlicIrqIdGpioGpio21	gpio_gpio 21
kTopEnglishbreakfastPlicIrqIdGpioGpio22	gpio_gpio 22
kTopEnglishbreakfastPlicIrqIdGpioGpio23	gpio_gpio 23
kTopEnglishbreakfastPlicIrqIdGpioGpio24	gpio_gpio 24
kTopEnglishbreakfastPlicIrqIdGpioGpio25	gpio_gpio 25
kTopEnglishbreakfastPlicIrqIdGpioGpio26	gpio_gpio 26
kTopEnglishbreakfastPlicIrqIdGpioGpio27	gpio_gpio 27
kTopEnglishbreakfastPlicIrqIdGpioGpio28	gpio_gpio 28
kTopEnglishbreakfastPlicIrqIdGpioGpio29	gpio_gpio 29
kTopEnglishbreakfastPlicIrqIdGpioGpio30	gpio_gpio 30
kTopEnglishbreakfastPlicIrqIdGpioGpio31	gpio_gpio 31
kTopEnglishbreakfastPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty	spi_device_upload_cmdfifo_not_empty
kTopEnglishbreakfastPlicIrqIdSpiDeviceUploadPayloadNotEmpty	spi_device_upload_payload_not_empty
kTopEnglishbreakfastPlicIrqIdSpiDeviceUploadPayloadOverflow	spi_device_upload_payload_overflow
kTopEnglishbreakfastPlicIrqIdSpiDeviceReadbufWatermark	spi_device_readbuf_watermark
kTopEnglishbreakfastPlicIrqIdSpiDeviceReadbufFlip	spi_device_readbuf_flip
kTopEnglishbreakfastPlicIrqIdSpiDeviceTpmHeaderNotEmpty	spi_device_tpm_header_not_empty
kTopEnglishbreakfastPlicIrqIdSpiDeviceTpmRdfifoCmdEnd	spi_device_tpm_rdfifo_cmd_end
kTopEnglishbreakfastPlicIrqIdSpiDeviceTpmRdfifoDrop	spi_device_tpm_rdfifo_drop
kTopEnglishbreakfastPlicIrqIdSpiHost0Error	spi_host0_error
kTopEnglishbreakfastPlicIrqIdSpiHost0SpiEvent	spi_host0_spi_event
kTopEnglishbreakfastPlicIrqIdUsbdevPktReceived	usbdev_pkt_received
kTopEnglishbreakfastPlicIrqIdUsbdevPktSent	usbdev_pkt_sent
kTopEnglishbreakfastPlicIrqIdUsbdevDisconnected	usbdev_disconnected
kTopEnglishbreakfastPlicIrqIdUsbdevHostLost	usbdev_host_lost
kTopEnglishbreakfastPlicIrqIdUsbdevLinkReset	usbdev_link_reset
kTopEnglishbreakfastPlicIrqIdUsbdevLinkSuspend	usbdev_link_suspend
kTopEnglishbreakfastPlicIrqIdUsbdevLinkResume	usbdev_link_resume
kTopEnglishbreakfastPlicIrqIdUsbdevAvOutEmpty	usbdev_av_out_empty
kTopEnglishbreakfastPlicIrqIdUsbdevRxFull	usbdev_rx_full
kTopEnglishbreakfastPlicIrqIdUsbdevAvOverflow	usbdev_av_overflow
kTopEnglishbreakfastPlicIrqIdUsbdevLinkInErr	usbdev_link_in_err
kTopEnglishbreakfastPlicIrqIdUsbdevRxCrcErr	usbdev_rx_crc_err
kTopEnglishbreakfastPlicIrqIdUsbdevRxPidErr	usbdev_rx_pid_err
kTopEnglishbreakfastPlicIrqIdUsbdevRxBitstuffErr	usbdev_rx_bitstuff_err
kTopEnglishbreakfastPlicIrqIdUsbdevFrame	usbdev_frame
kTopEnglishbreakfastPlicIrqIdUsbdevPowered	usbdev_powered
kTopEnglishbreakfastPlicIrqIdUsbdevLinkOutErr	usbdev_link_out_err
kTopEnglishbreakfastPlicIrqIdUsbdevAvSetupEmpty	usbdev_av_setup_empty
kTopEnglishbreakfastPlicIrqIdPwrmgrAonWakeup	pwrmgr_aon_wakeup
kTopEnglishbreakfastPlicIrqIdAonTimerAonWkupTimerExpired	aon_timer_aon_wkup_timer_expired
kTopEnglishbreakfastPlicIrqIdAonTimerAonWdogTimerBark	aon_timer_aon_wdog_timer_bark
kTopEnglishbreakfastPlicIrqIdFlashCtrlProgEmpty	flash_ctrl_prog_empty
kTopEnglishbreakfastPlicIrqIdFlashCtrlProgLvl	flash_ctrl_prog_lvl
kTopEnglishbreakfastPlicIrqIdFlashCtrlRdFull	flash_ctrl_rd_full
kTopEnglishbreakfastPlicIrqIdFlashCtrlRdLvl	flash_ctrl_rd_lvl
kTopEnglishbreakfastPlicIrqIdFlashCtrlOpDone	flash_ctrl_op_done
kTopEnglishbreakfastPlicIrqIdFlashCtrlCorrErr	flash_ctrl_corr_err

Definition at line 504 of file top_englishbreakfast.h.

◆ top_englishbreakfast_plic_peripheral

enum top_englishbreakfast_plic_peripheral

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

Enumerator
kTopEnglishbreakfastPlicPeripheralUnknown	Unknown Peripheral.
kTopEnglishbreakfastPlicPeripheralUart0	uart0
kTopEnglishbreakfastPlicPeripheralUart1	uart1
kTopEnglishbreakfastPlicPeripheralGpio	gpio
kTopEnglishbreakfastPlicPeripheralSpiDevice	spi_device
kTopEnglishbreakfastPlicPeripheralSpiHost0	spi_host0
kTopEnglishbreakfastPlicPeripheralUsbdev	usbdev
kTopEnglishbreakfastPlicPeripheralPwrmgrAon	pwrmgr_aon
kTopEnglishbreakfastPlicPeripheralAonTimerAon	aon_timer_aon
kTopEnglishbreakfastPlicPeripheralFlashCtrl	flash_ctrl

Definition at line 484 of file top_englishbreakfast.h.

◆ top_englishbreakfast_plic_target

enum top_englishbreakfast_plic_target

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumerator
kTopEnglishbreakfastPlicTargetIbex0	Ibex Core 0.

Definition at line 611 of file top_englishbreakfast.h.

◆ top_englishbreakfast_power_manager_reset_requests

enum top_englishbreakfast_power_manager_reset_requests

Power Manager Reset Request Signals.

Definition at line 923 of file top_englishbreakfast.h.

◆ top_englishbreakfast_power_manager_wake_ups

enum top_englishbreakfast_power_manager_wake_ups

Power Manager Wakeup Signals.

Definition at line 903 of file top_englishbreakfast.h.

◆ top_englishbreakfast_reset_manager_sw_resets

enum top_englishbreakfast_reset_manager_sw_resets

Reset Manager Software Controlled Resets.

Definition at line 913 of file top_englishbreakfast.h.

Variable Documentation

◆ top_englishbreakfast_plic_interrupt_for_peripheral

const top_englishbreakfast_plic_peripheral_t top_englishbreakfast_plic_interrupt_for_peripheral[88]

extern

PLIC Interrupt Source to Peripheral Map.

This array is a mapping from top_englishbreakfast_plic_irq_id_t to top_englishbreakfast_plic_peripheral_t.

Definition at line 19 of file top_englishbreakfast.c.

Macros

Typedefs

Enumerations

Variables

Detailed Description

Macro Definition Documentation

◆ NUM_DIO_PADS

◆ NUM_MIO_PADS

◆ PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET

◆ PINMUX_PERIPH_OUTSEL_IDX_OFFSET

◆ TOP_ENGLISHBREAKFAST_AES_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_AES_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_AON_TIMER_AON_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_AST_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_AST_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_CLKMGR_AON_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_EFLASH_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_EFLASH_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_GPIO_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_MMIO_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_MMIO_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_PINMUX_AON_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_PWRMGR_AON_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_RAM_MAIN_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_RAM_MAIN_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_ROM_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_ROM_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_RV_PLIC_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_RV_TIMER_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_SPI_DEVICE_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_SPI_HOST0_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_UART0_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_UART1_SIZE_BYTES

◆ TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR

◆ TOP_ENGLISHBREAKFAST_USBDEV_SIZE_BYTES

Typedef Documentation

◆ top_englishbreakfast_gateable_clocks_t

◆ top_englishbreakfast_hintable_clocks_t

◆ top_englishbreakfast_plic_irq_id_t

◆ top_englishbreakfast_plic_peripheral_t

◆ top_englishbreakfast_plic_target_t

Enumeration Type Documentation

◆ top_englishbreakfast_direct_pads

◆ top_englishbreakfast_gateable_clocks

◆ top_englishbreakfast_hintable_clocks

◆ top_englishbreakfast_muxed_pads

◆ top_englishbreakfast_pinmux_insel

◆ top_englishbreakfast_pinmux_mio_out

◆ top_englishbreakfast_pinmux_outsel

◆ top_englishbreakfast_pinmux_peripheral_in

◆ top_englishbreakfast_plic_irq_id