Software APIs
top_englishbreakfast.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
6// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
7// util/topgen.py -t hw/top_englishbreakfast/data/top_englishbreakfast.hjson \
8// -o hw/top_englishbreakfast/
9
10#ifndef OPENTITAN_HW_TOP_ENGLISHBREAKFAST_SW_AUTOGEN_TOP_ENGLISHBREAKFAST_H_
11#define OPENTITAN_HW_TOP_ENGLISHBREAKFAST_SW_AUTOGEN_TOP_ENGLISHBREAKFAST_H_
12
13/**
14 * @file
15 * @brief Top-specific Definitions
16 *
17 * This file contains preprocessor and type definitions for use within the
18 * device C/C++ codebase.
19 *
20 * These definitions are for information that depends on the top-specific chip
21 * configuration, which includes:
22 * - Device Memory Information (for Peripherals and Memory)
23 * - PLIC Interrupt ID Names and Source Mappings
24 * - Pinmux Pin/Select Names
25 * - Power Manager Wakeups
26 */
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32/**
33 * Peripheral base address for uart0 in top englishbreakfast.
34 *
35 * This should be used with #mmio_region_from_addr to access the memory-mapped
36 * registers associated with the peripheral (usually via a DIF).
37 */
38#define TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR 0x40000000u
39
40/**
41 * Peripheral size for uart0 in top englishbreakfast.
42 *
43 * This is the size (in bytes) of the peripheral's reserved memory area. All
44 * memory-mapped registers associated with this peripheral should have an
45 * address between #TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR and
46 * `TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR + TOP_ENGLISHBREAKFAST_UART0_SIZE_BYTES`.
47 */
48#define TOP_ENGLISHBREAKFAST_UART0_SIZE_BYTES 0x40u
49
50/**
51 * Peripheral base address for uart1 in top englishbreakfast.
52 *
53 * This should be used with #mmio_region_from_addr to access the memory-mapped
54 * registers associated with the peripheral (usually via a DIF).
55 */
56#define TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR 0x40010000u
57
58/**
59 * Peripheral size for uart1 in top englishbreakfast.
60 *
61 * This is the size (in bytes) of the peripheral's reserved memory area. All
62 * memory-mapped registers associated with this peripheral should have an
63 * address between #TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR and
64 * `TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR + TOP_ENGLISHBREAKFAST_UART1_SIZE_BYTES`.
65 */
66#define TOP_ENGLISHBREAKFAST_UART1_SIZE_BYTES 0x40u
67
68/**
69 * Peripheral base address for gpio in top englishbreakfast.
70 *
71 * This should be used with #mmio_region_from_addr to access the memory-mapped
72 * registers associated with the peripheral (usually via a DIF).
73 */
74#define TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR 0x40040000u
75
76/**
77 * Peripheral size for gpio in top englishbreakfast.
78 *
79 * This is the size (in bytes) of the peripheral's reserved memory area. All
80 * memory-mapped registers associated with this peripheral should have an
81 * address between #TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR and
82 * `TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR + TOP_ENGLISHBREAKFAST_GPIO_SIZE_BYTES`.
83 */
84#define TOP_ENGLISHBREAKFAST_GPIO_SIZE_BYTES 0x80u
85
86/**
87 * Peripheral base address for spi_device in top englishbreakfast.
88 *
89 * This should be used with #mmio_region_from_addr to access the memory-mapped
90 * registers associated with the peripheral (usually via a DIF).
91 */
92#define TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR 0x40050000u
93
94/**
95 * Peripheral size for spi_device in top englishbreakfast.
96 *
97 * This is the size (in bytes) of the peripheral's reserved memory area. All
98 * memory-mapped registers associated with this peripheral should have an
99 * address between #TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR and
100 * `TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR + TOP_ENGLISHBREAKFAST_SPI_DEVICE_SIZE_BYTES`.
101 */
102#define TOP_ENGLISHBREAKFAST_SPI_DEVICE_SIZE_BYTES 0x2000u
103
104/**
105 * Peripheral base address for spi_host0 in top englishbreakfast.
106 *
107 * This should be used with #mmio_region_from_addr to access the memory-mapped
108 * registers associated with the peripheral (usually via a DIF).
109 */
110#define TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR 0x40060000u
111
112/**
113 * Peripheral size for spi_host0 in top englishbreakfast.
114 *
115 * This is the size (in bytes) of the peripheral's reserved memory area. All
116 * memory-mapped registers associated with this peripheral should have an
117 * address between #TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR and
118 * `TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR + TOP_ENGLISHBREAKFAST_SPI_HOST0_SIZE_BYTES`.
119 */
120#define TOP_ENGLISHBREAKFAST_SPI_HOST0_SIZE_BYTES 0x40u
121
122/**
123 * Peripheral base address for rv_timer in top englishbreakfast.
124 *
125 * This should be used with #mmio_region_from_addr to access the memory-mapped
126 * registers associated with the peripheral (usually via a DIF).
127 */
128#define TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR 0x40100000u
129
130/**
131 * Peripheral size for rv_timer in top englishbreakfast.
132 *
133 * This is the size (in bytes) of the peripheral's reserved memory area. All
134 * memory-mapped registers associated with this peripheral should have an
135 * address between #TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR and
136 * `TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR + TOP_ENGLISHBREAKFAST_RV_TIMER_SIZE_BYTES`.
137 */
138#define TOP_ENGLISHBREAKFAST_RV_TIMER_SIZE_BYTES 0x200u
139
140/**
141 * Peripheral base address for usbdev in top englishbreakfast.
142 *
143 * This should be used with #mmio_region_from_addr to access the memory-mapped
144 * registers associated with the peripheral (usually via a DIF).
145 */
146#define TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR 0x40320000u
147
148/**
149 * Peripheral size for usbdev in top englishbreakfast.
150 *
151 * This is the size (in bytes) of the peripheral's reserved memory area. All
152 * memory-mapped registers associated with this peripheral should have an
153 * address between #TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR and
154 * `TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR + TOP_ENGLISHBREAKFAST_USBDEV_SIZE_BYTES`.
155 */
156#define TOP_ENGLISHBREAKFAST_USBDEV_SIZE_BYTES 0x1000u
157
158/**
159 * Peripheral base address for pwrmgr_aon in top englishbreakfast.
160 *
161 * This should be used with #mmio_region_from_addr to access the memory-mapped
162 * registers associated with the peripheral (usually via a DIF).
163 */
164#define TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR 0x40400000u
165
166/**
167 * Peripheral size for pwrmgr_aon in top englishbreakfast.
168 *
169 * This is the size (in bytes) of the peripheral's reserved memory area. All
170 * memory-mapped registers associated with this peripheral should have an
171 * address between #TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR and
172 * `TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_PWRMGR_AON_SIZE_BYTES`.
173 */
174#define TOP_ENGLISHBREAKFAST_PWRMGR_AON_SIZE_BYTES 0x80u
175
176/**
177 * Peripheral base address for rstmgr_aon in top englishbreakfast.
178 *
179 * This should be used with #mmio_region_from_addr to access the memory-mapped
180 * registers associated with the peripheral (usually via a DIF).
181 */
182#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR 0x40410000u
183
184/**
185 * Peripheral size for rstmgr_aon in top englishbreakfast.
186 *
187 * This is the size (in bytes) of the peripheral's reserved memory area. All
188 * memory-mapped registers associated with this peripheral should have an
189 * address between #TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR and
190 * `TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES`.
191 */
192#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES 0x80u
193
194/**
195 * Peripheral base address for clkmgr_aon in top englishbreakfast.
196 *
197 * This should be used with #mmio_region_from_addr to access the memory-mapped
198 * registers associated with the peripheral (usually via a DIF).
199 */
200#define TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR 0x40420000u
201
202/**
203 * Peripheral size for clkmgr_aon in top englishbreakfast.
204 *
205 * This is the size (in bytes) of the peripheral's reserved memory area. All
206 * memory-mapped registers associated with this peripheral should have an
207 * address between #TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR and
208 * `TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_CLKMGR_AON_SIZE_BYTES`.
209 */
210#define TOP_ENGLISHBREAKFAST_CLKMGR_AON_SIZE_BYTES 0x80u
211
212/**
213 * Peripheral base address for pinmux_aon in top englishbreakfast.
214 *
215 * This should be used with #mmio_region_from_addr to access the memory-mapped
216 * registers associated with the peripheral (usually via a DIF).
217 */
218#define TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR 0x40460000u
219
220/**
221 * Peripheral size for pinmux_aon in top englishbreakfast.
222 *
223 * This is the size (in bytes) of the peripheral's reserved memory area. All
224 * memory-mapped registers associated with this peripheral should have an
225 * address between #TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR and
226 * `TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_PINMUX_AON_SIZE_BYTES`.
227 */
228#define TOP_ENGLISHBREAKFAST_PINMUX_AON_SIZE_BYTES 0x1000u
229
230/**
231 * Peripheral base address for aon_timer_aon in top englishbreakfast.
232 *
233 * This should be used with #mmio_region_from_addr to access the memory-mapped
234 * registers associated with the peripheral (usually via a DIF).
235 */
236#define TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR 0x40470000u
237
238/**
239 * Peripheral size for aon_timer_aon in top englishbreakfast.
240 *
241 * This is the size (in bytes) of the peripheral's reserved memory area. All
242 * memory-mapped registers associated with this peripheral should have an
243 * address between #TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR and
244 * `TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_AON_TIMER_AON_SIZE_BYTES`.
245 */
246#define TOP_ENGLISHBREAKFAST_AON_TIMER_AON_SIZE_BYTES 0x40u
247
248/**
249 * Peripheral base address for ast in top englishbreakfast.
250 *
251 * This should be used with #mmio_region_from_addr to access the memory-mapped
252 * registers associated with the peripheral (usually via a DIF).
253 */
254#define TOP_ENGLISHBREAKFAST_AST_BASE_ADDR 0x40480000u
255
256/**
257 * Peripheral size for ast in top englishbreakfast.
258 *
259 * This is the size (in bytes) of the peripheral's reserved memory area. All
260 * memory-mapped registers associated with this peripheral should have an
261 * address between #TOP_ENGLISHBREAKFAST_AST_BASE_ADDR and
262 * `TOP_ENGLISHBREAKFAST_AST_BASE_ADDR + TOP_ENGLISHBREAKFAST_AST_SIZE_BYTES`.
263 */
264#define TOP_ENGLISHBREAKFAST_AST_SIZE_BYTES 0x400u
265
266/**
267 * Peripheral base address for core device on flash_ctrl in top englishbreakfast.
268 *
269 * This should be used with #mmio_region_from_addr to access the memory-mapped
270 * registers associated with the peripheral (usually via a DIF).
271 */
272#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
273
274/**
275 * Peripheral size for core device on flash_ctrl in top englishbreakfast.
276 *
277 * This is the size (in bytes) of the peripheral's reserved memory area. All
278 * memory-mapped registers associated with this peripheral should have an
279 * address between #TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR and
280 * `TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES`.
281 */
282#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
283
284/**
285 * Peripheral base address for prim device on flash_ctrl in top englishbreakfast.
286 *
287 * This should be used with #mmio_region_from_addr to access the memory-mapped
288 * registers associated with the peripheral (usually via a DIF).
289 */
290#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u
291
292/**
293 * Peripheral size for prim device on flash_ctrl in top englishbreakfast.
294 *
295 * This is the size (in bytes) of the peripheral's reserved memory area. All
296 * memory-mapped registers associated with this peripheral should have an
297 * address between #TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR and
298 * `TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES`.
299 */
300#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u
301
302/**
303 * Peripheral base address for rv_plic in top englishbreakfast.
304 *
305 * This should be used with #mmio_region_from_addr to access the memory-mapped
306 * registers associated with the peripheral (usually via a DIF).
307 */
308#define TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR 0x48000000u
309
310/**
311 * Peripheral size for rv_plic in top englishbreakfast.
312 *
313 * This is the size (in bytes) of the peripheral's reserved memory area. All
314 * memory-mapped registers associated with this peripheral should have an
315 * address between #TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR and
316 * `TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR + TOP_ENGLISHBREAKFAST_RV_PLIC_SIZE_BYTES`.
317 */
318#define TOP_ENGLISHBREAKFAST_RV_PLIC_SIZE_BYTES 0x8000000u
319
320/**
321 * Peripheral base address for aes in top englishbreakfast.
322 *
323 * This should be used with #mmio_region_from_addr to access the memory-mapped
324 * registers associated with the peripheral (usually via a DIF).
325 */
326#define TOP_ENGLISHBREAKFAST_AES_BASE_ADDR 0x41100000u
327
328/**
329 * Peripheral size for aes in top englishbreakfast.
330 *
331 * This is the size (in bytes) of the peripheral's reserved memory area. All
332 * memory-mapped registers associated with this peripheral should have an
333 * address between #TOP_ENGLISHBREAKFAST_AES_BASE_ADDR and
334 * `TOP_ENGLISHBREAKFAST_AES_BASE_ADDR + TOP_ENGLISHBREAKFAST_AES_SIZE_BYTES`.
335 */
336#define TOP_ENGLISHBREAKFAST_AES_SIZE_BYTES 0x100u
337
338/**
339 * Peripheral base address for regs device on sram_ctrl_main in top englishbreakfast.
340 *
341 * This should be used with #mmio_region_from_addr to access the memory-mapped
342 * registers associated with the peripheral (usually via a DIF).
343 */
344#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
345
346/**
347 * Peripheral size for regs device on sram_ctrl_main in top englishbreakfast.
348 *
349 * This is the size (in bytes) of the peripheral's reserved memory area. All
350 * memory-mapped registers associated with this peripheral should have an
351 * address between #TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
352 * `TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
353 */
354#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
355
356/**
357 * Peripheral base address for regs device on rom_ctrl in top englishbreakfast.
358 *
359 * This should be used with #mmio_region_from_addr to access the memory-mapped
360 * registers associated with the peripheral (usually via a DIF).
361 */
362#define TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
363
364/**
365 * Peripheral size for regs device on rom_ctrl in top englishbreakfast.
366 *
367 * This is the size (in bytes) of the peripheral's reserved memory area. All
368 * memory-mapped registers associated with this peripheral should have an
369 * address between #TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR and
370 * `TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR + TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_SIZE_BYTES`.
371 */
372#define TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_SIZE_BYTES 0x80u
373
374/**
375 * Peripheral base address for cfg device on rv_core_ibex in top englishbreakfast.
376 *
377 * This should be used with #mmio_region_from_addr to access the memory-mapped
378 * registers associated with the peripheral (usually via a DIF).
379 */
380#define TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u
381
382/**
383 * Peripheral size for cfg device on rv_core_ibex in top englishbreakfast.
384 *
385 * This is the size (in bytes) of the peripheral's reserved memory area. All
386 * memory-mapped registers associated with this peripheral should have an
387 * address between #TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR and
388 * `TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_SIZE_BYTES`.
389 */
390#define TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u
391
392
393/**
394 * Memory base address for mem memory on flash_ctrl in top englishbreakfast.
395 */
396#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
397
398/**
399 * Memory size for mem memory on flash_ctrl in top englishbreakfast.
400 */
401#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_SIZE_BYTES 0x10000u
402
403/**
404 * Memory base address for ram memory on sram_ctrl_main in top englishbreakfast.
405 */
406#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
407
408/**
409 * Memory size for ram memory on sram_ctrl_main in top englishbreakfast.
410 */
411#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
412
413/**
414 * Memory base address for rom memory on rom_ctrl in top englishbreakfast.
415 */
416#define TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR 0x8000u
417
418/**
419 * Memory size for rom memory on rom_ctrl in top englishbreakfast.
420 */
421#define TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
422
423
424/**
425 * PLIC Interrupt Source Peripheral.
426 *
427 * Enumeration used to determine which peripheral asserted the corresponding
428 * interrupt.
429 */
443
444/**
445 * PLIC Interrupt Source.
446 *
447 * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
448 * the same peripheral are guaranteed to be consecutive.
449 */
451 kTopEnglishbreakfastPlicIrqIdNone = 0, /**< No Interrupt */
452 kTopEnglishbreakfastPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
453 kTopEnglishbreakfastPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
455 kTopEnglishbreakfastPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
456 kTopEnglishbreakfastPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
457 kTopEnglishbreakfastPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
459 kTopEnglishbreakfastPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
461 kTopEnglishbreakfastPlicIrqIdUart1TxWatermark = 10, /**< uart1_tx_watermark */
462 kTopEnglishbreakfastPlicIrqIdUart1RxWatermark = 11, /**< uart1_rx_watermark */
464 kTopEnglishbreakfastPlicIrqIdUart1RxOverflow = 13, /**< uart1_rx_overflow */
465 kTopEnglishbreakfastPlicIrqIdUart1RxFrameErr = 14, /**< uart1_rx_frame_err */
466 kTopEnglishbreakfastPlicIrqIdUart1RxBreakErr = 15, /**< uart1_rx_break_err */
467 kTopEnglishbreakfastPlicIrqIdUart1RxTimeout = 16, /**< uart1_rx_timeout */
468 kTopEnglishbreakfastPlicIrqIdUart1RxParityErr = 17, /**< uart1_rx_parity_err */
469 kTopEnglishbreakfastPlicIrqIdUart1TxEmpty = 18, /**< uart1_tx_empty */
502 kTopEnglishbreakfastPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 51, /**< spi_device_upload_cmdfifo_not_empty */
503 kTopEnglishbreakfastPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 52, /**< spi_device_upload_payload_not_empty */
504 kTopEnglishbreakfastPlicIrqIdSpiDeviceUploadPayloadOverflow = 53, /**< spi_device_upload_payload_overflow */
505 kTopEnglishbreakfastPlicIrqIdSpiDeviceReadbufWatermark = 54, /**< spi_device_readbuf_watermark */
506 kTopEnglishbreakfastPlicIrqIdSpiDeviceReadbufFlip = 55, /**< spi_device_readbuf_flip */
507 kTopEnglishbreakfastPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 56, /**< spi_device_tpm_header_not_empty */
508 kTopEnglishbreakfastPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 57, /**< spi_device_tpm_rdfifo_cmd_end */
509 kTopEnglishbreakfastPlicIrqIdSpiDeviceTpmRdfifoDrop = 58, /**< spi_device_tpm_rdfifo_drop */
510 kTopEnglishbreakfastPlicIrqIdSpiHost0Error = 59, /**< spi_host0_error */
511 kTopEnglishbreakfastPlicIrqIdSpiHost0SpiEvent = 60, /**< spi_host0_spi_event */
512 kTopEnglishbreakfastPlicIrqIdUsbdevPktReceived = 61, /**< usbdev_pkt_received */
513 kTopEnglishbreakfastPlicIrqIdUsbdevPktSent = 62, /**< usbdev_pkt_sent */
514 kTopEnglishbreakfastPlicIrqIdUsbdevDisconnected = 63, /**< usbdev_disconnected */
515 kTopEnglishbreakfastPlicIrqIdUsbdevHostLost = 64, /**< usbdev_host_lost */
516 kTopEnglishbreakfastPlicIrqIdUsbdevLinkReset = 65, /**< usbdev_link_reset */
517 kTopEnglishbreakfastPlicIrqIdUsbdevLinkSuspend = 66, /**< usbdev_link_suspend */
518 kTopEnglishbreakfastPlicIrqIdUsbdevLinkResume = 67, /**< usbdev_link_resume */
519 kTopEnglishbreakfastPlicIrqIdUsbdevAvOutEmpty = 68, /**< usbdev_av_out_empty */
520 kTopEnglishbreakfastPlicIrqIdUsbdevRxFull = 69, /**< usbdev_rx_full */
521 kTopEnglishbreakfastPlicIrqIdUsbdevAvOverflow = 70, /**< usbdev_av_overflow */
522 kTopEnglishbreakfastPlicIrqIdUsbdevLinkInErr = 71, /**< usbdev_link_in_err */
523 kTopEnglishbreakfastPlicIrqIdUsbdevRxCrcErr = 72, /**< usbdev_rx_crc_err */
524 kTopEnglishbreakfastPlicIrqIdUsbdevRxPidErr = 73, /**< usbdev_rx_pid_err */
525 kTopEnglishbreakfastPlicIrqIdUsbdevRxBitstuffErr = 74, /**< usbdev_rx_bitstuff_err */
528 kTopEnglishbreakfastPlicIrqIdUsbdevLinkOutErr = 77, /**< usbdev_link_out_err */
529 kTopEnglishbreakfastPlicIrqIdUsbdevAvSetupEmpty = 78, /**< usbdev_av_setup_empty */
530 kTopEnglishbreakfastPlicIrqIdPwrmgrAonWakeup = 79, /**< pwrmgr_aon_wakeup */
531 kTopEnglishbreakfastPlicIrqIdAonTimerAonWkupTimerExpired = 80, /**< aon_timer_aon_wkup_timer_expired */
532 kTopEnglishbreakfastPlicIrqIdAonTimerAonWdogTimerBark = 81, /**< aon_timer_aon_wdog_timer_bark */
533 kTopEnglishbreakfastPlicIrqIdFlashCtrlProgEmpty = 82, /**< flash_ctrl_prog_empty */
534 kTopEnglishbreakfastPlicIrqIdFlashCtrlProgLvl = 83, /**< flash_ctrl_prog_lvl */
535 kTopEnglishbreakfastPlicIrqIdFlashCtrlRdFull = 84, /**< flash_ctrl_rd_full */
536 kTopEnglishbreakfastPlicIrqIdFlashCtrlRdLvl = 85, /**< flash_ctrl_rd_lvl */
537 kTopEnglishbreakfastPlicIrqIdFlashCtrlOpDone = 86, /**< flash_ctrl_op_done */
538 kTopEnglishbreakfastPlicIrqIdFlashCtrlCorrErr = 87, /**< flash_ctrl_corr_err */
539 kTopEnglishbreakfastPlicIrqIdLast = 87, /**< \internal The Last Valid Interrupt ID. */
541
542/**
543 * PLIC Interrupt Source to Peripheral Map
544 *
545 * This array is a mapping from `top_englishbreakfast_plic_irq_id_t` to
546 * `top_englishbreakfast_plic_peripheral_t`.
547 */
549 top_englishbreakfast_plic_interrupt_for_peripheral[88];
550
551/**
552 * PLIC Interrupt Target.
553 *
554 * Enumeration used to determine which set of IE, CC, threshold registers to
555 * access for a given interrupt target.
556 */
558 kTopEnglishbreakfastPlicTargetIbex0 = 0, /**< Ibex Core 0 */
559 kTopEnglishbreakfastPlicTargetLast = 0, /**< \internal Final PLIC target */
561
562
563#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
564
565// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
566// 0 and 1 are tied to value 0 and 1
567#define NUM_MIO_PADS 47
568#define NUM_DIO_PADS 14
569
570#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
571
572/**
573 * Pinmux Peripheral Input.
574 */
586 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio10 = 10, /**< Peripheral Input 10 */
587 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio11 = 11, /**< Peripheral Input 11 */
588 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio12 = 12, /**< Peripheral Input 12 */
589 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio13 = 13, /**< Peripheral Input 13 */
590 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio14 = 14, /**< Peripheral Input 14 */
591 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio15 = 15, /**< Peripheral Input 15 */
592 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio16 = 16, /**< Peripheral Input 16 */
593 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio17 = 17, /**< Peripheral Input 17 */
594 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio18 = 18, /**< Peripheral Input 18 */
595 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio19 = 19, /**< Peripheral Input 19 */
596 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio20 = 20, /**< Peripheral Input 20 */
597 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio21 = 21, /**< Peripheral Input 21 */
598 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio22 = 22, /**< Peripheral Input 22 */
599 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio23 = 23, /**< Peripheral Input 23 */
600 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio24 = 24, /**< Peripheral Input 24 */
601 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio25 = 25, /**< Peripheral Input 25 */
602 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio26 = 26, /**< Peripheral Input 26 */
603 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio27 = 27, /**< Peripheral Input 27 */
604 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio28 = 28, /**< Peripheral Input 28 */
605 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio29 = 29, /**< Peripheral Input 29 */
606 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio30 = 30, /**< Peripheral Input 30 */
607 kTopEnglishbreakfastPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */
608 kTopEnglishbreakfastPinmuxPeripheralInUart0Rx = 32, /**< Peripheral Input 32 */
609 kTopEnglishbreakfastPinmuxPeripheralInUart1Rx = 33, /**< Peripheral Input 33 */
614 kTopEnglishbreakfastPinmuxPeripheralInLast = 37, /**< \internal Last valid peripheral input */
616
617/**
618 * Pinmux MIO Input Selector.
619 */
621 kTopEnglishbreakfastPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
622 kTopEnglishbreakfastPinmuxInselConstantOne = 1, /**< Tie constantly to one */
633 kTopEnglishbreakfastPinmuxInselIob1 = 12, /**< MIO Pad 10 */
634 kTopEnglishbreakfastPinmuxInselIob2 = 13, /**< MIO Pad 11 */
635 kTopEnglishbreakfastPinmuxInselIob3 = 14, /**< MIO Pad 12 */
636 kTopEnglishbreakfastPinmuxInselIob4 = 15, /**< MIO Pad 13 */
637 kTopEnglishbreakfastPinmuxInselIob5 = 16, /**< MIO Pad 14 */
638 kTopEnglishbreakfastPinmuxInselIob6 = 17, /**< MIO Pad 15 */
639 kTopEnglishbreakfastPinmuxInselIob7 = 18, /**< MIO Pad 16 */
640 kTopEnglishbreakfastPinmuxInselIob8 = 19, /**< MIO Pad 17 */
641 kTopEnglishbreakfastPinmuxInselIob9 = 20, /**< MIO Pad 18 */
645 kTopEnglishbreakfastPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
646 kTopEnglishbreakfastPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
647 kTopEnglishbreakfastPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
648 kTopEnglishbreakfastPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
649 kTopEnglishbreakfastPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
650 kTopEnglishbreakfastPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
651 kTopEnglishbreakfastPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
652 kTopEnglishbreakfastPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
653 kTopEnglishbreakfastPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
654 kTopEnglishbreakfastPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
658 kTopEnglishbreakfastPinmuxInselIor0 = 37, /**< MIO Pad 35 */
659 kTopEnglishbreakfastPinmuxInselIor1 = 38, /**< MIO Pad 36 */
660 kTopEnglishbreakfastPinmuxInselIor2 = 39, /**< MIO Pad 37 */
661 kTopEnglishbreakfastPinmuxInselIor3 = 40, /**< MIO Pad 38 */
662 kTopEnglishbreakfastPinmuxInselIor4 = 41, /**< MIO Pad 39 */
663 kTopEnglishbreakfastPinmuxInselIor5 = 42, /**< MIO Pad 40 */
664 kTopEnglishbreakfastPinmuxInselIor6 = 43, /**< MIO Pad 41 */
665 kTopEnglishbreakfastPinmuxInselIor7 = 44, /**< MIO Pad 42 */
670 kTopEnglishbreakfastPinmuxInselLast = 48, /**< \internal Last valid insel value */
672
673/**
674 * Pinmux MIO Output.
675 */
724 kTopEnglishbreakfastPinmuxMioOutLast = 46, /**< \internal Last valid mio output */
726
727/**
728 * Pinmux Peripheral Output Selector.
729 */
731 kTopEnglishbreakfastPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
732 kTopEnglishbreakfastPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
733 kTopEnglishbreakfastPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
734 kTopEnglishbreakfastPinmuxOutselGpioGpio0 = 3, /**< Peripheral Output 0 */
735 kTopEnglishbreakfastPinmuxOutselGpioGpio1 = 4, /**< Peripheral Output 1 */
736 kTopEnglishbreakfastPinmuxOutselGpioGpio2 = 5, /**< Peripheral Output 2 */
737 kTopEnglishbreakfastPinmuxOutselGpioGpio3 = 6, /**< Peripheral Output 3 */
738 kTopEnglishbreakfastPinmuxOutselGpioGpio4 = 7, /**< Peripheral Output 4 */
739 kTopEnglishbreakfastPinmuxOutselGpioGpio5 = 8, /**< Peripheral Output 5 */
740 kTopEnglishbreakfastPinmuxOutselGpioGpio6 = 9, /**< Peripheral Output 6 */
741 kTopEnglishbreakfastPinmuxOutselGpioGpio7 = 10, /**< Peripheral Output 7 */
742 kTopEnglishbreakfastPinmuxOutselGpioGpio8 = 11, /**< Peripheral Output 8 */
743 kTopEnglishbreakfastPinmuxOutselGpioGpio9 = 12, /**< Peripheral Output 9 */
744 kTopEnglishbreakfastPinmuxOutselGpioGpio10 = 13, /**< Peripheral Output 10 */
745 kTopEnglishbreakfastPinmuxOutselGpioGpio11 = 14, /**< Peripheral Output 11 */
746 kTopEnglishbreakfastPinmuxOutselGpioGpio12 = 15, /**< Peripheral Output 12 */
747 kTopEnglishbreakfastPinmuxOutselGpioGpio13 = 16, /**< Peripheral Output 13 */
748 kTopEnglishbreakfastPinmuxOutselGpioGpio14 = 17, /**< Peripheral Output 14 */
749 kTopEnglishbreakfastPinmuxOutselGpioGpio15 = 18, /**< Peripheral Output 15 */
750 kTopEnglishbreakfastPinmuxOutselGpioGpio16 = 19, /**< Peripheral Output 16 */
751 kTopEnglishbreakfastPinmuxOutselGpioGpio17 = 20, /**< Peripheral Output 17 */
752 kTopEnglishbreakfastPinmuxOutselGpioGpio18 = 21, /**< Peripheral Output 18 */
753 kTopEnglishbreakfastPinmuxOutselGpioGpio19 = 22, /**< Peripheral Output 19 */
754 kTopEnglishbreakfastPinmuxOutselGpioGpio20 = 23, /**< Peripheral Output 20 */
755 kTopEnglishbreakfastPinmuxOutselGpioGpio21 = 24, /**< Peripheral Output 21 */
756 kTopEnglishbreakfastPinmuxOutselGpioGpio22 = 25, /**< Peripheral Output 22 */
757 kTopEnglishbreakfastPinmuxOutselGpioGpio23 = 26, /**< Peripheral Output 23 */
758 kTopEnglishbreakfastPinmuxOutselGpioGpio24 = 27, /**< Peripheral Output 24 */
759 kTopEnglishbreakfastPinmuxOutselGpioGpio25 = 28, /**< Peripheral Output 25 */
760 kTopEnglishbreakfastPinmuxOutselGpioGpio26 = 29, /**< Peripheral Output 26 */
761 kTopEnglishbreakfastPinmuxOutselGpioGpio27 = 30, /**< Peripheral Output 27 */
762 kTopEnglishbreakfastPinmuxOutselGpioGpio28 = 31, /**< Peripheral Output 28 */
763 kTopEnglishbreakfastPinmuxOutselGpioGpio29 = 32, /**< Peripheral Output 29 */
764 kTopEnglishbreakfastPinmuxOutselGpioGpio30 = 33, /**< Peripheral Output 30 */
765 kTopEnglishbreakfastPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */
766 kTopEnglishbreakfastPinmuxOutselUart0Tx = 35, /**< Peripheral Output 32 */
767 kTopEnglishbreakfastPinmuxOutselUart1Tx = 36, /**< Peripheral Output 33 */
768 kTopEnglishbreakfastPinmuxOutselFlashCtrlTdo = 37, /**< Peripheral Output 34 */
769 kTopEnglishbreakfastPinmuxOutselLast = 37, /**< \internal Last valid outsel value */
771
772/**
773 * Dedicated Pad Selects
774 */
776 kTopEnglishbreakfastDirectPadsSpiHost0Sd0 = 0, /**< */
777 kTopEnglishbreakfastDirectPadsSpiHost0Sd1 = 1, /**< */
778 kTopEnglishbreakfastDirectPadsSpiHost0Sd2 = 2, /**< */
779 kTopEnglishbreakfastDirectPadsSpiHost0Sd3 = 3, /**< */
780 kTopEnglishbreakfastDirectPadsSpiDeviceSd0 = 4, /**< */
781 kTopEnglishbreakfastDirectPadsSpiDeviceSd1 = 5, /**< */
782 kTopEnglishbreakfastDirectPadsSpiDeviceSd2 = 6, /**< */
783 kTopEnglishbreakfastDirectPadsSpiDeviceSd3 = 7, /**< */
784 kTopEnglishbreakfastDirectPadsUsbdevUsbDp = 8, /**< */
785 kTopEnglishbreakfastDirectPadsUsbdevUsbDn = 9, /**< */
786 kTopEnglishbreakfastDirectPadsSpiDeviceSck = 10, /**< */
787 kTopEnglishbreakfastDirectPadsSpiDeviceCsb = 11, /**< */
788 kTopEnglishbreakfastDirectPadsSpiHost0Sck = 12, /**< */
789 kTopEnglishbreakfastDirectPadsSpiHost0Csb = 13, /**< */
790 kTopEnglishbreakfastDirectPadsLast = 13, /**< \internal Last valid direct pad */
792
793/**
794 * Muxed Pad Selects
795 */
797 kTopEnglishbreakfastMuxedPadsIoa0 = 0, /**< */
798 kTopEnglishbreakfastMuxedPadsIoa1 = 1, /**< */
799 kTopEnglishbreakfastMuxedPadsIoa2 = 2, /**< */
800 kTopEnglishbreakfastMuxedPadsIoa3 = 3, /**< */
801 kTopEnglishbreakfastMuxedPadsIoa4 = 4, /**< */
802 kTopEnglishbreakfastMuxedPadsIoa5 = 5, /**< */
803 kTopEnglishbreakfastMuxedPadsIoa6 = 6, /**< */
804 kTopEnglishbreakfastMuxedPadsIoa7 = 7, /**< */
805 kTopEnglishbreakfastMuxedPadsIoa8 = 8, /**< */
806 kTopEnglishbreakfastMuxedPadsIob0 = 9, /**< */
807 kTopEnglishbreakfastMuxedPadsIob1 = 10, /**< */
808 kTopEnglishbreakfastMuxedPadsIob2 = 11, /**< */
809 kTopEnglishbreakfastMuxedPadsIob3 = 12, /**< */
810 kTopEnglishbreakfastMuxedPadsIob4 = 13, /**< */
811 kTopEnglishbreakfastMuxedPadsIob5 = 14, /**< */
812 kTopEnglishbreakfastMuxedPadsIob6 = 15, /**< */
813 kTopEnglishbreakfastMuxedPadsIob7 = 16, /**< */
814 kTopEnglishbreakfastMuxedPadsIob8 = 17, /**< */
815 kTopEnglishbreakfastMuxedPadsIob9 = 18, /**< */
816 kTopEnglishbreakfastMuxedPadsIob10 = 19, /**< */
817 kTopEnglishbreakfastMuxedPadsIob11 = 20, /**< */
818 kTopEnglishbreakfastMuxedPadsIob12 = 21, /**< */
819 kTopEnglishbreakfastMuxedPadsIoc0 = 22, /**< */
820 kTopEnglishbreakfastMuxedPadsIoc1 = 23, /**< */
821 kTopEnglishbreakfastMuxedPadsIoc2 = 24, /**< */
822 kTopEnglishbreakfastMuxedPadsIoc3 = 25, /**< */
823 kTopEnglishbreakfastMuxedPadsIoc4 = 26, /**< */
824 kTopEnglishbreakfastMuxedPadsIoc5 = 27, /**< */
825 kTopEnglishbreakfastMuxedPadsIoc6 = 28, /**< */
826 kTopEnglishbreakfastMuxedPadsIoc7 = 29, /**< */
827 kTopEnglishbreakfastMuxedPadsIoc8 = 30, /**< */
828 kTopEnglishbreakfastMuxedPadsIoc9 = 31, /**< */
829 kTopEnglishbreakfastMuxedPadsIoc10 = 32, /**< */
830 kTopEnglishbreakfastMuxedPadsIoc11 = 33, /**< */
831 kTopEnglishbreakfastMuxedPadsIoc12 = 34, /**< */
832 kTopEnglishbreakfastMuxedPadsIor0 = 35, /**< */
833 kTopEnglishbreakfastMuxedPadsIor1 = 36, /**< */
834 kTopEnglishbreakfastMuxedPadsIor2 = 37, /**< */
835 kTopEnglishbreakfastMuxedPadsIor3 = 38, /**< */
836 kTopEnglishbreakfastMuxedPadsIor4 = 39, /**< */
837 kTopEnglishbreakfastMuxedPadsIor5 = 40, /**< */
838 kTopEnglishbreakfastMuxedPadsIor6 = 41, /**< */
839 kTopEnglishbreakfastMuxedPadsIor7 = 42, /**< */
840 kTopEnglishbreakfastMuxedPadsIor10 = 43, /**< */
841 kTopEnglishbreakfastMuxedPadsIor11 = 44, /**< */
842 kTopEnglishbreakfastMuxedPadsIor12 = 45, /**< */
843 kTopEnglishbreakfastMuxedPadsIor13 = 46, /**< */
844 kTopEnglishbreakfastMuxedPadsLast = 46, /**< \internal Last valid muxed pad */
846
847/**
848 * Power Manager Wakeup Signals
849 */
851 kTopEnglishbreakfastPowerManagerWakeUpsPinmuxAonPinWkupReq = 0, /**< */
852 kTopEnglishbreakfastPowerManagerWakeUpsPinmuxAonUsbWkupReq = 1, /**< */
853 kTopEnglishbreakfastPowerManagerWakeUpsAonTimerAonWkupReq = 2, /**< */
854 kTopEnglishbreakfastPowerManagerWakeUpsLast = 2, /**< \internal Last valid pwrmgr wakeup signal */
856
857/**
858 * Reset Manager Software Controlled Resets
859 */
861 kTopEnglishbreakfastResetManagerSwResetsSpiDevice = 0, /**< */
862 kTopEnglishbreakfastResetManagerSwResetsSpiHost0 = 1, /**< */
863 kTopEnglishbreakfastResetManagerSwResetsUsb = 2, /**< */
864 kTopEnglishbreakfastResetManagerSwResetsLast = 2, /**< \internal Last valid rstmgr software reset request */
866
867/**
868 * Power Manager Reset Request Signals
869 */
871 kTopEnglishbreakfastPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 0, /**< */
872 kTopEnglishbreakfastPowerManagerResetRequestsLast = 0, /**< \internal Last valid pwrmgr reset_request signal */
874
875/**
876 * Clock Manager Software-Controlled ("Gated") Clocks.
877 *
878 * The Software has full control over these clocks.
879 */
881 kTopEnglishbreakfastGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
882 kTopEnglishbreakfastGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
883 kTopEnglishbreakfastGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
884 kTopEnglishbreakfastGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
885 kTopEnglishbreakfastGateableClocksLast = 3, /**< \internal Last Valid Gateable Clock */
887
888/**
889 * Clock Manager Software-Hinted Clocks.
890 *
891 * The Software has partial control over these clocks. It can ask them to stop,
892 * but the clock manager is in control of whether the clock actually is stopped.
893 */
895 kTopEnglishbreakfastHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */
896 kTopEnglishbreakfastHintableClocksLast = 0, /**< \internal Last Valid Hintable Clock */
898
899/**
900 * MMIO Region
901 *
902 * MMIO region excludes any memory that is separate from the module
903 * configuration space, i.e. ROM, main SRAM, and flash are excluded but
904 * retention SRAM, spi_device memory, or usbdev memory are included.
905 */
906#define TOP_ENGLISHBREAKFAST_MMIO_BASE_ADDR 0x40000000u
907#define TOP_ENGLISHBREAKFAST_MMIO_SIZE_BYTES 0x10000000u
908
909// Header Extern Guard
910#ifdef __cplusplus
911} // extern "C"
912#endif
913
914#endif // OPENTITAN_HW_TOP_ENGLISHBREAKFAST_SW_AUTOGEN_TOP_ENGLISHBREAKFAST_H_