top_earlgrey.h File Reference

Top-specific Definitions. More...

Go to the source code of this file.

Macros
#define	TOP_EARLGREY_UART0_BASE_ADDR   0x40000000u
	Peripheral base address for uart0 in top earlgrey.
#define	TOP_EARLGREY_UART0_SIZE_BYTES   0x40u
	Peripheral size for uart0 in top earlgrey.
#define	TOP_EARLGREY_UART1_BASE_ADDR   0x40010000u
	Peripheral base address for uart1 in top earlgrey.
#define	TOP_EARLGREY_UART1_SIZE_BYTES   0x40u
	Peripheral size for uart1 in top earlgrey.
#define	TOP_EARLGREY_UART2_BASE_ADDR   0x40020000u
	Peripheral base address for uart2 in top earlgrey.
#define	TOP_EARLGREY_UART2_SIZE_BYTES   0x40u
	Peripheral size for uart2 in top earlgrey.
#define	TOP_EARLGREY_UART3_BASE_ADDR   0x40030000u
	Peripheral base address for uart3 in top earlgrey.
#define	TOP_EARLGREY_UART3_SIZE_BYTES   0x40u
	Peripheral size for uart3 in top earlgrey.
#define	TOP_EARLGREY_GPIO0_BASE_ADDR   0x40040000u
	Peripheral base address for gpio0 in top earlgrey.
#define	TOP_EARLGREY_GPIO0_SIZE_BYTES   0x400u
	Peripheral size for gpio0 in top earlgrey.
#define	TOP_EARLGREY_GPIO1_BASE_ADDR   0x40050000u
	Peripheral base address for gpio1 in top earlgrey.
#define	TOP_EARLGREY_GPIO1_SIZE_BYTES   0x400u
	Peripheral size for gpio1 in top earlgrey.
#define	TOP_EARLGREY_SPI_DEVICE_BASE_ADDR   0x40060000u
	Peripheral base address for spi_device in top earlgrey.
#define	TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES   0x2000u
	Peripheral size for spi_device in top earlgrey.
#define	TOP_EARLGREY_I2C0_BASE_ADDR   0x40080000u
	Peripheral base address for i2c0 in top earlgrey.
#define	TOP_EARLGREY_I2C0_SIZE_BYTES   0x80u
	Peripheral size for i2c0 in top earlgrey.
#define	TOP_EARLGREY_I2C1_BASE_ADDR   0x40090000u
	Peripheral base address for i2c1 in top earlgrey.
#define	TOP_EARLGREY_I2C1_SIZE_BYTES   0x80u
	Peripheral size for i2c1 in top earlgrey.
#define	TOP_EARLGREY_I2C2_BASE_ADDR   0x400A0000u
	Peripheral base address for i2c2 in top earlgrey.
#define	TOP_EARLGREY_I2C2_SIZE_BYTES   0x80u
	Peripheral size for i2c2 in top earlgrey.
#define	TOP_EARLGREY_I3C0_BASE_ADDR   0x40330000u
	Peripheral base address for i3c0 in top earlgrey.
#define	TOP_EARLGREY_I3C0_SIZE_BYTES   0x2000u
	Peripheral size for i3c0 in top earlgrey.
#define	TOP_EARLGREY_I3C1_BASE_ADDR   0x40340000u
	Peripheral base address for i3c1 in top earlgrey.
#define	TOP_EARLGREY_I3C1_SIZE_BYTES   0x2000u
	Peripheral size for i3c1 in top earlgrey.
#define	TOP_EARLGREY_RV_TIMER_BASE_ADDR   0x40100000u
	Peripheral base address for rv_timer in top earlgrey.
#define	TOP_EARLGREY_RV_TIMER_SIZE_BYTES   0x200u
	Peripheral size for rv_timer in top earlgrey.
#define	TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR   0x40130000u
	Peripheral base address for core device on otp_ctrl in top earlgrey.
#define	TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES   0x2000u
	Peripheral size for core device on otp_ctrl in top earlgrey.
#define	TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR   0x40140000u
	Peripheral base address for regs device on lc_ctrl in top earlgrey.
#define	TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES   0x100u
	Peripheral size for regs device on lc_ctrl in top earlgrey.
#define	TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR   0x40150000u
	Peripheral base address for alert_handler in top earlgrey.
#define	TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES   0x800u
	Peripheral size for alert_handler in top earlgrey.
#define	TOP_EARLGREY_SPI_HOST0_BASE_ADDR   0x40300000u
	Peripheral base address for spi_host0 in top earlgrey.
#define	TOP_EARLGREY_SPI_HOST0_SIZE_BYTES   0x40u
	Peripheral size for spi_host0 in top earlgrey.
#define	TOP_EARLGREY_SPI_HOST1_BASE_ADDR   0x40310000u
	Peripheral base address for spi_host1 in top earlgrey.
#define	TOP_EARLGREY_SPI_HOST1_SIZE_BYTES   0x40u
	Peripheral size for spi_host1 in top earlgrey.
#define	TOP_EARLGREY_USBDEV_BASE_ADDR   0x40320000u
	Peripheral base address for usbdev in top earlgrey.
#define	TOP_EARLGREY_USBDEV_SIZE_BYTES   0x1000u
	Peripheral size for usbdev in top earlgrey.
#define	TOP_EARLGREY_PWRMGR_BASE_ADDR   0x40400000u
	Peripheral base address for pwrmgr in top earlgrey.
#define	TOP_EARLGREY_PWRMGR_SIZE_BYTES   0x80u
	Peripheral size for pwrmgr in top earlgrey.
#define	TOP_EARLGREY_RSTMGR_BASE_ADDR   0x40410000u
	Peripheral base address for rstmgr in top earlgrey.
#define	TOP_EARLGREY_RSTMGR_SIZE_BYTES   0x80u
	Peripheral size for rstmgr in top earlgrey.
#define	TOP_EARLGREY_CLKMGR_BASE_ADDR   0x40420000u
	Peripheral base address for clkmgr in top earlgrey.
#define	TOP_EARLGREY_CLKMGR_SIZE_BYTES   0x80u
	Peripheral size for clkmgr in top earlgrey.
#define	TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR   0x40430000u
	Peripheral base address for sysrst_ctrl in top earlgrey.
#define	TOP_EARLGREY_SYSRST_CTRL_SIZE_BYTES   0x100u
	Peripheral size for sysrst_ctrl in top earlgrey.
#define	TOP_EARLGREY_ADC_CTRL_BASE_ADDR   0x40440000u
	Peripheral base address for adc_ctrl in top earlgrey.
#define	TOP_EARLGREY_ADC_CTRL_SIZE_BYTES   0x80u
	Peripheral size for adc_ctrl in top earlgrey.
#define	TOP_EARLGREY_PINMUX_BASE_ADDR   0x40460000u
	Peripheral base address for pinmux in top earlgrey.
#define	TOP_EARLGREY_PINMUX_SIZE_BYTES   0x1000u
	Peripheral size for pinmux in top earlgrey.
#define	TOP_EARLGREY_AON_TIMER_BASE_ADDR   0x40470000u
	Peripheral base address for aon_timer in top earlgrey.
#define	TOP_EARLGREY_AON_TIMER_SIZE_BYTES   0x40u
	Peripheral size for aon_timer in top earlgrey.
#define	TOP_EARLGREY_AST_BASE_ADDR   0x40480000u
	Peripheral base address for ast in top earlgrey.
#define	TOP_EARLGREY_AST_SIZE_BYTES   0x400u
	Peripheral size for ast in top earlgrey.
#define	TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR   0x40490000u
	Peripheral base address for sensor_ctrl in top earlgrey.
#define	TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES   0x80u
	Peripheral size for sensor_ctrl in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_RET_REGS_BASE_ADDR   0x40500000u
	Peripheral base address for regs device on sram_ctrl_ret in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES   0x40u
	Peripheral size for regs device on sram_ctrl_ret in top earlgrey.
#define	TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR   0x41010000u
	Peripheral base address for core device on rram_ctrl in top earlgrey.
#define	TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES   0x400u
	Peripheral size for core device on rram_ctrl in top earlgrey.
#define	TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR   0x41018000u
	Peripheral base address for prim device on rram_macro in top earlgrey.
#define	TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES   0x10u
	Peripheral size for prim device on rram_macro in top earlgrey.
#define	TOP_EARLGREY_RV_DM_REGS_BASE_ADDR   0x41200000u
	Peripheral base address for regs device on rv_dm in top earlgrey.
#define	TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES   0x10u
	Peripheral size for regs device on rv_dm in top earlgrey.
#define	TOP_EARLGREY_RV_DM_MEM_BASE_ADDR   0x10000u
	Peripheral base address for mem device on rv_dm in top earlgrey.
#define	TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES   0x1000u
	Peripheral size for mem device on rv_dm in top earlgrey.
#define	TOP_EARLGREY_RV_PLIC_BASE_ADDR   0x48000000u
	Peripheral base address for rv_plic in top earlgrey.
#define	TOP_EARLGREY_RV_PLIC_SIZE_BYTES   0x8000000u
	Peripheral size for rv_plic in top earlgrey.
#define	TOP_EARLGREY_AES_BASE_ADDR   0x41100000u
	Peripheral base address for aes in top earlgrey.
#define	TOP_EARLGREY_AES_SIZE_BYTES   0x100u
	Peripheral size for aes in top earlgrey.
#define	TOP_EARLGREY_HMAC_BASE_ADDR   0x41110000u
	Peripheral base address for hmac in top earlgrey.
#define	TOP_EARLGREY_HMAC_SIZE_BYTES   0x2000u
	Peripheral size for hmac in top earlgrey.
#define	TOP_EARLGREY_KMAC_BASE_ADDR   0x41120000u
	Peripheral base address for kmac in top earlgrey.
#define	TOP_EARLGREY_KMAC_SIZE_BYTES   0x1000u
	Peripheral size for kmac in top earlgrey.
#define	TOP_EARLGREY_OTBN_BASE_ADDR   0x41130000u
	Peripheral base address for otbn in top earlgrey.
#define	TOP_EARLGREY_OTBN_SIZE_BYTES   0x10000u
	Peripheral size for otbn in top earlgrey.
#define	TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR   0x41140000u
	Peripheral base address for keymgr_dpe in top earlgrey.
#define	TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES   0x200u
	Peripheral size for keymgr_dpe in top earlgrey.
#define	TOP_EARLGREY_CSRNG_BASE_ADDR   0x41150000u
	Peripheral base address for csrng in top earlgrey.
#define	TOP_EARLGREY_CSRNG_SIZE_BYTES   0x80u
	Peripheral size for csrng in top earlgrey.
#define	TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR   0x41160000u
	Peripheral base address for entropy_src in top earlgrey.
#define	TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES   0x100u
	Peripheral size for entropy_src in top earlgrey.
#define	TOP_EARLGREY_EDN0_BASE_ADDR   0x41170000u
	Peripheral base address for edn0 in top earlgrey.
#define	TOP_EARLGREY_EDN0_SIZE_BYTES   0x80u
	Peripheral size for edn0 in top earlgrey.
#define	TOP_EARLGREY_EDN1_BASE_ADDR   0x41180000u
	Peripheral base address for edn1 in top earlgrey.
#define	TOP_EARLGREY_EDN1_SIZE_BYTES   0x80u
	Peripheral size for edn1 in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR   0x411C0000u
	Peripheral base address for regs device on sram_ctrl_main in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES   0x40u
	Peripheral size for regs device on sram_ctrl_main in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_SEC_REGS_BASE_ADDR   0x411D0000u
	Peripheral base address for regs device on sram_ctrl_sec in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_SEC_REGS_SIZE_BYTES   0x40u
	Peripheral size for regs device on sram_ctrl_sec in top earlgrey.
#define	TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR   0x411E0000u
	Peripheral base address for regs device on rom_ctrl in top earlgrey.
#define	TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES   0x80u
	Peripheral size for regs device on rom_ctrl in top earlgrey.
#define	TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR   0x411F0000u
	Peripheral base address for cfg device on rv_core_ibex in top earlgrey.
#define	TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES   0x100u
	Peripheral size for cfg device on rv_core_ibex in top earlgrey.
#define	TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_BASE_ADDR   0x411B0000u
	Peripheral base address for regs device on cheriot_mem_sys in top earlgrey.
#define	TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_SIZE_BYTES   0x40u
	Peripheral size for regs device on cheriot_mem_sys in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR   0x411A0000u
	Peripheral base address for regs device on sram_ctrl_meta in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES   0x40u
	Peripheral size for regs device on sram_ctrl_meta in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_RET_RAM_BASE_ADDR   0x40600000u
	Memory base address for ram memory on sram_ctrl_ret in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_RET_RAM_SIZE_BYTES   0x2000u
	Memory size for ram memory on sram_ctrl_ret in top earlgrey.
#define	TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR   0x30000000u
	Memory base address for host memory on rram_ctrl in top earlgrey.
#define	TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES   0x200000u
	Memory size for host memory on rram_ctrl in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR   0x10000000u
	Memory base address for ram memory on sram_ctrl_main in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES   0x20000u
	Memory size for ram memory on sram_ctrl_main in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_SEC_RAM_BASE_ADDR   0x10020000u
	Memory base address for ram memory on sram_ctrl_sec in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_SEC_RAM_SIZE_BYTES   0x10000u
	Memory size for ram memory on sram_ctrl_sec in top earlgrey.
#define	TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR   0x40000u
	Memory base address for rom memory on rom_ctrl in top earlgrey.
#define	TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES   0x30000u
	Memory size for rom memory on rom_ctrl in top earlgrey.
#define	TOP_EARLGREY_CHERIOT_MEM_SYS_REVBM_BASE_ADDR   0x11000000u
	Memory base address for revbm memory on cheriot_mem_sys in top earlgrey.
#define	TOP_EARLGREY_CHERIOT_MEM_SYS_REVBM_SIZE_BYTES   0xC00u
	Memory size for revbm memory on cheriot_mem_sys in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_META_RAM_BASE_ADDR   0x11000000u
	Memory base address for ram memory on sram_ctrl_meta in top earlgrey.
#define	TOP_EARLGREY_SRAM_CTRL_META_RAM_SIZE_BYTES   0x9800u
	Memory size for ram memory on sram_ctrl_meta in top earlgrey.
#define	PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET   2
#define	NUM_MIO_PADS   47
#define	NUM_DIO_PADS   16
#define	PINMUX_PERIPH_OUTSEL_IDX_OFFSET   3
#define	TOP_EARLGREY_MMIO_BASE_ADDR   0x40000000u
	MMIO Region.
#define	TOP_EARLGREY_MMIO_SIZE_BYTES   0x10000000u

Typedefs
typedef enum top_earlgrey_plic_peripheral	top_earlgrey_plic_peripheral_t
	PLIC Interrupt Source Peripheral.
typedef enum top_earlgrey_plic_irq_id	top_earlgrey_plic_irq_id_t
	PLIC Interrupt Source.
typedef enum top_earlgrey_plic_target	top_earlgrey_plic_target_t
	PLIC Interrupt Target.
typedef enum top_earlgrey_alert_peripheral	top_earlgrey_alert_peripheral_t
	Alert Handler Source Peripheral.
typedef enum top_earlgrey_alert_id	top_earlgrey_alert_id_t
	Alert Handler Alert Source.
typedef enum top_earlgrey_pinmux_peripheral_in	top_earlgrey_pinmux_peripheral_in_t
	Pinmux Peripheral Input.
typedef enum top_earlgrey_pinmux_insel	top_earlgrey_pinmux_insel_t
	Pinmux MIO Input Selector.
typedef enum top_earlgrey_pinmux_mio_out	top_earlgrey_pinmux_mio_out_t
	Pinmux MIO Output.
typedef enum top_earlgrey_pinmux_outsel	top_earlgrey_pinmux_outsel_t
	Pinmux Peripheral Output Selector.
typedef enum top_earlgrey_direct_pads	top_earlgrey_direct_pads_t
	Dedicated Pad Selects.
typedef enum top_earlgrey_muxed_pads	top_earlgrey_muxed_pads_t
	Muxed Pad Selects.
typedef enum top_earlgrey_power_manager_wake_ups	top_earlgrey_power_manager_wake_ups_t
	Power Manager Wakeup Signals.
typedef enum top_earlgrey_reset_manager_sw_resets	top_earlgrey_reset_manager_sw_resets_t
	Reset Manager Software Controlled Resets.
typedef enum top_earlgrey_power_manager_reset_requests	top_earlgrey_power_manager_reset_requests_t
	Power Manager Reset Request Signals.
typedef enum top_earlgrey_gateable_clocks	top_earlgrey_gateable_clocks_t
	Clock Manager Software-Controlled ("Gated") Clocks.
typedef enum top_earlgrey_hintable_clocks	top_earlgrey_hintable_clocks_t
	Clock Manager Software-Hinted Clocks.

Enumerations
enum	top_earlgrey_plic_peripheral {   kTopEarlgreyPlicPeripheralUnknown = 0 ,   kTopEarlgreyPlicPeripheralUart0 = 1 ,   kTopEarlgreyPlicPeripheralUart1 = 2 ,   kTopEarlgreyPlicPeripheralUart2 = 3 ,   kTopEarlgreyPlicPeripheralUart3 = 4 ,   kTopEarlgreyPlicPeripheralGpio0 = 5 ,   kTopEarlgreyPlicPeripheralGpio1 = 6 ,   kTopEarlgreyPlicPeripheralSpiDevice = 7 ,   kTopEarlgreyPlicPeripheralI2c0 = 8 ,   kTopEarlgreyPlicPeripheralI2c1 = 9 ,   kTopEarlgreyPlicPeripheralI2c2 = 10 ,   kTopEarlgreyPlicPeripheralI3c0 = 11 ,   kTopEarlgreyPlicPeripheralI3c1 = 12 ,   kTopEarlgreyPlicPeripheralRvTimer = 13 ,   kTopEarlgreyPlicPeripheralOtpCtrl = 14 ,   kTopEarlgreyPlicPeripheralAlertHandler = 15 ,   kTopEarlgreyPlicPeripheralSpiHost0 = 16 ,   kTopEarlgreyPlicPeripheralSpiHost1 = 17 ,   kTopEarlgreyPlicPeripheralUsbdev = 18 ,   kTopEarlgreyPlicPeripheralPwrmgr = 19 ,   kTopEarlgreyPlicPeripheralSysrstCtrl = 20 ,   kTopEarlgreyPlicPeripheralAdcCtrl = 21 ,   kTopEarlgreyPlicPeripheralAonTimer = 22 ,   kTopEarlgreyPlicPeripheralSensorCtrl = 23 ,   kTopEarlgreyPlicPeripheralRramCtrl = 24 ,   kTopEarlgreyPlicPeripheralHmac = 25 ,   kTopEarlgreyPlicPeripheralKmac = 26 ,   kTopEarlgreyPlicPeripheralOtbn = 27 ,   kTopEarlgreyPlicPeripheralKeymgrDpe = 28 ,   kTopEarlgreyPlicPeripheralCsrng = 29 ,   kTopEarlgreyPlicPeripheralEntropySrc = 30 ,   kTopEarlgreyPlicPeripheralEdn0 = 31 ,   kTopEarlgreyPlicPeripheralEdn1 = 32 ,   kTopEarlgreyPlicPeripheralCheriotMemSys = 33 ,   kTopEarlgreyPlicPeripheralLast = 33 }
	PLIC Interrupt Source Peripheral. More...
enum	top_earlgrey_plic_irq_id {   kTopEarlgreyPlicIrqIdNone = 0 ,   kTopEarlgreyPlicIrqIdUart0TxWatermark = 1 ,   kTopEarlgreyPlicIrqIdUart0RxWatermark = 2 ,   kTopEarlgreyPlicIrqIdUart0TxDone = 3 ,   kTopEarlgreyPlicIrqIdUart0RxOverflow = 4 ,   kTopEarlgreyPlicIrqIdUart0RxFrameErr = 5 ,   kTopEarlgreyPlicIrqIdUart0RxBreakErr = 6 ,   kTopEarlgreyPlicIrqIdUart0RxTimeout = 7 ,   kTopEarlgreyPlicIrqIdUart0RxParityErr = 8 ,   kTopEarlgreyPlicIrqIdUart0TxEmpty = 9 ,   kTopEarlgreyPlicIrqIdUart1TxWatermark = 10 ,   kTopEarlgreyPlicIrqIdUart1RxWatermark = 11 ,   kTopEarlgreyPlicIrqIdUart1TxDone = 12 ,   kTopEarlgreyPlicIrqIdUart1RxOverflow = 13 ,   kTopEarlgreyPlicIrqIdUart1RxFrameErr = 14 ,   kTopEarlgreyPlicIrqIdUart1RxBreakErr = 15 ,   kTopEarlgreyPlicIrqIdUart1RxTimeout = 16 ,   kTopEarlgreyPlicIrqIdUart1RxParityErr = 17 ,   kTopEarlgreyPlicIrqIdUart1TxEmpty = 18 ,   kTopEarlgreyPlicIrqIdUart2TxWatermark = 19 ,   kTopEarlgreyPlicIrqIdUart2RxWatermark = 20 ,   kTopEarlgreyPlicIrqIdUart2TxDone = 21 ,   kTopEarlgreyPlicIrqIdUart2RxOverflow = 22 ,   kTopEarlgreyPlicIrqIdUart2RxFrameErr = 23 ,   kTopEarlgreyPlicIrqIdUart2RxBreakErr = 24 ,   kTopEarlgreyPlicIrqIdUart2RxTimeout = 25 ,   kTopEarlgreyPlicIrqIdUart2RxParityErr = 26 ,   kTopEarlgreyPlicIrqIdUart2TxEmpty = 27 ,   kTopEarlgreyPlicIrqIdUart3TxWatermark = 28 ,   kTopEarlgreyPlicIrqIdUart3RxWatermark = 29 ,   kTopEarlgreyPlicIrqIdUart3TxDone = 30 ,   kTopEarlgreyPlicIrqIdUart3RxOverflow = 31 ,   kTopEarlgreyPlicIrqIdUart3RxFrameErr = 32 ,   kTopEarlgreyPlicIrqIdUart3RxBreakErr = 33 ,   kTopEarlgreyPlicIrqIdUart3RxTimeout = 34 ,   kTopEarlgreyPlicIrqIdUart3RxParityErr = 35 ,   kTopEarlgreyPlicIrqIdUart3TxEmpty = 36 ,   kTopEarlgreyPlicIrqIdGpio0Gpio0 = 37 ,   kTopEarlgreyPlicIrqIdGpio0Gpio1 = 38 ,   kTopEarlgreyPlicIrqIdGpio0Gpio2 = 39 ,   kTopEarlgreyPlicIrqIdGpio0Gpio3 = 40 ,   kTopEarlgreyPlicIrqIdGpio0Gpio4 = 41 ,   kTopEarlgreyPlicIrqIdGpio0Gpio5 = 42 ,   kTopEarlgreyPlicIrqIdGpio0Gpio6 = 43 ,   kTopEarlgreyPlicIrqIdGpio0Gpio7 = 44 ,   kTopEarlgreyPlicIrqIdGpio0Gpio8 = 45 ,   kTopEarlgreyPlicIrqIdGpio0Gpio9 = 46 ,   kTopEarlgreyPlicIrqIdGpio0Gpio10 = 47 ,   kTopEarlgreyPlicIrqIdGpio0Gpio11 = 48 ,   kTopEarlgreyPlicIrqIdGpio0Gpio12 = 49 ,   kTopEarlgreyPlicIrqIdGpio0Gpio13 = 50 ,   kTopEarlgreyPlicIrqIdGpio0Gpio14 = 51 ,   kTopEarlgreyPlicIrqIdGpio0Gpio15 = 52 ,   kTopEarlgreyPlicIrqIdGpio0Gpio16 = 53 ,   kTopEarlgreyPlicIrqIdGpio0Gpio17 = 54 ,   kTopEarlgreyPlicIrqIdGpio0Gpio18 = 55 ,   kTopEarlgreyPlicIrqIdGpio0Gpio19 = 56 ,   kTopEarlgreyPlicIrqIdGpio0Gpio20 = 57 ,   kTopEarlgreyPlicIrqIdGpio0Gpio21 = 58 ,   kTopEarlgreyPlicIrqIdGpio0Gpio22 = 59 ,   kTopEarlgreyPlicIrqIdGpio0Gpio23 = 60 ,   kTopEarlgreyPlicIrqIdGpio0Gpio24 = 61 ,   kTopEarlgreyPlicIrqIdGpio0Gpio25 = 62 ,   kTopEarlgreyPlicIrqIdGpio0Gpio26 = 63 ,   kTopEarlgreyPlicIrqIdGpio0Gpio27 = 64 ,   kTopEarlgreyPlicIrqIdGpio0Gpio28 = 65 ,   kTopEarlgreyPlicIrqIdGpio0Gpio29 = 66 ,   kTopEarlgreyPlicIrqIdGpio0Gpio30 = 67 ,   kTopEarlgreyPlicIrqIdGpio0Gpio31 = 68 ,   kTopEarlgreyPlicIrqIdGpio1Gpio0 = 69 ,   kTopEarlgreyPlicIrqIdGpio1Gpio1 = 70 ,   kTopEarlgreyPlicIrqIdGpio1Gpio2 = 71 ,   kTopEarlgreyPlicIrqIdGpio1Gpio3 = 72 ,   kTopEarlgreyPlicIrqIdGpio1Gpio4 = 73 ,   kTopEarlgreyPlicIrqIdGpio1Gpio5 = 74 ,   kTopEarlgreyPlicIrqIdGpio1Gpio6 = 75 ,   kTopEarlgreyPlicIrqIdGpio1Gpio7 = 76 ,   kTopEarlgreyPlicIrqIdGpio1Gpio8 = 77 ,   kTopEarlgreyPlicIrqIdGpio1Gpio9 = 78 ,   kTopEarlgreyPlicIrqIdGpio1Gpio10 = 79 ,   kTopEarlgreyPlicIrqIdGpio1Gpio11 = 80 ,   kTopEarlgreyPlicIrqIdGpio1Gpio12 = 81 ,   kTopEarlgreyPlicIrqIdGpio1Gpio13 = 82 ,   kTopEarlgreyPlicIrqIdGpio1Gpio14 = 83 ,   kTopEarlgreyPlicIrqIdGpio1Gpio15 = 84 ,   kTopEarlgreyPlicIrqIdGpio1Gpio16 = 85 ,   kTopEarlgreyPlicIrqIdGpio1Gpio17 = 86 ,   kTopEarlgreyPlicIrqIdGpio1Gpio18 = 87 ,   kTopEarlgreyPlicIrqIdGpio1Gpio19 = 88 ,   kTopEarlgreyPlicIrqIdGpio1Gpio20 = 89 ,   kTopEarlgreyPlicIrqIdGpio1Gpio21 = 90 ,   kTopEarlgreyPlicIrqIdGpio1Gpio22 = 91 ,   kTopEarlgreyPlicIrqIdGpio1Gpio23 = 92 ,   kTopEarlgreyPlicIrqIdGpio1Gpio24 = 93 ,   kTopEarlgreyPlicIrqIdGpio1Gpio25 = 94 ,   kTopEarlgreyPlicIrqIdGpio1Gpio26 = 95 ,   kTopEarlgreyPlicIrqIdGpio1Gpio27 = 96 ,   kTopEarlgreyPlicIrqIdGpio1Gpio28 = 97 ,   kTopEarlgreyPlicIrqIdGpio1Gpio29 = 98 ,   kTopEarlgreyPlicIrqIdGpio1Gpio30 = 99 ,   kTopEarlgreyPlicIrqIdGpio1Gpio31 = 100 ,   kTopEarlgreyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 101 ,   kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 102 ,   kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadOverflow = 103 ,   kTopEarlgreyPlicIrqIdSpiDeviceReadbufWatermark = 104 ,   kTopEarlgreyPlicIrqIdSpiDeviceReadbufFlip = 105 ,   kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 106 ,   kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 107 ,   kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoDrop = 108 ,   kTopEarlgreyPlicIrqIdI2c0FmtThreshold = 109 ,   kTopEarlgreyPlicIrqIdI2c0RxThreshold = 110 ,   kTopEarlgreyPlicIrqIdI2c0AcqThreshold = 111 ,   kTopEarlgreyPlicIrqIdI2c0RxOverflow = 112 ,   kTopEarlgreyPlicIrqIdI2c0ControllerHalt = 113 ,   kTopEarlgreyPlicIrqIdI2c0SclInterference = 114 ,   kTopEarlgreyPlicIrqIdI2c0SdaInterference = 115 ,   kTopEarlgreyPlicIrqIdI2c0StretchTimeout = 116 ,   kTopEarlgreyPlicIrqIdI2c0SdaUnstable = 117 ,   kTopEarlgreyPlicIrqIdI2c0CmdComplete = 118 ,   kTopEarlgreyPlicIrqIdI2c0TxStretch = 119 ,   kTopEarlgreyPlicIrqIdI2c0TxThreshold = 120 ,   kTopEarlgreyPlicIrqIdI2c0AcqStretch = 121 ,   kTopEarlgreyPlicIrqIdI2c0UnexpStop = 122 ,   kTopEarlgreyPlicIrqIdI2c0HostTimeout = 123 ,   kTopEarlgreyPlicIrqIdI2c1FmtThreshold = 124 ,   kTopEarlgreyPlicIrqIdI2c1RxThreshold = 125 ,   kTopEarlgreyPlicIrqIdI2c1AcqThreshold = 126 ,   kTopEarlgreyPlicIrqIdI2c1RxOverflow = 127 ,   kTopEarlgreyPlicIrqIdI2c1ControllerHalt = 128 ,   kTopEarlgreyPlicIrqIdI2c1SclInterference = 129 ,   kTopEarlgreyPlicIrqIdI2c1SdaInterference = 130 ,   kTopEarlgreyPlicIrqIdI2c1StretchTimeout = 131 ,   kTopEarlgreyPlicIrqIdI2c1SdaUnstable = 132 ,   kTopEarlgreyPlicIrqIdI2c1CmdComplete = 133 ,   kTopEarlgreyPlicIrqIdI2c1TxStretch = 134 ,   kTopEarlgreyPlicIrqIdI2c1TxThreshold = 135 ,   kTopEarlgreyPlicIrqIdI2c1AcqStretch = 136 ,   kTopEarlgreyPlicIrqIdI2c1UnexpStop = 137 ,   kTopEarlgreyPlicIrqIdI2c1HostTimeout = 138 ,   kTopEarlgreyPlicIrqIdI2c2FmtThreshold = 139 ,   kTopEarlgreyPlicIrqIdI2c2RxThreshold = 140 ,   kTopEarlgreyPlicIrqIdI2c2AcqThreshold = 141 ,   kTopEarlgreyPlicIrqIdI2c2RxOverflow = 142 ,   kTopEarlgreyPlicIrqIdI2c2ControllerHalt = 143 ,   kTopEarlgreyPlicIrqIdI2c2SclInterference = 144 ,   kTopEarlgreyPlicIrqIdI2c2SdaInterference = 145 ,   kTopEarlgreyPlicIrqIdI2c2StretchTimeout = 146 ,   kTopEarlgreyPlicIrqIdI2c2SdaUnstable = 147 ,   kTopEarlgreyPlicIrqIdI2c2CmdComplete = 148 ,   kTopEarlgreyPlicIrqIdI2c2TxStretch = 149 ,   kTopEarlgreyPlicIrqIdI2c2TxThreshold = 150 ,   kTopEarlgreyPlicIrqIdI2c2AcqStretch = 151 ,   kTopEarlgreyPlicIrqIdI2c2UnexpStop = 152 ,   kTopEarlgreyPlicIrqIdI2c2HostTimeout = 153 ,   kTopEarlgreyPlicIrqIdI3c0Hci = 154 ,   kTopEarlgreyPlicIrqIdI3c0Targ = 155 ,   kTopEarlgreyPlicIrqIdI3c1Hci = 156 ,   kTopEarlgreyPlicIrqIdI3c1Targ = 157 ,   kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 158 ,   kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 159 ,   kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 160 ,   kTopEarlgreyPlicIrqIdAlertHandlerClassa = 161 ,   kTopEarlgreyPlicIrqIdAlertHandlerClassb = 162 ,   kTopEarlgreyPlicIrqIdAlertHandlerClassc = 163 ,   kTopEarlgreyPlicIrqIdAlertHandlerClassd = 164 ,   kTopEarlgreyPlicIrqIdSpiHost0Error = 165 ,   kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 166 ,   kTopEarlgreyPlicIrqIdSpiHost1Error = 167 ,   kTopEarlgreyPlicIrqIdSpiHost1SpiEvent = 168 ,   kTopEarlgreyPlicIrqIdUsbdevPktReceived = 169 ,   kTopEarlgreyPlicIrqIdUsbdevPktSent = 170 ,   kTopEarlgreyPlicIrqIdUsbdevDisconnected = 171 ,   kTopEarlgreyPlicIrqIdUsbdevHostLost = 172 ,   kTopEarlgreyPlicIrqIdUsbdevLinkReset = 173 ,   kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 174 ,   kTopEarlgreyPlicIrqIdUsbdevLinkResume = 175 ,   kTopEarlgreyPlicIrqIdUsbdevAvOutEmpty = 176 ,   kTopEarlgreyPlicIrqIdUsbdevRxFull = 177 ,   kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 178 ,   kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 179 ,   kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 180 ,   kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 181 ,   kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 182 ,   kTopEarlgreyPlicIrqIdUsbdevFrame = 183 ,   kTopEarlgreyPlicIrqIdUsbdevPowered = 184 ,   kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 185 ,   kTopEarlgreyPlicIrqIdUsbdevAvSetupEmpty = 186 ,   kTopEarlgreyPlicIrqIdPwrmgrWakeup = 187 ,   kTopEarlgreyPlicIrqIdSysrstCtrlEventDetected = 188 ,   kTopEarlgreyPlicIrqIdAdcCtrlMatchPending = 189 ,   kTopEarlgreyPlicIrqIdAonTimerWkupTimerExpired = 190 ,   kTopEarlgreyPlicIrqIdAonTimerWdogTimerBark = 191 ,   kTopEarlgreyPlicIrqIdSensorCtrlIoStatusChange = 192 ,   kTopEarlgreyPlicIrqIdSensorCtrlInitStatusChange = 193 ,   kTopEarlgreyPlicIrqIdRramCtrlWrEmpty = 194 ,   kTopEarlgreyPlicIrqIdRramCtrlWrLvl = 195 ,   kTopEarlgreyPlicIrqIdRramCtrlRdFull = 196 ,   kTopEarlgreyPlicIrqIdRramCtrlRdLvl = 197 ,   kTopEarlgreyPlicIrqIdRramCtrlOpDone = 198 ,   kTopEarlgreyPlicIrqIdRramCtrlCorr1Err = 199 ,   kTopEarlgreyPlicIrqIdRramCtrlCorr2Err = 200 ,   kTopEarlgreyPlicIrqIdHmacHmacDone = 201 ,   kTopEarlgreyPlicIrqIdHmacFifoEmpty = 202 ,   kTopEarlgreyPlicIrqIdHmacHmacErr = 203 ,   kTopEarlgreyPlicIrqIdKmacKmacDone = 204 ,   kTopEarlgreyPlicIrqIdKmacFifoEmpty = 205 ,   kTopEarlgreyPlicIrqIdKmacKmacErr = 206 ,   kTopEarlgreyPlicIrqIdOtbnDone = 207 ,   kTopEarlgreyPlicIrqIdKeymgrDpeOpDone = 208 ,   kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 209 ,   kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 210 ,   kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 211 ,   kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 212 ,   kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 213 ,   kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 214 ,   kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 215 ,   kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 216 ,   kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 217 ,   kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 218 ,   kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 219 ,   kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 220 ,   kTopEarlgreyPlicIrqIdCheriotMemSysTbreDone = 221 ,   kTopEarlgreyPlicIrqIdLast = 221 }
	PLIC Interrupt Source. More...
enum	top_earlgrey_plic_target {   kTopEarlgreyPlicTargetIbex0 = 0 ,   kTopEarlgreyPlicTargetLast = 0 }
	PLIC Interrupt Target. More...
enum	top_earlgrey_alert_peripheral {   kTopEarlgreyAlertPeripheralExternal = 0 ,   kTopEarlgreyAlertPeripheralUart0 = 1 ,   kTopEarlgreyAlertPeripheralUart1 = 2 ,   kTopEarlgreyAlertPeripheralUart2 = 3 ,   kTopEarlgreyAlertPeripheralUart3 = 4 ,   kTopEarlgreyAlertPeripheralGpio0 = 5 ,   kTopEarlgreyAlertPeripheralGpio1 = 6 ,   kTopEarlgreyAlertPeripheralSpiDevice = 7 ,   kTopEarlgreyAlertPeripheralI2c0 = 8 ,   kTopEarlgreyAlertPeripheralI2c1 = 9 ,   kTopEarlgreyAlertPeripheralI2c2 = 10 ,   kTopEarlgreyAlertPeripheralI3c0 = 11 ,   kTopEarlgreyAlertPeripheralI3c1 = 12 ,   kTopEarlgreyAlertPeripheralRvTimer = 13 ,   kTopEarlgreyAlertPeripheralOtpCtrl = 14 ,   kTopEarlgreyAlertPeripheralLcCtrl = 15 ,   kTopEarlgreyAlertPeripheralSpiHost0 = 16 ,   kTopEarlgreyAlertPeripheralSpiHost1 = 17 ,   kTopEarlgreyAlertPeripheralUsbdev = 18 ,   kTopEarlgreyAlertPeripheralPwrmgr = 19 ,   kTopEarlgreyAlertPeripheralRstmgr = 20 ,   kTopEarlgreyAlertPeripheralClkmgr = 21 ,   kTopEarlgreyAlertPeripheralSysrstCtrl = 22 ,   kTopEarlgreyAlertPeripheralAdcCtrl = 23 ,   kTopEarlgreyAlertPeripheralPinmux = 24 ,   kTopEarlgreyAlertPeripheralAonTimer = 25 ,   kTopEarlgreyAlertPeripheralSensorCtrl = 26 ,   kTopEarlgreyAlertPeripheralSramCtrlRet = 27 ,   kTopEarlgreyAlertPeripheralRramCtrl = 28 ,   kTopEarlgreyAlertPeripheralRvDm = 29 ,   kTopEarlgreyAlertPeripheralRvPlic = 30 ,   kTopEarlgreyAlertPeripheralAes = 31 ,   kTopEarlgreyAlertPeripheralHmac = 32 ,   kTopEarlgreyAlertPeripheralKmac = 33 ,   kTopEarlgreyAlertPeripheralOtbn = 34 ,   kTopEarlgreyAlertPeripheralKeymgrDpe = 35 ,   kTopEarlgreyAlertPeripheralCsrng = 36 ,   kTopEarlgreyAlertPeripheralEntropySrc = 37 ,   kTopEarlgreyAlertPeripheralEdn0 = 38 ,   kTopEarlgreyAlertPeripheralEdn1 = 39 ,   kTopEarlgreyAlertPeripheralSramCtrlMain = 40 ,   kTopEarlgreyAlertPeripheralSramCtrlSec = 41 ,   kTopEarlgreyAlertPeripheralRomCtrl = 42 ,   kTopEarlgreyAlertPeripheralRvCoreIbex = 43 ,   kTopEarlgreyAlertPeripheralCheriotMemSys = 44 ,   kTopEarlgreyAlertPeripheralSramCtrlMeta = 45 ,   kTopEarlgreyAlertPeripheralLast = 45 }
	Alert Handler Source Peripheral. More...
enum	top_earlgrey_alert_id {   kTopEarlgreyAlertIdUart0FatalFault = 0 ,   kTopEarlgreyAlertIdUart1FatalFault = 1 ,   kTopEarlgreyAlertIdUart2FatalFault = 2 ,   kTopEarlgreyAlertIdUart3FatalFault = 3 ,   kTopEarlgreyAlertIdGpio0FatalFault = 4 ,   kTopEarlgreyAlertIdGpio1FatalFault = 5 ,   kTopEarlgreyAlertIdSpiDeviceFatalFault = 6 ,   kTopEarlgreyAlertIdI2c0FatalFault = 7 ,   kTopEarlgreyAlertIdI2c1FatalFault = 8 ,   kTopEarlgreyAlertIdI2c2FatalFault = 9 ,   kTopEarlgreyAlertIdI3c0FatalFault = 10 ,   kTopEarlgreyAlertIdI3c1FatalFault = 11 ,   kTopEarlgreyAlertIdRvTimerFatalFault = 12 ,   kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 13 ,   kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 14 ,   kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 15 ,   kTopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert = 16 ,   kTopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert = 17 ,   kTopEarlgreyAlertIdLcCtrlFatalProgError = 18 ,   kTopEarlgreyAlertIdLcCtrlFatalStateError = 19 ,   kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 20 ,   kTopEarlgreyAlertIdSpiHost0FatalFault = 21 ,   kTopEarlgreyAlertIdSpiHost1FatalFault = 22 ,   kTopEarlgreyAlertIdUsbdevFatalFault = 23 ,   kTopEarlgreyAlertIdPwrmgrFatalFault = 24 ,   kTopEarlgreyAlertIdRstmgrFatalFault = 25 ,   kTopEarlgreyAlertIdRstmgrFatalCnstyFault = 26 ,   kTopEarlgreyAlertIdClkmgrRecovFault = 27 ,   kTopEarlgreyAlertIdClkmgrFatalFault = 28 ,   kTopEarlgreyAlertIdSysrstCtrlFatalFault = 29 ,   kTopEarlgreyAlertIdAdcCtrlFatalFault = 30 ,   kTopEarlgreyAlertIdPinmuxFatalFault = 31 ,   kTopEarlgreyAlertIdAonTimerFatalFault = 32 ,   kTopEarlgreyAlertIdSensorCtrlRecovAlert = 33 ,   kTopEarlgreyAlertIdSensorCtrlFatalAlert = 34 ,   kTopEarlgreyAlertIdSramCtrlRetFatalError = 35 ,   kTopEarlgreyAlertIdRramCtrlRecovErr = 36 ,   kTopEarlgreyAlertIdRramCtrlFatalStdErr = 37 ,   kTopEarlgreyAlertIdRramCtrlFatalErr = 38 ,   kTopEarlgreyAlertIdRramCtrlFatalMacroErr = 39 ,   kTopEarlgreyAlertIdRramCtrlRecovMacroErr = 40 ,   kTopEarlgreyAlertIdRvDmFatalFault = 41 ,   kTopEarlgreyAlertIdRvPlicFatalFault = 42 ,   kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 43 ,   kTopEarlgreyAlertIdAesFatalFault = 44 ,   kTopEarlgreyAlertIdHmacFatalFault = 45 ,   kTopEarlgreyAlertIdKmacRecovOperationErr = 46 ,   kTopEarlgreyAlertIdKmacFatalFaultErr = 47 ,   kTopEarlgreyAlertIdOtbnFatal = 48 ,   kTopEarlgreyAlertIdOtbnRecov = 49 ,   kTopEarlgreyAlertIdKeymgrDpeRecovOperationErr = 50 ,   kTopEarlgreyAlertIdKeymgrDpeFatalFaultErr = 51 ,   kTopEarlgreyAlertIdCsrngRecovAlert = 52 ,   kTopEarlgreyAlertIdCsrngFatalAlert = 53 ,   kTopEarlgreyAlertIdEntropySrcRecovAlert = 54 ,   kTopEarlgreyAlertIdEntropySrcFatalAlert = 55 ,   kTopEarlgreyAlertIdEdn0RecovAlert = 56 ,   kTopEarlgreyAlertIdEdn0FatalAlert = 57 ,   kTopEarlgreyAlertIdEdn1RecovAlert = 58 ,   kTopEarlgreyAlertIdEdn1FatalAlert = 59 ,   kTopEarlgreyAlertIdSramCtrlMainFatalError = 60 ,   kTopEarlgreyAlertIdSramCtrlSecFatalError = 61 ,   kTopEarlgreyAlertIdRomCtrlFatal = 62 ,   kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 63 ,   kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 64 ,   kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 65 ,   kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 66 ,   kTopEarlgreyAlertIdCheriotMemSysFatalFault = 67 ,   kTopEarlgreyAlertIdSramCtrlMetaFatalError = 68 ,   kTopEarlgreyAlertIdLast = 68 }
	Alert Handler Alert Source. More...
enum	top_earlgrey_pinmux_peripheral_in {   kTopEarlgreyPinmuxPeripheralInGpio0Gpio0 = 0 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio1 = 1 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio2 = 2 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio3 = 3 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio4 = 4 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio5 = 5 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio6 = 6 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio7 = 7 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio8 = 8 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio9 = 9 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio10 = 10 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio11 = 11 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio12 = 12 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio13 = 13 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio14 = 14 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio15 = 15 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio16 = 16 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio17 = 17 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio18 = 18 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio19 = 19 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio20 = 20 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio21 = 21 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio22 = 22 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio23 = 23 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio24 = 24 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio25 = 25 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio26 = 26 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio27 = 27 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio28 = 28 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio29 = 29 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio30 = 30 ,   kTopEarlgreyPinmuxPeripheralInGpio0Gpio31 = 31 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio0 = 32 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio1 = 33 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio2 = 34 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio3 = 35 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio4 = 36 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio5 = 37 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio6 = 38 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio7 = 39 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio8 = 40 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio9 = 41 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio10 = 42 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio11 = 43 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio12 = 44 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio13 = 45 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio14 = 46 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio15 = 47 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio16 = 48 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio17 = 49 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio18 = 50 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio19 = 51 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio20 = 52 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio21 = 53 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio22 = 54 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio23 = 55 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio24 = 56 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio25 = 57 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio26 = 58 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio27 = 59 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio28 = 60 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio29 = 61 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio30 = 62 ,   kTopEarlgreyPinmuxPeripheralInGpio1Gpio31 = 63 ,   kTopEarlgreyPinmuxPeripheralInI2c0Sda = 64 ,   kTopEarlgreyPinmuxPeripheralInI2c0Scl = 65 ,   kTopEarlgreyPinmuxPeripheralInI2c1Sda = 66 ,   kTopEarlgreyPinmuxPeripheralInI2c1Scl = 67 ,   kTopEarlgreyPinmuxPeripheralInI2c2Sda = 68 ,   kTopEarlgreyPinmuxPeripheralInI2c2Scl = 69 ,   kTopEarlgreyPinmuxPeripheralInI3c0Scl = 70 ,   kTopEarlgreyPinmuxPeripheralInI3c0Sda = 71 ,   kTopEarlgreyPinmuxPeripheralInI3c1Scl = 72 ,   kTopEarlgreyPinmuxPeripheralInI3c1Sda = 73 ,   kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0 = 74 ,   kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1 = 75 ,   kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2 = 76 ,   kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3 = 77 ,   kTopEarlgreyPinmuxPeripheralInUart0Rx = 78 ,   kTopEarlgreyPinmuxPeripheralInUart1Rx = 79 ,   kTopEarlgreyPinmuxPeripheralInUart2Rx = 80 ,   kTopEarlgreyPinmuxPeripheralInUart3Rx = 81 ,   kTopEarlgreyPinmuxPeripheralInI3c0RstdetScl = 82 ,   kTopEarlgreyPinmuxPeripheralInI3c0RstdetSda = 83 ,   kTopEarlgreyPinmuxPeripheralInI3c1RstdetScl = 84 ,   kTopEarlgreyPinmuxPeripheralInI3c1RstdetSda = 85 ,   kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb = 86 ,   kTopEarlgreyPinmuxPeripheralInRramMacroTck = 87 ,   kTopEarlgreyPinmuxPeripheralInRramMacroTms = 88 ,   kTopEarlgreyPinmuxPeripheralInRramMacroTdi = 89 ,   kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent = 90 ,   kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In = 91 ,   kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In = 92 ,   kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey2In = 93 ,   kTopEarlgreyPinmuxPeripheralInSysrstCtrlPwrbIn = 94 ,   kTopEarlgreyPinmuxPeripheralInSysrstCtrlLidOpen = 95 ,   kTopEarlgreyPinmuxPeripheralInUsbdevSense = 96 ,   kTopEarlgreyPinmuxPeripheralInLast = 96 }
	Pinmux Peripheral Input. More...
enum	top_earlgrey_pinmux_insel {   kTopEarlgreyPinmuxInselConstantZero = 0 ,   kTopEarlgreyPinmuxInselConstantOne = 1 ,   kTopEarlgreyPinmuxInselIoa0 = 2 ,   kTopEarlgreyPinmuxInselIoa1 = 3 ,   kTopEarlgreyPinmuxInselIoa2 = 4 ,   kTopEarlgreyPinmuxInselIoa3 = 5 ,   kTopEarlgreyPinmuxInselIoa4 = 6 ,   kTopEarlgreyPinmuxInselIoa5 = 7 ,   kTopEarlgreyPinmuxInselIoa6 = 8 ,   kTopEarlgreyPinmuxInselIoa7 = 9 ,   kTopEarlgreyPinmuxInselIoa8 = 10 ,   kTopEarlgreyPinmuxInselIob0 = 11 ,   kTopEarlgreyPinmuxInselIob1 = 12 ,   kTopEarlgreyPinmuxInselIob2 = 13 ,   kTopEarlgreyPinmuxInselIob3 = 14 ,   kTopEarlgreyPinmuxInselIob4 = 15 ,   kTopEarlgreyPinmuxInselIob5 = 16 ,   kTopEarlgreyPinmuxInselIob6 = 17 ,   kTopEarlgreyPinmuxInselIob7 = 18 ,   kTopEarlgreyPinmuxInselIob8 = 19 ,   kTopEarlgreyPinmuxInselIob9 = 20 ,   kTopEarlgreyPinmuxInselIob10 = 21 ,   kTopEarlgreyPinmuxInselIob11 = 22 ,   kTopEarlgreyPinmuxInselIob12 = 23 ,   kTopEarlgreyPinmuxInselIoc0 = 24 ,   kTopEarlgreyPinmuxInselIoc1 = 25 ,   kTopEarlgreyPinmuxInselIoc2 = 26 ,   kTopEarlgreyPinmuxInselIoc3 = 27 ,   kTopEarlgreyPinmuxInselIoc4 = 28 ,   kTopEarlgreyPinmuxInselIoc5 = 29 ,   kTopEarlgreyPinmuxInselIoc6 = 30 ,   kTopEarlgreyPinmuxInselIoc7 = 31 ,   kTopEarlgreyPinmuxInselIoc8 = 32 ,   kTopEarlgreyPinmuxInselIoc9 = 33 ,   kTopEarlgreyPinmuxInselIoc10 = 34 ,   kTopEarlgreyPinmuxInselIoc11 = 35 ,   kTopEarlgreyPinmuxInselIoc12 = 36 ,   kTopEarlgreyPinmuxInselIor0 = 37 ,   kTopEarlgreyPinmuxInselIor1 = 38 ,   kTopEarlgreyPinmuxInselIor2 = 39 ,   kTopEarlgreyPinmuxInselIor3 = 40 ,   kTopEarlgreyPinmuxInselIor4 = 41 ,   kTopEarlgreyPinmuxInselIor5 = 42 ,   kTopEarlgreyPinmuxInselIor6 = 43 ,   kTopEarlgreyPinmuxInselIor7 = 44 ,   kTopEarlgreyPinmuxInselIor10 = 45 ,   kTopEarlgreyPinmuxInselIor11 = 46 ,   kTopEarlgreyPinmuxInselIor12 = 47 ,   kTopEarlgreyPinmuxInselIor13 = 48 ,   kTopEarlgreyPinmuxInselLast = 48 }
	Pinmux MIO Input Selector. More...
enum	top_earlgrey_pinmux_mio_out {   kTopEarlgreyPinmuxMioOutIoa0 = 0 ,   kTopEarlgreyPinmuxMioOutIoa1 = 1 ,   kTopEarlgreyPinmuxMioOutIoa2 = 2 ,   kTopEarlgreyPinmuxMioOutIoa3 = 3 ,   kTopEarlgreyPinmuxMioOutIoa4 = 4 ,   kTopEarlgreyPinmuxMioOutIoa5 = 5 ,   kTopEarlgreyPinmuxMioOutIoa6 = 6 ,   kTopEarlgreyPinmuxMioOutIoa7 = 7 ,   kTopEarlgreyPinmuxMioOutIoa8 = 8 ,   kTopEarlgreyPinmuxMioOutIob0 = 9 ,   kTopEarlgreyPinmuxMioOutIob1 = 10 ,   kTopEarlgreyPinmuxMioOutIob2 = 11 ,   kTopEarlgreyPinmuxMioOutIob3 = 12 ,   kTopEarlgreyPinmuxMioOutIob4 = 13 ,   kTopEarlgreyPinmuxMioOutIob5 = 14 ,   kTopEarlgreyPinmuxMioOutIob6 = 15 ,   kTopEarlgreyPinmuxMioOutIob7 = 16 ,   kTopEarlgreyPinmuxMioOutIob8 = 17 ,   kTopEarlgreyPinmuxMioOutIob9 = 18 ,   kTopEarlgreyPinmuxMioOutIob10 = 19 ,   kTopEarlgreyPinmuxMioOutIob11 = 20 ,   kTopEarlgreyPinmuxMioOutIob12 = 21 ,   kTopEarlgreyPinmuxMioOutIoc0 = 22 ,   kTopEarlgreyPinmuxMioOutIoc1 = 23 ,   kTopEarlgreyPinmuxMioOutIoc2 = 24 ,   kTopEarlgreyPinmuxMioOutIoc3 = 25 ,   kTopEarlgreyPinmuxMioOutIoc4 = 26 ,   kTopEarlgreyPinmuxMioOutIoc5 = 27 ,   kTopEarlgreyPinmuxMioOutIoc6 = 28 ,   kTopEarlgreyPinmuxMioOutIoc7 = 29 ,   kTopEarlgreyPinmuxMioOutIoc8 = 30 ,   kTopEarlgreyPinmuxMioOutIoc9 = 31 ,   kTopEarlgreyPinmuxMioOutIoc10 = 32 ,   kTopEarlgreyPinmuxMioOutIoc11 = 33 ,   kTopEarlgreyPinmuxMioOutIoc12 = 34 ,   kTopEarlgreyPinmuxMioOutIor0 = 35 ,   kTopEarlgreyPinmuxMioOutIor1 = 36 ,   kTopEarlgreyPinmuxMioOutIor2 = 37 ,   kTopEarlgreyPinmuxMioOutIor3 = 38 ,   kTopEarlgreyPinmuxMioOutIor4 = 39 ,   kTopEarlgreyPinmuxMioOutIor5 = 40 ,   kTopEarlgreyPinmuxMioOutIor6 = 41 ,   kTopEarlgreyPinmuxMioOutIor7 = 42 ,   kTopEarlgreyPinmuxMioOutIor10 = 43 ,   kTopEarlgreyPinmuxMioOutIor11 = 44 ,   kTopEarlgreyPinmuxMioOutIor12 = 45 ,   kTopEarlgreyPinmuxMioOutIor13 = 46 ,   kTopEarlgreyPinmuxMioOutLast = 46 }
	Pinmux MIO Output. More...
enum	top_earlgrey_pinmux_outsel {   kTopEarlgreyPinmuxOutselConstantZero = 0 ,   kTopEarlgreyPinmuxOutselConstantOne = 1 ,   kTopEarlgreyPinmuxOutselConstantHighZ = 2 ,   kTopEarlgreyPinmuxOutselGpio0Gpio0 = 3 ,   kTopEarlgreyPinmuxOutselGpio0Gpio1 = 4 ,   kTopEarlgreyPinmuxOutselGpio0Gpio2 = 5 ,   kTopEarlgreyPinmuxOutselGpio0Gpio3 = 6 ,   kTopEarlgreyPinmuxOutselGpio0Gpio4 = 7 ,   kTopEarlgreyPinmuxOutselGpio0Gpio5 = 8 ,   kTopEarlgreyPinmuxOutselGpio0Gpio6 = 9 ,   kTopEarlgreyPinmuxOutselGpio0Gpio7 = 10 ,   kTopEarlgreyPinmuxOutselGpio0Gpio8 = 11 ,   kTopEarlgreyPinmuxOutselGpio0Gpio9 = 12 ,   kTopEarlgreyPinmuxOutselGpio0Gpio10 = 13 ,   kTopEarlgreyPinmuxOutselGpio0Gpio11 = 14 ,   kTopEarlgreyPinmuxOutselGpio0Gpio12 = 15 ,   kTopEarlgreyPinmuxOutselGpio0Gpio13 = 16 ,   kTopEarlgreyPinmuxOutselGpio0Gpio14 = 17 ,   kTopEarlgreyPinmuxOutselGpio0Gpio15 = 18 ,   kTopEarlgreyPinmuxOutselGpio0Gpio16 = 19 ,   kTopEarlgreyPinmuxOutselGpio0Gpio17 = 20 ,   kTopEarlgreyPinmuxOutselGpio0Gpio18 = 21 ,   kTopEarlgreyPinmuxOutselGpio0Gpio19 = 22 ,   kTopEarlgreyPinmuxOutselGpio0Gpio20 = 23 ,   kTopEarlgreyPinmuxOutselGpio0Gpio21 = 24 ,   kTopEarlgreyPinmuxOutselGpio0Gpio22 = 25 ,   kTopEarlgreyPinmuxOutselGpio0Gpio23 = 26 ,   kTopEarlgreyPinmuxOutselGpio0Gpio24 = 27 ,   kTopEarlgreyPinmuxOutselGpio0Gpio25 = 28 ,   kTopEarlgreyPinmuxOutselGpio0Gpio26 = 29 ,   kTopEarlgreyPinmuxOutselGpio0Gpio27 = 30 ,   kTopEarlgreyPinmuxOutselGpio0Gpio28 = 31 ,   kTopEarlgreyPinmuxOutselGpio0Gpio29 = 32 ,   kTopEarlgreyPinmuxOutselGpio0Gpio30 = 33 ,   kTopEarlgreyPinmuxOutselGpio0Gpio31 = 34 ,   kTopEarlgreyPinmuxOutselGpio1Gpio0 = 35 ,   kTopEarlgreyPinmuxOutselGpio1Gpio1 = 36 ,   kTopEarlgreyPinmuxOutselGpio1Gpio2 = 37 ,   kTopEarlgreyPinmuxOutselGpio1Gpio3 = 38 ,   kTopEarlgreyPinmuxOutselGpio1Gpio4 = 39 ,   kTopEarlgreyPinmuxOutselGpio1Gpio5 = 40 ,   kTopEarlgreyPinmuxOutselGpio1Gpio6 = 41 ,   kTopEarlgreyPinmuxOutselGpio1Gpio7 = 42 ,   kTopEarlgreyPinmuxOutselGpio1Gpio8 = 43 ,   kTopEarlgreyPinmuxOutselGpio1Gpio9 = 44 ,   kTopEarlgreyPinmuxOutselGpio1Gpio10 = 45 ,   kTopEarlgreyPinmuxOutselGpio1Gpio11 = 46 ,   kTopEarlgreyPinmuxOutselGpio1Gpio12 = 47 ,   kTopEarlgreyPinmuxOutselGpio1Gpio13 = 48 ,   kTopEarlgreyPinmuxOutselGpio1Gpio14 = 49 ,   kTopEarlgreyPinmuxOutselGpio1Gpio15 = 50 ,   kTopEarlgreyPinmuxOutselGpio1Gpio16 = 51 ,   kTopEarlgreyPinmuxOutselGpio1Gpio17 = 52 ,   kTopEarlgreyPinmuxOutselGpio1Gpio18 = 53 ,   kTopEarlgreyPinmuxOutselGpio1Gpio19 = 54 ,   kTopEarlgreyPinmuxOutselGpio1Gpio20 = 55 ,   kTopEarlgreyPinmuxOutselGpio1Gpio21 = 56 ,   kTopEarlgreyPinmuxOutselGpio1Gpio22 = 57 ,   kTopEarlgreyPinmuxOutselGpio1Gpio23 = 58 ,   kTopEarlgreyPinmuxOutselGpio1Gpio24 = 59 ,   kTopEarlgreyPinmuxOutselGpio1Gpio25 = 60 ,   kTopEarlgreyPinmuxOutselGpio1Gpio26 = 61 ,   kTopEarlgreyPinmuxOutselGpio1Gpio27 = 62 ,   kTopEarlgreyPinmuxOutselGpio1Gpio28 = 63 ,   kTopEarlgreyPinmuxOutselGpio1Gpio29 = 64 ,   kTopEarlgreyPinmuxOutselGpio1Gpio30 = 65 ,   kTopEarlgreyPinmuxOutselGpio1Gpio31 = 66 ,   kTopEarlgreyPinmuxOutselI2c0Sda = 67 ,   kTopEarlgreyPinmuxOutselI2c0Scl = 68 ,   kTopEarlgreyPinmuxOutselI2c1Sda = 69 ,   kTopEarlgreyPinmuxOutselI2c1Scl = 70 ,   kTopEarlgreyPinmuxOutselI2c2Sda = 71 ,   kTopEarlgreyPinmuxOutselI2c2Scl = 72 ,   kTopEarlgreyPinmuxOutselI3c0Scl = 73 ,   kTopEarlgreyPinmuxOutselI3c0Sda = 74 ,   kTopEarlgreyPinmuxOutselI3c1Scl = 75 ,   kTopEarlgreyPinmuxOutselI3c1Sda = 76 ,   kTopEarlgreyPinmuxOutselSpiHost1Sd0 = 77 ,   kTopEarlgreyPinmuxOutselSpiHost1Sd1 = 78 ,   kTopEarlgreyPinmuxOutselSpiHost1Sd2 = 79 ,   kTopEarlgreyPinmuxOutselSpiHost1Sd3 = 80 ,   kTopEarlgreyPinmuxOutselUart0Tx = 81 ,   kTopEarlgreyPinmuxOutselUart1Tx = 82 ,   kTopEarlgreyPinmuxOutselUart2Tx = 83 ,   kTopEarlgreyPinmuxOutselUart3Tx = 84 ,   kTopEarlgreyPinmuxOutselI3c0CtrlSdaPu = 85 ,   kTopEarlgreyPinmuxOutselI3c1CtrlSdaPu = 86 ,   kTopEarlgreyPinmuxOutselSpiHost1Sck = 87 ,   kTopEarlgreyPinmuxOutselSpiHost1Csb = 88 ,   kTopEarlgreyPinmuxOutselRramMacroTdo = 89 ,   kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 = 90 ,   kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 = 91 ,   kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2 = 92 ,   kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut3 = 93 ,   kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut4 = 94 ,   kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut5 = 95 ,   kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut6 = 96 ,   kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut7 = 97 ,   kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut8 = 98 ,   kTopEarlgreyPinmuxOutselSysrstCtrlBatDisable = 99 ,   kTopEarlgreyPinmuxOutselSysrstCtrlKey0Out = 100 ,   kTopEarlgreyPinmuxOutselSysrstCtrlKey1Out = 101 ,   kTopEarlgreyPinmuxOutselSysrstCtrlKey2Out = 102 ,   kTopEarlgreyPinmuxOutselSysrstCtrlPwrbOut = 103 ,   kTopEarlgreyPinmuxOutselSysrstCtrlZ3Wakeup = 104 ,   kTopEarlgreyPinmuxOutselLast = 104 }
	Pinmux Peripheral Output Selector. More...
enum	top_earlgrey_direct_pads {   kTopEarlgreyDirectPadsUsbdevUsbDp = 0 ,   kTopEarlgreyDirectPadsUsbdevUsbDn = 1 ,   kTopEarlgreyDirectPadsSpiHost0Sd0 = 2 ,   kTopEarlgreyDirectPadsSpiHost0Sd1 = 3 ,   kTopEarlgreyDirectPadsSpiHost0Sd2 = 4 ,   kTopEarlgreyDirectPadsSpiHost0Sd3 = 5 ,   kTopEarlgreyDirectPadsSpiDeviceSd0 = 6 ,   kTopEarlgreyDirectPadsSpiDeviceSd1 = 7 ,   kTopEarlgreyDirectPadsSpiDeviceSd2 = 8 ,   kTopEarlgreyDirectPadsSpiDeviceSd3 = 9 ,   kTopEarlgreyDirectPadsSysrstCtrlEcRstL = 10 ,   kTopEarlgreyDirectPadsSysrstCtrlFlashWpL = 11 ,   kTopEarlgreyDirectPadsSpiDeviceSck = 12 ,   kTopEarlgreyDirectPadsSpiDeviceCsb = 13 ,   kTopEarlgreyDirectPadsSpiHost0Sck = 14 ,   kTopEarlgreyDirectPadsSpiHost0Csb = 15 ,   kTopEarlgreyDirectPadsLast = 15 }
	Dedicated Pad Selects. More...
enum	top_earlgrey_muxed_pads {   kTopEarlgreyMuxedPadsIoa0 = 0 ,   kTopEarlgreyMuxedPadsIoa1 = 1 ,   kTopEarlgreyMuxedPadsIoa2 = 2 ,   kTopEarlgreyMuxedPadsIoa3 = 3 ,   kTopEarlgreyMuxedPadsIoa4 = 4 ,   kTopEarlgreyMuxedPadsIoa5 = 5 ,   kTopEarlgreyMuxedPadsIoa6 = 6 ,   kTopEarlgreyMuxedPadsIoa7 = 7 ,   kTopEarlgreyMuxedPadsIoa8 = 8 ,   kTopEarlgreyMuxedPadsIob0 = 9 ,   kTopEarlgreyMuxedPadsIob1 = 10 ,   kTopEarlgreyMuxedPadsIob2 = 11 ,   kTopEarlgreyMuxedPadsIob3 = 12 ,   kTopEarlgreyMuxedPadsIob4 = 13 ,   kTopEarlgreyMuxedPadsIob5 = 14 ,   kTopEarlgreyMuxedPadsIob6 = 15 ,   kTopEarlgreyMuxedPadsIob7 = 16 ,   kTopEarlgreyMuxedPadsIob8 = 17 ,   kTopEarlgreyMuxedPadsIob9 = 18 ,   kTopEarlgreyMuxedPadsIob10 = 19 ,   kTopEarlgreyMuxedPadsIob11 = 20 ,   kTopEarlgreyMuxedPadsIob12 = 21 ,   kTopEarlgreyMuxedPadsIoc0 = 22 ,   kTopEarlgreyMuxedPadsIoc1 = 23 ,   kTopEarlgreyMuxedPadsIoc2 = 24 ,   kTopEarlgreyMuxedPadsIoc3 = 25 ,   kTopEarlgreyMuxedPadsIoc4 = 26 ,   kTopEarlgreyMuxedPadsIoc5 = 27 ,   kTopEarlgreyMuxedPadsIoc6 = 28 ,   kTopEarlgreyMuxedPadsIoc7 = 29 ,   kTopEarlgreyMuxedPadsIoc8 = 30 ,   kTopEarlgreyMuxedPadsIoc9 = 31 ,   kTopEarlgreyMuxedPadsIoc10 = 32 ,   kTopEarlgreyMuxedPadsIoc11 = 33 ,   kTopEarlgreyMuxedPadsIoc12 = 34 ,   kTopEarlgreyMuxedPadsIor0 = 35 ,   kTopEarlgreyMuxedPadsIor1 = 36 ,   kTopEarlgreyMuxedPadsIor2 = 37 ,   kTopEarlgreyMuxedPadsIor3 = 38 ,   kTopEarlgreyMuxedPadsIor4 = 39 ,   kTopEarlgreyMuxedPadsIor5 = 40 ,   kTopEarlgreyMuxedPadsIor6 = 41 ,   kTopEarlgreyMuxedPadsIor7 = 42 ,   kTopEarlgreyMuxedPadsIor10 = 43 ,   kTopEarlgreyMuxedPadsIor11 = 44 ,   kTopEarlgreyMuxedPadsIor12 = 45 ,   kTopEarlgreyMuxedPadsIor13 = 46 ,   kTopEarlgreyMuxedPadsLast = 46 }
	Muxed Pad Selects. More...
enum	top_earlgrey_power_manager_wake_ups {   kTopEarlgreyPowerManagerWakeUpsI3c0RstdetWkupReq = 0 ,   kTopEarlgreyPowerManagerWakeUpsI3c1RstdetWkupReq = 1 ,   kTopEarlgreyPowerManagerWakeUpsSysrstCtrlWkupReq = 2 ,   kTopEarlgreyPowerManagerWakeUpsAdcCtrlWkupReq = 3 ,   kTopEarlgreyPowerManagerWakeUpsPinmuxPinWkupReq = 4 ,   kTopEarlgreyPowerManagerWakeUpsPinmuxUsbWkupReq = 5 ,   kTopEarlgreyPowerManagerWakeUpsAonTimerWkupReq = 6 ,   kTopEarlgreyPowerManagerWakeUpsSensorCtrlWkupReq = 7 ,   kTopEarlgreyPowerManagerWakeUpsLast = 7 }
	Power Manager Wakeup Signals. More...
enum	top_earlgrey_reset_manager_sw_resets {   kTopEarlgreyResetManagerSwResetsSpiDevice = 0 ,   kTopEarlgreyResetManagerSwResetsSpiHost0 = 1 ,   kTopEarlgreyResetManagerSwResetsSpiHost1 = 2 ,   kTopEarlgreyResetManagerSwResetsUsb = 3 ,   kTopEarlgreyResetManagerSwResetsUsbAon = 4 ,   kTopEarlgreyResetManagerSwResetsI2c0 = 5 ,   kTopEarlgreyResetManagerSwResetsI2c1 = 6 ,   kTopEarlgreyResetManagerSwResetsI2c2 = 7 ,   kTopEarlgreyResetManagerSwResetsI3c0 = 8 ,   kTopEarlgreyResetManagerSwResetsI3c1 = 9 ,   kTopEarlgreyResetManagerSwResetsLast = 9 }
	Reset Manager Software Controlled Resets. More...
enum	top_earlgrey_power_manager_reset_requests {   kTopEarlgreyPowerManagerResetRequestsSysrstCtrlRstReq = 0 ,   kTopEarlgreyPowerManagerResetRequestsAonTimerAonTimerRstReq = 1 ,   kTopEarlgreyPowerManagerResetRequestsLast = 1 }
	Power Manager Reset Request Signals. More...
enum	top_earlgrey_gateable_clocks {   kTopEarlgreyGateableClocksIoDiv4Peri = 0 ,   kTopEarlgreyGateableClocksIoDiv2Peri = 1 ,   kTopEarlgreyGateableClocksIoPeri = 2 ,   kTopEarlgreyGateableClocksUsbPeri = 3 ,   kTopEarlgreyGateableClocksIoSpiHost1 = 4 ,   kTopEarlgreyGateableClocksLast = 4 }
	Clock Manager Software-Controlled ("Gated") Clocks. More...
enum	top_earlgrey_hintable_clocks {   kTopEarlgreyHintableClocksMainAes = 0 ,   kTopEarlgreyHintableClocksMainHmac = 1 ,   kTopEarlgreyHintableClocksMainKmac = 2 ,   kTopEarlgreyHintableClocksMainOtbn = 3 ,   kTopEarlgreyHintableClocksLast = 3 }
	Clock Manager Software-Hinted Clocks. More...

Variables
const top_earlgrey_plic_peripheral_t	top_earlgrey_plic_interrupt_for_peripheral [222]
	PLIC Interrupt Source to Peripheral Map.
const top_earlgrey_alert_peripheral_t	top_earlgrey_alert_for_peripheral [69]
	Alert Handler Alert Source to Peripheral Map.

Detailed Description

Top-specific Definitions.

This file contains preprocessor and type definitions for use within the device C/C++ codebase.

These definitions are for information that depends on the top-specific chip configuration, which includes:

• Device Memory Information (for Peripherals and Memory)
• PLIC Interrupt ID Names and Source Mappings
• Alert ID Names and Source Mappings
• Pinmux Pin/Select Names
• Power Manager Wakeups

Definition in file top_earlgrey.h.

Macro Definition Documentation

NUM_DIO_PADS

#define NUM_DIO_PADS   16

Definition at line 1433 of file top_earlgrey.h.

NUM_MIO_PADS

#define NUM_MIO_PADS   47

Definition at line 1432 of file top_earlgrey.h.

PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET   2

Definition at line 1428 of file top_earlgrey.h.

PINMUX_PERIPH_OUTSEL_IDX_OFFSET

#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET   3

Definition at line 1435 of file top_earlgrey.h.

TOP_EARLGREY_ADC_CTRL_BASE_ADDR

#define TOP_EARLGREY_ADC_CTRL_BASE_ADDR   0x40440000u

Peripheral base address for adc_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 453 of file top_earlgrey.h.

TOP_EARLGREY_ADC_CTRL_SIZE_BYTES

#define TOP_EARLGREY_ADC_CTRL_SIZE_BYTES   0x80u

Peripheral size for adc_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_ADC_CTRL_BASE_ADDR and TOP_EARLGREY_ADC_CTRL_BASE_ADDR + TOP_EARLGREY_ADC_CTRL_SIZE_BYTES.

Definition at line 463 of file top_earlgrey.h.

TOP_EARLGREY_AES_BASE_ADDR

#define TOP_EARLGREY_AES_BASE_ADDR   0x41100000u

Peripheral base address for aes in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 651 of file top_earlgrey.h.

TOP_EARLGREY_AES_SIZE_BYTES

#define TOP_EARLGREY_AES_SIZE_BYTES   0x100u

Peripheral size for aes in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_AES_BASE_ADDR and TOP_EARLGREY_AES_BASE_ADDR + TOP_EARLGREY_AES_SIZE_BYTES.

Definition at line 661 of file top_earlgrey.h.

TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR

#define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR   0x40150000u

Peripheral base address for alert_handler in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 309 of file top_earlgrey.h.

TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES

#define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES   0x800u

Peripheral size for alert_handler in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR and TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR + TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES.

Definition at line 319 of file top_earlgrey.h.

TOP_EARLGREY_AON_TIMER_BASE_ADDR

#define TOP_EARLGREY_AON_TIMER_BASE_ADDR   0x40470000u

Peripheral base address for aon_timer in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 489 of file top_earlgrey.h.

TOP_EARLGREY_AON_TIMER_SIZE_BYTES

#define TOP_EARLGREY_AON_TIMER_SIZE_BYTES   0x40u

Peripheral size for aon_timer in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_AON_TIMER_BASE_ADDR and TOP_EARLGREY_AON_TIMER_BASE_ADDR + TOP_EARLGREY_AON_TIMER_SIZE_BYTES.

Definition at line 499 of file top_earlgrey.h.

TOP_EARLGREY_AST_BASE_ADDR

#define TOP_EARLGREY_AST_BASE_ADDR   0x40480000u

Peripheral base address for ast in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 507 of file top_earlgrey.h.

TOP_EARLGREY_AST_SIZE_BYTES

#define TOP_EARLGREY_AST_SIZE_BYTES   0x400u

Peripheral size for ast in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_AST_BASE_ADDR and TOP_EARLGREY_AST_BASE_ADDR + TOP_EARLGREY_AST_SIZE_BYTES.

Definition at line 517 of file top_earlgrey.h.

TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_BASE_ADDR

#define TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_BASE_ADDR   0x411B0000u

Peripheral base address for regs device on cheriot_mem_sys in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 885 of file top_earlgrey.h.

TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_SIZE_BYTES

#define TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_SIZE_BYTES   0x40u

Peripheral size for regs device on cheriot_mem_sys in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_BASE_ADDR and TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_BASE_ADDR + TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_SIZE_BYTES.

Definition at line 895 of file top_earlgrey.h.

TOP_EARLGREY_CHERIOT_MEM_SYS_REVBM_BASE_ADDR

#define TOP_EARLGREY_CHERIOT_MEM_SYS_REVBM_BASE_ADDR   0x11000000u

Memory base address for revbm memory on cheriot_mem_sys in top earlgrey.

Definition at line 969 of file top_earlgrey.h.

TOP_EARLGREY_CHERIOT_MEM_SYS_REVBM_SIZE_BYTES

#define TOP_EARLGREY_CHERIOT_MEM_SYS_REVBM_SIZE_BYTES   0xC00u

Memory size for revbm memory on cheriot_mem_sys in top earlgrey.

Definition at line 974 of file top_earlgrey.h.

TOP_EARLGREY_CLKMGR_BASE_ADDR

#define TOP_EARLGREY_CLKMGR_BASE_ADDR   0x40420000u

Peripheral base address for clkmgr in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 417 of file top_earlgrey.h.

TOP_EARLGREY_CLKMGR_SIZE_BYTES

#define TOP_EARLGREY_CLKMGR_SIZE_BYTES   0x80u

Peripheral size for clkmgr in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_CLKMGR_BASE_ADDR and TOP_EARLGREY_CLKMGR_BASE_ADDR + TOP_EARLGREY_CLKMGR_SIZE_BYTES.

Definition at line 427 of file top_earlgrey.h.

TOP_EARLGREY_CSRNG_BASE_ADDR

#define TOP_EARLGREY_CSRNG_BASE_ADDR   0x41150000u

Peripheral base address for csrng in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 741 of file top_earlgrey.h.

TOP_EARLGREY_CSRNG_SIZE_BYTES

#define TOP_EARLGREY_CSRNG_SIZE_BYTES   0x80u

Peripheral size for csrng in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_CSRNG_BASE_ADDR and TOP_EARLGREY_CSRNG_BASE_ADDR + TOP_EARLGREY_CSRNG_SIZE_BYTES.

Definition at line 751 of file top_earlgrey.h.

TOP_EARLGREY_EDN0_BASE_ADDR

#define TOP_EARLGREY_EDN0_BASE_ADDR   0x41170000u

Peripheral base address for edn0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 777 of file top_earlgrey.h.

TOP_EARLGREY_EDN0_SIZE_BYTES

#define TOP_EARLGREY_EDN0_SIZE_BYTES   0x80u

Peripheral size for edn0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_EDN0_BASE_ADDR and TOP_EARLGREY_EDN0_BASE_ADDR + TOP_EARLGREY_EDN0_SIZE_BYTES.

Definition at line 787 of file top_earlgrey.h.

TOP_EARLGREY_EDN1_BASE_ADDR

#define TOP_EARLGREY_EDN1_BASE_ADDR   0x41180000u

Peripheral base address for edn1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 795 of file top_earlgrey.h.

TOP_EARLGREY_EDN1_SIZE_BYTES

#define TOP_EARLGREY_EDN1_SIZE_BYTES   0x80u

Peripheral size for edn1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_EDN1_BASE_ADDR and TOP_EARLGREY_EDN1_BASE_ADDR + TOP_EARLGREY_EDN1_SIZE_BYTES.

Definition at line 805 of file top_earlgrey.h.

TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR

#define TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR   0x41160000u

Peripheral base address for entropy_src in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 759 of file top_earlgrey.h.

TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES

#define TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES   0x100u

Peripheral size for entropy_src in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR and TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR + TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES.

Definition at line 769 of file top_earlgrey.h.

TOP_EARLGREY_GPIO0_BASE_ADDR

#define TOP_EARLGREY_GPIO0_BASE_ADDR   0x40040000u

Peripheral base address for gpio0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 111 of file top_earlgrey.h.

TOP_EARLGREY_GPIO0_SIZE_BYTES

#define TOP_EARLGREY_GPIO0_SIZE_BYTES   0x400u

Peripheral size for gpio0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_GPIO0_BASE_ADDR and TOP_EARLGREY_GPIO0_BASE_ADDR + TOP_EARLGREY_GPIO0_SIZE_BYTES.

Definition at line 121 of file top_earlgrey.h.

TOP_EARLGREY_GPIO1_BASE_ADDR

#define TOP_EARLGREY_GPIO1_BASE_ADDR   0x40050000u

Peripheral base address for gpio1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 129 of file top_earlgrey.h.

TOP_EARLGREY_GPIO1_SIZE_BYTES

#define TOP_EARLGREY_GPIO1_SIZE_BYTES   0x400u

Peripheral size for gpio1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_GPIO1_BASE_ADDR and TOP_EARLGREY_GPIO1_BASE_ADDR + TOP_EARLGREY_GPIO1_SIZE_BYTES.

Definition at line 139 of file top_earlgrey.h.

TOP_EARLGREY_HMAC_BASE_ADDR

#define TOP_EARLGREY_HMAC_BASE_ADDR   0x41110000u

Peripheral base address for hmac in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 669 of file top_earlgrey.h.

TOP_EARLGREY_HMAC_SIZE_BYTES

#define TOP_EARLGREY_HMAC_SIZE_BYTES   0x2000u

Peripheral size for hmac in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_HMAC_BASE_ADDR and TOP_EARLGREY_HMAC_BASE_ADDR + TOP_EARLGREY_HMAC_SIZE_BYTES.

Definition at line 679 of file top_earlgrey.h.

TOP_EARLGREY_I2C0_BASE_ADDR

#define TOP_EARLGREY_I2C0_BASE_ADDR   0x40080000u

Peripheral base address for i2c0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 165 of file top_earlgrey.h.

TOP_EARLGREY_I2C0_SIZE_BYTES

#define TOP_EARLGREY_I2C0_SIZE_BYTES   0x80u

Peripheral size for i2c0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_I2C0_BASE_ADDR and TOP_EARLGREY_I2C0_BASE_ADDR + TOP_EARLGREY_I2C0_SIZE_BYTES.

Definition at line 175 of file top_earlgrey.h.

TOP_EARLGREY_I2C1_BASE_ADDR

#define TOP_EARLGREY_I2C1_BASE_ADDR   0x40090000u

Peripheral base address for i2c1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 183 of file top_earlgrey.h.

TOP_EARLGREY_I2C1_SIZE_BYTES

#define TOP_EARLGREY_I2C1_SIZE_BYTES   0x80u

Peripheral size for i2c1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_I2C1_BASE_ADDR and TOP_EARLGREY_I2C1_BASE_ADDR + TOP_EARLGREY_I2C1_SIZE_BYTES.

Definition at line 193 of file top_earlgrey.h.

TOP_EARLGREY_I2C2_BASE_ADDR

#define TOP_EARLGREY_I2C2_BASE_ADDR   0x400A0000u

Peripheral base address for i2c2 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 201 of file top_earlgrey.h.

TOP_EARLGREY_I2C2_SIZE_BYTES

#define TOP_EARLGREY_I2C2_SIZE_BYTES   0x80u

Peripheral size for i2c2 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_I2C2_BASE_ADDR and TOP_EARLGREY_I2C2_BASE_ADDR + TOP_EARLGREY_I2C2_SIZE_BYTES.

Definition at line 211 of file top_earlgrey.h.

TOP_EARLGREY_I3C0_BASE_ADDR

#define TOP_EARLGREY_I3C0_BASE_ADDR   0x40330000u

Peripheral base address for i3c0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 219 of file top_earlgrey.h.

TOP_EARLGREY_I3C0_SIZE_BYTES

#define TOP_EARLGREY_I3C0_SIZE_BYTES   0x2000u

Peripheral size for i3c0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_I3C0_BASE_ADDR and TOP_EARLGREY_I3C0_BASE_ADDR + TOP_EARLGREY_I3C0_SIZE_BYTES.

Definition at line 229 of file top_earlgrey.h.

TOP_EARLGREY_I3C1_BASE_ADDR

#define TOP_EARLGREY_I3C1_BASE_ADDR   0x40340000u

Peripheral base address for i3c1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 237 of file top_earlgrey.h.

TOP_EARLGREY_I3C1_SIZE_BYTES

#define TOP_EARLGREY_I3C1_SIZE_BYTES   0x2000u

Peripheral size for i3c1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_I3C1_BASE_ADDR and TOP_EARLGREY_I3C1_BASE_ADDR + TOP_EARLGREY_I3C1_SIZE_BYTES.

Definition at line 247 of file top_earlgrey.h.

TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR

#define TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR   0x41140000u

Peripheral base address for keymgr_dpe in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 723 of file top_earlgrey.h.

TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES

#define TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES   0x200u

Peripheral size for keymgr_dpe in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR and TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR + TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES.

Definition at line 733 of file top_earlgrey.h.

TOP_EARLGREY_KMAC_BASE_ADDR

#define TOP_EARLGREY_KMAC_BASE_ADDR   0x41120000u

Peripheral base address for kmac in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 687 of file top_earlgrey.h.

TOP_EARLGREY_KMAC_SIZE_BYTES

#define TOP_EARLGREY_KMAC_SIZE_BYTES   0x1000u

Peripheral size for kmac in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_KMAC_BASE_ADDR and TOP_EARLGREY_KMAC_BASE_ADDR + TOP_EARLGREY_KMAC_SIZE_BYTES.

Definition at line 697 of file top_earlgrey.h.

TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR

#define TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR   0x40140000u

Peripheral base address for regs device on lc_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 291 of file top_earlgrey.h.

TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES

#define TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES   0x100u

Peripheral size for regs device on lc_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR and TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES.

Definition at line 301 of file top_earlgrey.h.

TOP_EARLGREY_MMIO_BASE_ADDR

#define TOP_EARLGREY_MMIO_BASE_ADDR   0x40000000u

MMIO Region.

MMIO region excludes any memory that is separate from the module configuration space, i.e. ROM, main SRAM, and RRAM are excluded but retention SRAM, spi_device memory, or usbdev memory are included.

Definition at line 1916 of file top_earlgrey.h.

TOP_EARLGREY_MMIO_SIZE_BYTES

#define TOP_EARLGREY_MMIO_SIZE_BYTES   0x10000000u

Definition at line 1917 of file top_earlgrey.h.

TOP_EARLGREY_OTBN_BASE_ADDR

#define TOP_EARLGREY_OTBN_BASE_ADDR   0x41130000u

Peripheral base address for otbn in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 705 of file top_earlgrey.h.

TOP_EARLGREY_OTBN_SIZE_BYTES

#define TOP_EARLGREY_OTBN_SIZE_BYTES   0x10000u

Peripheral size for otbn in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_OTBN_BASE_ADDR and TOP_EARLGREY_OTBN_BASE_ADDR + TOP_EARLGREY_OTBN_SIZE_BYTES.

Definition at line 715 of file top_earlgrey.h.

TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR

#define TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR   0x40130000u

Peripheral base address for core device on otp_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 273 of file top_earlgrey.h.

TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES

#define TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES   0x2000u

Peripheral size for core device on otp_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR and TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES.

Definition at line 283 of file top_earlgrey.h.

TOP_EARLGREY_PINMUX_BASE_ADDR

#define TOP_EARLGREY_PINMUX_BASE_ADDR   0x40460000u

Peripheral base address for pinmux in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 471 of file top_earlgrey.h.

TOP_EARLGREY_PINMUX_SIZE_BYTES

#define TOP_EARLGREY_PINMUX_SIZE_BYTES   0x1000u

Peripheral size for pinmux in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_PINMUX_BASE_ADDR and TOP_EARLGREY_PINMUX_BASE_ADDR + TOP_EARLGREY_PINMUX_SIZE_BYTES.

Definition at line 481 of file top_earlgrey.h.

TOP_EARLGREY_PWRMGR_BASE_ADDR

#define TOP_EARLGREY_PWRMGR_BASE_ADDR   0x40400000u

Peripheral base address for pwrmgr in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 381 of file top_earlgrey.h.

TOP_EARLGREY_PWRMGR_SIZE_BYTES

#define TOP_EARLGREY_PWRMGR_SIZE_BYTES   0x80u

Peripheral size for pwrmgr in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_PWRMGR_BASE_ADDR and TOP_EARLGREY_PWRMGR_BASE_ADDR + TOP_EARLGREY_PWRMGR_SIZE_BYTES.

Definition at line 391 of file top_earlgrey.h.

TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR

#define TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR   0x411E0000u

Peripheral base address for regs device on rom_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 849 of file top_earlgrey.h.

TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES

#define TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES   0x80u

Peripheral size for regs device on rom_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR and TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES.

Definition at line 859 of file top_earlgrey.h.

TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR

#define TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR   0x40000u

Memory base address for rom memory on rom_ctrl in top earlgrey.

Definition at line 959 of file top_earlgrey.h.

TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES

#define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES   0x30000u

Memory size for rom memory on rom_ctrl in top earlgrey.

Definition at line 964 of file top_earlgrey.h.

TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR

#define TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR   0x41010000u

Peripheral base address for core device on rram_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 561 of file top_earlgrey.h.

TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES

#define TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES   0x400u

Peripheral size for core device on rram_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR and TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES.

Definition at line 571 of file top_earlgrey.h.

TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR

#define TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR   0x30000000u

Memory base address for host memory on rram_ctrl in top earlgrey.

Definition at line 929 of file top_earlgrey.h.

TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES

#define TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES   0x200000u

Memory size for host memory on rram_ctrl in top earlgrey.

Definition at line 934 of file top_earlgrey.h.

TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR

#define TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR   0x41018000u

Peripheral base address for prim device on rram_macro in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 579 of file top_earlgrey.h.

TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES

#define TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES   0x10u

Peripheral size for prim device on rram_macro in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR and TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR + TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES.

Definition at line 589 of file top_earlgrey.h.

TOP_EARLGREY_RSTMGR_BASE_ADDR

#define TOP_EARLGREY_RSTMGR_BASE_ADDR   0x40410000u

Peripheral base address for rstmgr in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 399 of file top_earlgrey.h.

TOP_EARLGREY_RSTMGR_SIZE_BYTES

#define TOP_EARLGREY_RSTMGR_SIZE_BYTES   0x80u

Peripheral size for rstmgr in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RSTMGR_BASE_ADDR and TOP_EARLGREY_RSTMGR_BASE_ADDR + TOP_EARLGREY_RSTMGR_SIZE_BYTES.

Definition at line 409 of file top_earlgrey.h.

TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR

#define TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR   0x411F0000u

Peripheral base address for cfg device on rv_core_ibex in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 867 of file top_earlgrey.h.

TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES

#define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES   0x100u

Peripheral size for cfg device on rv_core_ibex in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR and TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES.

Definition at line 877 of file top_earlgrey.h.

TOP_EARLGREY_RV_DM_MEM_BASE_ADDR

#define TOP_EARLGREY_RV_DM_MEM_BASE_ADDR   0x10000u

Peripheral base address for mem device on rv_dm in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 615 of file top_earlgrey.h.

TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES

#define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES   0x1000u

Peripheral size for mem device on rv_dm in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_DM_MEM_BASE_ADDR and TOP_EARLGREY_RV_DM_MEM_BASE_ADDR + TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES.

Definition at line 625 of file top_earlgrey.h.

TOP_EARLGREY_RV_DM_REGS_BASE_ADDR

#define TOP_EARLGREY_RV_DM_REGS_BASE_ADDR   0x41200000u

Peripheral base address for regs device on rv_dm in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 597 of file top_earlgrey.h.

TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES

#define TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES   0x10u

Peripheral size for regs device on rv_dm in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_DM_REGS_BASE_ADDR and TOP_EARLGREY_RV_DM_REGS_BASE_ADDR + TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES.

Definition at line 607 of file top_earlgrey.h.

TOP_EARLGREY_RV_PLIC_BASE_ADDR

#define TOP_EARLGREY_RV_PLIC_BASE_ADDR   0x48000000u

Peripheral base address for rv_plic in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 633 of file top_earlgrey.h.

TOP_EARLGREY_RV_PLIC_SIZE_BYTES

#define TOP_EARLGREY_RV_PLIC_SIZE_BYTES   0x8000000u

Peripheral size for rv_plic in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_PLIC_BASE_ADDR and TOP_EARLGREY_RV_PLIC_BASE_ADDR + TOP_EARLGREY_RV_PLIC_SIZE_BYTES.

Definition at line 643 of file top_earlgrey.h.

TOP_EARLGREY_RV_TIMER_BASE_ADDR

#define TOP_EARLGREY_RV_TIMER_BASE_ADDR   0x40100000u

Peripheral base address for rv_timer in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 255 of file top_earlgrey.h.

TOP_EARLGREY_RV_TIMER_SIZE_BYTES

#define TOP_EARLGREY_RV_TIMER_SIZE_BYTES   0x200u

Peripheral size for rv_timer in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_TIMER_BASE_ADDR and TOP_EARLGREY_RV_TIMER_BASE_ADDR + TOP_EARLGREY_RV_TIMER_SIZE_BYTES.

Definition at line 265 of file top_earlgrey.h.

TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR

#define TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR   0x40490000u

Peripheral base address for sensor_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 525 of file top_earlgrey.h.

TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES

#define TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES   0x80u

Peripheral size for sensor_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR and TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES.

Definition at line 535 of file top_earlgrey.h.

TOP_EARLGREY_SPI_DEVICE_BASE_ADDR

#define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR   0x40060000u

Peripheral base address for spi_device in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 147 of file top_earlgrey.h.

TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES

#define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES   0x2000u

Peripheral size for spi_device in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SPI_DEVICE_BASE_ADDR and TOP_EARLGREY_SPI_DEVICE_BASE_ADDR + TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES.

Definition at line 157 of file top_earlgrey.h.

TOP_EARLGREY_SPI_HOST0_BASE_ADDR

#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR   0x40300000u

Peripheral base address for spi_host0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 327 of file top_earlgrey.h.

TOP_EARLGREY_SPI_HOST0_SIZE_BYTES

#define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES   0x40u

Peripheral size for spi_host0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SPI_HOST0_BASE_ADDR and TOP_EARLGREY_SPI_HOST0_BASE_ADDR + TOP_EARLGREY_SPI_HOST0_SIZE_BYTES.

Definition at line 337 of file top_earlgrey.h.

TOP_EARLGREY_SPI_HOST1_BASE_ADDR

#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR   0x40310000u

Peripheral base address for spi_host1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 345 of file top_earlgrey.h.

TOP_EARLGREY_SPI_HOST1_SIZE_BYTES

#define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES   0x40u

Peripheral size for spi_host1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SPI_HOST1_BASE_ADDR and TOP_EARLGREY_SPI_HOST1_BASE_ADDR + TOP_EARLGREY_SPI_HOST1_SIZE_BYTES.

Definition at line 355 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR   0x10000000u

Memory base address for ram memory on sram_ctrl_main in top earlgrey.

Definition at line 939 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES   0x20000u

Memory size for ram memory on sram_ctrl_main in top earlgrey.

Definition at line 944 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR   0x411C0000u

Peripheral base address for regs device on sram_ctrl_main in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 813 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES   0x40u

Peripheral size for regs device on sram_ctrl_main in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR and TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES.

Definition at line 823 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_META_RAM_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_META_RAM_BASE_ADDR   0x11000000u

Memory base address for ram memory on sram_ctrl_meta in top earlgrey.

Definition at line 979 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_META_RAM_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_META_RAM_SIZE_BYTES   0x9800u

Memory size for ram memory on sram_ctrl_meta in top earlgrey.

Definition at line 984 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR   0x411A0000u

Peripheral base address for regs device on sram_ctrl_meta in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 903 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES   0x40u

Peripheral size for regs device on sram_ctrl_meta in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR and TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES.

Definition at line 913 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_RET_RAM_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_RET_RAM_BASE_ADDR   0x40600000u

Memory base address for ram memory on sram_ctrl_ret in top earlgrey.

Definition at line 919 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_RET_RAM_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_RET_RAM_SIZE_BYTES   0x2000u

Memory size for ram memory on sram_ctrl_ret in top earlgrey.

Definition at line 924 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_RET_REGS_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_RET_REGS_BASE_ADDR   0x40500000u

Peripheral base address for regs device on sram_ctrl_ret in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 543 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES   0x40u

Peripheral size for regs device on sram_ctrl_ret in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SRAM_CTRL_RET_REGS_BASE_ADDR and TOP_EARLGREY_SRAM_CTRL_RET_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES.

Definition at line 553 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_SEC_RAM_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_SEC_RAM_BASE_ADDR   0x10020000u

Memory base address for ram memory on sram_ctrl_sec in top earlgrey.

Definition at line 949 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_SEC_RAM_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_SEC_RAM_SIZE_BYTES   0x10000u

Memory size for ram memory on sram_ctrl_sec in top earlgrey.

Definition at line 954 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_SEC_REGS_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_SEC_REGS_BASE_ADDR   0x411D0000u

Peripheral base address for regs device on sram_ctrl_sec in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 831 of file top_earlgrey.h.

TOP_EARLGREY_SRAM_CTRL_SEC_REGS_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_SEC_REGS_SIZE_BYTES   0x40u

Peripheral size for regs device on sram_ctrl_sec in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SRAM_CTRL_SEC_REGS_BASE_ADDR and TOP_EARLGREY_SRAM_CTRL_SEC_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_SEC_REGS_SIZE_BYTES.

Definition at line 841 of file top_earlgrey.h.

TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR

#define TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR   0x40430000u

Peripheral base address for sysrst_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 435 of file top_earlgrey.h.

TOP_EARLGREY_SYSRST_CTRL_SIZE_BYTES

#define TOP_EARLGREY_SYSRST_CTRL_SIZE_BYTES   0x100u

Peripheral size for sysrst_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR and TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR + TOP_EARLGREY_SYSRST_CTRL_SIZE_BYTES.

Definition at line 445 of file top_earlgrey.h.

TOP_EARLGREY_UART0_BASE_ADDR

#define TOP_EARLGREY_UART0_BASE_ADDR   0x40000000u

Peripheral base address for uart0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 39 of file top_earlgrey.h.

TOP_EARLGREY_UART0_SIZE_BYTES

#define TOP_EARLGREY_UART0_SIZE_BYTES   0x40u

Peripheral size for uart0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_UART0_BASE_ADDR and TOP_EARLGREY_UART0_BASE_ADDR + TOP_EARLGREY_UART0_SIZE_BYTES.

Definition at line 49 of file top_earlgrey.h.

TOP_EARLGREY_UART1_BASE_ADDR

#define TOP_EARLGREY_UART1_BASE_ADDR   0x40010000u

Peripheral base address for uart1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 57 of file top_earlgrey.h.

TOP_EARLGREY_UART1_SIZE_BYTES

#define TOP_EARLGREY_UART1_SIZE_BYTES   0x40u

Peripheral size for uart1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_UART1_BASE_ADDR and TOP_EARLGREY_UART1_BASE_ADDR + TOP_EARLGREY_UART1_SIZE_BYTES.

Definition at line 67 of file top_earlgrey.h.

TOP_EARLGREY_UART2_BASE_ADDR

#define TOP_EARLGREY_UART2_BASE_ADDR   0x40020000u

Peripheral base address for uart2 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 75 of file top_earlgrey.h.

TOP_EARLGREY_UART2_SIZE_BYTES

#define TOP_EARLGREY_UART2_SIZE_BYTES   0x40u

Peripheral size for uart2 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_UART2_BASE_ADDR and TOP_EARLGREY_UART2_BASE_ADDR + TOP_EARLGREY_UART2_SIZE_BYTES.

Definition at line 85 of file top_earlgrey.h.

TOP_EARLGREY_UART3_BASE_ADDR

#define TOP_EARLGREY_UART3_BASE_ADDR   0x40030000u

Peripheral base address for uart3 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 93 of file top_earlgrey.h.

TOP_EARLGREY_UART3_SIZE_BYTES

#define TOP_EARLGREY_UART3_SIZE_BYTES   0x40u

Peripheral size for uart3 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_UART3_BASE_ADDR and TOP_EARLGREY_UART3_BASE_ADDR + TOP_EARLGREY_UART3_SIZE_BYTES.

Definition at line 103 of file top_earlgrey.h.

TOP_EARLGREY_USBDEV_BASE_ADDR

#define TOP_EARLGREY_USBDEV_BASE_ADDR   0x40320000u

Peripheral base address for usbdev in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 363 of file top_earlgrey.h.

TOP_EARLGREY_USBDEV_SIZE_BYTES

#define TOP_EARLGREY_USBDEV_SIZE_BYTES   0x1000u

Peripheral size for usbdev in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_USBDEV_BASE_ADDR and TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES.

Definition at line 373 of file top_earlgrey.h.

Typedef Documentation

top_earlgrey_alert_id_t

typedef enum top_earlgrey_alert_id top_earlgrey_alert_id_t

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

top_earlgrey_alert_peripheral_t

typedef enum top_earlgrey_alert_peripheral top_earlgrey_alert_peripheral_t

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

top_earlgrey_gateable_clocks_t

typedef enum top_earlgrey_gateable_clocks top_earlgrey_gateable_clocks_t

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

top_earlgrey_hintable_clocks_t

typedef enum top_earlgrey_hintable_clocks top_earlgrey_hintable_clocks_t

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

top_earlgrey_plic_irq_id_t

typedef enum top_earlgrey_plic_irq_id top_earlgrey_plic_irq_id_t

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

top_earlgrey_plic_peripheral_t

typedef enum top_earlgrey_plic_peripheral top_earlgrey_plic_peripheral_t

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

top_earlgrey_plic_target_t

typedef enum top_earlgrey_plic_target top_earlgrey_plic_target_t

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumeration Type Documentation

top_earlgrey_alert_id

enum top_earlgrey_alert_id

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopEarlgreyAlertIdUart0FatalFault	uart0_fatal_fault
kTopEarlgreyAlertIdUart1FatalFault	uart1_fatal_fault
kTopEarlgreyAlertIdUart2FatalFault	uart2_fatal_fault
kTopEarlgreyAlertIdUart3FatalFault	uart3_fatal_fault
kTopEarlgreyAlertIdGpio0FatalFault	gpio0_fatal_fault
kTopEarlgreyAlertIdGpio1FatalFault	gpio1_fatal_fault
kTopEarlgreyAlertIdSpiDeviceFatalFault	spi_device_fatal_fault
kTopEarlgreyAlertIdI2c0FatalFault	i2c0_fatal_fault
kTopEarlgreyAlertIdI2c1FatalFault	i2c1_fatal_fault
kTopEarlgreyAlertIdI2c2FatalFault	i2c2_fatal_fault
kTopEarlgreyAlertIdI3c0FatalFault	i3c0_fatal_fault
kTopEarlgreyAlertIdI3c1FatalFault	i3c1_fatal_fault
kTopEarlgreyAlertIdRvTimerFatalFault	rv_timer_fatal_fault
kTopEarlgreyAlertIdOtpCtrlFatalMacroError	otp_ctrl_fatal_macro_error
kTopEarlgreyAlertIdOtpCtrlFatalCheckError	otp_ctrl_fatal_check_error
kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError	otp_ctrl_fatal_bus_integ_error
kTopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert	otp_ctrl_fatal_prim_otp_alert
kTopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert	otp_ctrl_recov_prim_otp_alert
kTopEarlgreyAlertIdLcCtrlFatalProgError	lc_ctrl_fatal_prog_error
kTopEarlgreyAlertIdLcCtrlFatalStateError	lc_ctrl_fatal_state_error
kTopEarlgreyAlertIdLcCtrlFatalBusIntegError	lc_ctrl_fatal_bus_integ_error
kTopEarlgreyAlertIdSpiHost0FatalFault	spi_host0_fatal_fault
kTopEarlgreyAlertIdSpiHost1FatalFault	spi_host1_fatal_fault
kTopEarlgreyAlertIdUsbdevFatalFault	usbdev_fatal_fault
kTopEarlgreyAlertIdPwrmgrFatalFault	pwrmgr_fatal_fault
kTopEarlgreyAlertIdRstmgrFatalFault	rstmgr_fatal_fault
kTopEarlgreyAlertIdRstmgrFatalCnstyFault	rstmgr_fatal_cnsty_fault
kTopEarlgreyAlertIdClkmgrRecovFault	clkmgr_recov_fault
kTopEarlgreyAlertIdClkmgrFatalFault	clkmgr_fatal_fault
kTopEarlgreyAlertIdSysrstCtrlFatalFault	sysrst_ctrl_fatal_fault
kTopEarlgreyAlertIdAdcCtrlFatalFault	adc_ctrl_fatal_fault
kTopEarlgreyAlertIdPinmuxFatalFault	pinmux_fatal_fault
kTopEarlgreyAlertIdAonTimerFatalFault	aon_timer_fatal_fault
kTopEarlgreyAlertIdSensorCtrlRecovAlert	sensor_ctrl_recov_alert
kTopEarlgreyAlertIdSensorCtrlFatalAlert	sensor_ctrl_fatal_alert
kTopEarlgreyAlertIdSramCtrlRetFatalError	sram_ctrl_ret_fatal_error
kTopEarlgreyAlertIdRramCtrlRecovErr	rram_ctrl_recov_err
kTopEarlgreyAlertIdRramCtrlFatalStdErr	rram_ctrl_fatal_std_err
kTopEarlgreyAlertIdRramCtrlFatalErr	rram_ctrl_fatal_err
kTopEarlgreyAlertIdRramCtrlFatalMacroErr	rram_ctrl_fatal_macro_err
kTopEarlgreyAlertIdRramCtrlRecovMacroErr	rram_ctrl_recov_macro_err
kTopEarlgreyAlertIdRvDmFatalFault	rv_dm_fatal_fault
kTopEarlgreyAlertIdRvPlicFatalFault	rv_plic_fatal_fault
kTopEarlgreyAlertIdAesRecovCtrlUpdateErr	aes_recov_ctrl_update_err
kTopEarlgreyAlertIdAesFatalFault	aes_fatal_fault
kTopEarlgreyAlertIdHmacFatalFault	hmac_fatal_fault
kTopEarlgreyAlertIdKmacRecovOperationErr	kmac_recov_operation_err
kTopEarlgreyAlertIdKmacFatalFaultErr	kmac_fatal_fault_err
kTopEarlgreyAlertIdOtbnFatal	otbn_fatal
kTopEarlgreyAlertIdOtbnRecov	otbn_recov
kTopEarlgreyAlertIdKeymgrDpeRecovOperationErr	keymgr_dpe_recov_operation_err
kTopEarlgreyAlertIdKeymgrDpeFatalFaultErr	keymgr_dpe_fatal_fault_err
kTopEarlgreyAlertIdCsrngRecovAlert	csrng_recov_alert
kTopEarlgreyAlertIdCsrngFatalAlert	csrng_fatal_alert
kTopEarlgreyAlertIdEntropySrcRecovAlert	entropy_src_recov_alert
kTopEarlgreyAlertIdEntropySrcFatalAlert	entropy_src_fatal_alert
kTopEarlgreyAlertIdEdn0RecovAlert	edn0_recov_alert
kTopEarlgreyAlertIdEdn0FatalAlert	edn0_fatal_alert
kTopEarlgreyAlertIdEdn1RecovAlert	edn1_recov_alert
kTopEarlgreyAlertIdEdn1FatalAlert	edn1_fatal_alert
kTopEarlgreyAlertIdSramCtrlMainFatalError	sram_ctrl_main_fatal_error
kTopEarlgreyAlertIdSramCtrlSecFatalError	sram_ctrl_sec_fatal_error
kTopEarlgreyAlertIdRomCtrlFatal	rom_ctrl_fatal
kTopEarlgreyAlertIdRvCoreIbexFatalSwErr	rv_core_ibex_fatal_sw_err
kTopEarlgreyAlertIdRvCoreIbexRecovSwErr	rv_core_ibex_recov_sw_err
kTopEarlgreyAlertIdRvCoreIbexFatalHwErr	rv_core_ibex_fatal_hw_err
kTopEarlgreyAlertIdRvCoreIbexRecovHwErr	rv_core_ibex_recov_hw_err
kTopEarlgreyAlertIdCheriotMemSysFatalFault	cheriot_mem_sys_fatal_fault
kTopEarlgreyAlertIdSramCtrlMetaFatalError	sram_ctrl_meta_fatal_error

Definition at line 1346 of file top_earlgrey.h.

top_earlgrey_alert_peripheral

enum top_earlgrey_alert_peripheral

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

Enumerator
kTopEarlgreyAlertPeripheralExternal	External Peripheral.
kTopEarlgreyAlertPeripheralUart0	uart0
kTopEarlgreyAlertPeripheralUart1	uart1
kTopEarlgreyAlertPeripheralUart2	uart2
kTopEarlgreyAlertPeripheralUart3	uart3
kTopEarlgreyAlertPeripheralGpio0	gpio0
kTopEarlgreyAlertPeripheralGpio1	gpio1
kTopEarlgreyAlertPeripheralSpiDevice	spi_device
kTopEarlgreyAlertPeripheralI2c0	i2c0
kTopEarlgreyAlertPeripheralI2c1	i2c1
kTopEarlgreyAlertPeripheralI2c2	i2c2
kTopEarlgreyAlertPeripheralI3c0	i3c0
kTopEarlgreyAlertPeripheralI3c1	i3c1
kTopEarlgreyAlertPeripheralRvTimer	rv_timer
kTopEarlgreyAlertPeripheralOtpCtrl	otp_ctrl
kTopEarlgreyAlertPeripheralLcCtrl	lc_ctrl
kTopEarlgreyAlertPeripheralSpiHost0	spi_host0
kTopEarlgreyAlertPeripheralSpiHost1	spi_host1
kTopEarlgreyAlertPeripheralUsbdev	usbdev
kTopEarlgreyAlertPeripheralPwrmgr	pwrmgr
kTopEarlgreyAlertPeripheralRstmgr	rstmgr
kTopEarlgreyAlertPeripheralClkmgr	clkmgr
kTopEarlgreyAlertPeripheralSysrstCtrl	sysrst_ctrl
kTopEarlgreyAlertPeripheralAdcCtrl	adc_ctrl
kTopEarlgreyAlertPeripheralPinmux	pinmux
kTopEarlgreyAlertPeripheralAonTimer	aon_timer
kTopEarlgreyAlertPeripheralSensorCtrl	sensor_ctrl
kTopEarlgreyAlertPeripheralSramCtrlRet	sram_ctrl_ret
kTopEarlgreyAlertPeripheralRramCtrl	rram_ctrl
kTopEarlgreyAlertPeripheralRvDm	rv_dm
kTopEarlgreyAlertPeripheralRvPlic	rv_plic
kTopEarlgreyAlertPeripheralAes	aes
kTopEarlgreyAlertPeripheralHmac	hmac
kTopEarlgreyAlertPeripheralKmac	kmac
kTopEarlgreyAlertPeripheralOtbn	otbn
kTopEarlgreyAlertPeripheralKeymgrDpe	keymgr_dpe
kTopEarlgreyAlertPeripheralCsrng	csrng
kTopEarlgreyAlertPeripheralEntropySrc	entropy_src
kTopEarlgreyAlertPeripheralEdn0	edn0
kTopEarlgreyAlertPeripheralEdn1	edn1
kTopEarlgreyAlertPeripheralSramCtrlMain	sram_ctrl_main
kTopEarlgreyAlertPeripheralSramCtrlSec	sram_ctrl_sec
kTopEarlgreyAlertPeripheralRomCtrl	rom_ctrl
kTopEarlgreyAlertPeripheralRvCoreIbex	rv_core_ibex
kTopEarlgreyAlertPeripheralCheriotMemSys	cheriot_mem_sys
kTopEarlgreyAlertPeripheralSramCtrlMeta	sram_ctrl_meta

Definition at line 1290 of file top_earlgrey.h.

top_earlgrey_direct_pads

enum top_earlgrey_direct_pads

Dedicated Pad Selects.

Definition at line 1766 of file top_earlgrey.h.

top_earlgrey_gateable_clocks

enum top_earlgrey_gateable_clocks

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

Enumerator
kTopEarlgreyGateableClocksIoDiv4Peri	Clock clk_io_div4_peri in group peri.
kTopEarlgreyGateableClocksIoDiv2Peri	Clock clk_io_div2_peri in group peri.
kTopEarlgreyGateableClocksIoPeri	Clock clk_io_peri in group peri.
kTopEarlgreyGateableClocksUsbPeri	Clock clk_usb_peri in group peri.
kTopEarlgreyGateableClocksIoSpiHost1	Clock clk_io_spi_host1 in group spi_host1.

Definition at line 1886 of file top_earlgrey.h.

top_earlgrey_hintable_clocks

enum top_earlgrey_hintable_clocks

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

Enumerator
kTopEarlgreyHintableClocksMainAes	Clock clk_main_aes in group trans.
kTopEarlgreyHintableClocksMainHmac	Clock clk_main_hmac in group trans.
kTopEarlgreyHintableClocksMainKmac	Clock clk_main_kmac in group trans.
kTopEarlgreyHintableClocksMainOtbn	Clock clk_main_otbn in group trans.

Definition at line 1901 of file top_earlgrey.h.

top_earlgrey_muxed_pads

enum top_earlgrey_muxed_pads

Muxed Pad Selects.

Definition at line 1789 of file top_earlgrey.h.

top_earlgrey_pinmux_insel

enum top_earlgrey_pinmux_insel

Pinmux MIO Input Selector.

Enumerator
kTopEarlgreyPinmuxInselConstantZero	Tie constantly to zero.
kTopEarlgreyPinmuxInselConstantOne	Tie constantly to one.
kTopEarlgreyPinmuxInselIoa0	MIO Pad 0.
kTopEarlgreyPinmuxInselIoa1	MIO Pad 1.
kTopEarlgreyPinmuxInselIoa2	MIO Pad 2.
kTopEarlgreyPinmuxInselIoa3	MIO Pad 3.
kTopEarlgreyPinmuxInselIoa4	MIO Pad 4.
kTopEarlgreyPinmuxInselIoa5	MIO Pad 5.
kTopEarlgreyPinmuxInselIoa6	MIO Pad 6.
kTopEarlgreyPinmuxInselIoa7	MIO Pad 7.
kTopEarlgreyPinmuxInselIoa8	MIO Pad 8.
kTopEarlgreyPinmuxInselIob0	MIO Pad 9.
kTopEarlgreyPinmuxInselIob1	MIO Pad 10.
kTopEarlgreyPinmuxInselIob2	MIO Pad 11.
kTopEarlgreyPinmuxInselIob3	MIO Pad 12.
kTopEarlgreyPinmuxInselIob4	MIO Pad 13.
kTopEarlgreyPinmuxInselIob5	MIO Pad 14.
kTopEarlgreyPinmuxInselIob6	MIO Pad 15.
kTopEarlgreyPinmuxInselIob7	MIO Pad 16.
kTopEarlgreyPinmuxInselIob8	MIO Pad 17.
kTopEarlgreyPinmuxInselIob9	MIO Pad 18.
kTopEarlgreyPinmuxInselIob10	MIO Pad 19.
kTopEarlgreyPinmuxInselIob11	MIO Pad 20.
kTopEarlgreyPinmuxInselIob12	MIO Pad 21.
kTopEarlgreyPinmuxInselIoc0	MIO Pad 22.
kTopEarlgreyPinmuxInselIoc1	MIO Pad 23.
kTopEarlgreyPinmuxInselIoc2	MIO Pad 24.
kTopEarlgreyPinmuxInselIoc3	MIO Pad 25.
kTopEarlgreyPinmuxInselIoc4	MIO Pad 26.
kTopEarlgreyPinmuxInselIoc5	MIO Pad 27.
kTopEarlgreyPinmuxInselIoc6	MIO Pad 28.
kTopEarlgreyPinmuxInselIoc7	MIO Pad 29.
kTopEarlgreyPinmuxInselIoc8	MIO Pad 30.
kTopEarlgreyPinmuxInselIoc9	MIO Pad 31.
kTopEarlgreyPinmuxInselIoc10	MIO Pad 32.
kTopEarlgreyPinmuxInselIoc11	MIO Pad 33.
kTopEarlgreyPinmuxInselIoc12	MIO Pad 34.
kTopEarlgreyPinmuxInselIor0	MIO Pad 35.
kTopEarlgreyPinmuxInselIor1	MIO Pad 36.
kTopEarlgreyPinmuxInselIor2	MIO Pad 37.
kTopEarlgreyPinmuxInselIor3	MIO Pad 38.
kTopEarlgreyPinmuxInselIor4	MIO Pad 39.
kTopEarlgreyPinmuxInselIor5	MIO Pad 40.
kTopEarlgreyPinmuxInselIor6	MIO Pad 41.
kTopEarlgreyPinmuxInselIor7	MIO Pad 42.
kTopEarlgreyPinmuxInselIor10	MIO Pad 43.
kTopEarlgreyPinmuxInselIor11	MIO Pad 44.
kTopEarlgreyPinmuxInselIor12	MIO Pad 45.
kTopEarlgreyPinmuxInselIor13	MIO Pad 46.

Definition at line 1544 of file top_earlgrey.h.

top_earlgrey_pinmux_mio_out

enum top_earlgrey_pinmux_mio_out

Pinmux MIO Output.

Enumerator
kTopEarlgreyPinmuxMioOutIoa0	MIO Pad 0.
kTopEarlgreyPinmuxMioOutIoa1	MIO Pad 1.
kTopEarlgreyPinmuxMioOutIoa2	MIO Pad 2.
kTopEarlgreyPinmuxMioOutIoa3	MIO Pad 3.
kTopEarlgreyPinmuxMioOutIoa4	MIO Pad 4.
kTopEarlgreyPinmuxMioOutIoa5	MIO Pad 5.
kTopEarlgreyPinmuxMioOutIoa6	MIO Pad 6.
kTopEarlgreyPinmuxMioOutIoa7	MIO Pad 7.
kTopEarlgreyPinmuxMioOutIoa8	MIO Pad 8.
kTopEarlgreyPinmuxMioOutIob0	MIO Pad 9.
kTopEarlgreyPinmuxMioOutIob1	MIO Pad 10.
kTopEarlgreyPinmuxMioOutIob2	MIO Pad 11.
kTopEarlgreyPinmuxMioOutIob3	MIO Pad 12.
kTopEarlgreyPinmuxMioOutIob4	MIO Pad 13.
kTopEarlgreyPinmuxMioOutIob5	MIO Pad 14.
kTopEarlgreyPinmuxMioOutIob6	MIO Pad 15.
kTopEarlgreyPinmuxMioOutIob7	MIO Pad 16.
kTopEarlgreyPinmuxMioOutIob8	MIO Pad 17.
kTopEarlgreyPinmuxMioOutIob9	MIO Pad 18.
kTopEarlgreyPinmuxMioOutIob10	MIO Pad 19.
kTopEarlgreyPinmuxMioOutIob11	MIO Pad 20.
kTopEarlgreyPinmuxMioOutIob12	MIO Pad 21.
kTopEarlgreyPinmuxMioOutIoc0	MIO Pad 22.
kTopEarlgreyPinmuxMioOutIoc1	MIO Pad 23.
kTopEarlgreyPinmuxMioOutIoc2	MIO Pad 24.
kTopEarlgreyPinmuxMioOutIoc3	MIO Pad 25.
kTopEarlgreyPinmuxMioOutIoc4	MIO Pad 26.
kTopEarlgreyPinmuxMioOutIoc5	MIO Pad 27.
kTopEarlgreyPinmuxMioOutIoc6	MIO Pad 28.
kTopEarlgreyPinmuxMioOutIoc7	MIO Pad 29.
kTopEarlgreyPinmuxMioOutIoc8	MIO Pad 30.
kTopEarlgreyPinmuxMioOutIoc9	MIO Pad 31.
kTopEarlgreyPinmuxMioOutIoc10	MIO Pad 32.
kTopEarlgreyPinmuxMioOutIoc11	MIO Pad 33.
kTopEarlgreyPinmuxMioOutIoc12	MIO Pad 34.
kTopEarlgreyPinmuxMioOutIor0	MIO Pad 35.
kTopEarlgreyPinmuxMioOutIor1	MIO Pad 36.
kTopEarlgreyPinmuxMioOutIor2	MIO Pad 37.
kTopEarlgreyPinmuxMioOutIor3	MIO Pad 38.
kTopEarlgreyPinmuxMioOutIor4	MIO Pad 39.
kTopEarlgreyPinmuxMioOutIor5	MIO Pad 40.
kTopEarlgreyPinmuxMioOutIor6	MIO Pad 41.
kTopEarlgreyPinmuxMioOutIor7	MIO Pad 42.
kTopEarlgreyPinmuxMioOutIor10	MIO Pad 43.
kTopEarlgreyPinmuxMioOutIor11	MIO Pad 44.
kTopEarlgreyPinmuxMioOutIor12	MIO Pad 45.
kTopEarlgreyPinmuxMioOutIor13	MIO Pad 46.

Definition at line 1600 of file top_earlgrey.h.

top_earlgrey_pinmux_outsel

enum top_earlgrey_pinmux_outsel

Pinmux Peripheral Output Selector.

Enumerator
kTopEarlgreyPinmuxOutselConstantZero	Tie constantly to zero.
kTopEarlgreyPinmuxOutselConstantOne	Tie constantly to one.
kTopEarlgreyPinmuxOutselConstantHighZ	Tie constantly to high-Z.
kTopEarlgreyPinmuxOutselGpio0Gpio0	Peripheral Output 0.
kTopEarlgreyPinmuxOutselGpio0Gpio1	Peripheral Output 1.
kTopEarlgreyPinmuxOutselGpio0Gpio2	Peripheral Output 2.
kTopEarlgreyPinmuxOutselGpio0Gpio3	Peripheral Output 3.
kTopEarlgreyPinmuxOutselGpio0Gpio4	Peripheral Output 4.
kTopEarlgreyPinmuxOutselGpio0Gpio5	Peripheral Output 5.
kTopEarlgreyPinmuxOutselGpio0Gpio6	Peripheral Output 6.
kTopEarlgreyPinmuxOutselGpio0Gpio7	Peripheral Output 7.
kTopEarlgreyPinmuxOutselGpio0Gpio8	Peripheral Output 8.
kTopEarlgreyPinmuxOutselGpio0Gpio9	Peripheral Output 9.
kTopEarlgreyPinmuxOutselGpio0Gpio10	Peripheral Output 10.
kTopEarlgreyPinmuxOutselGpio0Gpio11	Peripheral Output 11.
kTopEarlgreyPinmuxOutselGpio0Gpio12	Peripheral Output 12.
kTopEarlgreyPinmuxOutselGpio0Gpio13	Peripheral Output 13.
kTopEarlgreyPinmuxOutselGpio0Gpio14	Peripheral Output 14.
kTopEarlgreyPinmuxOutselGpio0Gpio15	Peripheral Output 15.
kTopEarlgreyPinmuxOutselGpio0Gpio16	Peripheral Output 16.
kTopEarlgreyPinmuxOutselGpio0Gpio17	Peripheral Output 17.
kTopEarlgreyPinmuxOutselGpio0Gpio18	Peripheral Output 18.
kTopEarlgreyPinmuxOutselGpio0Gpio19	Peripheral Output 19.
kTopEarlgreyPinmuxOutselGpio0Gpio20	Peripheral Output 20.
kTopEarlgreyPinmuxOutselGpio0Gpio21	Peripheral Output 21.
kTopEarlgreyPinmuxOutselGpio0Gpio22	Peripheral Output 22.
kTopEarlgreyPinmuxOutselGpio0Gpio23	Peripheral Output 23.
kTopEarlgreyPinmuxOutselGpio0Gpio24	Peripheral Output 24.
kTopEarlgreyPinmuxOutselGpio0Gpio25	Peripheral Output 25.
kTopEarlgreyPinmuxOutselGpio0Gpio26	Peripheral Output 26.
kTopEarlgreyPinmuxOutselGpio0Gpio27	Peripheral Output 27.
kTopEarlgreyPinmuxOutselGpio0Gpio28	Peripheral Output 28.
kTopEarlgreyPinmuxOutselGpio0Gpio29	Peripheral Output 29.
kTopEarlgreyPinmuxOutselGpio0Gpio30	Peripheral Output 30.
kTopEarlgreyPinmuxOutselGpio0Gpio31	Peripheral Output 31.
kTopEarlgreyPinmuxOutselGpio1Gpio0	Peripheral Output 32.
kTopEarlgreyPinmuxOutselGpio1Gpio1	Peripheral Output 33.
kTopEarlgreyPinmuxOutselGpio1Gpio2	Peripheral Output 34.
kTopEarlgreyPinmuxOutselGpio1Gpio3	Peripheral Output 35.
kTopEarlgreyPinmuxOutselGpio1Gpio4	Peripheral Output 36.
kTopEarlgreyPinmuxOutselGpio1Gpio5	Peripheral Output 37.
kTopEarlgreyPinmuxOutselGpio1Gpio6	Peripheral Output 38.
kTopEarlgreyPinmuxOutselGpio1Gpio7	Peripheral Output 39.
kTopEarlgreyPinmuxOutselGpio1Gpio8	Peripheral Output 40.
kTopEarlgreyPinmuxOutselGpio1Gpio9	Peripheral Output 41.
kTopEarlgreyPinmuxOutselGpio1Gpio10	Peripheral Output 42.
kTopEarlgreyPinmuxOutselGpio1Gpio11	Peripheral Output 43.
kTopEarlgreyPinmuxOutselGpio1Gpio12	Peripheral Output 44.
kTopEarlgreyPinmuxOutselGpio1Gpio13	Peripheral Output 45.
kTopEarlgreyPinmuxOutselGpio1Gpio14	Peripheral Output 46.
kTopEarlgreyPinmuxOutselGpio1Gpio15	Peripheral Output 47.
kTopEarlgreyPinmuxOutselGpio1Gpio16	Peripheral Output 48.
kTopEarlgreyPinmuxOutselGpio1Gpio17	Peripheral Output 49.
kTopEarlgreyPinmuxOutselGpio1Gpio18	Peripheral Output 50.
kTopEarlgreyPinmuxOutselGpio1Gpio19	Peripheral Output 51.
kTopEarlgreyPinmuxOutselGpio1Gpio20	Peripheral Output 52.
kTopEarlgreyPinmuxOutselGpio1Gpio21	Peripheral Output 53.
kTopEarlgreyPinmuxOutselGpio1Gpio22	Peripheral Output 54.
kTopEarlgreyPinmuxOutselGpio1Gpio23	Peripheral Output 55.
kTopEarlgreyPinmuxOutselGpio1Gpio24	Peripheral Output 56.
kTopEarlgreyPinmuxOutselGpio1Gpio25	Peripheral Output 57.
kTopEarlgreyPinmuxOutselGpio1Gpio26	Peripheral Output 58.
kTopEarlgreyPinmuxOutselGpio1Gpio27	Peripheral Output 59.
kTopEarlgreyPinmuxOutselGpio1Gpio28	Peripheral Output 60.
kTopEarlgreyPinmuxOutselGpio1Gpio29	Peripheral Output 61.
kTopEarlgreyPinmuxOutselGpio1Gpio30	Peripheral Output 62.
kTopEarlgreyPinmuxOutselGpio1Gpio31	Peripheral Output 63.
kTopEarlgreyPinmuxOutselI2c0Sda	Peripheral Output 64.
kTopEarlgreyPinmuxOutselI2c0Scl	Peripheral Output 65.
kTopEarlgreyPinmuxOutselI2c1Sda	Peripheral Output 66.
kTopEarlgreyPinmuxOutselI2c1Scl	Peripheral Output 67.
kTopEarlgreyPinmuxOutselI2c2Sda	Peripheral Output 68.
kTopEarlgreyPinmuxOutselI2c2Scl	Peripheral Output 69.
kTopEarlgreyPinmuxOutselI3c0Scl	Peripheral Output 70.
kTopEarlgreyPinmuxOutselI3c0Sda	Peripheral Output 71.
kTopEarlgreyPinmuxOutselI3c1Scl	Peripheral Output 72.
kTopEarlgreyPinmuxOutselI3c1Sda	Peripheral Output 73.
kTopEarlgreyPinmuxOutselSpiHost1Sd0	Peripheral Output 74.
kTopEarlgreyPinmuxOutselSpiHost1Sd1	Peripheral Output 75.
kTopEarlgreyPinmuxOutselSpiHost1Sd2	Peripheral Output 76.
kTopEarlgreyPinmuxOutselSpiHost1Sd3	Peripheral Output 77.
kTopEarlgreyPinmuxOutselUart0Tx	Peripheral Output 78.
kTopEarlgreyPinmuxOutselUart1Tx	Peripheral Output 79.
kTopEarlgreyPinmuxOutselUart2Tx	Peripheral Output 80.
kTopEarlgreyPinmuxOutselUart3Tx	Peripheral Output 81.
kTopEarlgreyPinmuxOutselI3c0CtrlSdaPu	Peripheral Output 82.
kTopEarlgreyPinmuxOutselI3c1CtrlSdaPu	Peripheral Output 83.
kTopEarlgreyPinmuxOutselSpiHost1Sck	Peripheral Output 84.
kTopEarlgreyPinmuxOutselSpiHost1Csb	Peripheral Output 85.
kTopEarlgreyPinmuxOutselRramMacroTdo	Peripheral Output 86.
kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0	Peripheral Output 87.
kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1	Peripheral Output 88.
kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2	Peripheral Output 89.
kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut3	Peripheral Output 90.
kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut4	Peripheral Output 91.
kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut5	Peripheral Output 92.
kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut6	Peripheral Output 93.
kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut7	Peripheral Output 94.
kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut8	Peripheral Output 95.
kTopEarlgreyPinmuxOutselSysrstCtrlBatDisable	Peripheral Output 96.
kTopEarlgreyPinmuxOutselSysrstCtrlKey0Out	Peripheral Output 97.
kTopEarlgreyPinmuxOutselSysrstCtrlKey1Out	Peripheral Output 98.
kTopEarlgreyPinmuxOutselSysrstCtrlKey2Out	Peripheral Output 99.
kTopEarlgreyPinmuxOutselSysrstCtrlPwrbOut	Peripheral Output 100.
kTopEarlgreyPinmuxOutselSysrstCtrlZ3Wakeup	Peripheral Output 101.

Definition at line 1654 of file top_earlgrey.h.

top_earlgrey_pinmux_peripheral_in

enum top_earlgrey_pinmux_peripheral_in

Pinmux Peripheral Input.

Enumerator
kTopEarlgreyPinmuxPeripheralInGpio0Gpio0	Peripheral Input 0.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio1	Peripheral Input 1.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio2	Peripheral Input 2.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio3	Peripheral Input 3.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio4	Peripheral Input 4.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio5	Peripheral Input 5.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio6	Peripheral Input 6.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio7	Peripheral Input 7.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio8	Peripheral Input 8.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio9	Peripheral Input 9.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio10	Peripheral Input 10.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio11	Peripheral Input 11.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio12	Peripheral Input 12.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio13	Peripheral Input 13.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio14	Peripheral Input 14.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio15	Peripheral Input 15.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio16	Peripheral Input 16.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio17	Peripheral Input 17.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio18	Peripheral Input 18.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio19	Peripheral Input 19.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio20	Peripheral Input 20.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio21	Peripheral Input 21.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio22	Peripheral Input 22.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio23	Peripheral Input 23.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio24	Peripheral Input 24.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio25	Peripheral Input 25.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio26	Peripheral Input 26.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio27	Peripheral Input 27.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio28	Peripheral Input 28.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio29	Peripheral Input 29.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio30	Peripheral Input 30.
kTopEarlgreyPinmuxPeripheralInGpio0Gpio31	Peripheral Input 31.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio0	Peripheral Input 32.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio1	Peripheral Input 33.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio2	Peripheral Input 34.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio3	Peripheral Input 35.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio4	Peripheral Input 36.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio5	Peripheral Input 37.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio6	Peripheral Input 38.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio7	Peripheral Input 39.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio8	Peripheral Input 40.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio9	Peripheral Input 41.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio10	Peripheral Input 42.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio11	Peripheral Input 43.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio12	Peripheral Input 44.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio13	Peripheral Input 45.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio14	Peripheral Input 46.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio15	Peripheral Input 47.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio16	Peripheral Input 48.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio17	Peripheral Input 49.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio18	Peripheral Input 50.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio19	Peripheral Input 51.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio20	Peripheral Input 52.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio21	Peripheral Input 53.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio22	Peripheral Input 54.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio23	Peripheral Input 55.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio24	Peripheral Input 56.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio25	Peripheral Input 57.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio26	Peripheral Input 58.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio27	Peripheral Input 59.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio28	Peripheral Input 60.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio29	Peripheral Input 61.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio30	Peripheral Input 62.
kTopEarlgreyPinmuxPeripheralInGpio1Gpio31	Peripheral Input 63.
kTopEarlgreyPinmuxPeripheralInI2c0Sda	Peripheral Input 64.
kTopEarlgreyPinmuxPeripheralInI2c0Scl	Peripheral Input 65.
kTopEarlgreyPinmuxPeripheralInI2c1Sda	Peripheral Input 66.
kTopEarlgreyPinmuxPeripheralInI2c1Scl	Peripheral Input 67.
kTopEarlgreyPinmuxPeripheralInI2c2Sda	Peripheral Input 68.
kTopEarlgreyPinmuxPeripheralInI2c2Scl	Peripheral Input 69.
kTopEarlgreyPinmuxPeripheralInI3c0Scl	Peripheral Input 70.
kTopEarlgreyPinmuxPeripheralInI3c0Sda	Peripheral Input 71.
kTopEarlgreyPinmuxPeripheralInI3c1Scl	Peripheral Input 72.
kTopEarlgreyPinmuxPeripheralInI3c1Sda	Peripheral Input 73.
kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0	Peripheral Input 74.
kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1	Peripheral Input 75.
kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2	Peripheral Input 76.
kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3	Peripheral Input 77.
kTopEarlgreyPinmuxPeripheralInUart0Rx	Peripheral Input 78.
kTopEarlgreyPinmuxPeripheralInUart1Rx	Peripheral Input 79.
kTopEarlgreyPinmuxPeripheralInUart2Rx	Peripheral Input 80.
kTopEarlgreyPinmuxPeripheralInUart3Rx	Peripheral Input 81.
kTopEarlgreyPinmuxPeripheralInI3c0RstdetScl	Peripheral Input 82.
kTopEarlgreyPinmuxPeripheralInI3c0RstdetSda	Peripheral Input 83.
kTopEarlgreyPinmuxPeripheralInI3c1RstdetScl	Peripheral Input 84.
kTopEarlgreyPinmuxPeripheralInI3c1RstdetSda	Peripheral Input 85.
kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb	Peripheral Input 86.
kTopEarlgreyPinmuxPeripheralInRramMacroTck	Peripheral Input 87.
kTopEarlgreyPinmuxPeripheralInRramMacroTms	Peripheral Input 88.
kTopEarlgreyPinmuxPeripheralInRramMacroTdi	Peripheral Input 89.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent	Peripheral Input 90.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In	Peripheral Input 91.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In	Peripheral Input 92.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey2In	Peripheral Input 93.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlPwrbIn	Peripheral Input 94.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlLidOpen	Peripheral Input 95.
kTopEarlgreyPinmuxPeripheralInUsbdevSense	Peripheral Input 96.

Definition at line 1440 of file top_earlgrey.h.

top_earlgrey_plic_irq_id

enum top_earlgrey_plic_irq_id

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopEarlgreyPlicIrqIdNone	No Interrupt.
kTopEarlgreyPlicIrqIdUart0TxWatermark	uart0_tx_watermark
kTopEarlgreyPlicIrqIdUart0RxWatermark	uart0_rx_watermark
kTopEarlgreyPlicIrqIdUart0TxDone	uart0_tx_done
kTopEarlgreyPlicIrqIdUart0RxOverflow	uart0_rx_overflow
kTopEarlgreyPlicIrqIdUart0RxFrameErr	uart0_rx_frame_err
kTopEarlgreyPlicIrqIdUart0RxBreakErr	uart0_rx_break_err
kTopEarlgreyPlicIrqIdUart0RxTimeout	uart0_rx_timeout
kTopEarlgreyPlicIrqIdUart0RxParityErr	uart0_rx_parity_err
kTopEarlgreyPlicIrqIdUart0TxEmpty	uart0_tx_empty
kTopEarlgreyPlicIrqIdUart1TxWatermark	uart1_tx_watermark
kTopEarlgreyPlicIrqIdUart1RxWatermark	uart1_rx_watermark
kTopEarlgreyPlicIrqIdUart1TxDone	uart1_tx_done
kTopEarlgreyPlicIrqIdUart1RxOverflow	uart1_rx_overflow
kTopEarlgreyPlicIrqIdUart1RxFrameErr	uart1_rx_frame_err
kTopEarlgreyPlicIrqIdUart1RxBreakErr	uart1_rx_break_err
kTopEarlgreyPlicIrqIdUart1RxTimeout	uart1_rx_timeout
kTopEarlgreyPlicIrqIdUart1RxParityErr	uart1_rx_parity_err
kTopEarlgreyPlicIrqIdUart1TxEmpty	uart1_tx_empty
kTopEarlgreyPlicIrqIdUart2TxWatermark	uart2_tx_watermark
kTopEarlgreyPlicIrqIdUart2RxWatermark	uart2_rx_watermark
kTopEarlgreyPlicIrqIdUart2TxDone	uart2_tx_done
kTopEarlgreyPlicIrqIdUart2RxOverflow	uart2_rx_overflow
kTopEarlgreyPlicIrqIdUart2RxFrameErr	uart2_rx_frame_err
kTopEarlgreyPlicIrqIdUart2RxBreakErr	uart2_rx_break_err
kTopEarlgreyPlicIrqIdUart2RxTimeout	uart2_rx_timeout
kTopEarlgreyPlicIrqIdUart2RxParityErr	uart2_rx_parity_err
kTopEarlgreyPlicIrqIdUart2TxEmpty	uart2_tx_empty
kTopEarlgreyPlicIrqIdUart3TxWatermark	uart3_tx_watermark
kTopEarlgreyPlicIrqIdUart3RxWatermark	uart3_rx_watermark
kTopEarlgreyPlicIrqIdUart3TxDone	uart3_tx_done
kTopEarlgreyPlicIrqIdUart3RxOverflow	uart3_rx_overflow
kTopEarlgreyPlicIrqIdUart3RxFrameErr	uart3_rx_frame_err
kTopEarlgreyPlicIrqIdUart3RxBreakErr	uart3_rx_break_err
kTopEarlgreyPlicIrqIdUart3RxTimeout	uart3_rx_timeout
kTopEarlgreyPlicIrqIdUart3RxParityErr	uart3_rx_parity_err
kTopEarlgreyPlicIrqIdUart3TxEmpty	uart3_tx_empty
kTopEarlgreyPlicIrqIdGpio0Gpio0	gpio0_gpio 0
kTopEarlgreyPlicIrqIdGpio0Gpio1	gpio0_gpio 1
kTopEarlgreyPlicIrqIdGpio0Gpio2	gpio0_gpio 2
kTopEarlgreyPlicIrqIdGpio0Gpio3	gpio0_gpio 3
kTopEarlgreyPlicIrqIdGpio0Gpio4	gpio0_gpio 4
kTopEarlgreyPlicIrqIdGpio0Gpio5	gpio0_gpio 5
kTopEarlgreyPlicIrqIdGpio0Gpio6	gpio0_gpio 6
kTopEarlgreyPlicIrqIdGpio0Gpio7	gpio0_gpio 7
kTopEarlgreyPlicIrqIdGpio0Gpio8	gpio0_gpio 8
kTopEarlgreyPlicIrqIdGpio0Gpio9	gpio0_gpio 9
kTopEarlgreyPlicIrqIdGpio0Gpio10	gpio0_gpio 10
kTopEarlgreyPlicIrqIdGpio0Gpio11	gpio0_gpio 11
kTopEarlgreyPlicIrqIdGpio0Gpio12	gpio0_gpio 12
kTopEarlgreyPlicIrqIdGpio0Gpio13	gpio0_gpio 13
kTopEarlgreyPlicIrqIdGpio0Gpio14	gpio0_gpio 14
kTopEarlgreyPlicIrqIdGpio0Gpio15	gpio0_gpio 15
kTopEarlgreyPlicIrqIdGpio0Gpio16	gpio0_gpio 16
kTopEarlgreyPlicIrqIdGpio0Gpio17	gpio0_gpio 17
kTopEarlgreyPlicIrqIdGpio0Gpio18	gpio0_gpio 18
kTopEarlgreyPlicIrqIdGpio0Gpio19	gpio0_gpio 19
kTopEarlgreyPlicIrqIdGpio0Gpio20	gpio0_gpio 20
kTopEarlgreyPlicIrqIdGpio0Gpio21	gpio0_gpio 21
kTopEarlgreyPlicIrqIdGpio0Gpio22	gpio0_gpio 22
kTopEarlgreyPlicIrqIdGpio0Gpio23	gpio0_gpio 23
kTopEarlgreyPlicIrqIdGpio0Gpio24	gpio0_gpio 24
kTopEarlgreyPlicIrqIdGpio0Gpio25	gpio0_gpio 25
kTopEarlgreyPlicIrqIdGpio0Gpio26	gpio0_gpio 26
kTopEarlgreyPlicIrqIdGpio0Gpio27	gpio0_gpio 27
kTopEarlgreyPlicIrqIdGpio0Gpio28	gpio0_gpio 28
kTopEarlgreyPlicIrqIdGpio0Gpio29	gpio0_gpio 29
kTopEarlgreyPlicIrqIdGpio0Gpio30	gpio0_gpio 30
kTopEarlgreyPlicIrqIdGpio0Gpio31	gpio0_gpio 31
kTopEarlgreyPlicIrqIdGpio1Gpio0	gpio1_gpio 0
kTopEarlgreyPlicIrqIdGpio1Gpio1	gpio1_gpio 1
kTopEarlgreyPlicIrqIdGpio1Gpio2	gpio1_gpio 2
kTopEarlgreyPlicIrqIdGpio1Gpio3	gpio1_gpio 3
kTopEarlgreyPlicIrqIdGpio1Gpio4	gpio1_gpio 4
kTopEarlgreyPlicIrqIdGpio1Gpio5	gpio1_gpio 5
kTopEarlgreyPlicIrqIdGpio1Gpio6	gpio1_gpio 6
kTopEarlgreyPlicIrqIdGpio1Gpio7	gpio1_gpio 7
kTopEarlgreyPlicIrqIdGpio1Gpio8	gpio1_gpio 8
kTopEarlgreyPlicIrqIdGpio1Gpio9	gpio1_gpio 9
kTopEarlgreyPlicIrqIdGpio1Gpio10	gpio1_gpio 10
kTopEarlgreyPlicIrqIdGpio1Gpio11	gpio1_gpio 11
kTopEarlgreyPlicIrqIdGpio1Gpio12	gpio1_gpio 12
kTopEarlgreyPlicIrqIdGpio1Gpio13	gpio1_gpio 13
kTopEarlgreyPlicIrqIdGpio1Gpio14	gpio1_gpio 14
kTopEarlgreyPlicIrqIdGpio1Gpio15	gpio1_gpio 15
kTopEarlgreyPlicIrqIdGpio1Gpio16	gpio1_gpio 16
kTopEarlgreyPlicIrqIdGpio1Gpio17	gpio1_gpio 17
kTopEarlgreyPlicIrqIdGpio1Gpio18	gpio1_gpio 18
kTopEarlgreyPlicIrqIdGpio1Gpio19	gpio1_gpio 19
kTopEarlgreyPlicIrqIdGpio1Gpio20	gpio1_gpio 20
kTopEarlgreyPlicIrqIdGpio1Gpio21	gpio1_gpio 21
kTopEarlgreyPlicIrqIdGpio1Gpio22	gpio1_gpio 22
kTopEarlgreyPlicIrqIdGpio1Gpio23	gpio1_gpio 23
kTopEarlgreyPlicIrqIdGpio1Gpio24	gpio1_gpio 24
kTopEarlgreyPlicIrqIdGpio1Gpio25	gpio1_gpio 25
kTopEarlgreyPlicIrqIdGpio1Gpio26	gpio1_gpio 26
kTopEarlgreyPlicIrqIdGpio1Gpio27	gpio1_gpio 27
kTopEarlgreyPlicIrqIdGpio1Gpio28	gpio1_gpio 28
kTopEarlgreyPlicIrqIdGpio1Gpio29	gpio1_gpio 29
kTopEarlgreyPlicIrqIdGpio1Gpio30	gpio1_gpio 30
kTopEarlgreyPlicIrqIdGpio1Gpio31	gpio1_gpio 31
kTopEarlgreyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty	spi_device_upload_cmdfifo_not_empty
kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadNotEmpty	spi_device_upload_payload_not_empty
kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadOverflow	spi_device_upload_payload_overflow
kTopEarlgreyPlicIrqIdSpiDeviceReadbufWatermark	spi_device_readbuf_watermark
kTopEarlgreyPlicIrqIdSpiDeviceReadbufFlip	spi_device_readbuf_flip
kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty	spi_device_tpm_header_not_empty
kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoCmdEnd	spi_device_tpm_rdfifo_cmd_end
kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoDrop	spi_device_tpm_rdfifo_drop
kTopEarlgreyPlicIrqIdI2c0FmtThreshold	i2c0_fmt_threshold
kTopEarlgreyPlicIrqIdI2c0RxThreshold	i2c0_rx_threshold
kTopEarlgreyPlicIrqIdI2c0AcqThreshold	i2c0_acq_threshold
kTopEarlgreyPlicIrqIdI2c0RxOverflow	i2c0_rx_overflow
kTopEarlgreyPlicIrqIdI2c0ControllerHalt	i2c0_controller_halt
kTopEarlgreyPlicIrqIdI2c0SclInterference	i2c0_scl_interference
kTopEarlgreyPlicIrqIdI2c0SdaInterference	i2c0_sda_interference
kTopEarlgreyPlicIrqIdI2c0StretchTimeout	i2c0_stretch_timeout
kTopEarlgreyPlicIrqIdI2c0SdaUnstable	i2c0_sda_unstable
kTopEarlgreyPlicIrqIdI2c0CmdComplete	i2c0_cmd_complete
kTopEarlgreyPlicIrqIdI2c0TxStretch	i2c0_tx_stretch
kTopEarlgreyPlicIrqIdI2c0TxThreshold	i2c0_tx_threshold
kTopEarlgreyPlicIrqIdI2c0AcqStretch	i2c0_acq_stretch
kTopEarlgreyPlicIrqIdI2c0UnexpStop	i2c0_unexp_stop
kTopEarlgreyPlicIrqIdI2c0HostTimeout	i2c0_host_timeout
kTopEarlgreyPlicIrqIdI2c1FmtThreshold	i2c1_fmt_threshold
kTopEarlgreyPlicIrqIdI2c1RxThreshold	i2c1_rx_threshold
kTopEarlgreyPlicIrqIdI2c1AcqThreshold	i2c1_acq_threshold
kTopEarlgreyPlicIrqIdI2c1RxOverflow	i2c1_rx_overflow
kTopEarlgreyPlicIrqIdI2c1ControllerHalt	i2c1_controller_halt
kTopEarlgreyPlicIrqIdI2c1SclInterference	i2c1_scl_interference
kTopEarlgreyPlicIrqIdI2c1SdaInterference	i2c1_sda_interference
kTopEarlgreyPlicIrqIdI2c1StretchTimeout	i2c1_stretch_timeout
kTopEarlgreyPlicIrqIdI2c1SdaUnstable	i2c1_sda_unstable
kTopEarlgreyPlicIrqIdI2c1CmdComplete	i2c1_cmd_complete
kTopEarlgreyPlicIrqIdI2c1TxStretch	i2c1_tx_stretch
kTopEarlgreyPlicIrqIdI2c1TxThreshold	i2c1_tx_threshold
kTopEarlgreyPlicIrqIdI2c1AcqStretch	i2c1_acq_stretch
kTopEarlgreyPlicIrqIdI2c1UnexpStop	i2c1_unexp_stop
kTopEarlgreyPlicIrqIdI2c1HostTimeout	i2c1_host_timeout
kTopEarlgreyPlicIrqIdI2c2FmtThreshold	i2c2_fmt_threshold
kTopEarlgreyPlicIrqIdI2c2RxThreshold	i2c2_rx_threshold
kTopEarlgreyPlicIrqIdI2c2AcqThreshold	i2c2_acq_threshold
kTopEarlgreyPlicIrqIdI2c2RxOverflow	i2c2_rx_overflow
kTopEarlgreyPlicIrqIdI2c2ControllerHalt	i2c2_controller_halt
kTopEarlgreyPlicIrqIdI2c2SclInterference	i2c2_scl_interference
kTopEarlgreyPlicIrqIdI2c2SdaInterference	i2c2_sda_interference
kTopEarlgreyPlicIrqIdI2c2StretchTimeout	i2c2_stretch_timeout
kTopEarlgreyPlicIrqIdI2c2SdaUnstable	i2c2_sda_unstable
kTopEarlgreyPlicIrqIdI2c2CmdComplete	i2c2_cmd_complete
kTopEarlgreyPlicIrqIdI2c2TxStretch	i2c2_tx_stretch
kTopEarlgreyPlicIrqIdI2c2TxThreshold	i2c2_tx_threshold
kTopEarlgreyPlicIrqIdI2c2AcqStretch	i2c2_acq_stretch
kTopEarlgreyPlicIrqIdI2c2UnexpStop	i2c2_unexp_stop
kTopEarlgreyPlicIrqIdI2c2HostTimeout	i2c2_host_timeout
kTopEarlgreyPlicIrqIdI3c0Hci	i3c0_hci
kTopEarlgreyPlicIrqIdI3c0Targ	i3c0_targ
kTopEarlgreyPlicIrqIdI3c1Hci	i3c1_hci
kTopEarlgreyPlicIrqIdI3c1Targ	i3c1_targ
kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0	rv_timer_timer_expired_hart0_timer0
kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone	otp_ctrl_otp_operation_done
kTopEarlgreyPlicIrqIdOtpCtrlOtpError	otp_ctrl_otp_error
kTopEarlgreyPlicIrqIdAlertHandlerClassa	alert_handler_classa
kTopEarlgreyPlicIrqIdAlertHandlerClassb	alert_handler_classb
kTopEarlgreyPlicIrqIdAlertHandlerClassc	alert_handler_classc
kTopEarlgreyPlicIrqIdAlertHandlerClassd	alert_handler_classd
kTopEarlgreyPlicIrqIdSpiHost0Error	spi_host0_error
kTopEarlgreyPlicIrqIdSpiHost0SpiEvent	spi_host0_spi_event
kTopEarlgreyPlicIrqIdSpiHost1Error	spi_host1_error
kTopEarlgreyPlicIrqIdSpiHost1SpiEvent	spi_host1_spi_event
kTopEarlgreyPlicIrqIdUsbdevPktReceived	usbdev_pkt_received
kTopEarlgreyPlicIrqIdUsbdevPktSent	usbdev_pkt_sent
kTopEarlgreyPlicIrqIdUsbdevDisconnected	usbdev_disconnected
kTopEarlgreyPlicIrqIdUsbdevHostLost	usbdev_host_lost
kTopEarlgreyPlicIrqIdUsbdevLinkReset	usbdev_link_reset
kTopEarlgreyPlicIrqIdUsbdevLinkSuspend	usbdev_link_suspend
kTopEarlgreyPlicIrqIdUsbdevLinkResume	usbdev_link_resume
kTopEarlgreyPlicIrqIdUsbdevAvOutEmpty	usbdev_av_out_empty
kTopEarlgreyPlicIrqIdUsbdevRxFull	usbdev_rx_full
kTopEarlgreyPlicIrqIdUsbdevAvOverflow	usbdev_av_overflow
kTopEarlgreyPlicIrqIdUsbdevLinkInErr	usbdev_link_in_err
kTopEarlgreyPlicIrqIdUsbdevRxCrcErr	usbdev_rx_crc_err
kTopEarlgreyPlicIrqIdUsbdevRxPidErr	usbdev_rx_pid_err
kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr	usbdev_rx_bitstuff_err
kTopEarlgreyPlicIrqIdUsbdevFrame	usbdev_frame
kTopEarlgreyPlicIrqIdUsbdevPowered	usbdev_powered
kTopEarlgreyPlicIrqIdUsbdevLinkOutErr	usbdev_link_out_err
kTopEarlgreyPlicIrqIdUsbdevAvSetupEmpty	usbdev_av_setup_empty
kTopEarlgreyPlicIrqIdPwrmgrWakeup	pwrmgr_wakeup
kTopEarlgreyPlicIrqIdSysrstCtrlEventDetected	sysrst_ctrl_event_detected
kTopEarlgreyPlicIrqIdAdcCtrlMatchPending	adc_ctrl_match_pending
kTopEarlgreyPlicIrqIdAonTimerWkupTimerExpired	aon_timer_wkup_timer_expired
kTopEarlgreyPlicIrqIdAonTimerWdogTimerBark	aon_timer_wdog_timer_bark
kTopEarlgreyPlicIrqIdSensorCtrlIoStatusChange	sensor_ctrl_io_status_change
kTopEarlgreyPlicIrqIdSensorCtrlInitStatusChange	sensor_ctrl_init_status_change
kTopEarlgreyPlicIrqIdRramCtrlWrEmpty	rram_ctrl_wr_empty
kTopEarlgreyPlicIrqIdRramCtrlWrLvl	rram_ctrl_wr_lvl
kTopEarlgreyPlicIrqIdRramCtrlRdFull	rram_ctrl_rd_full
kTopEarlgreyPlicIrqIdRramCtrlRdLvl	rram_ctrl_rd_lvl
kTopEarlgreyPlicIrqIdRramCtrlOpDone	rram_ctrl_op_done
kTopEarlgreyPlicIrqIdRramCtrlCorr1Err	rram_ctrl_corr1_err
kTopEarlgreyPlicIrqIdRramCtrlCorr2Err	rram_ctrl_corr2_err
kTopEarlgreyPlicIrqIdHmacHmacDone	hmac_hmac_done
kTopEarlgreyPlicIrqIdHmacFifoEmpty	hmac_fifo_empty
kTopEarlgreyPlicIrqIdHmacHmacErr	hmac_hmac_err
kTopEarlgreyPlicIrqIdKmacKmacDone	kmac_kmac_done
kTopEarlgreyPlicIrqIdKmacFifoEmpty	kmac_fifo_empty
kTopEarlgreyPlicIrqIdKmacKmacErr	kmac_kmac_err
kTopEarlgreyPlicIrqIdOtbnDone	otbn_done
kTopEarlgreyPlicIrqIdKeymgrDpeOpDone	keymgr_dpe_op_done
kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone	csrng_cs_cmd_req_done
kTopEarlgreyPlicIrqIdCsrngCsEntropyReq	csrng_cs_entropy_req
kTopEarlgreyPlicIrqIdCsrngCsHwInstExc	csrng_cs_hw_inst_exc
kTopEarlgreyPlicIrqIdCsrngCsFatalErr	csrng_cs_fatal_err
kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid	entropy_src_es_entropy_valid
kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed	entropy_src_es_health_test_failed
kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady	entropy_src_es_observe_fifo_ready
kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr	entropy_src_es_fatal_err
kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone	edn0_edn_cmd_req_done
kTopEarlgreyPlicIrqIdEdn0EdnFatalErr	edn0_edn_fatal_err
kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone	edn1_edn_cmd_req_done
kTopEarlgreyPlicIrqIdEdn1EdnFatalErr	edn1_edn_fatal_err
kTopEarlgreyPlicIrqIdCheriotMemSysTbreDone	cheriot_mem_sys_tbre_done

Definition at line 1037 of file top_earlgrey.h.

top_earlgrey_plic_peripheral

enum top_earlgrey_plic_peripheral

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

Enumerator
kTopEarlgreyPlicPeripheralUnknown	Unknown Peripheral.
kTopEarlgreyPlicPeripheralUart0	uart0
kTopEarlgreyPlicPeripheralUart1	uart1
kTopEarlgreyPlicPeripheralUart2	uart2
kTopEarlgreyPlicPeripheralUart3	uart3
kTopEarlgreyPlicPeripheralGpio0	gpio0
kTopEarlgreyPlicPeripheralGpio1	gpio1
kTopEarlgreyPlicPeripheralSpiDevice	spi_device
kTopEarlgreyPlicPeripheralI2c0	i2c0
kTopEarlgreyPlicPeripheralI2c1	i2c1
kTopEarlgreyPlicPeripheralI2c2	i2c2
kTopEarlgreyPlicPeripheralI3c0	i3c0
kTopEarlgreyPlicPeripheralI3c1	i3c1
kTopEarlgreyPlicPeripheralRvTimer	rv_timer
kTopEarlgreyPlicPeripheralOtpCtrl	otp_ctrl
kTopEarlgreyPlicPeripheralAlertHandler	alert_handler
kTopEarlgreyPlicPeripheralSpiHost0	spi_host0
kTopEarlgreyPlicPeripheralSpiHost1	spi_host1
kTopEarlgreyPlicPeripheralUsbdev	usbdev
kTopEarlgreyPlicPeripheralPwrmgr	pwrmgr
kTopEarlgreyPlicPeripheralSysrstCtrl	sysrst_ctrl
kTopEarlgreyPlicPeripheralAdcCtrl	adc_ctrl
kTopEarlgreyPlicPeripheralAonTimer	aon_timer
kTopEarlgreyPlicPeripheralSensorCtrl	sensor_ctrl
kTopEarlgreyPlicPeripheralRramCtrl	rram_ctrl
kTopEarlgreyPlicPeripheralHmac	hmac
kTopEarlgreyPlicPeripheralKmac	kmac
kTopEarlgreyPlicPeripheralOtbn	otbn
kTopEarlgreyPlicPeripheralKeymgrDpe	keymgr_dpe
kTopEarlgreyPlicPeripheralCsrng	csrng
kTopEarlgreyPlicPeripheralEntropySrc	entropy_src
kTopEarlgreyPlicPeripheralEdn0	edn0
kTopEarlgreyPlicPeripheralEdn1	edn1
kTopEarlgreyPlicPeripheralCheriotMemSys	cheriot_mem_sys

Definition at line 993 of file top_earlgrey.h.

top_earlgrey_plic_target

enum top_earlgrey_plic_target

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumerator
kTopEarlgreyPlicTargetIbex0	Ibex Core 0.

Definition at line 1278 of file top_earlgrey.h.

top_earlgrey_power_manager_reset_requests

enum top_earlgrey_power_manager_reset_requests

Power Manager Reset Request Signals.

Definition at line 1875 of file top_earlgrey.h.

top_earlgrey_power_manager_wake_ups

enum top_earlgrey_power_manager_wake_ups

Power Manager Wakeup Signals.

Definition at line 1843 of file top_earlgrey.h.

top_earlgrey_reset_manager_sw_resets

enum top_earlgrey_reset_manager_sw_resets

Reset Manager Software Controlled Resets.

Definition at line 1858 of file top_earlgrey.h.

Variable Documentation

top_earlgrey_alert_for_peripheral

const top_earlgrey_alert_peripheral_t top_earlgrey_alert_for_peripheral[69]

extern

Alert Handler Alert Source to Peripheral Map.

This array is a mapping from top_earlgrey_alert_id_t to top_earlgrey_alert_peripheral_t.

Definition at line 19 of file top_earlgrey.c.

top_earlgrey_plic_interrupt_for_peripheral

const top_earlgrey_plic_peripheral_t top_earlgrey_plic_interrupt_for_peripheral[222]

extern

PLIC Interrupt Source to Peripheral Map.

This array is a mapping from top_earlgrey_plic_irq_id_t to top_earlgrey_plic_peripheral_t.

Definition at line 98 of file top_earlgrey.c.