(45edf908c9)

Top-specific Definitions. More...

Macros
#define	TOP_EARLGREY_UART0_BASE_ADDR 0x40000000u
	Peripheral base address for uart0 in top earlgrey. More...

#define	TOP_EARLGREY_UART0_SIZE_BYTES 0x40u
	Peripheral size for uart0 in top earlgrey. More...

#define	TOP_EARLGREY_UART1_BASE_ADDR 0x40010000u
	Peripheral base address for uart1 in top earlgrey. More...

#define	TOP_EARLGREY_UART1_SIZE_BYTES 0x40u
	Peripheral size for uart1 in top earlgrey. More...

#define	TOP_EARLGREY_UART2_BASE_ADDR 0x40020000u
	Peripheral base address for uart2 in top earlgrey. More...

#define	TOP_EARLGREY_UART2_SIZE_BYTES 0x40u
	Peripheral size for uart2 in top earlgrey. More...

#define	TOP_EARLGREY_UART3_BASE_ADDR 0x40030000u
	Peripheral base address for uart3 in top earlgrey. More...

#define	TOP_EARLGREY_UART3_SIZE_BYTES 0x40u
	Peripheral size for uart3 in top earlgrey. More...

#define	TOP_EARLGREY_GPIO_BASE_ADDR 0x40040000u
	Peripheral base address for gpio in top earlgrey. More...

#define	TOP_EARLGREY_GPIO_SIZE_BYTES 0x80u
	Peripheral size for gpio in top earlgrey. More...

#define	TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40050000u
	Peripheral base address for spi_device in top earlgrey. More...

#define	TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x2000u
	Peripheral size for spi_device in top earlgrey. More...

#define	TOP_EARLGREY_I2C0_BASE_ADDR 0x40080000u
	Peripheral base address for i2c0 in top earlgrey. More...

#define	TOP_EARLGREY_I2C0_SIZE_BYTES 0x80u
	Peripheral size for i2c0 in top earlgrey. More...

#define	TOP_EARLGREY_I2C1_BASE_ADDR 0x40090000u
	Peripheral base address for i2c1 in top earlgrey. More...

#define	TOP_EARLGREY_I2C1_SIZE_BYTES 0x80u
	Peripheral size for i2c1 in top earlgrey. More...

#define	TOP_EARLGREY_I2C2_BASE_ADDR 0x400A0000u
	Peripheral base address for i2c2 in top earlgrey. More...

#define	TOP_EARLGREY_I2C2_SIZE_BYTES 0x80u
	Peripheral size for i2c2 in top earlgrey. More...

#define	TOP_EARLGREY_PATTGEN_BASE_ADDR 0x400E0000u
	Peripheral base address for pattgen in top earlgrey. More...

#define	TOP_EARLGREY_PATTGEN_SIZE_BYTES 0x40u
	Peripheral size for pattgen in top earlgrey. More...

#define	TOP_EARLGREY_RV_TIMER_BASE_ADDR 0x40100000u
	Peripheral base address for rv_timer in top earlgrey. More...

#define	TOP_EARLGREY_RV_TIMER_SIZE_BYTES 0x200u
	Peripheral size for rv_timer in top earlgrey. More...

#define	TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR 0x40130000u
	Peripheral base address for core device on otp_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES 0x1000u
	Peripheral size for core device on otp_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR 0x40138000u
	Peripheral base address for prim device on otp_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_OTP_CTRL_PRIM_SIZE_BYTES 0x20u
	Peripheral size for prim device on otp_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR 0x40140000u
	Peripheral base address for regs device on lc_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES 0x100u
	Peripheral size for regs device on lc_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR 0x0u
	Peripheral base address for dmi device on lc_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES 0x1000u
	Peripheral size for dmi device on lc_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x40150000u
	Peripheral base address for alert_handler in top earlgrey. More...

#define	TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x800u
	Peripheral size for alert_handler in top earlgrey. More...

#define	TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40300000u
	Peripheral base address for spi_host0 in top earlgrey. More...

#define	TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x40u
	Peripheral size for spi_host0 in top earlgrey. More...

#define	TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40310000u
	Peripheral base address for spi_host1 in top earlgrey. More...

#define	TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x40u
	Peripheral size for spi_host1 in top earlgrey. More...

#define	TOP_EARLGREY_USBDEV_BASE_ADDR 0x40320000u
	Peripheral base address for usbdev in top earlgrey. More...

#define	TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000u
	Peripheral size for usbdev in top earlgrey. More...

#define	TOP_EARLGREY_PWRMGR_AON_BASE_ADDR 0x40400000u
	Peripheral base address for pwrmgr_aon in top earlgrey. More...

#define	TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for pwrmgr_aon in top earlgrey. More...

#define	TOP_EARLGREY_RSTMGR_AON_BASE_ADDR 0x40410000u
	Peripheral base address for rstmgr_aon in top earlgrey. More...

#define	TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for rstmgr_aon in top earlgrey. More...

#define	TOP_EARLGREY_CLKMGR_AON_BASE_ADDR 0x40420000u
	Peripheral base address for clkmgr_aon in top earlgrey. More...

#define	TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES 0x80u
	Peripheral size for clkmgr_aon in top earlgrey. More...

#define	TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
	Peripheral base address for sysrst_ctrl_aon in top earlgrey. More...

#define	TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES 0x100u
	Peripheral size for sysrst_ctrl_aon in top earlgrey. More...

#define	TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR 0x40440000u
	Peripheral base address for adc_ctrl_aon in top earlgrey. More...

#define	TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES 0x80u
	Peripheral size for adc_ctrl_aon in top earlgrey. More...

#define	TOP_EARLGREY_PWM_AON_BASE_ADDR 0x40450000u
	Peripheral base address for pwm_aon in top earlgrey. More...

#define	TOP_EARLGREY_PWM_AON_SIZE_BYTES 0x80u
	Peripheral size for pwm_aon in top earlgrey. More...

#define	TOP_EARLGREY_PINMUX_AON_BASE_ADDR 0x40460000u
	Peripheral base address for pinmux_aon in top earlgrey. More...

#define	TOP_EARLGREY_PINMUX_AON_SIZE_BYTES 0x1000u
	Peripheral size for pinmux_aon in top earlgrey. More...

#define	TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR 0x40470000u
	Peripheral base address for aon_timer_aon in top earlgrey. More...

#define	TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES 0x40u
	Peripheral size for aon_timer_aon in top earlgrey. More...

#define	TOP_EARLGREY_AST_BASE_ADDR 0x40480000u
	Peripheral base address for ast in top earlgrey. More...

#define	TOP_EARLGREY_AST_SIZE_BYTES 0x400u
	Peripheral size for ast in top earlgrey. More...

#define	TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR 0x40490000u
	Peripheral base address for sensor_ctrl_aon in top earlgrey. More...

#define	TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES 0x80u
	Peripheral size for sensor_ctrl_aon in top earlgrey. More...

#define	TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
	Peripheral base address for regs device on sram_ctrl_ret_aon in top earlgrey. More...

#define	TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u
	Peripheral size for regs device on sram_ctrl_ret_aon in top earlgrey. More...

#define	TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
	Peripheral base address for ram device on sram_ctrl_ret_aon in top earlgrey. More...

#define	TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
	Peripheral size for ram device on sram_ctrl_ret_aon in top earlgrey. More...

#define	TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
	Peripheral base address for core device on flash_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
	Peripheral size for core device on flash_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u
	Peripheral base address for prim device on flash_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u
	Peripheral size for prim device on flash_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
	Peripheral base address for mem device on flash_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u
	Peripheral size for mem device on flash_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_RV_DM_REGS_BASE_ADDR 0x41200000u
	Peripheral base address for regs device on rv_dm in top earlgrey. More...

#define	TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES 0x10u
	Peripheral size for regs device on rv_dm in top earlgrey. More...

#define	TOP_EARLGREY_RV_DM_MEM_BASE_ADDR 0x10000u
	Peripheral base address for mem device on rv_dm in top earlgrey. More...

#define	TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000u
	Peripheral size for mem device on rv_dm in top earlgrey. More...

#define	TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000u
	Peripheral base address for dbg device on rv_dm in top earlgrey. More...

#define	TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200u
	Peripheral size for dbg device on rv_dm in top earlgrey. More...

#define	TOP_EARLGREY_RV_PLIC_BASE_ADDR 0x48000000u
	Peripheral base address for rv_plic in top earlgrey. More...

#define	TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x8000000u
	Peripheral size for rv_plic in top earlgrey. More...

#define	TOP_EARLGREY_AES_BASE_ADDR 0x41100000u
	Peripheral base address for aes in top earlgrey. More...

#define	TOP_EARLGREY_AES_SIZE_BYTES 0x100u
	Peripheral size for aes in top earlgrey. More...

#define	TOP_EARLGREY_HMAC_BASE_ADDR 0x41110000u
	Peripheral base address for hmac in top earlgrey. More...

#define	TOP_EARLGREY_HMAC_SIZE_BYTES 0x2000u
	Peripheral size for hmac in top earlgrey. More...

#define	TOP_EARLGREY_KMAC_BASE_ADDR 0x41120000u
	Peripheral base address for kmac in top earlgrey. More...

#define	TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000u
	Peripheral size for kmac in top earlgrey. More...

#define	TOP_EARLGREY_OTBN_BASE_ADDR 0x41130000u
	Peripheral base address for otbn in top earlgrey. More...

#define	TOP_EARLGREY_OTBN_SIZE_BYTES 0x10000u
	Peripheral size for otbn in top earlgrey. More...

#define	TOP_EARLGREY_KEYMGR_BASE_ADDR 0x41140000u
	Peripheral base address for keymgr in top earlgrey. More...

#define	TOP_EARLGREY_KEYMGR_SIZE_BYTES 0x100u
	Peripheral size for keymgr in top earlgrey. More...

#define	TOP_EARLGREY_CSRNG_BASE_ADDR 0x41150000u
	Peripheral base address for csrng in top earlgrey. More...

#define	TOP_EARLGREY_CSRNG_SIZE_BYTES 0x80u
	Peripheral size for csrng in top earlgrey. More...

#define	TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR 0x41160000u
	Peripheral base address for entropy_src in top earlgrey. More...

#define	TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES 0x100u
	Peripheral size for entropy_src in top earlgrey. More...

#define	TOP_EARLGREY_EDN0_BASE_ADDR 0x41170000u
	Peripheral base address for edn0 in top earlgrey. More...

#define	TOP_EARLGREY_EDN0_SIZE_BYTES 0x80u
	Peripheral size for edn0 in top earlgrey. More...

#define	TOP_EARLGREY_EDN1_BASE_ADDR 0x41180000u
	Peripheral base address for edn1 in top earlgrey. More...

#define	TOP_EARLGREY_EDN1_SIZE_BYTES 0x80u
	Peripheral size for edn1 in top earlgrey. More...

#define	TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
	Peripheral base address for regs device on sram_ctrl_main in top earlgrey. More...

#define	TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
	Peripheral size for regs device on sram_ctrl_main in top earlgrey. More...

#define	TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
	Peripheral base address for ram device on sram_ctrl_main in top earlgrey. More...

#define	TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
	Peripheral size for ram device on sram_ctrl_main in top earlgrey. More...

#define	TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
	Peripheral base address for regs device on rom_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES 0x80u
	Peripheral size for regs device on rom_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR 0x8000u
	Peripheral base address for rom device on rom_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
	Peripheral size for rom device on rom_ctrl in top earlgrey. More...

#define	TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u
	Peripheral base address for cfg device on rv_core_ibex in top earlgrey. More...

#define	TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u
	Peripheral size for cfg device on rv_core_ibex in top earlgrey. More...

#define	TOP_EARLGREY_RAM_RET_AON_BASE_ADDR 0x40600000u
	Memory base address for ram_ret_aon in top earlgrey.

#define	TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES 0x1000u
	Memory size for ram_ret_aon in top earlgrey.

#define	TOP_EARLGREY_EFLASH_BASE_ADDR 0x20000000u
	Memory base address for eflash in top earlgrey.

#define	TOP_EARLGREY_EFLASH_SIZE_BYTES 0x100000u
	Memory size for eflash in top earlgrey.

#define	TOP_EARLGREY_RAM_MAIN_BASE_ADDR 0x10000000u
	Memory base address for ram_main in top earlgrey.

#define	TOP_EARLGREY_RAM_MAIN_SIZE_BYTES 0x20000u
	Memory size for ram_main in top earlgrey.

#define	TOP_EARLGREY_ROM_BASE_ADDR 0x8000u
	Memory base address for rom in top earlgrey.

#define	TOP_EARLGREY_ROM_SIZE_BYTES 0x8000u
	Memory size for rom in top earlgrey.

#define	PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2

#define	NUM_MIO_PADS 47

#define	NUM_DIO_PADS 16

#define	PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3

#define	TOP_EARLGREY_MMIO_BASE_ADDR 0x40000000u
	MMIO Region. More...

#define	TOP_EARLGREY_MMIO_SIZE_BYTES 0x10000000u

Typedefs
typedef enum top_earlgrey_plic_peripheral	top_earlgrey_plic_peripheral_t
	PLIC Interrupt Source Peripheral. More...

typedef enum top_earlgrey_plic_irq_id	top_earlgrey_plic_irq_id_t
	PLIC Interrupt Source. More...

typedef enum top_earlgrey_plic_target	top_earlgrey_plic_target_t
	PLIC Interrupt Target. More...

typedef enum top_earlgrey_alert_peripheral	top_earlgrey_alert_peripheral_t
	Alert Handler Source Peripheral. More...

typedef enum top_earlgrey_alert_id	top_earlgrey_alert_id_t
	Alert Handler Alert Source. More...

typedef enum top_earlgrey_pinmux_peripheral_in	top_earlgrey_pinmux_peripheral_in_t
	Pinmux Peripheral Input.

typedef enum top_earlgrey_pinmux_insel	top_earlgrey_pinmux_insel_t
	Pinmux MIO Input Selector.

typedef enum top_earlgrey_pinmux_mio_out	top_earlgrey_pinmux_mio_out_t
	Pinmux MIO Output.

typedef enum top_earlgrey_pinmux_outsel	top_earlgrey_pinmux_outsel_t
	Pinmux Peripheral Output Selector.

typedef enum top_earlgrey_direct_pads	top_earlgrey_direct_pads_t
	Dedicated Pad Selects.

typedef enum top_earlgrey_muxed_pads	top_earlgrey_muxed_pads_t
	Muxed Pad Selects.

typedef enum top_earlgrey_power_manager_wake_ups	top_earlgrey_power_manager_wake_ups_t
	Power Manager Wakeup Signals.

typedef enum top_earlgrey_reset_manager_sw_resets	top_earlgrey_reset_manager_sw_resets_t
	Reset Manager Software Controlled Resets.

typedef enum top_earlgrey_power_manager_reset_requests	top_earlgrey_power_manager_reset_requests_t
	Power Manager Reset Request Signals.

typedef enum top_earlgrey_gateable_clocks	top_earlgrey_gateable_clocks_t
	Clock Manager Software-Controlled ("Gated") Clocks. More...

typedef enum top_earlgrey_hintable_clocks	top_earlgrey_hintable_clocks_t
	Clock Manager Software-Hinted Clocks. More...

Enumerations
enum	top_earlgrey_plic_peripheral { kTopEarlgreyPlicPeripheralUnknown = 0 , kTopEarlgreyPlicPeripheralUart0 = 1 , kTopEarlgreyPlicPeripheralUart1 = 2 , kTopEarlgreyPlicPeripheralUart2 = 3 , kTopEarlgreyPlicPeripheralUart3 = 4 , kTopEarlgreyPlicPeripheralGpio = 5 , kTopEarlgreyPlicPeripheralSpiDevice = 6 , kTopEarlgreyPlicPeripheralI2c0 = 7 , kTopEarlgreyPlicPeripheralI2c1 = 8 , kTopEarlgreyPlicPeripheralI2c2 = 9 , kTopEarlgreyPlicPeripheralPattgen = 10 , kTopEarlgreyPlicPeripheralRvTimer = 11 , kTopEarlgreyPlicPeripheralOtpCtrl = 12 , kTopEarlgreyPlicPeripheralAlertHandler = 13 , kTopEarlgreyPlicPeripheralSpiHost0 = 14 , kTopEarlgreyPlicPeripheralSpiHost1 = 15 , kTopEarlgreyPlicPeripheralUsbdev = 16 , kTopEarlgreyPlicPeripheralPwrmgrAon = 17 , kTopEarlgreyPlicPeripheralSysrstCtrlAon = 18 , kTopEarlgreyPlicPeripheralAdcCtrlAon = 19 , kTopEarlgreyPlicPeripheralAonTimerAon = 20 , kTopEarlgreyPlicPeripheralSensorCtrlAon = 21 , kTopEarlgreyPlicPeripheralFlashCtrl = 22 , kTopEarlgreyPlicPeripheralHmac = 23 , kTopEarlgreyPlicPeripheralKmac = 24 , kTopEarlgreyPlicPeripheralOtbn = 25 , kTopEarlgreyPlicPeripheralKeymgr = 26 , kTopEarlgreyPlicPeripheralCsrng = 27 , kTopEarlgreyPlicPeripheralEntropySrc = 28 , kTopEarlgreyPlicPeripheralEdn0 = 29 , kTopEarlgreyPlicPeripheralEdn1 = 30 , kTopEarlgreyPlicPeripheralLast = 30 }
	PLIC Interrupt Source Peripheral. More...

enum	top_earlgrey_plic_irq_id { kTopEarlgreyPlicIrqIdNone = 0 , kTopEarlgreyPlicIrqIdUart0TxWatermark = 1 , kTopEarlgreyPlicIrqIdUart0RxWatermark = 2 , kTopEarlgreyPlicIrqIdUart0TxDone = 3 , kTopEarlgreyPlicIrqIdUart0RxOverflow = 4 , kTopEarlgreyPlicIrqIdUart0RxFrameErr = 5 , kTopEarlgreyPlicIrqIdUart0RxBreakErr = 6 , kTopEarlgreyPlicIrqIdUart0RxTimeout = 7 , kTopEarlgreyPlicIrqIdUart0RxParityErr = 8 , kTopEarlgreyPlicIrqIdUart0TxEmpty = 9 , kTopEarlgreyPlicIrqIdUart1TxWatermark = 10 , kTopEarlgreyPlicIrqIdUart1RxWatermark = 11 , kTopEarlgreyPlicIrqIdUart1TxDone = 12 , kTopEarlgreyPlicIrqIdUart1RxOverflow = 13 , kTopEarlgreyPlicIrqIdUart1RxFrameErr = 14 , kTopEarlgreyPlicIrqIdUart1RxBreakErr = 15 , kTopEarlgreyPlicIrqIdUart1RxTimeout = 16 , kTopEarlgreyPlicIrqIdUart1RxParityErr = 17 , kTopEarlgreyPlicIrqIdUart1TxEmpty = 18 , kTopEarlgreyPlicIrqIdUart2TxWatermark = 19 , kTopEarlgreyPlicIrqIdUart2RxWatermark = 20 , kTopEarlgreyPlicIrqIdUart2TxDone = 21 , kTopEarlgreyPlicIrqIdUart2RxOverflow = 22 , kTopEarlgreyPlicIrqIdUart2RxFrameErr = 23 , kTopEarlgreyPlicIrqIdUart2RxBreakErr = 24 , kTopEarlgreyPlicIrqIdUart2RxTimeout = 25 , kTopEarlgreyPlicIrqIdUart2RxParityErr = 26 , kTopEarlgreyPlicIrqIdUart2TxEmpty = 27 , kTopEarlgreyPlicIrqIdUart3TxWatermark = 28 , kTopEarlgreyPlicIrqIdUart3RxWatermark = 29 , kTopEarlgreyPlicIrqIdUart3TxDone = 30 , kTopEarlgreyPlicIrqIdUart3RxOverflow = 31 , kTopEarlgreyPlicIrqIdUart3RxFrameErr = 32 , kTopEarlgreyPlicIrqIdUart3RxBreakErr = 33 , kTopEarlgreyPlicIrqIdUart3RxTimeout = 34 , kTopEarlgreyPlicIrqIdUart3RxParityErr = 35 , kTopEarlgreyPlicIrqIdUart3TxEmpty = 36 , kTopEarlgreyPlicIrqIdGpioGpio0 = 37 , kTopEarlgreyPlicIrqIdGpioGpio1 = 38 , kTopEarlgreyPlicIrqIdGpioGpio2 = 39 , kTopEarlgreyPlicIrqIdGpioGpio3 = 40 , kTopEarlgreyPlicIrqIdGpioGpio4 = 41 , kTopEarlgreyPlicIrqIdGpioGpio5 = 42 , kTopEarlgreyPlicIrqIdGpioGpio6 = 43 , kTopEarlgreyPlicIrqIdGpioGpio7 = 44 , kTopEarlgreyPlicIrqIdGpioGpio8 = 45 , kTopEarlgreyPlicIrqIdGpioGpio9 = 46 , kTopEarlgreyPlicIrqIdGpioGpio10 = 47 , kTopEarlgreyPlicIrqIdGpioGpio11 = 48 , kTopEarlgreyPlicIrqIdGpioGpio12 = 49 , kTopEarlgreyPlicIrqIdGpioGpio13 = 50 , kTopEarlgreyPlicIrqIdGpioGpio14 = 51 , kTopEarlgreyPlicIrqIdGpioGpio15 = 52 , kTopEarlgreyPlicIrqIdGpioGpio16 = 53 , kTopEarlgreyPlicIrqIdGpioGpio17 = 54 , kTopEarlgreyPlicIrqIdGpioGpio18 = 55 , kTopEarlgreyPlicIrqIdGpioGpio19 = 56 , kTopEarlgreyPlicIrqIdGpioGpio20 = 57 , kTopEarlgreyPlicIrqIdGpioGpio21 = 58 , kTopEarlgreyPlicIrqIdGpioGpio22 = 59 , kTopEarlgreyPlicIrqIdGpioGpio23 = 60 , kTopEarlgreyPlicIrqIdGpioGpio24 = 61 , kTopEarlgreyPlicIrqIdGpioGpio25 = 62 , kTopEarlgreyPlicIrqIdGpioGpio26 = 63 , kTopEarlgreyPlicIrqIdGpioGpio27 = 64 , kTopEarlgreyPlicIrqIdGpioGpio28 = 65 , kTopEarlgreyPlicIrqIdGpioGpio29 = 66 , kTopEarlgreyPlicIrqIdGpioGpio30 = 67 , kTopEarlgreyPlicIrqIdGpioGpio31 = 68 , kTopEarlgreyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 69 , kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 70 , kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadOverflow = 71 , kTopEarlgreyPlicIrqIdSpiDeviceReadbufWatermark = 72 , kTopEarlgreyPlicIrqIdSpiDeviceReadbufFlip = 73 , kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 74 , kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 75 , kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoDrop = 76 , kTopEarlgreyPlicIrqIdI2c0FmtThreshold = 77 , kTopEarlgreyPlicIrqIdI2c0RxThreshold = 78 , kTopEarlgreyPlicIrqIdI2c0AcqThreshold = 79 , kTopEarlgreyPlicIrqIdI2c0RxOverflow = 80 , kTopEarlgreyPlicIrqIdI2c0ControllerHalt = 81 , kTopEarlgreyPlicIrqIdI2c0SclInterference = 82 , kTopEarlgreyPlicIrqIdI2c0SdaInterference = 83 , kTopEarlgreyPlicIrqIdI2c0StretchTimeout = 84 , kTopEarlgreyPlicIrqIdI2c0SdaUnstable = 85 , kTopEarlgreyPlicIrqIdI2c0CmdComplete = 86 , kTopEarlgreyPlicIrqIdI2c0TxStretch = 87 , kTopEarlgreyPlicIrqIdI2c0TxThreshold = 88 , kTopEarlgreyPlicIrqIdI2c0AcqStretch = 89 , kTopEarlgreyPlicIrqIdI2c0UnexpStop = 90 , kTopEarlgreyPlicIrqIdI2c0HostTimeout = 91 , kTopEarlgreyPlicIrqIdI2c1FmtThreshold = 92 , kTopEarlgreyPlicIrqIdI2c1RxThreshold = 93 , kTopEarlgreyPlicIrqIdI2c1AcqThreshold = 94 , kTopEarlgreyPlicIrqIdI2c1RxOverflow = 95 , kTopEarlgreyPlicIrqIdI2c1ControllerHalt = 96 , kTopEarlgreyPlicIrqIdI2c1SclInterference = 97 , kTopEarlgreyPlicIrqIdI2c1SdaInterference = 98 , kTopEarlgreyPlicIrqIdI2c1StretchTimeout = 99 , kTopEarlgreyPlicIrqIdI2c1SdaUnstable = 100 , kTopEarlgreyPlicIrqIdI2c1CmdComplete = 101 , kTopEarlgreyPlicIrqIdI2c1TxStretch = 102 , kTopEarlgreyPlicIrqIdI2c1TxThreshold = 103 , kTopEarlgreyPlicIrqIdI2c1AcqStretch = 104 , kTopEarlgreyPlicIrqIdI2c1UnexpStop = 105 , kTopEarlgreyPlicIrqIdI2c1HostTimeout = 106 , kTopEarlgreyPlicIrqIdI2c2FmtThreshold = 107 , kTopEarlgreyPlicIrqIdI2c2RxThreshold = 108 , kTopEarlgreyPlicIrqIdI2c2AcqThreshold = 109 , kTopEarlgreyPlicIrqIdI2c2RxOverflow = 110 , kTopEarlgreyPlicIrqIdI2c2ControllerHalt = 111 , kTopEarlgreyPlicIrqIdI2c2SclInterference = 112 , kTopEarlgreyPlicIrqIdI2c2SdaInterference = 113 , kTopEarlgreyPlicIrqIdI2c2StretchTimeout = 114 , kTopEarlgreyPlicIrqIdI2c2SdaUnstable = 115 , kTopEarlgreyPlicIrqIdI2c2CmdComplete = 116 , kTopEarlgreyPlicIrqIdI2c2TxStretch = 117 , kTopEarlgreyPlicIrqIdI2c2TxThreshold = 118 , kTopEarlgreyPlicIrqIdI2c2AcqStretch = 119 , kTopEarlgreyPlicIrqIdI2c2UnexpStop = 120 , kTopEarlgreyPlicIrqIdI2c2HostTimeout = 121 , kTopEarlgreyPlicIrqIdPattgenDoneCh0 = 122 , kTopEarlgreyPlicIrqIdPattgenDoneCh1 = 123 , kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 124 , kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 125 , kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 126 , kTopEarlgreyPlicIrqIdAlertHandlerClassa = 127 , kTopEarlgreyPlicIrqIdAlertHandlerClassb = 128 , kTopEarlgreyPlicIrqIdAlertHandlerClassc = 129 , kTopEarlgreyPlicIrqIdAlertHandlerClassd = 130 , kTopEarlgreyPlicIrqIdSpiHost0Error = 131 , kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 132 , kTopEarlgreyPlicIrqIdSpiHost1Error = 133 , kTopEarlgreyPlicIrqIdSpiHost1SpiEvent = 134 , kTopEarlgreyPlicIrqIdUsbdevPktReceived = 135 , kTopEarlgreyPlicIrqIdUsbdevPktSent = 136 , kTopEarlgreyPlicIrqIdUsbdevDisconnected = 137 , kTopEarlgreyPlicIrqIdUsbdevHostLost = 138 , kTopEarlgreyPlicIrqIdUsbdevLinkReset = 139 , kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 140 , kTopEarlgreyPlicIrqIdUsbdevLinkResume = 141 , kTopEarlgreyPlicIrqIdUsbdevAvOutEmpty = 142 , kTopEarlgreyPlicIrqIdUsbdevRxFull = 143 , kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 144 , kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 145 , kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 146 , kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 147 , kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 148 , kTopEarlgreyPlicIrqIdUsbdevFrame = 149 , kTopEarlgreyPlicIrqIdUsbdevPowered = 150 , kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 151 , kTopEarlgreyPlicIrqIdUsbdevAvSetupEmpty = 152 , kTopEarlgreyPlicIrqIdPwrmgrAonWakeup = 153 , kTopEarlgreyPlicIrqIdSysrstCtrlAonEventDetected = 154 , kTopEarlgreyPlicIrqIdAdcCtrlAonMatchPending = 155 , kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired = 156 , kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark = 157 , kTopEarlgreyPlicIrqIdSensorCtrlAonIoStatusChange = 158 , kTopEarlgreyPlicIrqIdSensorCtrlAonInitStatusChange = 159 , kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 160 , kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 161 , kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 162 , kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 163 , kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 164 , kTopEarlgreyPlicIrqIdFlashCtrlCorrErr = 165 , kTopEarlgreyPlicIrqIdHmacHmacDone = 166 , kTopEarlgreyPlicIrqIdHmacFifoEmpty = 167 , kTopEarlgreyPlicIrqIdHmacHmacErr = 168 , kTopEarlgreyPlicIrqIdKmacKmacDone = 169 , kTopEarlgreyPlicIrqIdKmacFifoEmpty = 170 , kTopEarlgreyPlicIrqIdKmacKmacErr = 171 , kTopEarlgreyPlicIrqIdOtbnDone = 172 , kTopEarlgreyPlicIrqIdKeymgrOpDone = 173 , kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 174 , kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 175 , kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 176 , kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 177 , kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 178 , kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 179 , kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 180 , kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 181 , kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 182 , kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 183 , kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 184 , kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 185 , kTopEarlgreyPlicIrqIdLast = 185 }
	PLIC Interrupt Source. More...

enum	top_earlgrey_plic_target { kTopEarlgreyPlicTargetIbex0 = 0 , kTopEarlgreyPlicTargetLast = 0 }
	PLIC Interrupt Target. More...

enum	top_earlgrey_alert_peripheral { kTopEarlgreyAlertPeripheralUart0 = 0 , kTopEarlgreyAlertPeripheralUart1 = 1 , kTopEarlgreyAlertPeripheralUart2 = 2 , kTopEarlgreyAlertPeripheralUart3 = 3 , kTopEarlgreyAlertPeripheralGpio = 4 , kTopEarlgreyAlertPeripheralSpiDevice = 5 , kTopEarlgreyAlertPeripheralI2c0 = 6 , kTopEarlgreyAlertPeripheralI2c1 = 7 , kTopEarlgreyAlertPeripheralI2c2 = 8 , kTopEarlgreyAlertPeripheralPattgen = 9 , kTopEarlgreyAlertPeripheralRvTimer = 10 , kTopEarlgreyAlertPeripheralOtpCtrl = 11 , kTopEarlgreyAlertPeripheralLcCtrl = 12 , kTopEarlgreyAlertPeripheralSpiHost0 = 13 , kTopEarlgreyAlertPeripheralSpiHost1 = 14 , kTopEarlgreyAlertPeripheralUsbdev = 15 , kTopEarlgreyAlertPeripheralPwrmgrAon = 16 , kTopEarlgreyAlertPeripheralRstmgrAon = 17 , kTopEarlgreyAlertPeripheralClkmgrAon = 18 , kTopEarlgreyAlertPeripheralSysrstCtrlAon = 19 , kTopEarlgreyAlertPeripheralAdcCtrlAon = 20 , kTopEarlgreyAlertPeripheralPwmAon = 21 , kTopEarlgreyAlertPeripheralPinmuxAon = 22 , kTopEarlgreyAlertPeripheralAonTimerAon = 23 , kTopEarlgreyAlertPeripheralSensorCtrlAon = 24 , kTopEarlgreyAlertPeripheralSramCtrlRetAon = 25 , kTopEarlgreyAlertPeripheralFlashCtrl = 26 , kTopEarlgreyAlertPeripheralRvDm = 27 , kTopEarlgreyAlertPeripheralRvPlic = 28 , kTopEarlgreyAlertPeripheralAes = 29 , kTopEarlgreyAlertPeripheralHmac = 30 , kTopEarlgreyAlertPeripheralKmac = 31 , kTopEarlgreyAlertPeripheralOtbn = 32 , kTopEarlgreyAlertPeripheralKeymgr = 33 , kTopEarlgreyAlertPeripheralCsrng = 34 , kTopEarlgreyAlertPeripheralEntropySrc = 35 , kTopEarlgreyAlertPeripheralEdn0 = 36 , kTopEarlgreyAlertPeripheralEdn1 = 37 , kTopEarlgreyAlertPeripheralSramCtrlMain = 38 , kTopEarlgreyAlertPeripheralRomCtrl = 39 , kTopEarlgreyAlertPeripheralRvCoreIbex = 40 , kTopEarlgreyAlertPeripheralLast = 40 }
	Alert Handler Source Peripheral. More...

enum	top_earlgrey_alert_id { kTopEarlgreyAlertIdUart0FatalFault = 0 , kTopEarlgreyAlertIdUart1FatalFault = 1 , kTopEarlgreyAlertIdUart2FatalFault = 2 , kTopEarlgreyAlertIdUart3FatalFault = 3 , kTopEarlgreyAlertIdGpioFatalFault = 4 , kTopEarlgreyAlertIdSpiDeviceFatalFault = 5 , kTopEarlgreyAlertIdI2c0FatalFault = 6 , kTopEarlgreyAlertIdI2c1FatalFault = 7 , kTopEarlgreyAlertIdI2c2FatalFault = 8 , kTopEarlgreyAlertIdPattgenFatalFault = 9 , kTopEarlgreyAlertIdRvTimerFatalFault = 10 , kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 11 , kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 12 , kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 13 , kTopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert = 14 , kTopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert = 15 , kTopEarlgreyAlertIdLcCtrlFatalProgError = 16 , kTopEarlgreyAlertIdLcCtrlFatalStateError = 17 , kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 18 , kTopEarlgreyAlertIdSpiHost0FatalFault = 19 , kTopEarlgreyAlertIdSpiHost1FatalFault = 20 , kTopEarlgreyAlertIdUsbdevFatalFault = 21 , kTopEarlgreyAlertIdPwrmgrAonFatalFault = 22 , kTopEarlgreyAlertIdRstmgrAonFatalFault = 23 , kTopEarlgreyAlertIdRstmgrAonFatalCnstyFault = 24 , kTopEarlgreyAlertIdClkmgrAonRecovFault = 25 , kTopEarlgreyAlertIdClkmgrAonFatalFault = 26 , kTopEarlgreyAlertIdSysrstCtrlAonFatalFault = 27 , kTopEarlgreyAlertIdAdcCtrlAonFatalFault = 28 , kTopEarlgreyAlertIdPwmAonFatalFault = 29 , kTopEarlgreyAlertIdPinmuxAonFatalFault = 30 , kTopEarlgreyAlertIdAonTimerAonFatalFault = 31 , kTopEarlgreyAlertIdSensorCtrlAonRecovAlert = 32 , kTopEarlgreyAlertIdSensorCtrlAonFatalAlert = 33 , kTopEarlgreyAlertIdSramCtrlRetAonFatalError = 34 , kTopEarlgreyAlertIdFlashCtrlRecovErr = 35 , kTopEarlgreyAlertIdFlashCtrlFatalStdErr = 36 , kTopEarlgreyAlertIdFlashCtrlFatalErr = 37 , kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 38 , kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 39 , kTopEarlgreyAlertIdRvDmFatalFault = 40 , kTopEarlgreyAlertIdRvPlicFatalFault = 41 , kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 42 , kTopEarlgreyAlertIdAesFatalFault = 43 , kTopEarlgreyAlertIdHmacFatalFault = 44 , kTopEarlgreyAlertIdKmacRecovOperationErr = 45 , kTopEarlgreyAlertIdKmacFatalFaultErr = 46 , kTopEarlgreyAlertIdOtbnFatal = 47 , kTopEarlgreyAlertIdOtbnRecov = 48 , kTopEarlgreyAlertIdKeymgrRecovOperationErr = 49 , kTopEarlgreyAlertIdKeymgrFatalFaultErr = 50 , kTopEarlgreyAlertIdCsrngRecovAlert = 51 , kTopEarlgreyAlertIdCsrngFatalAlert = 52 , kTopEarlgreyAlertIdEntropySrcRecovAlert = 53 , kTopEarlgreyAlertIdEntropySrcFatalAlert = 54 , kTopEarlgreyAlertIdEdn0RecovAlert = 55 , kTopEarlgreyAlertIdEdn0FatalAlert = 56 , kTopEarlgreyAlertIdEdn1RecovAlert = 57 , kTopEarlgreyAlertIdEdn1FatalAlert = 58 , kTopEarlgreyAlertIdSramCtrlMainFatalError = 59 , kTopEarlgreyAlertIdRomCtrlFatal = 60 , kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 61 , kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 62 , kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 63 , kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 64 , kTopEarlgreyAlertIdLast = 64 }
	Alert Handler Alert Source. More...

enum	top_earlgrey_pinmux_peripheral_in { kTopEarlgreyPinmuxPeripheralInGpioGpio0 = 0 , kTopEarlgreyPinmuxPeripheralInGpioGpio1 = 1 , kTopEarlgreyPinmuxPeripheralInGpioGpio2 = 2 , kTopEarlgreyPinmuxPeripheralInGpioGpio3 = 3 , kTopEarlgreyPinmuxPeripheralInGpioGpio4 = 4 , kTopEarlgreyPinmuxPeripheralInGpioGpio5 = 5 , kTopEarlgreyPinmuxPeripheralInGpioGpio6 = 6 , kTopEarlgreyPinmuxPeripheralInGpioGpio7 = 7 , kTopEarlgreyPinmuxPeripheralInGpioGpio8 = 8 , kTopEarlgreyPinmuxPeripheralInGpioGpio9 = 9 , kTopEarlgreyPinmuxPeripheralInGpioGpio10 = 10 , kTopEarlgreyPinmuxPeripheralInGpioGpio11 = 11 , kTopEarlgreyPinmuxPeripheralInGpioGpio12 = 12 , kTopEarlgreyPinmuxPeripheralInGpioGpio13 = 13 , kTopEarlgreyPinmuxPeripheralInGpioGpio14 = 14 , kTopEarlgreyPinmuxPeripheralInGpioGpio15 = 15 , kTopEarlgreyPinmuxPeripheralInGpioGpio16 = 16 , kTopEarlgreyPinmuxPeripheralInGpioGpio17 = 17 , kTopEarlgreyPinmuxPeripheralInGpioGpio18 = 18 , kTopEarlgreyPinmuxPeripheralInGpioGpio19 = 19 , kTopEarlgreyPinmuxPeripheralInGpioGpio20 = 20 , kTopEarlgreyPinmuxPeripheralInGpioGpio21 = 21 , kTopEarlgreyPinmuxPeripheralInGpioGpio22 = 22 , kTopEarlgreyPinmuxPeripheralInGpioGpio23 = 23 , kTopEarlgreyPinmuxPeripheralInGpioGpio24 = 24 , kTopEarlgreyPinmuxPeripheralInGpioGpio25 = 25 , kTopEarlgreyPinmuxPeripheralInGpioGpio26 = 26 , kTopEarlgreyPinmuxPeripheralInGpioGpio27 = 27 , kTopEarlgreyPinmuxPeripheralInGpioGpio28 = 28 , kTopEarlgreyPinmuxPeripheralInGpioGpio29 = 29 , kTopEarlgreyPinmuxPeripheralInGpioGpio30 = 30 , kTopEarlgreyPinmuxPeripheralInGpioGpio31 = 31 , kTopEarlgreyPinmuxPeripheralInI2c0Sda = 32 , kTopEarlgreyPinmuxPeripheralInI2c0Scl = 33 , kTopEarlgreyPinmuxPeripheralInI2c1Sda = 34 , kTopEarlgreyPinmuxPeripheralInI2c1Scl = 35 , kTopEarlgreyPinmuxPeripheralInI2c2Sda = 36 , kTopEarlgreyPinmuxPeripheralInI2c2Scl = 37 , kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0 = 38 , kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1 = 39 , kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2 = 40 , kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3 = 41 , kTopEarlgreyPinmuxPeripheralInUart0Rx = 42 , kTopEarlgreyPinmuxPeripheralInUart1Rx = 43 , kTopEarlgreyPinmuxPeripheralInUart2Rx = 44 , kTopEarlgreyPinmuxPeripheralInUart3Rx = 45 , kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb = 46 , kTopEarlgreyPinmuxPeripheralInFlashCtrlTck = 47 , kTopEarlgreyPinmuxPeripheralInFlashCtrlTms = 48 , kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi = 49 , kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonAcPresent = 50 , kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey0In = 51 , kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey1In = 52 , kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey2In = 53 , kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonPwrbIn = 54 , kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonLidOpen = 55 , kTopEarlgreyPinmuxPeripheralInUsbdevSense = 56 , kTopEarlgreyPinmuxPeripheralInLast = 56 }
	Pinmux Peripheral Input. More...

enum	top_earlgrey_pinmux_insel { kTopEarlgreyPinmuxInselConstantZero = 0 , kTopEarlgreyPinmuxInselConstantOne = 1 , kTopEarlgreyPinmuxInselIoa0 = 2 , kTopEarlgreyPinmuxInselIoa1 = 3 , kTopEarlgreyPinmuxInselIoa2 = 4 , kTopEarlgreyPinmuxInselIoa3 = 5 , kTopEarlgreyPinmuxInselIoa4 = 6 , kTopEarlgreyPinmuxInselIoa5 = 7 , kTopEarlgreyPinmuxInselIoa6 = 8 , kTopEarlgreyPinmuxInselIoa7 = 9 , kTopEarlgreyPinmuxInselIoa8 = 10 , kTopEarlgreyPinmuxInselIob0 = 11 , kTopEarlgreyPinmuxInselIob1 = 12 , kTopEarlgreyPinmuxInselIob2 = 13 , kTopEarlgreyPinmuxInselIob3 = 14 , kTopEarlgreyPinmuxInselIob4 = 15 , kTopEarlgreyPinmuxInselIob5 = 16 , kTopEarlgreyPinmuxInselIob6 = 17 , kTopEarlgreyPinmuxInselIob7 = 18 , kTopEarlgreyPinmuxInselIob8 = 19 , kTopEarlgreyPinmuxInselIob9 = 20 , kTopEarlgreyPinmuxInselIob10 = 21 , kTopEarlgreyPinmuxInselIob11 = 22 , kTopEarlgreyPinmuxInselIob12 = 23 , kTopEarlgreyPinmuxInselIoc0 = 24 , kTopEarlgreyPinmuxInselIoc1 = 25 , kTopEarlgreyPinmuxInselIoc2 = 26 , kTopEarlgreyPinmuxInselIoc3 = 27 , kTopEarlgreyPinmuxInselIoc4 = 28 , kTopEarlgreyPinmuxInselIoc5 = 29 , kTopEarlgreyPinmuxInselIoc6 = 30 , kTopEarlgreyPinmuxInselIoc7 = 31 , kTopEarlgreyPinmuxInselIoc8 = 32 , kTopEarlgreyPinmuxInselIoc9 = 33 , kTopEarlgreyPinmuxInselIoc10 = 34 , kTopEarlgreyPinmuxInselIoc11 = 35 , kTopEarlgreyPinmuxInselIoc12 = 36 , kTopEarlgreyPinmuxInselIor0 = 37 , kTopEarlgreyPinmuxInselIor1 = 38 , kTopEarlgreyPinmuxInselIor2 = 39 , kTopEarlgreyPinmuxInselIor3 = 40 , kTopEarlgreyPinmuxInselIor4 = 41 , kTopEarlgreyPinmuxInselIor5 = 42 , kTopEarlgreyPinmuxInselIor6 = 43 , kTopEarlgreyPinmuxInselIor7 = 44 , kTopEarlgreyPinmuxInselIor10 = 45 , kTopEarlgreyPinmuxInselIor11 = 46 , kTopEarlgreyPinmuxInselIor12 = 47 , kTopEarlgreyPinmuxInselIor13 = 48 , kTopEarlgreyPinmuxInselLast = 48 }
	Pinmux MIO Input Selector. More...

enum	top_earlgrey_pinmux_mio_out { kTopEarlgreyPinmuxMioOutIoa0 = 0 , kTopEarlgreyPinmuxMioOutIoa1 = 1 , kTopEarlgreyPinmuxMioOutIoa2 = 2 , kTopEarlgreyPinmuxMioOutIoa3 = 3 , kTopEarlgreyPinmuxMioOutIoa4 = 4 , kTopEarlgreyPinmuxMioOutIoa5 = 5 , kTopEarlgreyPinmuxMioOutIoa6 = 6 , kTopEarlgreyPinmuxMioOutIoa7 = 7 , kTopEarlgreyPinmuxMioOutIoa8 = 8 , kTopEarlgreyPinmuxMioOutIob0 = 9 , kTopEarlgreyPinmuxMioOutIob1 = 10 , kTopEarlgreyPinmuxMioOutIob2 = 11 , kTopEarlgreyPinmuxMioOutIob3 = 12 , kTopEarlgreyPinmuxMioOutIob4 = 13 , kTopEarlgreyPinmuxMioOutIob5 = 14 , kTopEarlgreyPinmuxMioOutIob6 = 15 , kTopEarlgreyPinmuxMioOutIob7 = 16 , kTopEarlgreyPinmuxMioOutIob8 = 17 , kTopEarlgreyPinmuxMioOutIob9 = 18 , kTopEarlgreyPinmuxMioOutIob10 = 19 , kTopEarlgreyPinmuxMioOutIob11 = 20 , kTopEarlgreyPinmuxMioOutIob12 = 21 , kTopEarlgreyPinmuxMioOutIoc0 = 22 , kTopEarlgreyPinmuxMioOutIoc1 = 23 , kTopEarlgreyPinmuxMioOutIoc2 = 24 , kTopEarlgreyPinmuxMioOutIoc3 = 25 , kTopEarlgreyPinmuxMioOutIoc4 = 26 , kTopEarlgreyPinmuxMioOutIoc5 = 27 , kTopEarlgreyPinmuxMioOutIoc6 = 28 , kTopEarlgreyPinmuxMioOutIoc7 = 29 , kTopEarlgreyPinmuxMioOutIoc8 = 30 , kTopEarlgreyPinmuxMioOutIoc9 = 31 , kTopEarlgreyPinmuxMioOutIoc10 = 32 , kTopEarlgreyPinmuxMioOutIoc11 = 33 , kTopEarlgreyPinmuxMioOutIoc12 = 34 , kTopEarlgreyPinmuxMioOutIor0 = 35 , kTopEarlgreyPinmuxMioOutIor1 = 36 , kTopEarlgreyPinmuxMioOutIor2 = 37 , kTopEarlgreyPinmuxMioOutIor3 = 38 , kTopEarlgreyPinmuxMioOutIor4 = 39 , kTopEarlgreyPinmuxMioOutIor5 = 40 , kTopEarlgreyPinmuxMioOutIor6 = 41 , kTopEarlgreyPinmuxMioOutIor7 = 42 , kTopEarlgreyPinmuxMioOutIor10 = 43 , kTopEarlgreyPinmuxMioOutIor11 = 44 , kTopEarlgreyPinmuxMioOutIor12 = 45 , kTopEarlgreyPinmuxMioOutIor13 = 46 , kTopEarlgreyPinmuxMioOutLast = 46 }
	Pinmux MIO Output. More...

enum	top_earlgrey_pinmux_outsel { kTopEarlgreyPinmuxOutselConstantZero = 0 , kTopEarlgreyPinmuxOutselConstantOne = 1 , kTopEarlgreyPinmuxOutselConstantHighZ = 2 , kTopEarlgreyPinmuxOutselGpioGpio0 = 3 , kTopEarlgreyPinmuxOutselGpioGpio1 = 4 , kTopEarlgreyPinmuxOutselGpioGpio2 = 5 , kTopEarlgreyPinmuxOutselGpioGpio3 = 6 , kTopEarlgreyPinmuxOutselGpioGpio4 = 7 , kTopEarlgreyPinmuxOutselGpioGpio5 = 8 , kTopEarlgreyPinmuxOutselGpioGpio6 = 9 , kTopEarlgreyPinmuxOutselGpioGpio7 = 10 , kTopEarlgreyPinmuxOutselGpioGpio8 = 11 , kTopEarlgreyPinmuxOutselGpioGpio9 = 12 , kTopEarlgreyPinmuxOutselGpioGpio10 = 13 , kTopEarlgreyPinmuxOutselGpioGpio11 = 14 , kTopEarlgreyPinmuxOutselGpioGpio12 = 15 , kTopEarlgreyPinmuxOutselGpioGpio13 = 16 , kTopEarlgreyPinmuxOutselGpioGpio14 = 17 , kTopEarlgreyPinmuxOutselGpioGpio15 = 18 , kTopEarlgreyPinmuxOutselGpioGpio16 = 19 , kTopEarlgreyPinmuxOutselGpioGpio17 = 20 , kTopEarlgreyPinmuxOutselGpioGpio18 = 21 , kTopEarlgreyPinmuxOutselGpioGpio19 = 22 , kTopEarlgreyPinmuxOutselGpioGpio20 = 23 , kTopEarlgreyPinmuxOutselGpioGpio21 = 24 , kTopEarlgreyPinmuxOutselGpioGpio22 = 25 , kTopEarlgreyPinmuxOutselGpioGpio23 = 26 , kTopEarlgreyPinmuxOutselGpioGpio24 = 27 , kTopEarlgreyPinmuxOutselGpioGpio25 = 28 , kTopEarlgreyPinmuxOutselGpioGpio26 = 29 , kTopEarlgreyPinmuxOutselGpioGpio27 = 30 , kTopEarlgreyPinmuxOutselGpioGpio28 = 31 , kTopEarlgreyPinmuxOutselGpioGpio29 = 32 , kTopEarlgreyPinmuxOutselGpioGpio30 = 33 , kTopEarlgreyPinmuxOutselGpioGpio31 = 34 , kTopEarlgreyPinmuxOutselI2c0Sda = 35 , kTopEarlgreyPinmuxOutselI2c0Scl = 36 , kTopEarlgreyPinmuxOutselI2c1Sda = 37 , kTopEarlgreyPinmuxOutselI2c1Scl = 38 , kTopEarlgreyPinmuxOutselI2c2Sda = 39 , kTopEarlgreyPinmuxOutselI2c2Scl = 40 , kTopEarlgreyPinmuxOutselSpiHost1Sd0 = 41 , kTopEarlgreyPinmuxOutselSpiHost1Sd1 = 42 , kTopEarlgreyPinmuxOutselSpiHost1Sd2 = 43 , kTopEarlgreyPinmuxOutselSpiHost1Sd3 = 44 , kTopEarlgreyPinmuxOutselUart0Tx = 45 , kTopEarlgreyPinmuxOutselUart1Tx = 46 , kTopEarlgreyPinmuxOutselUart2Tx = 47 , kTopEarlgreyPinmuxOutselUart3Tx = 48 , kTopEarlgreyPinmuxOutselPattgenPda0Tx = 49 , kTopEarlgreyPinmuxOutselPattgenPcl0Tx = 50 , kTopEarlgreyPinmuxOutselPattgenPda1Tx = 51 , kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 52 , kTopEarlgreyPinmuxOutselSpiHost1Sck = 53 , kTopEarlgreyPinmuxOutselSpiHost1Csb = 54 , kTopEarlgreyPinmuxOutselFlashCtrlTdo = 55 , kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0 = 56 , kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1 = 57 , kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2 = 58 , kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut3 = 59 , kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut4 = 60 , kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut5 = 61 , kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut6 = 62 , kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut7 = 63 , kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut8 = 64 , kTopEarlgreyPinmuxOutselPwmAonPwm0 = 65 , kTopEarlgreyPinmuxOutselPwmAonPwm1 = 66 , kTopEarlgreyPinmuxOutselPwmAonPwm2 = 67 , kTopEarlgreyPinmuxOutselPwmAonPwm3 = 68 , kTopEarlgreyPinmuxOutselPwmAonPwm4 = 69 , kTopEarlgreyPinmuxOutselPwmAonPwm5 = 70 , kTopEarlgreyPinmuxOutselOtpCtrlTest0 = 71 , kTopEarlgreyPinmuxOutselSysrstCtrlAonBatDisable = 72 , kTopEarlgreyPinmuxOutselSysrstCtrlAonKey0Out = 73 , kTopEarlgreyPinmuxOutselSysrstCtrlAonKey1Out = 74 , kTopEarlgreyPinmuxOutselSysrstCtrlAonKey2Out = 75 , kTopEarlgreyPinmuxOutselSysrstCtrlAonPwrbOut = 76 , kTopEarlgreyPinmuxOutselSysrstCtrlAonZ3Wakeup = 77 , kTopEarlgreyPinmuxOutselLast = 77 }
	Pinmux Peripheral Output Selector. More...

enum	top_earlgrey_direct_pads { kTopEarlgreyDirectPadsUsbdevUsbDp = 0 , kTopEarlgreyDirectPadsUsbdevUsbDn = 1 , kTopEarlgreyDirectPadsSpiHost0Sd0 = 2 , kTopEarlgreyDirectPadsSpiHost0Sd1 = 3 , kTopEarlgreyDirectPadsSpiHost0Sd2 = 4 , kTopEarlgreyDirectPadsSpiHost0Sd3 = 5 , kTopEarlgreyDirectPadsSpiDeviceSd0 = 6 , kTopEarlgreyDirectPadsSpiDeviceSd1 = 7 , kTopEarlgreyDirectPadsSpiDeviceSd2 = 8 , kTopEarlgreyDirectPadsSpiDeviceSd3 = 9 , kTopEarlgreyDirectPadsSysrstCtrlAonEcRstL = 10 , kTopEarlgreyDirectPadsSysrstCtrlAonFlashWpL = 11 , kTopEarlgreyDirectPadsSpiDeviceSck = 12 , kTopEarlgreyDirectPadsSpiDeviceCsb = 13 , kTopEarlgreyDirectPadsSpiHost0Sck = 14 , kTopEarlgreyDirectPadsSpiHost0Csb = 15 , kTopEarlgreyDirectPadsLast = 15 }
	Dedicated Pad Selects.

enum	top_earlgrey_muxed_pads { kTopEarlgreyMuxedPadsIoa0 = 0 , kTopEarlgreyMuxedPadsIoa1 = 1 , kTopEarlgreyMuxedPadsIoa2 = 2 , kTopEarlgreyMuxedPadsIoa3 = 3 , kTopEarlgreyMuxedPadsIoa4 = 4 , kTopEarlgreyMuxedPadsIoa5 = 5 , kTopEarlgreyMuxedPadsIoa6 = 6 , kTopEarlgreyMuxedPadsIoa7 = 7 , kTopEarlgreyMuxedPadsIoa8 = 8 , kTopEarlgreyMuxedPadsIob0 = 9 , kTopEarlgreyMuxedPadsIob1 = 10 , kTopEarlgreyMuxedPadsIob2 = 11 , kTopEarlgreyMuxedPadsIob3 = 12 , kTopEarlgreyMuxedPadsIob4 = 13 , kTopEarlgreyMuxedPadsIob5 = 14 , kTopEarlgreyMuxedPadsIob6 = 15 , kTopEarlgreyMuxedPadsIob7 = 16 , kTopEarlgreyMuxedPadsIob8 = 17 , kTopEarlgreyMuxedPadsIob9 = 18 , kTopEarlgreyMuxedPadsIob10 = 19 , kTopEarlgreyMuxedPadsIob11 = 20 , kTopEarlgreyMuxedPadsIob12 = 21 , kTopEarlgreyMuxedPadsIoc0 = 22 , kTopEarlgreyMuxedPadsIoc1 = 23 , kTopEarlgreyMuxedPadsIoc2 = 24 , kTopEarlgreyMuxedPadsIoc3 = 25 , kTopEarlgreyMuxedPadsIoc4 = 26 , kTopEarlgreyMuxedPadsIoc5 = 27 , kTopEarlgreyMuxedPadsIoc6 = 28 , kTopEarlgreyMuxedPadsIoc7 = 29 , kTopEarlgreyMuxedPadsIoc8 = 30 , kTopEarlgreyMuxedPadsIoc9 = 31 , kTopEarlgreyMuxedPadsIoc10 = 32 , kTopEarlgreyMuxedPadsIoc11 = 33 , kTopEarlgreyMuxedPadsIoc12 = 34 , kTopEarlgreyMuxedPadsIor0 = 35 , kTopEarlgreyMuxedPadsIor1 = 36 , kTopEarlgreyMuxedPadsIor2 = 37 , kTopEarlgreyMuxedPadsIor3 = 38 , kTopEarlgreyMuxedPadsIor4 = 39 , kTopEarlgreyMuxedPadsIor5 = 40 , kTopEarlgreyMuxedPadsIor6 = 41 , kTopEarlgreyMuxedPadsIor7 = 42 , kTopEarlgreyMuxedPadsIor10 = 43 , kTopEarlgreyMuxedPadsIor11 = 44 , kTopEarlgreyMuxedPadsIor12 = 45 , kTopEarlgreyMuxedPadsIor13 = 46 , kTopEarlgreyMuxedPadsLast = 46 }
	Muxed Pad Selects.

enum	top_earlgrey_power_manager_wake_ups { kTopEarlgreyPowerManagerWakeUpsSysrstCtrlAonWkupReq = 0 , kTopEarlgreyPowerManagerWakeUpsAdcCtrlAonWkupReq = 1 , kTopEarlgreyPowerManagerWakeUpsPinmuxAonPinWkupReq = 2 , kTopEarlgreyPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3 , kTopEarlgreyPowerManagerWakeUpsAonTimerAonWkupReq = 4 , kTopEarlgreyPowerManagerWakeUpsSensorCtrlAonWkupReq = 5 , kTopEarlgreyPowerManagerWakeUpsLast = 5 }
	Power Manager Wakeup Signals.

enum	top_earlgrey_reset_manager_sw_resets { kTopEarlgreyResetManagerSwResetsSpiDevice = 0 , kTopEarlgreyResetManagerSwResetsSpiHost0 = 1 , kTopEarlgreyResetManagerSwResetsSpiHost1 = 2 , kTopEarlgreyResetManagerSwResetsUsb = 3 , kTopEarlgreyResetManagerSwResetsUsbAon = 4 , kTopEarlgreyResetManagerSwResetsI2c0 = 5 , kTopEarlgreyResetManagerSwResetsI2c1 = 6 , kTopEarlgreyResetManagerSwResetsI2c2 = 7 , kTopEarlgreyResetManagerSwResetsLast = 7 }
	Reset Manager Software Controlled Resets.

enum	top_earlgrey_power_manager_reset_requests { kTopEarlgreyPowerManagerResetRequestsSysrstCtrlAonRstReq = 0 , kTopEarlgreyPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1 , kTopEarlgreyPowerManagerResetRequestsLast = 1 }
	Power Manager Reset Request Signals.

enum	top_earlgrey_gateable_clocks { kTopEarlgreyGateableClocksIoDiv4Peri = 0 , kTopEarlgreyGateableClocksIoDiv2Peri = 1 , kTopEarlgreyGateableClocksIoPeri = 2 , kTopEarlgreyGateableClocksUsbPeri = 3 , kTopEarlgreyGateableClocksLast = 3 }
	Clock Manager Software-Controlled ("Gated") Clocks. More...

enum	top_earlgrey_hintable_clocks { kTopEarlgreyHintableClocksMainAes = 0 , kTopEarlgreyHintableClocksMainHmac = 1 , kTopEarlgreyHintableClocksMainKmac = 2 , kTopEarlgreyHintableClocksMainOtbn = 3 , kTopEarlgreyHintableClocksLast = 3 }
	Clock Manager Software-Hinted Clocks. More...

Variables
const top_earlgrey_plic_peripheral_t	top_earlgrey_plic_interrupt_for_peripheral [186]
	PLIC Interrupt Source to Peripheral Map. More...

const top_earlgrey_alert_peripheral_t	top_earlgrey_alert_for_peripheral [65]
	Alert Handler Alert Source to Peripheral Map. More...

Detailed Description

Top-specific Definitions.

This file contains preprocessor and type definitions for use within the device C/C++ codebase.

These definitions are for information that depends on the top-specific chip configuration, which includes:

Device Memory Information (for Peripherals and Memory)
PLIC Interrupt ID Names and Source Mappings
Alert ID Names and Source Mappings
Pinmux Pin/Select Names
Power Manager Wakeups

Definition in file top_earlgrey.h.

Macro Definition Documentation

◆ TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR

#define TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR 0x40440000u

Peripheral base address for adc_ctrl_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 453 of file top_earlgrey.h.

◆ TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES

#define TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES 0x80u

Peripheral size for adc_ctrl_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR and TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR + TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES.

Definition at line 463 of file top_earlgrey.h.

◆ TOP_EARLGREY_AES_BASE_ADDR

#define TOP_EARLGREY_AES_BASE_ADDR 0x41100000u

Peripheral base address for aes in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 723 of file top_earlgrey.h.

◆ TOP_EARLGREY_AES_SIZE_BYTES

#define TOP_EARLGREY_AES_SIZE_BYTES 0x100u

Peripheral size for aes in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_AES_BASE_ADDR and TOP_EARLGREY_AES_BASE_ADDR + TOP_EARLGREY_AES_SIZE_BYTES.

Definition at line 733 of file top_earlgrey.h.

◆ TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR

#define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x40150000u

Peripheral base address for alert_handler in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 309 of file top_earlgrey.h.

◆ TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES

#define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x800u

Peripheral size for alert_handler in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR and TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR + TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES.

Definition at line 319 of file top_earlgrey.h.

◆ TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR

#define TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR 0x40470000u

Peripheral base address for aon_timer_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 507 of file top_earlgrey.h.

◆ TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES

#define TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES 0x40u

Peripheral size for aon_timer_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR and TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR + TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES.

Definition at line 517 of file top_earlgrey.h.

◆ TOP_EARLGREY_AST_BASE_ADDR

#define TOP_EARLGREY_AST_BASE_ADDR 0x40480000u

Peripheral base address for ast in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 525 of file top_earlgrey.h.

◆ TOP_EARLGREY_AST_SIZE_BYTES

#define TOP_EARLGREY_AST_SIZE_BYTES 0x400u

Peripheral size for ast in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_AST_BASE_ADDR and TOP_EARLGREY_AST_BASE_ADDR + TOP_EARLGREY_AST_SIZE_BYTES.

Definition at line 535 of file top_earlgrey.h.

◆ TOP_EARLGREY_CLKMGR_AON_BASE_ADDR

#define TOP_EARLGREY_CLKMGR_AON_BASE_ADDR 0x40420000u

Peripheral base address for clkmgr_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 417 of file top_earlgrey.h.

◆ TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES

#define TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES 0x80u

Peripheral size for clkmgr_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_CLKMGR_AON_BASE_ADDR and TOP_EARLGREY_CLKMGR_AON_BASE_ADDR + TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES.

Definition at line 427 of file top_earlgrey.h.

◆ TOP_EARLGREY_CSRNG_BASE_ADDR

#define TOP_EARLGREY_CSRNG_BASE_ADDR 0x41150000u

Peripheral base address for csrng in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 813 of file top_earlgrey.h.

◆ TOP_EARLGREY_CSRNG_SIZE_BYTES

#define TOP_EARLGREY_CSRNG_SIZE_BYTES 0x80u

Peripheral size for csrng in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_CSRNG_BASE_ADDR and TOP_EARLGREY_CSRNG_BASE_ADDR + TOP_EARLGREY_CSRNG_SIZE_BYTES.

Definition at line 823 of file top_earlgrey.h.

◆ TOP_EARLGREY_EDN0_BASE_ADDR

#define TOP_EARLGREY_EDN0_BASE_ADDR 0x41170000u

Peripheral base address for edn0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 849 of file top_earlgrey.h.

◆ TOP_EARLGREY_EDN0_SIZE_BYTES

#define TOP_EARLGREY_EDN0_SIZE_BYTES 0x80u

Peripheral size for edn0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_EDN0_BASE_ADDR and TOP_EARLGREY_EDN0_BASE_ADDR + TOP_EARLGREY_EDN0_SIZE_BYTES.

Definition at line 859 of file top_earlgrey.h.

◆ TOP_EARLGREY_EDN1_BASE_ADDR

#define TOP_EARLGREY_EDN1_BASE_ADDR 0x41180000u

Peripheral base address for edn1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 867 of file top_earlgrey.h.

◆ TOP_EARLGREY_EDN1_SIZE_BYTES

#define TOP_EARLGREY_EDN1_SIZE_BYTES 0x80u

Peripheral size for edn1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_EDN1_BASE_ADDR and TOP_EARLGREY_EDN1_BASE_ADDR + TOP_EARLGREY_EDN1_SIZE_BYTES.

Definition at line 877 of file top_earlgrey.h.

◆ TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR

#define TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR 0x41160000u

Peripheral base address for entropy_src in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 831 of file top_earlgrey.h.

◆ TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES

#define TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES 0x100u

Peripheral size for entropy_src in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR and TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR + TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES.

Definition at line 841 of file top_earlgrey.h.

◆ TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR

#define TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u

Peripheral base address for core device on flash_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 597 of file top_earlgrey.h.

◆ TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES

#define TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200u

Peripheral size for core device on flash_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR and TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES.

Definition at line 607 of file top_earlgrey.h.

◆ TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR

#define TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u

Peripheral base address for mem device on flash_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 633 of file top_earlgrey.h.

◆ TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES

#define TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u

Peripheral size for mem device on flash_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR and TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES.

Definition at line 643 of file top_earlgrey.h.

◆ TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR

#define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u

Peripheral base address for prim device on flash_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 615 of file top_earlgrey.h.

◆ TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES

#define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u

Peripheral size for prim device on flash_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR and TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES.

Definition at line 625 of file top_earlgrey.h.

◆ TOP_EARLGREY_GPIO_BASE_ADDR

#define TOP_EARLGREY_GPIO_BASE_ADDR 0x40040000u

Peripheral base address for gpio in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 111 of file top_earlgrey.h.

◆ TOP_EARLGREY_GPIO_SIZE_BYTES

#define TOP_EARLGREY_GPIO_SIZE_BYTES 0x80u

Peripheral size for gpio in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_GPIO_BASE_ADDR and TOP_EARLGREY_GPIO_BASE_ADDR + TOP_EARLGREY_GPIO_SIZE_BYTES.

Definition at line 121 of file top_earlgrey.h.

◆ TOP_EARLGREY_HMAC_BASE_ADDR

#define TOP_EARLGREY_HMAC_BASE_ADDR 0x41110000u

Peripheral base address for hmac in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 741 of file top_earlgrey.h.

◆ TOP_EARLGREY_HMAC_SIZE_BYTES

#define TOP_EARLGREY_HMAC_SIZE_BYTES 0x2000u

Peripheral size for hmac in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_HMAC_BASE_ADDR and TOP_EARLGREY_HMAC_BASE_ADDR + TOP_EARLGREY_HMAC_SIZE_BYTES.

Definition at line 751 of file top_earlgrey.h.

◆ TOP_EARLGREY_I2C0_BASE_ADDR

#define TOP_EARLGREY_I2C0_BASE_ADDR 0x40080000u

Peripheral base address for i2c0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 147 of file top_earlgrey.h.

◆ TOP_EARLGREY_I2C0_SIZE_BYTES

#define TOP_EARLGREY_I2C0_SIZE_BYTES 0x80u

Peripheral size for i2c0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_I2C0_BASE_ADDR and TOP_EARLGREY_I2C0_BASE_ADDR + TOP_EARLGREY_I2C0_SIZE_BYTES.

Definition at line 157 of file top_earlgrey.h.

◆ TOP_EARLGREY_I2C1_BASE_ADDR

#define TOP_EARLGREY_I2C1_BASE_ADDR 0x40090000u

Peripheral base address for i2c1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 165 of file top_earlgrey.h.

◆ TOP_EARLGREY_I2C1_SIZE_BYTES

#define TOP_EARLGREY_I2C1_SIZE_BYTES 0x80u

Peripheral size for i2c1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_I2C1_BASE_ADDR and TOP_EARLGREY_I2C1_BASE_ADDR + TOP_EARLGREY_I2C1_SIZE_BYTES.

Definition at line 175 of file top_earlgrey.h.

◆ TOP_EARLGREY_I2C2_BASE_ADDR

#define TOP_EARLGREY_I2C2_BASE_ADDR 0x400A0000u

Peripheral base address for i2c2 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 183 of file top_earlgrey.h.

◆ TOP_EARLGREY_I2C2_SIZE_BYTES

#define TOP_EARLGREY_I2C2_SIZE_BYTES 0x80u

Peripheral size for i2c2 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_I2C2_BASE_ADDR and TOP_EARLGREY_I2C2_BASE_ADDR + TOP_EARLGREY_I2C2_SIZE_BYTES.

Definition at line 193 of file top_earlgrey.h.

◆ TOP_EARLGREY_KEYMGR_BASE_ADDR

#define TOP_EARLGREY_KEYMGR_BASE_ADDR 0x41140000u

Peripheral base address for keymgr in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 795 of file top_earlgrey.h.

◆ TOP_EARLGREY_KEYMGR_SIZE_BYTES

#define TOP_EARLGREY_KEYMGR_SIZE_BYTES 0x100u

Peripheral size for keymgr in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_KEYMGR_BASE_ADDR and TOP_EARLGREY_KEYMGR_BASE_ADDR + TOP_EARLGREY_KEYMGR_SIZE_BYTES.

Definition at line 805 of file top_earlgrey.h.

◆ TOP_EARLGREY_KMAC_BASE_ADDR

#define TOP_EARLGREY_KMAC_BASE_ADDR 0x41120000u

Peripheral base address for kmac in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 759 of file top_earlgrey.h.

◆ TOP_EARLGREY_KMAC_SIZE_BYTES

#define TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000u

Peripheral size for kmac in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_KMAC_BASE_ADDR and TOP_EARLGREY_KMAC_BASE_ADDR + TOP_EARLGREY_KMAC_SIZE_BYTES.

Definition at line 769 of file top_earlgrey.h.

◆ TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR

#define TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR 0x0u

Peripheral base address for dmi device on lc_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 291 of file top_earlgrey.h.

◆ TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES

#define TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES 0x1000u

Peripheral size for dmi device on lc_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR and TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR + TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES.

Definition at line 301 of file top_earlgrey.h.

◆ TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR

#define TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR 0x40140000u

Peripheral base address for regs device on lc_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 273 of file top_earlgrey.h.

◆ TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES

#define TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES 0x100u

Peripheral size for regs device on lc_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR and TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES.

Definition at line 283 of file top_earlgrey.h.

◆ TOP_EARLGREY_MMIO_BASE_ADDR

#define TOP_EARLGREY_MMIO_BASE_ADDR 0x40000000u

MMIO Region.

MMIO region excludes any memory that is separate from the module configuration space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM, spi_device memory, or usbdev memory are included.

Definition at line 1819 of file top_earlgrey.h.

◆ TOP_EARLGREY_OTBN_BASE_ADDR

#define TOP_EARLGREY_OTBN_BASE_ADDR 0x41130000u

Peripheral base address for otbn in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 777 of file top_earlgrey.h.

◆ TOP_EARLGREY_OTBN_SIZE_BYTES

#define TOP_EARLGREY_OTBN_SIZE_BYTES 0x10000u

Peripheral size for otbn in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_OTBN_BASE_ADDR and TOP_EARLGREY_OTBN_BASE_ADDR + TOP_EARLGREY_OTBN_SIZE_BYTES.

Definition at line 787 of file top_earlgrey.h.

◆ TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR

#define TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR 0x40130000u

Peripheral base address for core device on otp_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 237 of file top_earlgrey.h.

◆ TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES

#define TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES 0x1000u

Peripheral size for core device on otp_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR and TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES.

Definition at line 247 of file top_earlgrey.h.

◆ TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR

#define TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR 0x40138000u

Peripheral base address for prim device on otp_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 255 of file top_earlgrey.h.

◆ TOP_EARLGREY_OTP_CTRL_PRIM_SIZE_BYTES

#define TOP_EARLGREY_OTP_CTRL_PRIM_SIZE_BYTES 0x20u

Peripheral size for prim device on otp_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR and TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_PRIM_SIZE_BYTES.

Definition at line 265 of file top_earlgrey.h.

◆ TOP_EARLGREY_PATTGEN_BASE_ADDR

#define TOP_EARLGREY_PATTGEN_BASE_ADDR 0x400E0000u

Peripheral base address for pattgen in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 201 of file top_earlgrey.h.

◆ TOP_EARLGREY_PATTGEN_SIZE_BYTES

#define TOP_EARLGREY_PATTGEN_SIZE_BYTES 0x40u

Peripheral size for pattgen in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_PATTGEN_BASE_ADDR and TOP_EARLGREY_PATTGEN_BASE_ADDR + TOP_EARLGREY_PATTGEN_SIZE_BYTES.

Definition at line 211 of file top_earlgrey.h.

◆ TOP_EARLGREY_PINMUX_AON_BASE_ADDR

#define TOP_EARLGREY_PINMUX_AON_BASE_ADDR 0x40460000u

Peripheral base address for pinmux_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 489 of file top_earlgrey.h.

◆ TOP_EARLGREY_PINMUX_AON_SIZE_BYTES

#define TOP_EARLGREY_PINMUX_AON_SIZE_BYTES 0x1000u

Peripheral size for pinmux_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_PINMUX_AON_BASE_ADDR and TOP_EARLGREY_PINMUX_AON_BASE_ADDR + TOP_EARLGREY_PINMUX_AON_SIZE_BYTES.

Definition at line 499 of file top_earlgrey.h.

◆ TOP_EARLGREY_PWM_AON_BASE_ADDR

#define TOP_EARLGREY_PWM_AON_BASE_ADDR 0x40450000u

Peripheral base address for pwm_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 471 of file top_earlgrey.h.

◆ TOP_EARLGREY_PWM_AON_SIZE_BYTES

#define TOP_EARLGREY_PWM_AON_SIZE_BYTES 0x80u

Peripheral size for pwm_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_PWM_AON_BASE_ADDR and TOP_EARLGREY_PWM_AON_BASE_ADDR + TOP_EARLGREY_PWM_AON_SIZE_BYTES.

Definition at line 481 of file top_earlgrey.h.

◆ TOP_EARLGREY_PWRMGR_AON_BASE_ADDR

#define TOP_EARLGREY_PWRMGR_AON_BASE_ADDR 0x40400000u

Peripheral base address for pwrmgr_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 381 of file top_earlgrey.h.

◆ TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES

#define TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES 0x80u

Peripheral size for pwrmgr_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_PWRMGR_AON_BASE_ADDR and TOP_EARLGREY_PWRMGR_AON_BASE_ADDR + TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES.

Definition at line 391 of file top_earlgrey.h.

◆ TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR

#define TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u

Peripheral base address for regs device on rom_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 921 of file top_earlgrey.h.

◆ TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES

#define TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES 0x80u

Peripheral size for regs device on rom_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR and TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES.

Definition at line 931 of file top_earlgrey.h.

◆ TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR

#define TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR 0x8000u

Peripheral base address for rom device on rom_ctrl in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 939 of file top_earlgrey.h.

◆ TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES

#define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x8000u

Peripheral size for rom device on rom_ctrl in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR and TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES.

Definition at line 949 of file top_earlgrey.h.

◆ TOP_EARLGREY_RSTMGR_AON_BASE_ADDR

#define TOP_EARLGREY_RSTMGR_AON_BASE_ADDR 0x40410000u

Peripheral base address for rstmgr_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 399 of file top_earlgrey.h.

◆ TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES

#define TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES 0x80u

Peripheral size for rstmgr_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RSTMGR_AON_BASE_ADDR and TOP_EARLGREY_RSTMGR_AON_BASE_ADDR + TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES.

Definition at line 409 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR

#define TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u

Peripheral base address for cfg device on rv_core_ibex in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 957 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES

#define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u

Peripheral size for cfg device on rv_core_ibex in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR and TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES.

Definition at line 967 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_DM_DBG_BASE_ADDR

#define TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000u

Peripheral base address for dbg device on rv_dm in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 687 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES

#define TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200u

Peripheral size for dbg device on rv_dm in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_DM_DBG_BASE_ADDR and TOP_EARLGREY_RV_DM_DBG_BASE_ADDR + TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES.

Definition at line 697 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_DM_MEM_BASE_ADDR

#define TOP_EARLGREY_RV_DM_MEM_BASE_ADDR 0x10000u

Peripheral base address for mem device on rv_dm in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 669 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES

#define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000u

Peripheral size for mem device on rv_dm in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_DM_MEM_BASE_ADDR and TOP_EARLGREY_RV_DM_MEM_BASE_ADDR + TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES.

Definition at line 679 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_DM_REGS_BASE_ADDR

#define TOP_EARLGREY_RV_DM_REGS_BASE_ADDR 0x41200000u

Peripheral base address for regs device on rv_dm in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 651 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES

#define TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES 0x10u

Peripheral size for regs device on rv_dm in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_DM_REGS_BASE_ADDR and TOP_EARLGREY_RV_DM_REGS_BASE_ADDR + TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES.

Definition at line 661 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_PLIC_BASE_ADDR

#define TOP_EARLGREY_RV_PLIC_BASE_ADDR 0x48000000u

Peripheral base address for rv_plic in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 705 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_PLIC_SIZE_BYTES

#define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x8000000u

Peripheral size for rv_plic in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_PLIC_BASE_ADDR and TOP_EARLGREY_RV_PLIC_BASE_ADDR + TOP_EARLGREY_RV_PLIC_SIZE_BYTES.

Definition at line 715 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_TIMER_BASE_ADDR

#define TOP_EARLGREY_RV_TIMER_BASE_ADDR 0x40100000u

Peripheral base address for rv_timer in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 219 of file top_earlgrey.h.

◆ TOP_EARLGREY_RV_TIMER_SIZE_BYTES

#define TOP_EARLGREY_RV_TIMER_SIZE_BYTES 0x200u

Peripheral size for rv_timer in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_RV_TIMER_BASE_ADDR and TOP_EARLGREY_RV_TIMER_BASE_ADDR + TOP_EARLGREY_RV_TIMER_SIZE_BYTES.

Definition at line 229 of file top_earlgrey.h.

◆ TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR

#define TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR 0x40490000u

Peripheral base address for sensor_ctrl_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 543 of file top_earlgrey.h.

◆ TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES

#define TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES 0x80u

Peripheral size for sensor_ctrl_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR and TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES.

Definition at line 553 of file top_earlgrey.h.

◆ TOP_EARLGREY_SPI_DEVICE_BASE_ADDR

#define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40050000u

Peripheral base address for spi_device in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 129 of file top_earlgrey.h.

◆ TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES

#define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x2000u

Peripheral size for spi_device in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SPI_DEVICE_BASE_ADDR and TOP_EARLGREY_SPI_DEVICE_BASE_ADDR + TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES.

Definition at line 139 of file top_earlgrey.h.

◆ TOP_EARLGREY_SPI_HOST0_BASE_ADDR

#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40300000u

Peripheral base address for spi_host0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 327 of file top_earlgrey.h.

◆ TOP_EARLGREY_SPI_HOST0_SIZE_BYTES

#define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x40u

Peripheral size for spi_host0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SPI_HOST0_BASE_ADDR and TOP_EARLGREY_SPI_HOST0_BASE_ADDR + TOP_EARLGREY_SPI_HOST0_SIZE_BYTES.

Definition at line 337 of file top_earlgrey.h.

◆ TOP_EARLGREY_SPI_HOST1_BASE_ADDR

#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40310000u

Peripheral base address for spi_host1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 345 of file top_earlgrey.h.

◆ TOP_EARLGREY_SPI_HOST1_SIZE_BYTES

#define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x40u

Peripheral size for spi_host1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SPI_HOST1_BASE_ADDR and TOP_EARLGREY_SPI_HOST1_BASE_ADDR + TOP_EARLGREY_SPI_HOST1_SIZE_BYTES.

Definition at line 355 of file top_earlgrey.h.

◆ TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u

Peripheral base address for ram device on sram_ctrl_main in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 903 of file top_earlgrey.h.

◆ TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u

Peripheral size for ram device on sram_ctrl_main in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR and TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES.

Definition at line 913 of file top_earlgrey.h.

◆ TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u

Peripheral base address for regs device on sram_ctrl_main in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 885 of file top_earlgrey.h.

◆ TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u

Peripheral size for regs device on sram_ctrl_main in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR and TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES.

Definition at line 895 of file top_earlgrey.h.

◆ TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u

Peripheral base address for ram device on sram_ctrl_ret_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 579 of file top_earlgrey.h.

◆ TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u

Peripheral size for ram device on sram_ctrl_ret_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES.

Definition at line 589 of file top_earlgrey.h.

◆ TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR

#define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u

Peripheral base address for regs device on sram_ctrl_ret_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 561 of file top_earlgrey.h.

◆ TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES

#define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u

Peripheral size for regs device on sram_ctrl_ret_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES.

Definition at line 571 of file top_earlgrey.h.

◆ TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR

#define TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u

Peripheral base address for sysrst_ctrl_aon in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 435 of file top_earlgrey.h.

◆ TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES

#define TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES 0x100u

Peripheral size for sysrst_ctrl_aon in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR and TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR + TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES.

Definition at line 445 of file top_earlgrey.h.

◆ TOP_EARLGREY_UART0_BASE_ADDR

#define TOP_EARLGREY_UART0_BASE_ADDR 0x40000000u

Peripheral base address for uart0 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 39 of file top_earlgrey.h.

◆ TOP_EARLGREY_UART0_SIZE_BYTES

#define TOP_EARLGREY_UART0_SIZE_BYTES 0x40u

Peripheral size for uart0 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_UART0_BASE_ADDR and TOP_EARLGREY_UART0_BASE_ADDR + TOP_EARLGREY_UART0_SIZE_BYTES.

Definition at line 49 of file top_earlgrey.h.

◆ TOP_EARLGREY_UART1_BASE_ADDR

#define TOP_EARLGREY_UART1_BASE_ADDR 0x40010000u

Peripheral base address for uart1 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 57 of file top_earlgrey.h.

◆ TOP_EARLGREY_UART1_SIZE_BYTES

#define TOP_EARLGREY_UART1_SIZE_BYTES 0x40u

Peripheral size for uart1 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_UART1_BASE_ADDR and TOP_EARLGREY_UART1_BASE_ADDR + TOP_EARLGREY_UART1_SIZE_BYTES.

Definition at line 67 of file top_earlgrey.h.

◆ TOP_EARLGREY_UART2_BASE_ADDR

#define TOP_EARLGREY_UART2_BASE_ADDR 0x40020000u

Peripheral base address for uart2 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 75 of file top_earlgrey.h.

◆ TOP_EARLGREY_UART2_SIZE_BYTES

#define TOP_EARLGREY_UART2_SIZE_BYTES 0x40u

Peripheral size for uart2 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_UART2_BASE_ADDR and TOP_EARLGREY_UART2_BASE_ADDR + TOP_EARLGREY_UART2_SIZE_BYTES.

Definition at line 85 of file top_earlgrey.h.

◆ TOP_EARLGREY_UART3_BASE_ADDR

#define TOP_EARLGREY_UART3_BASE_ADDR 0x40030000u

Peripheral base address for uart3 in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 93 of file top_earlgrey.h.

◆ TOP_EARLGREY_UART3_SIZE_BYTES

#define TOP_EARLGREY_UART3_SIZE_BYTES 0x40u

Peripheral size for uart3 in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_UART3_BASE_ADDR and TOP_EARLGREY_UART3_BASE_ADDR + TOP_EARLGREY_UART3_SIZE_BYTES.

Definition at line 103 of file top_earlgrey.h.

◆ TOP_EARLGREY_USBDEV_BASE_ADDR

#define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40320000u

Peripheral base address for usbdev in top earlgrey.

This should be used with mmio_region_from_addr to access the memory-mapped registers associated with the peripheral (usually via a DIF).

Definition at line 363 of file top_earlgrey.h.

◆ TOP_EARLGREY_USBDEV_SIZE_BYTES

#define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000u

Peripheral size for usbdev in top earlgrey.

This is the size (in bytes) of the peripheral's reserved memory area. All memory-mapped registers associated with this peripheral should have an address between TOP_EARLGREY_USBDEV_BASE_ADDR and TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES.

Definition at line 373 of file top_earlgrey.h.

Typedef Documentation

◆ top_earlgrey_alert_id_t

typedef enum top_earlgrey_alert_id top_earlgrey_alert_id_t

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

◆ top_earlgrey_alert_peripheral_t

typedef enum top_earlgrey_alert_peripheral top_earlgrey_alert_peripheral_t

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

◆ top_earlgrey_gateable_clocks_t

typedef enum top_earlgrey_gateable_clocks top_earlgrey_gateable_clocks_t

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

◆ top_earlgrey_hintable_clocks_t

typedef enum top_earlgrey_hintable_clocks top_earlgrey_hintable_clocks_t

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

◆ top_earlgrey_plic_irq_id_t

typedef enum top_earlgrey_plic_irq_id top_earlgrey_plic_irq_id_t

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

◆ top_earlgrey_plic_peripheral_t

typedef enum top_earlgrey_plic_peripheral top_earlgrey_plic_peripheral_t

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

◆ top_earlgrey_plic_target_t

typedef enum top_earlgrey_plic_target top_earlgrey_plic_target_t

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumeration Type Documentation

◆ top_earlgrey_alert_id

enum top_earlgrey_alert_id

Alert Handler Alert Source.

Enumeration of all Alert Handler Alert Sources. The alert sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopEarlgreyAlertIdUart0FatalFault	uart0_fatal_fault
kTopEarlgreyAlertIdUart1FatalFault	uart1_fatal_fault
kTopEarlgreyAlertIdUart2FatalFault	uart2_fatal_fault
kTopEarlgreyAlertIdUart3FatalFault	uart3_fatal_fault
kTopEarlgreyAlertIdGpioFatalFault	gpio_fatal_fault
kTopEarlgreyAlertIdSpiDeviceFatalFault	spi_device_fatal_fault
kTopEarlgreyAlertIdI2c0FatalFault	i2c0_fatal_fault
kTopEarlgreyAlertIdI2c1FatalFault	i2c1_fatal_fault
kTopEarlgreyAlertIdI2c2FatalFault	i2c2_fatal_fault
kTopEarlgreyAlertIdPattgenFatalFault	pattgen_fatal_fault
kTopEarlgreyAlertIdRvTimerFatalFault	rv_timer_fatal_fault
kTopEarlgreyAlertIdOtpCtrlFatalMacroError	otp_ctrl_fatal_macro_error
kTopEarlgreyAlertIdOtpCtrlFatalCheckError	otp_ctrl_fatal_check_error
kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError	otp_ctrl_fatal_bus_integ_error
kTopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert	otp_ctrl_fatal_prim_otp_alert
kTopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert	otp_ctrl_recov_prim_otp_alert
kTopEarlgreyAlertIdLcCtrlFatalProgError	lc_ctrl_fatal_prog_error
kTopEarlgreyAlertIdLcCtrlFatalStateError	lc_ctrl_fatal_state_error
kTopEarlgreyAlertIdLcCtrlFatalBusIntegError	lc_ctrl_fatal_bus_integ_error
kTopEarlgreyAlertIdSpiHost0FatalFault	spi_host0_fatal_fault
kTopEarlgreyAlertIdSpiHost1FatalFault	spi_host1_fatal_fault
kTopEarlgreyAlertIdUsbdevFatalFault	usbdev_fatal_fault
kTopEarlgreyAlertIdPwrmgrAonFatalFault	pwrmgr_aon_fatal_fault
kTopEarlgreyAlertIdRstmgrAonFatalFault	rstmgr_aon_fatal_fault
kTopEarlgreyAlertIdRstmgrAonFatalCnstyFault	rstmgr_aon_fatal_cnsty_fault
kTopEarlgreyAlertIdClkmgrAonRecovFault	clkmgr_aon_recov_fault
kTopEarlgreyAlertIdClkmgrAonFatalFault	clkmgr_aon_fatal_fault
kTopEarlgreyAlertIdSysrstCtrlAonFatalFault	sysrst_ctrl_aon_fatal_fault
kTopEarlgreyAlertIdAdcCtrlAonFatalFault	adc_ctrl_aon_fatal_fault
kTopEarlgreyAlertIdPwmAonFatalFault	pwm_aon_fatal_fault
kTopEarlgreyAlertIdPinmuxAonFatalFault	pinmux_aon_fatal_fault
kTopEarlgreyAlertIdAonTimerAonFatalFault	aon_timer_aon_fatal_fault
kTopEarlgreyAlertIdSensorCtrlAonRecovAlert	sensor_ctrl_aon_recov_alert
kTopEarlgreyAlertIdSensorCtrlAonFatalAlert	sensor_ctrl_aon_fatal_alert
kTopEarlgreyAlertIdSramCtrlRetAonFatalError	sram_ctrl_ret_aon_fatal_error
kTopEarlgreyAlertIdFlashCtrlRecovErr	flash_ctrl_recov_err
kTopEarlgreyAlertIdFlashCtrlFatalStdErr	flash_ctrl_fatal_std_err
kTopEarlgreyAlertIdFlashCtrlFatalErr	flash_ctrl_fatal_err
kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert	flash_ctrl_fatal_prim_flash_alert
kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert	flash_ctrl_recov_prim_flash_alert
kTopEarlgreyAlertIdRvDmFatalFault	rv_dm_fatal_fault
kTopEarlgreyAlertIdRvPlicFatalFault	rv_plic_fatal_fault
kTopEarlgreyAlertIdAesRecovCtrlUpdateErr	aes_recov_ctrl_update_err
kTopEarlgreyAlertIdAesFatalFault	aes_fatal_fault
kTopEarlgreyAlertIdHmacFatalFault	hmac_fatal_fault
kTopEarlgreyAlertIdKmacRecovOperationErr	kmac_recov_operation_err
kTopEarlgreyAlertIdKmacFatalFaultErr	kmac_fatal_fault_err
kTopEarlgreyAlertIdOtbnFatal	otbn_fatal
kTopEarlgreyAlertIdOtbnRecov	otbn_recov
kTopEarlgreyAlertIdKeymgrRecovOperationErr	keymgr_recov_operation_err
kTopEarlgreyAlertIdKeymgrFatalFaultErr	keymgr_fatal_fault_err
kTopEarlgreyAlertIdCsrngRecovAlert	csrng_recov_alert
kTopEarlgreyAlertIdCsrngFatalAlert	csrng_fatal_alert
kTopEarlgreyAlertIdEntropySrcRecovAlert	entropy_src_recov_alert
kTopEarlgreyAlertIdEntropySrcFatalAlert	entropy_src_fatal_alert
kTopEarlgreyAlertIdEdn0RecovAlert	edn0_recov_alert
kTopEarlgreyAlertIdEdn0FatalAlert	edn0_fatal_alert
kTopEarlgreyAlertIdEdn1RecovAlert	edn1_recov_alert
kTopEarlgreyAlertIdEdn1FatalAlert	edn1_fatal_alert
kTopEarlgreyAlertIdSramCtrlMainFatalError	sram_ctrl_main_fatal_error
kTopEarlgreyAlertIdRomCtrlFatal	rom_ctrl_fatal
kTopEarlgreyAlertIdRvCoreIbexFatalSwErr	rv_core_ibex_fatal_sw_err
kTopEarlgreyAlertIdRvCoreIbexRecovSwErr	rv_core_ibex_recov_sw_err
kTopEarlgreyAlertIdRvCoreIbexFatalHwErr	rv_core_ibex_fatal_hw_err
kTopEarlgreyAlertIdRvCoreIbexRecovHwErr	rv_core_ibex_recov_hw_err

Definition at line 1325 of file top_earlgrey.h.

◆ top_earlgrey_alert_peripheral

enum top_earlgrey_alert_peripheral

Alert Handler Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding alert.

Enumerator
kTopEarlgreyAlertPeripheralUart0	uart0
kTopEarlgreyAlertPeripheralUart1	uart1
kTopEarlgreyAlertPeripheralUart2	uart2
kTopEarlgreyAlertPeripheralUart3	uart3
kTopEarlgreyAlertPeripheralGpio	gpio
kTopEarlgreyAlertPeripheralSpiDevice	spi_device
kTopEarlgreyAlertPeripheralI2c0	i2c0
kTopEarlgreyAlertPeripheralI2c1	i2c1
kTopEarlgreyAlertPeripheralI2c2	i2c2
kTopEarlgreyAlertPeripheralPattgen	pattgen
kTopEarlgreyAlertPeripheralRvTimer	rv_timer
kTopEarlgreyAlertPeripheralOtpCtrl	otp_ctrl
kTopEarlgreyAlertPeripheralLcCtrl	lc_ctrl
kTopEarlgreyAlertPeripheralSpiHost0	spi_host0
kTopEarlgreyAlertPeripheralSpiHost1	spi_host1
kTopEarlgreyAlertPeripheralUsbdev	usbdev
kTopEarlgreyAlertPeripheralPwrmgrAon	pwrmgr_aon
kTopEarlgreyAlertPeripheralRstmgrAon	rstmgr_aon
kTopEarlgreyAlertPeripheralClkmgrAon	clkmgr_aon
kTopEarlgreyAlertPeripheralSysrstCtrlAon	sysrst_ctrl_aon
kTopEarlgreyAlertPeripheralAdcCtrlAon	adc_ctrl_aon
kTopEarlgreyAlertPeripheralPwmAon	pwm_aon
kTopEarlgreyAlertPeripheralPinmuxAon	pinmux_aon
kTopEarlgreyAlertPeripheralAonTimerAon	aon_timer_aon
kTopEarlgreyAlertPeripheralSensorCtrlAon	sensor_ctrl_aon
kTopEarlgreyAlertPeripheralSramCtrlRetAon	sram_ctrl_ret_aon
kTopEarlgreyAlertPeripheralFlashCtrl	flash_ctrl
kTopEarlgreyAlertPeripheralRvDm	rv_dm
kTopEarlgreyAlertPeripheralRvPlic	rv_plic
kTopEarlgreyAlertPeripheralAes	aes
kTopEarlgreyAlertPeripheralHmac	hmac
kTopEarlgreyAlertPeripheralKmac	kmac
kTopEarlgreyAlertPeripheralOtbn	otbn
kTopEarlgreyAlertPeripheralKeymgr	keymgr
kTopEarlgreyAlertPeripheralCsrng	csrng
kTopEarlgreyAlertPeripheralEntropySrc	entropy_src
kTopEarlgreyAlertPeripheralEdn0	edn0
kTopEarlgreyAlertPeripheralEdn1	edn1
kTopEarlgreyAlertPeripheralSramCtrlMain	sram_ctrl_main
kTopEarlgreyAlertPeripheralRomCtrl	rom_ctrl
kTopEarlgreyAlertPeripheralRvCoreIbex	rv_core_ibex

Definition at line 1274 of file top_earlgrey.h.

◆ top_earlgrey_gateable_clocks

enum top_earlgrey_gateable_clocks

Clock Manager Software-Controlled ("Gated") Clocks.

The Software has full control over these clocks.

Enumerator
kTopEarlgreyGateableClocksIoDiv4Peri	Clock clk_io_div4_peri in group peri.
kTopEarlgreyGateableClocksIoDiv2Peri	Clock clk_io_div2_peri in group peri.
kTopEarlgreyGateableClocksIoPeri	Clock clk_io_peri in group peri.
kTopEarlgreyGateableClocksUsbPeri	Clock clk_usb_peri in group peri.

Definition at line 1790 of file top_earlgrey.h.

◆ top_earlgrey_hintable_clocks

enum top_earlgrey_hintable_clocks

Clock Manager Software-Hinted Clocks.

The Software has partial control over these clocks. It can ask them to stop, but the clock manager is in control of whether the clock actually is stopped.

Enumerator
kTopEarlgreyHintableClocksMainAes	Clock clk_main_aes in group trans.
kTopEarlgreyHintableClocksMainHmac	Clock clk_main_hmac in group trans.
kTopEarlgreyHintableClocksMainKmac	Clock clk_main_kmac in group trans.
kTopEarlgreyHintableClocksMainOtbn	Clock clk_main_otbn in group trans.

Definition at line 1804 of file top_earlgrey.h.

◆ top_earlgrey_pinmux_insel

enum top_earlgrey_pinmux_insel

Pinmux MIO Input Selector.

Enumerator
kTopEarlgreyPinmuxInselConstantZero	Tie constantly to zero.
kTopEarlgreyPinmuxInselConstantOne	Tie constantly to one.
kTopEarlgreyPinmuxInselIoa0	MIO Pad 0.
kTopEarlgreyPinmuxInselIoa1	MIO Pad 1.
kTopEarlgreyPinmuxInselIoa2	MIO Pad 2.
kTopEarlgreyPinmuxInselIoa3	MIO Pad 3.
kTopEarlgreyPinmuxInselIoa4	MIO Pad 4.
kTopEarlgreyPinmuxInselIoa5	MIO Pad 5.
kTopEarlgreyPinmuxInselIoa6	MIO Pad 6.
kTopEarlgreyPinmuxInselIoa7	MIO Pad 7.
kTopEarlgreyPinmuxInselIoa8	MIO Pad 8.
kTopEarlgreyPinmuxInselIob0	MIO Pad 9.
kTopEarlgreyPinmuxInselIob1	MIO Pad 10.
kTopEarlgreyPinmuxInselIob2	MIO Pad 11.
kTopEarlgreyPinmuxInselIob3	MIO Pad 12.
kTopEarlgreyPinmuxInselIob4	MIO Pad 13.
kTopEarlgreyPinmuxInselIob5	MIO Pad 14.
kTopEarlgreyPinmuxInselIob6	MIO Pad 15.
kTopEarlgreyPinmuxInselIob7	MIO Pad 16.
kTopEarlgreyPinmuxInselIob8	MIO Pad 17.
kTopEarlgreyPinmuxInselIob9	MIO Pad 18.
kTopEarlgreyPinmuxInselIob10	MIO Pad 19.
kTopEarlgreyPinmuxInselIob11	MIO Pad 20.
kTopEarlgreyPinmuxInselIob12	MIO Pad 21.
kTopEarlgreyPinmuxInselIoc0	MIO Pad 22.
kTopEarlgreyPinmuxInselIoc1	MIO Pad 23.
kTopEarlgreyPinmuxInselIoc2	MIO Pad 24.
kTopEarlgreyPinmuxInselIoc3	MIO Pad 25.
kTopEarlgreyPinmuxInselIoc4	MIO Pad 26.
kTopEarlgreyPinmuxInselIoc5	MIO Pad 27.
kTopEarlgreyPinmuxInselIoc6	MIO Pad 28.
kTopEarlgreyPinmuxInselIoc7	MIO Pad 29.
kTopEarlgreyPinmuxInselIoc8	MIO Pad 30.
kTopEarlgreyPinmuxInselIoc9	MIO Pad 31.
kTopEarlgreyPinmuxInselIoc10	MIO Pad 32.
kTopEarlgreyPinmuxInselIoc11	MIO Pad 33.
kTopEarlgreyPinmuxInselIoc12	MIO Pad 34.
kTopEarlgreyPinmuxInselIor0	MIO Pad 35.
kTopEarlgreyPinmuxInselIor1	MIO Pad 36.
kTopEarlgreyPinmuxInselIor2	MIO Pad 37.
kTopEarlgreyPinmuxInselIor3	MIO Pad 38.
kTopEarlgreyPinmuxInselIor4	MIO Pad 39.
kTopEarlgreyPinmuxInselIor5	MIO Pad 40.
kTopEarlgreyPinmuxInselIor6	MIO Pad 41.
kTopEarlgreyPinmuxInselIor7	MIO Pad 42.
kTopEarlgreyPinmuxInselIor10	MIO Pad 43.
kTopEarlgreyPinmuxInselIor11	MIO Pad 44.
kTopEarlgreyPinmuxInselIor12	MIO Pad 45.
kTopEarlgreyPinmuxInselIor13	MIO Pad 46.

Definition at line 1479 of file top_earlgrey.h.

◆ top_earlgrey_pinmux_mio_out

enum top_earlgrey_pinmux_mio_out

Pinmux MIO Output.

Enumerator
kTopEarlgreyPinmuxMioOutIoa0	MIO Pad 0.
kTopEarlgreyPinmuxMioOutIoa1	MIO Pad 1.
kTopEarlgreyPinmuxMioOutIoa2	MIO Pad 2.
kTopEarlgreyPinmuxMioOutIoa3	MIO Pad 3.
kTopEarlgreyPinmuxMioOutIoa4	MIO Pad 4.
kTopEarlgreyPinmuxMioOutIoa5	MIO Pad 5.
kTopEarlgreyPinmuxMioOutIoa6	MIO Pad 6.
kTopEarlgreyPinmuxMioOutIoa7	MIO Pad 7.
kTopEarlgreyPinmuxMioOutIoa8	MIO Pad 8.
kTopEarlgreyPinmuxMioOutIob0	MIO Pad 9.
kTopEarlgreyPinmuxMioOutIob1	MIO Pad 10.
kTopEarlgreyPinmuxMioOutIob2	MIO Pad 11.
kTopEarlgreyPinmuxMioOutIob3	MIO Pad 12.
kTopEarlgreyPinmuxMioOutIob4	MIO Pad 13.
kTopEarlgreyPinmuxMioOutIob5	MIO Pad 14.
kTopEarlgreyPinmuxMioOutIob6	MIO Pad 15.
kTopEarlgreyPinmuxMioOutIob7	MIO Pad 16.
kTopEarlgreyPinmuxMioOutIob8	MIO Pad 17.
kTopEarlgreyPinmuxMioOutIob9	MIO Pad 18.
kTopEarlgreyPinmuxMioOutIob10	MIO Pad 19.
kTopEarlgreyPinmuxMioOutIob11	MIO Pad 20.
kTopEarlgreyPinmuxMioOutIob12	MIO Pad 21.
kTopEarlgreyPinmuxMioOutIoc0	MIO Pad 22.
kTopEarlgreyPinmuxMioOutIoc1	MIO Pad 23.
kTopEarlgreyPinmuxMioOutIoc2	MIO Pad 24.
kTopEarlgreyPinmuxMioOutIoc3	MIO Pad 25.
kTopEarlgreyPinmuxMioOutIoc4	MIO Pad 26.
kTopEarlgreyPinmuxMioOutIoc5	MIO Pad 27.
kTopEarlgreyPinmuxMioOutIoc6	MIO Pad 28.
kTopEarlgreyPinmuxMioOutIoc7	MIO Pad 29.
kTopEarlgreyPinmuxMioOutIoc8	MIO Pad 30.
kTopEarlgreyPinmuxMioOutIoc9	MIO Pad 31.
kTopEarlgreyPinmuxMioOutIoc10	MIO Pad 32.
kTopEarlgreyPinmuxMioOutIoc11	MIO Pad 33.
kTopEarlgreyPinmuxMioOutIoc12	MIO Pad 34.
kTopEarlgreyPinmuxMioOutIor0	MIO Pad 35.
kTopEarlgreyPinmuxMioOutIor1	MIO Pad 36.
kTopEarlgreyPinmuxMioOutIor2	MIO Pad 37.
kTopEarlgreyPinmuxMioOutIor3	MIO Pad 38.
kTopEarlgreyPinmuxMioOutIor4	MIO Pad 39.
kTopEarlgreyPinmuxMioOutIor5	MIO Pad 40.
kTopEarlgreyPinmuxMioOutIor6	MIO Pad 41.
kTopEarlgreyPinmuxMioOutIor7	MIO Pad 42.
kTopEarlgreyPinmuxMioOutIor10	MIO Pad 43.
kTopEarlgreyPinmuxMioOutIor11	MIO Pad 44.
kTopEarlgreyPinmuxMioOutIor12	MIO Pad 45.
kTopEarlgreyPinmuxMioOutIor13	MIO Pad 46.

Definition at line 1535 of file top_earlgrey.h.

◆ top_earlgrey_pinmux_outsel

enum top_earlgrey_pinmux_outsel

Pinmux Peripheral Output Selector.

Enumerator
kTopEarlgreyPinmuxOutselConstantZero	Tie constantly to zero.
kTopEarlgreyPinmuxOutselConstantOne	Tie constantly to one.
kTopEarlgreyPinmuxOutselConstantHighZ	Tie constantly to high-Z.
kTopEarlgreyPinmuxOutselGpioGpio0	Peripheral Output 0.
kTopEarlgreyPinmuxOutselGpioGpio1	Peripheral Output 1.
kTopEarlgreyPinmuxOutselGpioGpio2	Peripheral Output 2.
kTopEarlgreyPinmuxOutselGpioGpio3	Peripheral Output 3.
kTopEarlgreyPinmuxOutselGpioGpio4	Peripheral Output 4.
kTopEarlgreyPinmuxOutselGpioGpio5	Peripheral Output 5.
kTopEarlgreyPinmuxOutselGpioGpio6	Peripheral Output 6.
kTopEarlgreyPinmuxOutselGpioGpio7	Peripheral Output 7.
kTopEarlgreyPinmuxOutselGpioGpio8	Peripheral Output 8.
kTopEarlgreyPinmuxOutselGpioGpio9	Peripheral Output 9.
kTopEarlgreyPinmuxOutselGpioGpio10	Peripheral Output 10.
kTopEarlgreyPinmuxOutselGpioGpio11	Peripheral Output 11.
kTopEarlgreyPinmuxOutselGpioGpio12	Peripheral Output 12.
kTopEarlgreyPinmuxOutselGpioGpio13	Peripheral Output 13.
kTopEarlgreyPinmuxOutselGpioGpio14	Peripheral Output 14.
kTopEarlgreyPinmuxOutselGpioGpio15	Peripheral Output 15.
kTopEarlgreyPinmuxOutselGpioGpio16	Peripheral Output 16.
kTopEarlgreyPinmuxOutselGpioGpio17	Peripheral Output 17.
kTopEarlgreyPinmuxOutselGpioGpio18	Peripheral Output 18.
kTopEarlgreyPinmuxOutselGpioGpio19	Peripheral Output 19.
kTopEarlgreyPinmuxOutselGpioGpio20	Peripheral Output 20.
kTopEarlgreyPinmuxOutselGpioGpio21	Peripheral Output 21.
kTopEarlgreyPinmuxOutselGpioGpio22	Peripheral Output 22.
kTopEarlgreyPinmuxOutselGpioGpio23	Peripheral Output 23.
kTopEarlgreyPinmuxOutselGpioGpio24	Peripheral Output 24.
kTopEarlgreyPinmuxOutselGpioGpio25	Peripheral Output 25.
kTopEarlgreyPinmuxOutselGpioGpio26	Peripheral Output 26.
kTopEarlgreyPinmuxOutselGpioGpio27	Peripheral Output 27.
kTopEarlgreyPinmuxOutselGpioGpio28	Peripheral Output 28.
kTopEarlgreyPinmuxOutselGpioGpio29	Peripheral Output 29.
kTopEarlgreyPinmuxOutselGpioGpio30	Peripheral Output 30.
kTopEarlgreyPinmuxOutselGpioGpio31	Peripheral Output 31.
kTopEarlgreyPinmuxOutselI2c0Sda	Peripheral Output 32.
kTopEarlgreyPinmuxOutselI2c0Scl	Peripheral Output 33.
kTopEarlgreyPinmuxOutselI2c1Sda	Peripheral Output 34.
kTopEarlgreyPinmuxOutselI2c1Scl	Peripheral Output 35.
kTopEarlgreyPinmuxOutselI2c2Sda	Peripheral Output 36.
kTopEarlgreyPinmuxOutselI2c2Scl	Peripheral Output 37.
kTopEarlgreyPinmuxOutselSpiHost1Sd0	Peripheral Output 38.
kTopEarlgreyPinmuxOutselSpiHost1Sd1	Peripheral Output 39.
kTopEarlgreyPinmuxOutselSpiHost1Sd2	Peripheral Output 40.
kTopEarlgreyPinmuxOutselSpiHost1Sd3	Peripheral Output 41.
kTopEarlgreyPinmuxOutselUart0Tx	Peripheral Output 42.
kTopEarlgreyPinmuxOutselUart1Tx	Peripheral Output 43.
kTopEarlgreyPinmuxOutselUart2Tx	Peripheral Output 44.
kTopEarlgreyPinmuxOutselUart3Tx	Peripheral Output 45.
kTopEarlgreyPinmuxOutselPattgenPda0Tx	Peripheral Output 46.
kTopEarlgreyPinmuxOutselPattgenPcl0Tx	Peripheral Output 47.
kTopEarlgreyPinmuxOutselPattgenPda1Tx	Peripheral Output 48.
kTopEarlgreyPinmuxOutselPattgenPcl1Tx	Peripheral Output 49.
kTopEarlgreyPinmuxOutselSpiHost1Sck	Peripheral Output 50.
kTopEarlgreyPinmuxOutselSpiHost1Csb	Peripheral Output 51.
kTopEarlgreyPinmuxOutselFlashCtrlTdo	Peripheral Output 52.
kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0	Peripheral Output 53.
kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1	Peripheral Output 54.
kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2	Peripheral Output 55.
kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut3	Peripheral Output 56.
kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut4	Peripheral Output 57.
kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut5	Peripheral Output 58.
kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut6	Peripheral Output 59.
kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut7	Peripheral Output 60.
kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut8	Peripheral Output 61.
kTopEarlgreyPinmuxOutselPwmAonPwm0	Peripheral Output 62.
kTopEarlgreyPinmuxOutselPwmAonPwm1	Peripheral Output 63.
kTopEarlgreyPinmuxOutselPwmAonPwm2	Peripheral Output 64.
kTopEarlgreyPinmuxOutselPwmAonPwm3	Peripheral Output 65.
kTopEarlgreyPinmuxOutselPwmAonPwm4	Peripheral Output 66.
kTopEarlgreyPinmuxOutselPwmAonPwm5	Peripheral Output 67.
kTopEarlgreyPinmuxOutselOtpCtrlTest0	Peripheral Output 68.
kTopEarlgreyPinmuxOutselSysrstCtrlAonBatDisable	Peripheral Output 69.
kTopEarlgreyPinmuxOutselSysrstCtrlAonKey0Out	Peripheral Output 70.
kTopEarlgreyPinmuxOutselSysrstCtrlAonKey1Out	Peripheral Output 71.
kTopEarlgreyPinmuxOutselSysrstCtrlAonKey2Out	Peripheral Output 72.
kTopEarlgreyPinmuxOutselSysrstCtrlAonPwrbOut	Peripheral Output 73.
kTopEarlgreyPinmuxOutselSysrstCtrlAonZ3Wakeup	Peripheral Output 74.

Definition at line 1589 of file top_earlgrey.h.

◆ top_earlgrey_pinmux_peripheral_in

enum top_earlgrey_pinmux_peripheral_in

Pinmux Peripheral Input.

Enumerator
kTopEarlgreyPinmuxPeripheralInGpioGpio0	Peripheral Input 0.
kTopEarlgreyPinmuxPeripheralInGpioGpio1	Peripheral Input 1.
kTopEarlgreyPinmuxPeripheralInGpioGpio2	Peripheral Input 2.
kTopEarlgreyPinmuxPeripheralInGpioGpio3	Peripheral Input 3.
kTopEarlgreyPinmuxPeripheralInGpioGpio4	Peripheral Input 4.
kTopEarlgreyPinmuxPeripheralInGpioGpio5	Peripheral Input 5.
kTopEarlgreyPinmuxPeripheralInGpioGpio6	Peripheral Input 6.
kTopEarlgreyPinmuxPeripheralInGpioGpio7	Peripheral Input 7.
kTopEarlgreyPinmuxPeripheralInGpioGpio8	Peripheral Input 8.
kTopEarlgreyPinmuxPeripheralInGpioGpio9	Peripheral Input 9.
kTopEarlgreyPinmuxPeripheralInGpioGpio10	Peripheral Input 10.
kTopEarlgreyPinmuxPeripheralInGpioGpio11	Peripheral Input 11.
kTopEarlgreyPinmuxPeripheralInGpioGpio12	Peripheral Input 12.
kTopEarlgreyPinmuxPeripheralInGpioGpio13	Peripheral Input 13.
kTopEarlgreyPinmuxPeripheralInGpioGpio14	Peripheral Input 14.
kTopEarlgreyPinmuxPeripheralInGpioGpio15	Peripheral Input 15.
kTopEarlgreyPinmuxPeripheralInGpioGpio16	Peripheral Input 16.
kTopEarlgreyPinmuxPeripheralInGpioGpio17	Peripheral Input 17.
kTopEarlgreyPinmuxPeripheralInGpioGpio18	Peripheral Input 18.
kTopEarlgreyPinmuxPeripheralInGpioGpio19	Peripheral Input 19.
kTopEarlgreyPinmuxPeripheralInGpioGpio20	Peripheral Input 20.
kTopEarlgreyPinmuxPeripheralInGpioGpio21	Peripheral Input 21.
kTopEarlgreyPinmuxPeripheralInGpioGpio22	Peripheral Input 22.
kTopEarlgreyPinmuxPeripheralInGpioGpio23	Peripheral Input 23.
kTopEarlgreyPinmuxPeripheralInGpioGpio24	Peripheral Input 24.
kTopEarlgreyPinmuxPeripheralInGpioGpio25	Peripheral Input 25.
kTopEarlgreyPinmuxPeripheralInGpioGpio26	Peripheral Input 26.
kTopEarlgreyPinmuxPeripheralInGpioGpio27	Peripheral Input 27.
kTopEarlgreyPinmuxPeripheralInGpioGpio28	Peripheral Input 28.
kTopEarlgreyPinmuxPeripheralInGpioGpio29	Peripheral Input 29.
kTopEarlgreyPinmuxPeripheralInGpioGpio30	Peripheral Input 30.
kTopEarlgreyPinmuxPeripheralInGpioGpio31	Peripheral Input 31.
kTopEarlgreyPinmuxPeripheralInI2c0Sda	Peripheral Input 32.
kTopEarlgreyPinmuxPeripheralInI2c0Scl	Peripheral Input 33.
kTopEarlgreyPinmuxPeripheralInI2c1Sda	Peripheral Input 34.
kTopEarlgreyPinmuxPeripheralInI2c1Scl	Peripheral Input 35.
kTopEarlgreyPinmuxPeripheralInI2c2Sda	Peripheral Input 36.
kTopEarlgreyPinmuxPeripheralInI2c2Scl	Peripheral Input 37.
kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0	Peripheral Input 38.
kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1	Peripheral Input 39.
kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2	Peripheral Input 40.
kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3	Peripheral Input 41.
kTopEarlgreyPinmuxPeripheralInUart0Rx	Peripheral Input 42.
kTopEarlgreyPinmuxPeripheralInUart1Rx	Peripheral Input 43.
kTopEarlgreyPinmuxPeripheralInUart2Rx	Peripheral Input 44.
kTopEarlgreyPinmuxPeripheralInUart3Rx	Peripheral Input 45.
kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb	Peripheral Input 46.
kTopEarlgreyPinmuxPeripheralInFlashCtrlTck	Peripheral Input 47.
kTopEarlgreyPinmuxPeripheralInFlashCtrlTms	Peripheral Input 48.
kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi	Peripheral Input 49.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonAcPresent	Peripheral Input 50.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey0In	Peripheral Input 51.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey1In	Peripheral Input 52.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey2In	Peripheral Input 53.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonPwrbIn	Peripheral Input 54.
kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonLidOpen	Peripheral Input 55.
kTopEarlgreyPinmuxPeripheralInUsbdevSense	Peripheral Input 56.

Definition at line 1415 of file top_earlgrey.h.

◆ top_earlgrey_plic_irq_id

enum top_earlgrey_plic_irq_id

PLIC Interrupt Source.

Enumeration of all PLIC interrupt sources. The interrupt sources belonging to the same peripheral are guaranteed to be consecutive.

Enumerator
kTopEarlgreyPlicIrqIdNone	No Interrupt.
kTopEarlgreyPlicIrqIdUart0TxWatermark	uart0_tx_watermark
kTopEarlgreyPlicIrqIdUart0RxWatermark	uart0_rx_watermark
kTopEarlgreyPlicIrqIdUart0TxDone	uart0_tx_done
kTopEarlgreyPlicIrqIdUart0RxOverflow	uart0_rx_overflow
kTopEarlgreyPlicIrqIdUart0RxFrameErr	uart0_rx_frame_err
kTopEarlgreyPlicIrqIdUart0RxBreakErr	uart0_rx_break_err
kTopEarlgreyPlicIrqIdUart0RxTimeout	uart0_rx_timeout
kTopEarlgreyPlicIrqIdUart0RxParityErr	uart0_rx_parity_err
kTopEarlgreyPlicIrqIdUart0TxEmpty	uart0_tx_empty
kTopEarlgreyPlicIrqIdUart1TxWatermark	uart1_tx_watermark
kTopEarlgreyPlicIrqIdUart1RxWatermark	uart1_rx_watermark
kTopEarlgreyPlicIrqIdUart1TxDone	uart1_tx_done
kTopEarlgreyPlicIrqIdUart1RxOverflow	uart1_rx_overflow
kTopEarlgreyPlicIrqIdUart1RxFrameErr	uart1_rx_frame_err
kTopEarlgreyPlicIrqIdUart1RxBreakErr	uart1_rx_break_err
kTopEarlgreyPlicIrqIdUart1RxTimeout	uart1_rx_timeout
kTopEarlgreyPlicIrqIdUart1RxParityErr	uart1_rx_parity_err
kTopEarlgreyPlicIrqIdUart1TxEmpty	uart1_tx_empty
kTopEarlgreyPlicIrqIdUart2TxWatermark	uart2_tx_watermark
kTopEarlgreyPlicIrqIdUart2RxWatermark	uart2_rx_watermark
kTopEarlgreyPlicIrqIdUart2TxDone	uart2_tx_done
kTopEarlgreyPlicIrqIdUart2RxOverflow	uart2_rx_overflow
kTopEarlgreyPlicIrqIdUart2RxFrameErr	uart2_rx_frame_err
kTopEarlgreyPlicIrqIdUart2RxBreakErr	uart2_rx_break_err
kTopEarlgreyPlicIrqIdUart2RxTimeout	uart2_rx_timeout
kTopEarlgreyPlicIrqIdUart2RxParityErr	uart2_rx_parity_err
kTopEarlgreyPlicIrqIdUart2TxEmpty	uart2_tx_empty
kTopEarlgreyPlicIrqIdUart3TxWatermark	uart3_tx_watermark
kTopEarlgreyPlicIrqIdUart3RxWatermark	uart3_rx_watermark
kTopEarlgreyPlicIrqIdUart3TxDone	uart3_tx_done
kTopEarlgreyPlicIrqIdUart3RxOverflow	uart3_rx_overflow
kTopEarlgreyPlicIrqIdUart3RxFrameErr	uart3_rx_frame_err
kTopEarlgreyPlicIrqIdUart3RxBreakErr	uart3_rx_break_err
kTopEarlgreyPlicIrqIdUart3RxTimeout	uart3_rx_timeout
kTopEarlgreyPlicIrqIdUart3RxParityErr	uart3_rx_parity_err
kTopEarlgreyPlicIrqIdUart3TxEmpty	uart3_tx_empty
kTopEarlgreyPlicIrqIdGpioGpio0	gpio_gpio 0
kTopEarlgreyPlicIrqIdGpioGpio1	gpio_gpio 1
kTopEarlgreyPlicIrqIdGpioGpio2	gpio_gpio 2
kTopEarlgreyPlicIrqIdGpioGpio3	gpio_gpio 3
kTopEarlgreyPlicIrqIdGpioGpio4	gpio_gpio 4
kTopEarlgreyPlicIrqIdGpioGpio5	gpio_gpio 5
kTopEarlgreyPlicIrqIdGpioGpio6	gpio_gpio 6
kTopEarlgreyPlicIrqIdGpioGpio7	gpio_gpio 7
kTopEarlgreyPlicIrqIdGpioGpio8	gpio_gpio 8
kTopEarlgreyPlicIrqIdGpioGpio9	gpio_gpio 9
kTopEarlgreyPlicIrqIdGpioGpio10	gpio_gpio 10
kTopEarlgreyPlicIrqIdGpioGpio11	gpio_gpio 11
kTopEarlgreyPlicIrqIdGpioGpio12	gpio_gpio 12
kTopEarlgreyPlicIrqIdGpioGpio13	gpio_gpio 13
kTopEarlgreyPlicIrqIdGpioGpio14	gpio_gpio 14
kTopEarlgreyPlicIrqIdGpioGpio15	gpio_gpio 15
kTopEarlgreyPlicIrqIdGpioGpio16	gpio_gpio 16
kTopEarlgreyPlicIrqIdGpioGpio17	gpio_gpio 17
kTopEarlgreyPlicIrqIdGpioGpio18	gpio_gpio 18
kTopEarlgreyPlicIrqIdGpioGpio19	gpio_gpio 19
kTopEarlgreyPlicIrqIdGpioGpio20	gpio_gpio 20
kTopEarlgreyPlicIrqIdGpioGpio21	gpio_gpio 21
kTopEarlgreyPlicIrqIdGpioGpio22	gpio_gpio 22
kTopEarlgreyPlicIrqIdGpioGpio23	gpio_gpio 23
kTopEarlgreyPlicIrqIdGpioGpio24	gpio_gpio 24
kTopEarlgreyPlicIrqIdGpioGpio25	gpio_gpio 25
kTopEarlgreyPlicIrqIdGpioGpio26	gpio_gpio 26
kTopEarlgreyPlicIrqIdGpioGpio27	gpio_gpio 27
kTopEarlgreyPlicIrqIdGpioGpio28	gpio_gpio 28
kTopEarlgreyPlicIrqIdGpioGpio29	gpio_gpio 29
kTopEarlgreyPlicIrqIdGpioGpio30	gpio_gpio 30
kTopEarlgreyPlicIrqIdGpioGpio31	gpio_gpio 31
kTopEarlgreyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty	spi_device_upload_cmdfifo_not_empty
kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadNotEmpty	spi_device_upload_payload_not_empty
kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadOverflow	spi_device_upload_payload_overflow
kTopEarlgreyPlicIrqIdSpiDeviceReadbufWatermark	spi_device_readbuf_watermark
kTopEarlgreyPlicIrqIdSpiDeviceReadbufFlip	spi_device_readbuf_flip
kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty	spi_device_tpm_header_not_empty
kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoCmdEnd	spi_device_tpm_rdfifo_cmd_end
kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoDrop	spi_device_tpm_rdfifo_drop
kTopEarlgreyPlicIrqIdI2c0FmtThreshold	i2c0_fmt_threshold
kTopEarlgreyPlicIrqIdI2c0RxThreshold	i2c0_rx_threshold
kTopEarlgreyPlicIrqIdI2c0AcqThreshold	i2c0_acq_threshold
kTopEarlgreyPlicIrqIdI2c0RxOverflow	i2c0_rx_overflow
kTopEarlgreyPlicIrqIdI2c0ControllerHalt	i2c0_controller_halt
kTopEarlgreyPlicIrqIdI2c0SclInterference	i2c0_scl_interference
kTopEarlgreyPlicIrqIdI2c0SdaInterference	i2c0_sda_interference
kTopEarlgreyPlicIrqIdI2c0StretchTimeout	i2c0_stretch_timeout
kTopEarlgreyPlicIrqIdI2c0SdaUnstable	i2c0_sda_unstable
kTopEarlgreyPlicIrqIdI2c0CmdComplete	i2c0_cmd_complete
kTopEarlgreyPlicIrqIdI2c0TxStretch	i2c0_tx_stretch
kTopEarlgreyPlicIrqIdI2c0TxThreshold	i2c0_tx_threshold
kTopEarlgreyPlicIrqIdI2c0AcqStretch	i2c0_acq_stretch
kTopEarlgreyPlicIrqIdI2c0UnexpStop	i2c0_unexp_stop
kTopEarlgreyPlicIrqIdI2c0HostTimeout	i2c0_host_timeout
kTopEarlgreyPlicIrqIdI2c1FmtThreshold	i2c1_fmt_threshold
kTopEarlgreyPlicIrqIdI2c1RxThreshold	i2c1_rx_threshold
kTopEarlgreyPlicIrqIdI2c1AcqThreshold	i2c1_acq_threshold
kTopEarlgreyPlicIrqIdI2c1RxOverflow	i2c1_rx_overflow
kTopEarlgreyPlicIrqIdI2c1ControllerHalt	i2c1_controller_halt
kTopEarlgreyPlicIrqIdI2c1SclInterference	i2c1_scl_interference
kTopEarlgreyPlicIrqIdI2c1SdaInterference	i2c1_sda_interference
kTopEarlgreyPlicIrqIdI2c1StretchTimeout	i2c1_stretch_timeout
kTopEarlgreyPlicIrqIdI2c1SdaUnstable	i2c1_sda_unstable
kTopEarlgreyPlicIrqIdI2c1CmdComplete	i2c1_cmd_complete
kTopEarlgreyPlicIrqIdI2c1TxStretch	i2c1_tx_stretch
kTopEarlgreyPlicIrqIdI2c1TxThreshold	i2c1_tx_threshold
kTopEarlgreyPlicIrqIdI2c1AcqStretch	i2c1_acq_stretch
kTopEarlgreyPlicIrqIdI2c1UnexpStop	i2c1_unexp_stop
kTopEarlgreyPlicIrqIdI2c1HostTimeout	i2c1_host_timeout
kTopEarlgreyPlicIrqIdI2c2FmtThreshold	i2c2_fmt_threshold
kTopEarlgreyPlicIrqIdI2c2RxThreshold	i2c2_rx_threshold
kTopEarlgreyPlicIrqIdI2c2AcqThreshold	i2c2_acq_threshold
kTopEarlgreyPlicIrqIdI2c2RxOverflow	i2c2_rx_overflow
kTopEarlgreyPlicIrqIdI2c2ControllerHalt	i2c2_controller_halt
kTopEarlgreyPlicIrqIdI2c2SclInterference	i2c2_scl_interference
kTopEarlgreyPlicIrqIdI2c2SdaInterference	i2c2_sda_interference
kTopEarlgreyPlicIrqIdI2c2StretchTimeout	i2c2_stretch_timeout
kTopEarlgreyPlicIrqIdI2c2SdaUnstable	i2c2_sda_unstable
kTopEarlgreyPlicIrqIdI2c2CmdComplete	i2c2_cmd_complete
kTopEarlgreyPlicIrqIdI2c2TxStretch	i2c2_tx_stretch
kTopEarlgreyPlicIrqIdI2c2TxThreshold	i2c2_tx_threshold
kTopEarlgreyPlicIrqIdI2c2AcqStretch	i2c2_acq_stretch
kTopEarlgreyPlicIrqIdI2c2UnexpStop	i2c2_unexp_stop
kTopEarlgreyPlicIrqIdI2c2HostTimeout	i2c2_host_timeout
kTopEarlgreyPlicIrqIdPattgenDoneCh0	pattgen_done_ch0
kTopEarlgreyPlicIrqIdPattgenDoneCh1	pattgen_done_ch1
kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0	rv_timer_timer_expired_hart0_timer0
kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone	otp_ctrl_otp_operation_done
kTopEarlgreyPlicIrqIdOtpCtrlOtpError	otp_ctrl_otp_error
kTopEarlgreyPlicIrqIdAlertHandlerClassa	alert_handler_classa
kTopEarlgreyPlicIrqIdAlertHandlerClassb	alert_handler_classb
kTopEarlgreyPlicIrqIdAlertHandlerClassc	alert_handler_classc
kTopEarlgreyPlicIrqIdAlertHandlerClassd	alert_handler_classd
kTopEarlgreyPlicIrqIdSpiHost0Error	spi_host0_error
kTopEarlgreyPlicIrqIdSpiHost0SpiEvent	spi_host0_spi_event
kTopEarlgreyPlicIrqIdSpiHost1Error	spi_host1_error
kTopEarlgreyPlicIrqIdSpiHost1SpiEvent	spi_host1_spi_event
kTopEarlgreyPlicIrqIdUsbdevPktReceived	usbdev_pkt_received
kTopEarlgreyPlicIrqIdUsbdevPktSent	usbdev_pkt_sent
kTopEarlgreyPlicIrqIdUsbdevDisconnected	usbdev_disconnected
kTopEarlgreyPlicIrqIdUsbdevHostLost	usbdev_host_lost
kTopEarlgreyPlicIrqIdUsbdevLinkReset	usbdev_link_reset
kTopEarlgreyPlicIrqIdUsbdevLinkSuspend	usbdev_link_suspend
kTopEarlgreyPlicIrqIdUsbdevLinkResume	usbdev_link_resume
kTopEarlgreyPlicIrqIdUsbdevAvOutEmpty	usbdev_av_out_empty
kTopEarlgreyPlicIrqIdUsbdevRxFull	usbdev_rx_full
kTopEarlgreyPlicIrqIdUsbdevAvOverflow	usbdev_av_overflow
kTopEarlgreyPlicIrqIdUsbdevLinkInErr	usbdev_link_in_err
kTopEarlgreyPlicIrqIdUsbdevRxCrcErr	usbdev_rx_crc_err
kTopEarlgreyPlicIrqIdUsbdevRxPidErr	usbdev_rx_pid_err
kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr	usbdev_rx_bitstuff_err
kTopEarlgreyPlicIrqIdUsbdevFrame	usbdev_frame
kTopEarlgreyPlicIrqIdUsbdevPowered	usbdev_powered
kTopEarlgreyPlicIrqIdUsbdevLinkOutErr	usbdev_link_out_err
kTopEarlgreyPlicIrqIdUsbdevAvSetupEmpty	usbdev_av_setup_empty
kTopEarlgreyPlicIrqIdPwrmgrAonWakeup	pwrmgr_aon_wakeup
kTopEarlgreyPlicIrqIdSysrstCtrlAonEventDetected	sysrst_ctrl_aon_event_detected
kTopEarlgreyPlicIrqIdAdcCtrlAonMatchPending	adc_ctrl_aon_match_pending
kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired	aon_timer_aon_wkup_timer_expired
kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark	aon_timer_aon_wdog_timer_bark
kTopEarlgreyPlicIrqIdSensorCtrlAonIoStatusChange	sensor_ctrl_aon_io_status_change
kTopEarlgreyPlicIrqIdSensorCtrlAonInitStatusChange	sensor_ctrl_aon_init_status_change
kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty	flash_ctrl_prog_empty
kTopEarlgreyPlicIrqIdFlashCtrlProgLvl	flash_ctrl_prog_lvl
kTopEarlgreyPlicIrqIdFlashCtrlRdFull	flash_ctrl_rd_full
kTopEarlgreyPlicIrqIdFlashCtrlRdLvl	flash_ctrl_rd_lvl
kTopEarlgreyPlicIrqIdFlashCtrlOpDone	flash_ctrl_op_done
kTopEarlgreyPlicIrqIdFlashCtrlCorrErr	flash_ctrl_corr_err
kTopEarlgreyPlicIrqIdHmacHmacDone	hmac_hmac_done
kTopEarlgreyPlicIrqIdHmacFifoEmpty	hmac_fifo_empty
kTopEarlgreyPlicIrqIdHmacHmacErr	hmac_hmac_err
kTopEarlgreyPlicIrqIdKmacKmacDone	kmac_kmac_done
kTopEarlgreyPlicIrqIdKmacFifoEmpty	kmac_fifo_empty
kTopEarlgreyPlicIrqIdKmacKmacErr	kmac_kmac_err
kTopEarlgreyPlicIrqIdOtbnDone	otbn_done
kTopEarlgreyPlicIrqIdKeymgrOpDone	keymgr_op_done
kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone	csrng_cs_cmd_req_done
kTopEarlgreyPlicIrqIdCsrngCsEntropyReq	csrng_cs_entropy_req
kTopEarlgreyPlicIrqIdCsrngCsHwInstExc	csrng_cs_hw_inst_exc
kTopEarlgreyPlicIrqIdCsrngCsFatalErr	csrng_cs_fatal_err
kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid	entropy_src_es_entropy_valid
kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed	entropy_src_es_health_test_failed
kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady	entropy_src_es_observe_fifo_ready
kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr	entropy_src_es_fatal_err
kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone	edn0_edn_cmd_req_done
kTopEarlgreyPlicIrqIdEdn0EdnFatalErr	edn0_edn_fatal_err
kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone	edn1_edn_cmd_req_done
kTopEarlgreyPlicIrqIdEdn1EdnFatalErr	edn1_edn_fatal_err

Definition at line 1058 of file top_earlgrey.h.

◆ top_earlgrey_plic_peripheral

enum top_earlgrey_plic_peripheral

PLIC Interrupt Source Peripheral.

Enumeration used to determine which peripheral asserted the corresponding interrupt.

Enumerator
kTopEarlgreyPlicPeripheralUnknown	Unknown Peripheral.
kTopEarlgreyPlicPeripheralUart0	uart0
kTopEarlgreyPlicPeripheralUart1	uart1
kTopEarlgreyPlicPeripheralUart2	uart2
kTopEarlgreyPlicPeripheralUart3	uart3
kTopEarlgreyPlicPeripheralGpio	gpio
kTopEarlgreyPlicPeripheralSpiDevice	spi_device
kTopEarlgreyPlicPeripheralI2c0	i2c0
kTopEarlgreyPlicPeripheralI2c1	i2c1
kTopEarlgreyPlicPeripheralI2c2	i2c2
kTopEarlgreyPlicPeripheralPattgen	pattgen
kTopEarlgreyPlicPeripheralRvTimer	rv_timer
kTopEarlgreyPlicPeripheralOtpCtrl	otp_ctrl
kTopEarlgreyPlicPeripheralAlertHandler	alert_handler
kTopEarlgreyPlicPeripheralSpiHost0	spi_host0
kTopEarlgreyPlicPeripheralSpiHost1	spi_host1
kTopEarlgreyPlicPeripheralUsbdev	usbdev
kTopEarlgreyPlicPeripheralPwrmgrAon	pwrmgr_aon
kTopEarlgreyPlicPeripheralSysrstCtrlAon	sysrst_ctrl_aon
kTopEarlgreyPlicPeripheralAdcCtrlAon	adc_ctrl_aon
kTopEarlgreyPlicPeripheralAonTimerAon	aon_timer_aon
kTopEarlgreyPlicPeripheralSensorCtrlAon	sensor_ctrl_aon
kTopEarlgreyPlicPeripheralFlashCtrl	flash_ctrl
kTopEarlgreyPlicPeripheralHmac	hmac
kTopEarlgreyPlicPeripheralKmac	kmac
kTopEarlgreyPlicPeripheralOtbn	otbn
kTopEarlgreyPlicPeripheralKeymgr	keymgr
kTopEarlgreyPlicPeripheralCsrng	csrng
kTopEarlgreyPlicPeripheralEntropySrc	entropy_src
kTopEarlgreyPlicPeripheralEdn0	edn0
kTopEarlgreyPlicPeripheralEdn1	edn1

Definition at line 1017 of file top_earlgrey.h.

◆ top_earlgrey_plic_target

enum top_earlgrey_plic_target

PLIC Interrupt Target.

Enumeration used to determine which set of IE, CC, threshold registers to access for a given interrupt target.

Enumerator
kTopEarlgreyPlicTargetIbex0	Ibex Core 0.

Definition at line 1263 of file top_earlgrey.h.

Variable Documentation

◆ top_earlgrey_alert_for_peripheral

const top_earlgrey_alert_peripheral_t top_earlgrey_alert_for_peripheral[65]

extern

Alert Handler Alert Source to Peripheral Map.

This array is a mapping from top_earlgrey_alert_id_t to top_earlgrey_alert_peripheral_t.

Definition at line 19 of file top_earlgrey.c.

◆ top_earlgrey_plic_interrupt_for_peripheral

const top_earlgrey_plic_peripheral_t top_earlgrey_plic_interrupt_for_peripheral[186]

extern

PLIC Interrupt Source to Peripheral Map.

This array is a mapping from top_earlgrey_plic_irq_id_t to top_earlgrey_plic_peripheral_t.

Definition at line 95 of file top_earlgrey.c.

(45edf908c9)

Macros

Typedefs

Enumerations

Variables

Detailed Description

Macro Definition Documentation

◆ TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR

◆ TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES

◆ TOP_EARLGREY_AES_BASE_ADDR

◆ TOP_EARLGREY_AES_SIZE_BYTES

◆ TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR

◆ TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES

◆ TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR

◆ TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES

◆ TOP_EARLGREY_AST_BASE_ADDR

◆ TOP_EARLGREY_AST_SIZE_BYTES

◆ TOP_EARLGREY_CLKMGR_AON_BASE_ADDR

◆ TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES

◆ TOP_EARLGREY_CSRNG_BASE_ADDR

◆ TOP_EARLGREY_CSRNG_SIZE_BYTES

◆ TOP_EARLGREY_EDN0_BASE_ADDR

◆ TOP_EARLGREY_EDN0_SIZE_BYTES

◆ TOP_EARLGREY_EDN1_BASE_ADDR

◆ TOP_EARLGREY_EDN1_SIZE_BYTES

◆ TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR

◆ TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES

◆ TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR

◆ TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES

◆ TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR

◆ TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES

◆ TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR

◆ TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES

◆ TOP_EARLGREY_GPIO_BASE_ADDR

◆ TOP_EARLGREY_GPIO_SIZE_BYTES

◆ TOP_EARLGREY_HMAC_BASE_ADDR

◆ TOP_EARLGREY_HMAC_SIZE_BYTES

◆ TOP_EARLGREY_I2C0_BASE_ADDR

◆ TOP_EARLGREY_I2C0_SIZE_BYTES

◆ TOP_EARLGREY_I2C1_BASE_ADDR

◆ TOP_EARLGREY_I2C1_SIZE_BYTES

◆ TOP_EARLGREY_I2C2_BASE_ADDR

◆ TOP_EARLGREY_I2C2_SIZE_BYTES

◆ TOP_EARLGREY_KEYMGR_BASE_ADDR

◆ TOP_EARLGREY_KEYMGR_SIZE_BYTES

◆ TOP_EARLGREY_KMAC_BASE_ADDR

◆ TOP_EARLGREY_KMAC_SIZE_BYTES

◆ TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR

◆ TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES

◆ TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR

◆ TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES

◆ TOP_EARLGREY_MMIO_BASE_ADDR

◆ TOP_EARLGREY_OTBN_BASE_ADDR

◆ TOP_EARLGREY_OTBN_SIZE_BYTES

◆ TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR

◆ TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES

◆ TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR

◆ TOP_EARLGREY_OTP_CTRL_PRIM_SIZE_BYTES

◆ TOP_EARLGREY_PATTGEN_BASE_ADDR

◆ TOP_EARLGREY_PATTGEN_SIZE_BYTES

◆ TOP_EARLGREY_PINMUX_AON_BASE_ADDR

◆ TOP_EARLGREY_PINMUX_AON_SIZE_BYTES

◆ TOP_EARLGREY_PWM_AON_BASE_ADDR

◆ TOP_EARLGREY_PWM_AON_SIZE_BYTES

◆ TOP_EARLGREY_PWRMGR_AON_BASE_ADDR

◆ TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES

◆ TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR

◆ TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES

◆ TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR

◆ TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES

◆ TOP_EARLGREY_RSTMGR_AON_BASE_ADDR

◆ TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES

◆ TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR

◆ TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES

◆ TOP_EARLGREY_RV_DM_DBG_BASE_ADDR

◆ TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES

◆ TOP_EARLGREY_RV_DM_MEM_BASE_ADDR

◆ TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES

◆ TOP_EARLGREY_RV_DM_REGS_BASE_ADDR

◆ TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES