Software APIs
top_earlgrey.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
6// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
7// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson
8// -o hw/top_earlgrey/
9
10#ifndef OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_H_
11#define OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_H_
12
13/**
14 * @file
15 * @brief Top-specific Definitions
16 *
17 * This file contains preprocessor and type definitions for use within the
18 * device C/C++ codebase.
19 *
20 * These definitions are for information that depends on the top-specific chip
21 * configuration, which includes:
22 * - Device Memory Information (for Peripherals and Memory)
23 * - PLIC Interrupt ID Names and Source Mappings
24 * - Alert ID Names and Source Mappings
25 * - Pinmux Pin/Select Names
26 * - Power Manager Wakeups
27 */
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/**
34 * Peripheral base address for uart0 in top earlgrey.
35 *
36 * This should be used with #mmio_region_from_addr to access the memory-mapped
37 * registers associated with the peripheral (usually via a DIF).
38 */
39#define TOP_EARLGREY_UART0_BASE_ADDR 0x40000000u
40
41/**
42 * Peripheral size for uart0 in top earlgrey.
43 *
44 * This is the size (in bytes) of the peripheral's reserved memory area. All
45 * memory-mapped registers associated with this peripheral should have an
46 * address between #TOP_EARLGREY_UART0_BASE_ADDR and
47 * `TOP_EARLGREY_UART0_BASE_ADDR + TOP_EARLGREY_UART0_SIZE_BYTES`.
48 */
49#define TOP_EARLGREY_UART0_SIZE_BYTES 0x40u
50
51/**
52 * Peripheral base address for uart1 in top earlgrey.
53 *
54 * This should be used with #mmio_region_from_addr to access the memory-mapped
55 * registers associated with the peripheral (usually via a DIF).
56 */
57#define TOP_EARLGREY_UART1_BASE_ADDR 0x40010000u
58
59/**
60 * Peripheral size for uart1 in top earlgrey.
61 *
62 * This is the size (in bytes) of the peripheral's reserved memory area. All
63 * memory-mapped registers associated with this peripheral should have an
64 * address between #TOP_EARLGREY_UART1_BASE_ADDR and
65 * `TOP_EARLGREY_UART1_BASE_ADDR + TOP_EARLGREY_UART1_SIZE_BYTES`.
66 */
67#define TOP_EARLGREY_UART1_SIZE_BYTES 0x40u
68
69/**
70 * Peripheral base address for uart2 in top earlgrey.
71 *
72 * This should be used with #mmio_region_from_addr to access the memory-mapped
73 * registers associated with the peripheral (usually via a DIF).
74 */
75#define TOP_EARLGREY_UART2_BASE_ADDR 0x40020000u
76
77/**
78 * Peripheral size for uart2 in top earlgrey.
79 *
80 * This is the size (in bytes) of the peripheral's reserved memory area. All
81 * memory-mapped registers associated with this peripheral should have an
82 * address between #TOP_EARLGREY_UART2_BASE_ADDR and
83 * `TOP_EARLGREY_UART2_BASE_ADDR + TOP_EARLGREY_UART2_SIZE_BYTES`.
84 */
85#define TOP_EARLGREY_UART2_SIZE_BYTES 0x40u
86
87/**
88 * Peripheral base address for uart3 in top earlgrey.
89 *
90 * This should be used with #mmio_region_from_addr to access the memory-mapped
91 * registers associated with the peripheral (usually via a DIF).
92 */
93#define TOP_EARLGREY_UART3_BASE_ADDR 0x40030000u
94
95/**
96 * Peripheral size for uart3 in top earlgrey.
97 *
98 * This is the size (in bytes) of the peripheral's reserved memory area. All
99 * memory-mapped registers associated with this peripheral should have an
100 * address between #TOP_EARLGREY_UART3_BASE_ADDR and
101 * `TOP_EARLGREY_UART3_BASE_ADDR + TOP_EARLGREY_UART3_SIZE_BYTES`.
102 */
103#define TOP_EARLGREY_UART3_SIZE_BYTES 0x40u
104
105/**
106 * Peripheral base address for gpio0 in top earlgrey.
107 *
108 * This should be used with #mmio_region_from_addr to access the memory-mapped
109 * registers associated with the peripheral (usually via a DIF).
110 */
111#define TOP_EARLGREY_GPIO0_BASE_ADDR 0x40040000u
112
113/**
114 * Peripheral size for gpio0 in top earlgrey.
115 *
116 * This is the size (in bytes) of the peripheral's reserved memory area. All
117 * memory-mapped registers associated with this peripheral should have an
118 * address between #TOP_EARLGREY_GPIO0_BASE_ADDR and
119 * `TOP_EARLGREY_GPIO0_BASE_ADDR + TOP_EARLGREY_GPIO0_SIZE_BYTES`.
120 */
121#define TOP_EARLGREY_GPIO0_SIZE_BYTES 0x400u
122
123/**
124 * Peripheral base address for gpio1 in top earlgrey.
125 *
126 * This should be used with #mmio_region_from_addr to access the memory-mapped
127 * registers associated with the peripheral (usually via a DIF).
128 */
129#define TOP_EARLGREY_GPIO1_BASE_ADDR 0x40050000u
130
131/**
132 * Peripheral size for gpio1 in top earlgrey.
133 *
134 * This is the size (in bytes) of the peripheral's reserved memory area. All
135 * memory-mapped registers associated with this peripheral should have an
136 * address between #TOP_EARLGREY_GPIO1_BASE_ADDR and
137 * `TOP_EARLGREY_GPIO1_BASE_ADDR + TOP_EARLGREY_GPIO1_SIZE_BYTES`.
138 */
139#define TOP_EARLGREY_GPIO1_SIZE_BYTES 0x400u
140
141/**
142 * Peripheral base address for spi_device in top earlgrey.
143 *
144 * This should be used with #mmio_region_from_addr to access the memory-mapped
145 * registers associated with the peripheral (usually via a DIF).
146 */
147#define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40060000u
148
149/**
150 * Peripheral size for spi_device in top earlgrey.
151 *
152 * This is the size (in bytes) of the peripheral's reserved memory area. All
153 * memory-mapped registers associated with this peripheral should have an
154 * address between #TOP_EARLGREY_SPI_DEVICE_BASE_ADDR and
155 * `TOP_EARLGREY_SPI_DEVICE_BASE_ADDR + TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES`.
156 */
157#define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x2000u
158
159/**
160 * Peripheral base address for i2c0 in top earlgrey.
161 *
162 * This should be used with #mmio_region_from_addr to access the memory-mapped
163 * registers associated with the peripheral (usually via a DIF).
164 */
165#define TOP_EARLGREY_I2C0_BASE_ADDR 0x40080000u
166
167/**
168 * Peripheral size for i2c0 in top earlgrey.
169 *
170 * This is the size (in bytes) of the peripheral's reserved memory area. All
171 * memory-mapped registers associated with this peripheral should have an
172 * address between #TOP_EARLGREY_I2C0_BASE_ADDR and
173 * `TOP_EARLGREY_I2C0_BASE_ADDR + TOP_EARLGREY_I2C0_SIZE_BYTES`.
174 */
175#define TOP_EARLGREY_I2C0_SIZE_BYTES 0x80u
176
177/**
178 * Peripheral base address for i2c1 in top earlgrey.
179 *
180 * This should be used with #mmio_region_from_addr to access the memory-mapped
181 * registers associated with the peripheral (usually via a DIF).
182 */
183#define TOP_EARLGREY_I2C1_BASE_ADDR 0x40090000u
184
185/**
186 * Peripheral size for i2c1 in top earlgrey.
187 *
188 * This is the size (in bytes) of the peripheral's reserved memory area. All
189 * memory-mapped registers associated with this peripheral should have an
190 * address between #TOP_EARLGREY_I2C1_BASE_ADDR and
191 * `TOP_EARLGREY_I2C1_BASE_ADDR + TOP_EARLGREY_I2C1_SIZE_BYTES`.
192 */
193#define TOP_EARLGREY_I2C1_SIZE_BYTES 0x80u
194
195/**
196 * Peripheral base address for i2c2 in top earlgrey.
197 *
198 * This should be used with #mmio_region_from_addr to access the memory-mapped
199 * registers associated with the peripheral (usually via a DIF).
200 */
201#define TOP_EARLGREY_I2C2_BASE_ADDR 0x400A0000u
202
203/**
204 * Peripheral size for i2c2 in top earlgrey.
205 *
206 * This is the size (in bytes) of the peripheral's reserved memory area. All
207 * memory-mapped registers associated with this peripheral should have an
208 * address between #TOP_EARLGREY_I2C2_BASE_ADDR and
209 * `TOP_EARLGREY_I2C2_BASE_ADDR + TOP_EARLGREY_I2C2_SIZE_BYTES`.
210 */
211#define TOP_EARLGREY_I2C2_SIZE_BYTES 0x80u
212
213/**
214 * Peripheral base address for i3c0 in top earlgrey.
215 *
216 * This should be used with #mmio_region_from_addr to access the memory-mapped
217 * registers associated with the peripheral (usually via a DIF).
218 */
219#define TOP_EARLGREY_I3C0_BASE_ADDR 0x40330000u
220
221/**
222 * Peripheral size for i3c0 in top earlgrey.
223 *
224 * This is the size (in bytes) of the peripheral's reserved memory area. All
225 * memory-mapped registers associated with this peripheral should have an
226 * address between #TOP_EARLGREY_I3C0_BASE_ADDR and
227 * `TOP_EARLGREY_I3C0_BASE_ADDR + TOP_EARLGREY_I3C0_SIZE_BYTES`.
228 */
229#define TOP_EARLGREY_I3C0_SIZE_BYTES 0x2000u
230
231/**
232 * Peripheral base address for i3c1 in top earlgrey.
233 *
234 * This should be used with #mmio_region_from_addr to access the memory-mapped
235 * registers associated with the peripheral (usually via a DIF).
236 */
237#define TOP_EARLGREY_I3C1_BASE_ADDR 0x40340000u
238
239/**
240 * Peripheral size for i3c1 in top earlgrey.
241 *
242 * This is the size (in bytes) of the peripheral's reserved memory area. All
243 * memory-mapped registers associated with this peripheral should have an
244 * address between #TOP_EARLGREY_I3C1_BASE_ADDR and
245 * `TOP_EARLGREY_I3C1_BASE_ADDR + TOP_EARLGREY_I3C1_SIZE_BYTES`.
246 */
247#define TOP_EARLGREY_I3C1_SIZE_BYTES 0x2000u
248
249/**
250 * Peripheral base address for rv_timer in top earlgrey.
251 *
252 * This should be used with #mmio_region_from_addr to access the memory-mapped
253 * registers associated with the peripheral (usually via a DIF).
254 */
255#define TOP_EARLGREY_RV_TIMER_BASE_ADDR 0x40100000u
256
257/**
258 * Peripheral size for rv_timer in top earlgrey.
259 *
260 * This is the size (in bytes) of the peripheral's reserved memory area. All
261 * memory-mapped registers associated with this peripheral should have an
262 * address between #TOP_EARLGREY_RV_TIMER_BASE_ADDR and
263 * `TOP_EARLGREY_RV_TIMER_BASE_ADDR + TOP_EARLGREY_RV_TIMER_SIZE_BYTES`.
264 */
265#define TOP_EARLGREY_RV_TIMER_SIZE_BYTES 0x200u
266
267/**
268 * Peripheral base address for core device on otp_ctrl in top earlgrey.
269 *
270 * This should be used with #mmio_region_from_addr to access the memory-mapped
271 * registers associated with the peripheral (usually via a DIF).
272 */
273#define TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR 0x40130000u
274
275/**
276 * Peripheral size for core device on otp_ctrl in top earlgrey.
277 *
278 * This is the size (in bytes) of the peripheral's reserved memory area. All
279 * memory-mapped registers associated with this peripheral should have an
280 * address between #TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR and
281 * `TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES`.
282 */
283#define TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES 0x2000u
284
285/**
286 * Peripheral base address for regs device on lc_ctrl in top earlgrey.
287 *
288 * This should be used with #mmio_region_from_addr to access the memory-mapped
289 * registers associated with the peripheral (usually via a DIF).
290 */
291#define TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR 0x40140000u
292
293/**
294 * Peripheral size for regs device on lc_ctrl in top earlgrey.
295 *
296 * This is the size (in bytes) of the peripheral's reserved memory area. All
297 * memory-mapped registers associated with this peripheral should have an
298 * address between #TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR and
299 * `TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES`.
300 */
301#define TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES 0x100u
302
303/**
304 * Peripheral base address for alert_handler in top earlgrey.
305 *
306 * This should be used with #mmio_region_from_addr to access the memory-mapped
307 * registers associated with the peripheral (usually via a DIF).
308 */
309#define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x40150000u
310
311/**
312 * Peripheral size for alert_handler in top earlgrey.
313 *
314 * This is the size (in bytes) of the peripheral's reserved memory area. All
315 * memory-mapped registers associated with this peripheral should have an
316 * address between #TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR and
317 * `TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR + TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES`.
318 */
319#define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x800u
320
321/**
322 * Peripheral base address for spi_host0 in top earlgrey.
323 *
324 * This should be used with #mmio_region_from_addr to access the memory-mapped
325 * registers associated with the peripheral (usually via a DIF).
326 */
327#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40300000u
328
329/**
330 * Peripheral size for spi_host0 in top earlgrey.
331 *
332 * This is the size (in bytes) of the peripheral's reserved memory area. All
333 * memory-mapped registers associated with this peripheral should have an
334 * address between #TOP_EARLGREY_SPI_HOST0_BASE_ADDR and
335 * `TOP_EARLGREY_SPI_HOST0_BASE_ADDR + TOP_EARLGREY_SPI_HOST0_SIZE_BYTES`.
336 */
337#define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x40u
338
339/**
340 * Peripheral base address for spi_host1 in top earlgrey.
341 *
342 * This should be used with #mmio_region_from_addr to access the memory-mapped
343 * registers associated with the peripheral (usually via a DIF).
344 */
345#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40310000u
346
347/**
348 * Peripheral size for spi_host1 in top earlgrey.
349 *
350 * This is the size (in bytes) of the peripheral's reserved memory area. All
351 * memory-mapped registers associated with this peripheral should have an
352 * address between #TOP_EARLGREY_SPI_HOST1_BASE_ADDR and
353 * `TOP_EARLGREY_SPI_HOST1_BASE_ADDR + TOP_EARLGREY_SPI_HOST1_SIZE_BYTES`.
354 */
355#define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x40u
356
357/**
358 * Peripheral base address for usbdev in top earlgrey.
359 *
360 * This should be used with #mmio_region_from_addr to access the memory-mapped
361 * registers associated with the peripheral (usually via a DIF).
362 */
363#define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40320000u
364
365/**
366 * Peripheral size for usbdev in top earlgrey.
367 *
368 * This is the size (in bytes) of the peripheral's reserved memory area. All
369 * memory-mapped registers associated with this peripheral should have an
370 * address between #TOP_EARLGREY_USBDEV_BASE_ADDR and
371 * `TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES`.
372 */
373#define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000u
374
375/**
376 * Peripheral base address for pwrmgr in top earlgrey.
377 *
378 * This should be used with #mmio_region_from_addr to access the memory-mapped
379 * registers associated with the peripheral (usually via a DIF).
380 */
381#define TOP_EARLGREY_PWRMGR_BASE_ADDR 0x40400000u
382
383/**
384 * Peripheral size for pwrmgr in top earlgrey.
385 *
386 * This is the size (in bytes) of the peripheral's reserved memory area. All
387 * memory-mapped registers associated with this peripheral should have an
388 * address between #TOP_EARLGREY_PWRMGR_BASE_ADDR and
389 * `TOP_EARLGREY_PWRMGR_BASE_ADDR + TOP_EARLGREY_PWRMGR_SIZE_BYTES`.
390 */
391#define TOP_EARLGREY_PWRMGR_SIZE_BYTES 0x80u
392
393/**
394 * Peripheral base address for rstmgr in top earlgrey.
395 *
396 * This should be used with #mmio_region_from_addr to access the memory-mapped
397 * registers associated with the peripheral (usually via a DIF).
398 */
399#define TOP_EARLGREY_RSTMGR_BASE_ADDR 0x40410000u
400
401/**
402 * Peripheral size for rstmgr in top earlgrey.
403 *
404 * This is the size (in bytes) of the peripheral's reserved memory area. All
405 * memory-mapped registers associated with this peripheral should have an
406 * address between #TOP_EARLGREY_RSTMGR_BASE_ADDR and
407 * `TOP_EARLGREY_RSTMGR_BASE_ADDR + TOP_EARLGREY_RSTMGR_SIZE_BYTES`.
408 */
409#define TOP_EARLGREY_RSTMGR_SIZE_BYTES 0x80u
410
411/**
412 * Peripheral base address for clkmgr in top earlgrey.
413 *
414 * This should be used with #mmio_region_from_addr to access the memory-mapped
415 * registers associated with the peripheral (usually via a DIF).
416 */
417#define TOP_EARLGREY_CLKMGR_BASE_ADDR 0x40420000u
418
419/**
420 * Peripheral size for clkmgr in top earlgrey.
421 *
422 * This is the size (in bytes) of the peripheral's reserved memory area. All
423 * memory-mapped registers associated with this peripheral should have an
424 * address between #TOP_EARLGREY_CLKMGR_BASE_ADDR and
425 * `TOP_EARLGREY_CLKMGR_BASE_ADDR + TOP_EARLGREY_CLKMGR_SIZE_BYTES`.
426 */
427#define TOP_EARLGREY_CLKMGR_SIZE_BYTES 0x80u
428
429/**
430 * Peripheral base address for sysrst_ctrl in top earlgrey.
431 *
432 * This should be used with #mmio_region_from_addr to access the memory-mapped
433 * registers associated with the peripheral (usually via a DIF).
434 */
435#define TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR 0x40430000u
436
437/**
438 * Peripheral size for sysrst_ctrl in top earlgrey.
439 *
440 * This is the size (in bytes) of the peripheral's reserved memory area. All
441 * memory-mapped registers associated with this peripheral should have an
442 * address between #TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR and
443 * `TOP_EARLGREY_SYSRST_CTRL_BASE_ADDR + TOP_EARLGREY_SYSRST_CTRL_SIZE_BYTES`.
444 */
445#define TOP_EARLGREY_SYSRST_CTRL_SIZE_BYTES 0x100u
446
447/**
448 * Peripheral base address for adc_ctrl in top earlgrey.
449 *
450 * This should be used with #mmio_region_from_addr to access the memory-mapped
451 * registers associated with the peripheral (usually via a DIF).
452 */
453#define TOP_EARLGREY_ADC_CTRL_BASE_ADDR 0x40440000u
454
455/**
456 * Peripheral size for adc_ctrl in top earlgrey.
457 *
458 * This is the size (in bytes) of the peripheral's reserved memory area. All
459 * memory-mapped registers associated with this peripheral should have an
460 * address between #TOP_EARLGREY_ADC_CTRL_BASE_ADDR and
461 * `TOP_EARLGREY_ADC_CTRL_BASE_ADDR + TOP_EARLGREY_ADC_CTRL_SIZE_BYTES`.
462 */
463#define TOP_EARLGREY_ADC_CTRL_SIZE_BYTES 0x80u
464
465/**
466 * Peripheral base address for pinmux in top earlgrey.
467 *
468 * This should be used with #mmio_region_from_addr to access the memory-mapped
469 * registers associated with the peripheral (usually via a DIF).
470 */
471#define TOP_EARLGREY_PINMUX_BASE_ADDR 0x40460000u
472
473/**
474 * Peripheral size for pinmux in top earlgrey.
475 *
476 * This is the size (in bytes) of the peripheral's reserved memory area. All
477 * memory-mapped registers associated with this peripheral should have an
478 * address between #TOP_EARLGREY_PINMUX_BASE_ADDR and
479 * `TOP_EARLGREY_PINMUX_BASE_ADDR + TOP_EARLGREY_PINMUX_SIZE_BYTES`.
480 */
481#define TOP_EARLGREY_PINMUX_SIZE_BYTES 0x1000u
482
483/**
484 * Peripheral base address for aon_timer in top earlgrey.
485 *
486 * This should be used with #mmio_region_from_addr to access the memory-mapped
487 * registers associated with the peripheral (usually via a DIF).
488 */
489#define TOP_EARLGREY_AON_TIMER_BASE_ADDR 0x40470000u
490
491/**
492 * Peripheral size for aon_timer in top earlgrey.
493 *
494 * This is the size (in bytes) of the peripheral's reserved memory area. All
495 * memory-mapped registers associated with this peripheral should have an
496 * address between #TOP_EARLGREY_AON_TIMER_BASE_ADDR and
497 * `TOP_EARLGREY_AON_TIMER_BASE_ADDR + TOP_EARLGREY_AON_TIMER_SIZE_BYTES`.
498 */
499#define TOP_EARLGREY_AON_TIMER_SIZE_BYTES 0x40u
500
501/**
502 * Peripheral base address for ast in top earlgrey.
503 *
504 * This should be used with #mmio_region_from_addr to access the memory-mapped
505 * registers associated with the peripheral (usually via a DIF).
506 */
507#define TOP_EARLGREY_AST_BASE_ADDR 0x40480000u
508
509/**
510 * Peripheral size for ast in top earlgrey.
511 *
512 * This is the size (in bytes) of the peripheral's reserved memory area. All
513 * memory-mapped registers associated with this peripheral should have an
514 * address between #TOP_EARLGREY_AST_BASE_ADDR and
515 * `TOP_EARLGREY_AST_BASE_ADDR + TOP_EARLGREY_AST_SIZE_BYTES`.
516 */
517#define TOP_EARLGREY_AST_SIZE_BYTES 0x400u
518
519/**
520 * Peripheral base address for sensor_ctrl in top earlgrey.
521 *
522 * This should be used with #mmio_region_from_addr to access the memory-mapped
523 * registers associated with the peripheral (usually via a DIF).
524 */
525#define TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR 0x40490000u
526
527/**
528 * Peripheral size for sensor_ctrl in top earlgrey.
529 *
530 * This is the size (in bytes) of the peripheral's reserved memory area. All
531 * memory-mapped registers associated with this peripheral should have an
532 * address between #TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR and
533 * `TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES`.
534 */
535#define TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES 0x80u
536
537/**
538 * Peripheral base address for regs device on sram_ctrl_ret in top earlgrey.
539 *
540 * This should be used with #mmio_region_from_addr to access the memory-mapped
541 * registers associated with the peripheral (usually via a DIF).
542 */
543#define TOP_EARLGREY_SRAM_CTRL_RET_REGS_BASE_ADDR 0x40500000u
544
545/**
546 * Peripheral size for regs device on sram_ctrl_ret in top earlgrey.
547 *
548 * This is the size (in bytes) of the peripheral's reserved memory area. All
549 * memory-mapped registers associated with this peripheral should have an
550 * address between #TOP_EARLGREY_SRAM_CTRL_RET_REGS_BASE_ADDR and
551 * `TOP_EARLGREY_SRAM_CTRL_RET_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES`.
552 */
553#define TOP_EARLGREY_SRAM_CTRL_RET_REGS_SIZE_BYTES 0x40u
554
555/**
556 * Peripheral base address for core device on rram_ctrl in top earlgrey.
557 *
558 * This should be used with #mmio_region_from_addr to access the memory-mapped
559 * registers associated with the peripheral (usually via a DIF).
560 */
561#define TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR 0x41010000u
562
563/**
564 * Peripheral size for core device on rram_ctrl in top earlgrey.
565 *
566 * This is the size (in bytes) of the peripheral's reserved memory area. All
567 * memory-mapped registers associated with this peripheral should have an
568 * address between #TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR and
569 * `TOP_EARLGREY_RRAM_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES`.
570 */
571#define TOP_EARLGREY_RRAM_CTRL_CORE_SIZE_BYTES 0x400u
572
573/**
574 * Peripheral base address for prim device on rram_macro in top earlgrey.
575 *
576 * This should be used with #mmio_region_from_addr to access the memory-mapped
577 * registers associated with the peripheral (usually via a DIF).
578 */
579#define TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR 0x41018000u
580
581/**
582 * Peripheral size for prim device on rram_macro in top earlgrey.
583 *
584 * This is the size (in bytes) of the peripheral's reserved memory area. All
585 * memory-mapped registers associated with this peripheral should have an
586 * address between #TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR and
587 * `TOP_EARLGREY_RRAM_MACRO_PRIM_BASE_ADDR + TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES`.
588 */
589#define TOP_EARLGREY_RRAM_MACRO_PRIM_SIZE_BYTES 0x10u
590
591/**
592 * Peripheral base address for regs device on rv_dm in top earlgrey.
593 *
594 * This should be used with #mmio_region_from_addr to access the memory-mapped
595 * registers associated with the peripheral (usually via a DIF).
596 */
597#define TOP_EARLGREY_RV_DM_REGS_BASE_ADDR 0x41200000u
598
599/**
600 * Peripheral size for regs device on rv_dm in top earlgrey.
601 *
602 * This is the size (in bytes) of the peripheral's reserved memory area. All
603 * memory-mapped registers associated with this peripheral should have an
604 * address between #TOP_EARLGREY_RV_DM_REGS_BASE_ADDR and
605 * `TOP_EARLGREY_RV_DM_REGS_BASE_ADDR + TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES`.
606 */
607#define TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES 0x10u
608
609/**
610 * Peripheral base address for mem device on rv_dm in top earlgrey.
611 *
612 * This should be used with #mmio_region_from_addr to access the memory-mapped
613 * registers associated with the peripheral (usually via a DIF).
614 */
615#define TOP_EARLGREY_RV_DM_MEM_BASE_ADDR 0x10000u
616
617/**
618 * Peripheral size for mem device on rv_dm in top earlgrey.
619 *
620 * This is the size (in bytes) of the peripheral's reserved memory area. All
621 * memory-mapped registers associated with this peripheral should have an
622 * address between #TOP_EARLGREY_RV_DM_MEM_BASE_ADDR and
623 * `TOP_EARLGREY_RV_DM_MEM_BASE_ADDR + TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES`.
624 */
625#define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000u
626
627/**
628 * Peripheral base address for rv_plic in top earlgrey.
629 *
630 * This should be used with #mmio_region_from_addr to access the memory-mapped
631 * registers associated with the peripheral (usually via a DIF).
632 */
633#define TOP_EARLGREY_RV_PLIC_BASE_ADDR 0x48000000u
634
635/**
636 * Peripheral size for rv_plic in top earlgrey.
637 *
638 * This is the size (in bytes) of the peripheral's reserved memory area. All
639 * memory-mapped registers associated with this peripheral should have an
640 * address between #TOP_EARLGREY_RV_PLIC_BASE_ADDR and
641 * `TOP_EARLGREY_RV_PLIC_BASE_ADDR + TOP_EARLGREY_RV_PLIC_SIZE_BYTES`.
642 */
643#define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x8000000u
644
645/**
646 * Peripheral base address for aes in top earlgrey.
647 *
648 * This should be used with #mmio_region_from_addr to access the memory-mapped
649 * registers associated with the peripheral (usually via a DIF).
650 */
651#define TOP_EARLGREY_AES_BASE_ADDR 0x41100000u
652
653/**
654 * Peripheral size for aes in top earlgrey.
655 *
656 * This is the size (in bytes) of the peripheral's reserved memory area. All
657 * memory-mapped registers associated with this peripheral should have an
658 * address between #TOP_EARLGREY_AES_BASE_ADDR and
659 * `TOP_EARLGREY_AES_BASE_ADDR + TOP_EARLGREY_AES_SIZE_BYTES`.
660 */
661#define TOP_EARLGREY_AES_SIZE_BYTES 0x100u
662
663/**
664 * Peripheral base address for hmac in top earlgrey.
665 *
666 * This should be used with #mmio_region_from_addr to access the memory-mapped
667 * registers associated with the peripheral (usually via a DIF).
668 */
669#define TOP_EARLGREY_HMAC_BASE_ADDR 0x41110000u
670
671/**
672 * Peripheral size for hmac in top earlgrey.
673 *
674 * This is the size (in bytes) of the peripheral's reserved memory area. All
675 * memory-mapped registers associated with this peripheral should have an
676 * address between #TOP_EARLGREY_HMAC_BASE_ADDR and
677 * `TOP_EARLGREY_HMAC_BASE_ADDR + TOP_EARLGREY_HMAC_SIZE_BYTES`.
678 */
679#define TOP_EARLGREY_HMAC_SIZE_BYTES 0x2000u
680
681/**
682 * Peripheral base address for kmac in top earlgrey.
683 *
684 * This should be used with #mmio_region_from_addr to access the memory-mapped
685 * registers associated with the peripheral (usually via a DIF).
686 */
687#define TOP_EARLGREY_KMAC_BASE_ADDR 0x41120000u
688
689/**
690 * Peripheral size for kmac in top earlgrey.
691 *
692 * This is the size (in bytes) of the peripheral's reserved memory area. All
693 * memory-mapped registers associated with this peripheral should have an
694 * address between #TOP_EARLGREY_KMAC_BASE_ADDR and
695 * `TOP_EARLGREY_KMAC_BASE_ADDR + TOP_EARLGREY_KMAC_SIZE_BYTES`.
696 */
697#define TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000u
698
699/**
700 * Peripheral base address for otbn in top earlgrey.
701 *
702 * This should be used with #mmio_region_from_addr to access the memory-mapped
703 * registers associated with the peripheral (usually via a DIF).
704 */
705#define TOP_EARLGREY_OTBN_BASE_ADDR 0x41130000u
706
707/**
708 * Peripheral size for otbn in top earlgrey.
709 *
710 * This is the size (in bytes) of the peripheral's reserved memory area. All
711 * memory-mapped registers associated with this peripheral should have an
712 * address between #TOP_EARLGREY_OTBN_BASE_ADDR and
713 * `TOP_EARLGREY_OTBN_BASE_ADDR + TOP_EARLGREY_OTBN_SIZE_BYTES`.
714 */
715#define TOP_EARLGREY_OTBN_SIZE_BYTES 0x10000u
716
717/**
718 * Peripheral base address for keymgr_dpe in top earlgrey.
719 *
720 * This should be used with #mmio_region_from_addr to access the memory-mapped
721 * registers associated with the peripheral (usually via a DIF).
722 */
723#define TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR 0x41140000u
724
725/**
726 * Peripheral size for keymgr_dpe in top earlgrey.
727 *
728 * This is the size (in bytes) of the peripheral's reserved memory area. All
729 * memory-mapped registers associated with this peripheral should have an
730 * address between #TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR and
731 * `TOP_EARLGREY_KEYMGR_DPE_BASE_ADDR + TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES`.
732 */
733#define TOP_EARLGREY_KEYMGR_DPE_SIZE_BYTES 0x200u
734
735/**
736 * Peripheral base address for csrng in top earlgrey.
737 *
738 * This should be used with #mmio_region_from_addr to access the memory-mapped
739 * registers associated with the peripheral (usually via a DIF).
740 */
741#define TOP_EARLGREY_CSRNG_BASE_ADDR 0x41150000u
742
743/**
744 * Peripheral size for csrng in top earlgrey.
745 *
746 * This is the size (in bytes) of the peripheral's reserved memory area. All
747 * memory-mapped registers associated with this peripheral should have an
748 * address between #TOP_EARLGREY_CSRNG_BASE_ADDR and
749 * `TOP_EARLGREY_CSRNG_BASE_ADDR + TOP_EARLGREY_CSRNG_SIZE_BYTES`.
750 */
751#define TOP_EARLGREY_CSRNG_SIZE_BYTES 0x80u
752
753/**
754 * Peripheral base address for entropy_src in top earlgrey.
755 *
756 * This should be used with #mmio_region_from_addr to access the memory-mapped
757 * registers associated with the peripheral (usually via a DIF).
758 */
759#define TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR 0x41160000u
760
761/**
762 * Peripheral size for entropy_src in top earlgrey.
763 *
764 * This is the size (in bytes) of the peripheral's reserved memory area. All
765 * memory-mapped registers associated with this peripheral should have an
766 * address between #TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR and
767 * `TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR + TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES`.
768 */
769#define TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES 0x100u
770
771/**
772 * Peripheral base address for edn0 in top earlgrey.
773 *
774 * This should be used with #mmio_region_from_addr to access the memory-mapped
775 * registers associated with the peripheral (usually via a DIF).
776 */
777#define TOP_EARLGREY_EDN0_BASE_ADDR 0x41170000u
778
779/**
780 * Peripheral size for edn0 in top earlgrey.
781 *
782 * This is the size (in bytes) of the peripheral's reserved memory area. All
783 * memory-mapped registers associated with this peripheral should have an
784 * address between #TOP_EARLGREY_EDN0_BASE_ADDR and
785 * `TOP_EARLGREY_EDN0_BASE_ADDR + TOP_EARLGREY_EDN0_SIZE_BYTES`.
786 */
787#define TOP_EARLGREY_EDN0_SIZE_BYTES 0x80u
788
789/**
790 * Peripheral base address for edn1 in top earlgrey.
791 *
792 * This should be used with #mmio_region_from_addr to access the memory-mapped
793 * registers associated with the peripheral (usually via a DIF).
794 */
795#define TOP_EARLGREY_EDN1_BASE_ADDR 0x41180000u
796
797/**
798 * Peripheral size for edn1 in top earlgrey.
799 *
800 * This is the size (in bytes) of the peripheral's reserved memory area. All
801 * memory-mapped registers associated with this peripheral should have an
802 * address between #TOP_EARLGREY_EDN1_BASE_ADDR and
803 * `TOP_EARLGREY_EDN1_BASE_ADDR + TOP_EARLGREY_EDN1_SIZE_BYTES`.
804 */
805#define TOP_EARLGREY_EDN1_SIZE_BYTES 0x80u
806
807/**
808 * Peripheral base address for regs device on sram_ctrl_main in top earlgrey.
809 *
810 * This should be used with #mmio_region_from_addr to access the memory-mapped
811 * registers associated with the peripheral (usually via a DIF).
812 */
813#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
814
815/**
816 * Peripheral size for regs device on sram_ctrl_main in top earlgrey.
817 *
818 * This is the size (in bytes) of the peripheral's reserved memory area. All
819 * memory-mapped registers associated with this peripheral should have an
820 * address between #TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
821 * `TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
822 */
823#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
824
825/**
826 * Peripheral base address for regs device on sram_ctrl_sec in top earlgrey.
827 *
828 * This should be used with #mmio_region_from_addr to access the memory-mapped
829 * registers associated with the peripheral (usually via a DIF).
830 */
831#define TOP_EARLGREY_SRAM_CTRL_SEC_REGS_BASE_ADDR 0x411D0000u
832
833/**
834 * Peripheral size for regs device on sram_ctrl_sec in top earlgrey.
835 *
836 * This is the size (in bytes) of the peripheral's reserved memory area. All
837 * memory-mapped registers associated with this peripheral should have an
838 * address between #TOP_EARLGREY_SRAM_CTRL_SEC_REGS_BASE_ADDR and
839 * `TOP_EARLGREY_SRAM_CTRL_SEC_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_SEC_REGS_SIZE_BYTES`.
840 */
841#define TOP_EARLGREY_SRAM_CTRL_SEC_REGS_SIZE_BYTES 0x40u
842
843/**
844 * Peripheral base address for regs device on rom_ctrl in top earlgrey.
845 *
846 * This should be used with #mmio_region_from_addr to access the memory-mapped
847 * registers associated with the peripheral (usually via a DIF).
848 */
849#define TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
850
851/**
852 * Peripheral size for regs device on rom_ctrl in top earlgrey.
853 *
854 * This is the size (in bytes) of the peripheral's reserved memory area. All
855 * memory-mapped registers associated with this peripheral should have an
856 * address between #TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR and
857 * `TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES`.
858 */
859#define TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES 0x80u
860
861/**
862 * Peripheral base address for cfg device on rv_core_ibex in top earlgrey.
863 *
864 * This should be used with #mmio_region_from_addr to access the memory-mapped
865 * registers associated with the peripheral (usually via a DIF).
866 */
867#define TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u
868
869/**
870 * Peripheral size for cfg device on rv_core_ibex in top earlgrey.
871 *
872 * This is the size (in bytes) of the peripheral's reserved memory area. All
873 * memory-mapped registers associated with this peripheral should have an
874 * address between #TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR and
875 * `TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES`.
876 */
877#define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u
878
879/**
880 * Peripheral base address for regs device on cheriot_mem_sys in top earlgrey.
881 *
882 * This should be used with #mmio_region_from_addr to access the memory-mapped
883 * registers associated with the peripheral (usually via a DIF).
884 */
885#define TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_BASE_ADDR 0x411B0000u
886
887/**
888 * Peripheral size for regs device on cheriot_mem_sys in top earlgrey.
889 *
890 * This is the size (in bytes) of the peripheral's reserved memory area. All
891 * memory-mapped registers associated with this peripheral should have an
892 * address between #TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_BASE_ADDR and
893 * `TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_BASE_ADDR + TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_SIZE_BYTES`.
894 */
895#define TOP_EARLGREY_CHERIOT_MEM_SYS_REGS_SIZE_BYTES 0x40u
896
897/**
898 * Peripheral base address for regs device on sram_ctrl_meta in top earlgrey.
899 *
900 * This should be used with #mmio_region_from_addr to access the memory-mapped
901 * registers associated with the peripheral (usually via a DIF).
902 */
903#define TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR 0x411A0000u
904
905/**
906 * Peripheral size for regs device on sram_ctrl_meta in top earlgrey.
907 *
908 * This is the size (in bytes) of the peripheral's reserved memory area. All
909 * memory-mapped registers associated with this peripheral should have an
910 * address between #TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR and
911 * `TOP_EARLGREY_SRAM_CTRL_META_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES`.
912 */
913#define TOP_EARLGREY_SRAM_CTRL_META_REGS_SIZE_BYTES 0x40u
914
915
916/**
917 * Memory base address for ram memory on sram_ctrl_ret in top earlgrey.
918 */
919#define TOP_EARLGREY_SRAM_CTRL_RET_RAM_BASE_ADDR 0x40600000u
920
921/**
922 * Memory size for ram memory on sram_ctrl_ret in top earlgrey.
923 */
924#define TOP_EARLGREY_SRAM_CTRL_RET_RAM_SIZE_BYTES 0x2000u
925
926/**
927 * Memory base address for host memory on rram_ctrl in top earlgrey.
928 */
929#define TOP_EARLGREY_RRAM_CTRL_HOST_BASE_ADDR 0x30000000u
930
931/**
932 * Memory size for host memory on rram_ctrl in top earlgrey.
933 */
934#define TOP_EARLGREY_RRAM_CTRL_HOST_SIZE_BYTES 0x200000u
935
936/**
937 * Memory base address for ram memory on sram_ctrl_main in top earlgrey.
938 */
939#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
940
941/**
942 * Memory size for ram memory on sram_ctrl_main in top earlgrey.
943 */
944#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
945
946/**
947 * Memory base address for ram memory on sram_ctrl_sec in top earlgrey.
948 */
949#define TOP_EARLGREY_SRAM_CTRL_SEC_RAM_BASE_ADDR 0x10020000u
950
951/**
952 * Memory size for ram memory on sram_ctrl_sec in top earlgrey.
953 */
954#define TOP_EARLGREY_SRAM_CTRL_SEC_RAM_SIZE_BYTES 0x10000u
955
956/**
957 * Memory base address for rom memory on rom_ctrl in top earlgrey.
958 */
959#define TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR 0x40000u
960
961/**
962 * Memory size for rom memory on rom_ctrl in top earlgrey.
963 */
964#define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x30000u
965
966/**
967 * Memory base address for revbm memory on cheriot_mem_sys in top earlgrey.
968 */
969#define TOP_EARLGREY_CHERIOT_MEM_SYS_REVBM_BASE_ADDR 0x11000000u
970
971/**
972 * Memory size for revbm memory on cheriot_mem_sys in top earlgrey.
973 */
974#define TOP_EARLGREY_CHERIOT_MEM_SYS_REVBM_SIZE_BYTES 0xC00u
975
976/**
977 * Memory base address for ram memory on sram_ctrl_meta in top earlgrey.
978 */
979#define TOP_EARLGREY_SRAM_CTRL_META_RAM_BASE_ADDR 0x11000000u
980
981/**
982 * Memory size for ram memory on sram_ctrl_meta in top earlgrey.
983 */
984#define TOP_EARLGREY_SRAM_CTRL_META_RAM_SIZE_BYTES 0x9800u
985
986
987/**
988 * PLIC Interrupt Source Peripheral.
989 *
990 * Enumeration used to determine which peripheral asserted the corresponding
991 * interrupt.
992 */
993typedef enum top_earlgrey_plic_peripheral {
994 kTopEarlgreyPlicPeripheralUnknown = 0, /**< Unknown Peripheral */
995 kTopEarlgreyPlicPeripheralUart0 = 1, /**< uart0 */
996 kTopEarlgreyPlicPeripheralUart1 = 2, /**< uart1 */
997 kTopEarlgreyPlicPeripheralUart2 = 3, /**< uart2 */
998 kTopEarlgreyPlicPeripheralUart3 = 4, /**< uart3 */
999 kTopEarlgreyPlicPeripheralGpio0 = 5, /**< gpio0 */
1000 kTopEarlgreyPlicPeripheralGpio1 = 6, /**< gpio1 */
1001 kTopEarlgreyPlicPeripheralSpiDevice = 7, /**< spi_device */
1002 kTopEarlgreyPlicPeripheralI2c0 = 8, /**< i2c0 */
1003 kTopEarlgreyPlicPeripheralI2c1 = 9, /**< i2c1 */
1004 kTopEarlgreyPlicPeripheralI2c2 = 10, /**< i2c2 */
1005 kTopEarlgreyPlicPeripheralI3c0 = 11, /**< i3c0 */
1006 kTopEarlgreyPlicPeripheralI3c1 = 12, /**< i3c1 */
1007 kTopEarlgreyPlicPeripheralRvTimer = 13, /**< rv_timer */
1008 kTopEarlgreyPlicPeripheralOtpCtrl = 14, /**< otp_ctrl */
1009 kTopEarlgreyPlicPeripheralAlertHandler = 15, /**< alert_handler */
1010 kTopEarlgreyPlicPeripheralSpiHost0 = 16, /**< spi_host0 */
1011 kTopEarlgreyPlicPeripheralSpiHost1 = 17, /**< spi_host1 */
1012 kTopEarlgreyPlicPeripheralUsbdev = 18, /**< usbdev */
1013 kTopEarlgreyPlicPeripheralPwrmgr = 19, /**< pwrmgr */
1014 kTopEarlgreyPlicPeripheralSysrstCtrl = 20, /**< sysrst_ctrl */
1015 kTopEarlgreyPlicPeripheralAdcCtrl = 21, /**< adc_ctrl */
1016 kTopEarlgreyPlicPeripheralAonTimer = 22, /**< aon_timer */
1017 kTopEarlgreyPlicPeripheralSensorCtrl = 23, /**< sensor_ctrl */
1018 kTopEarlgreyPlicPeripheralRramCtrl = 24, /**< rram_ctrl */
1019 kTopEarlgreyPlicPeripheralHmac = 25, /**< hmac */
1020 kTopEarlgreyPlicPeripheralKmac = 26, /**< kmac */
1021 kTopEarlgreyPlicPeripheralOtbn = 27, /**< otbn */
1022 kTopEarlgreyPlicPeripheralKeymgrDpe = 28, /**< keymgr_dpe */
1023 kTopEarlgreyPlicPeripheralCsrng = 29, /**< csrng */
1024 kTopEarlgreyPlicPeripheralEntropySrc = 30, /**< entropy_src */
1025 kTopEarlgreyPlicPeripheralEdn0 = 31, /**< edn0 */
1026 kTopEarlgreyPlicPeripheralEdn1 = 32, /**< edn1 */
1027 kTopEarlgreyPlicPeripheralCheriotMemSys = 33, /**< cheriot_mem_sys */
1028 kTopEarlgreyPlicPeripheralLast = 33, /**< \internal Final PLIC peripheral */
1029} top_earlgrey_plic_peripheral_t;
1030
1031/**
1032 * PLIC Interrupt Source.
1033 *
1034 * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
1035 * the same peripheral are guaranteed to be consecutive.
1036 */
1037typedef enum top_earlgrey_plic_irq_id {
1038 kTopEarlgreyPlicIrqIdNone = 0, /**< No Interrupt */
1039 kTopEarlgreyPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
1040 kTopEarlgreyPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
1041 kTopEarlgreyPlicIrqIdUart0TxDone = 3, /**< uart0_tx_done */
1042 kTopEarlgreyPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
1043 kTopEarlgreyPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
1044 kTopEarlgreyPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
1045 kTopEarlgreyPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
1046 kTopEarlgreyPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
1047 kTopEarlgreyPlicIrqIdUart0TxEmpty = 9, /**< uart0_tx_empty */
1048 kTopEarlgreyPlicIrqIdUart1TxWatermark = 10, /**< uart1_tx_watermark */
1049 kTopEarlgreyPlicIrqIdUart1RxWatermark = 11, /**< uart1_rx_watermark */
1050 kTopEarlgreyPlicIrqIdUart1TxDone = 12, /**< uart1_tx_done */
1051 kTopEarlgreyPlicIrqIdUart1RxOverflow = 13, /**< uart1_rx_overflow */
1052 kTopEarlgreyPlicIrqIdUart1RxFrameErr = 14, /**< uart1_rx_frame_err */
1053 kTopEarlgreyPlicIrqIdUart1RxBreakErr = 15, /**< uart1_rx_break_err */
1054 kTopEarlgreyPlicIrqIdUart1RxTimeout = 16, /**< uart1_rx_timeout */
1055 kTopEarlgreyPlicIrqIdUart1RxParityErr = 17, /**< uart1_rx_parity_err */
1056 kTopEarlgreyPlicIrqIdUart1TxEmpty = 18, /**< uart1_tx_empty */
1057 kTopEarlgreyPlicIrqIdUart2TxWatermark = 19, /**< uart2_tx_watermark */
1058 kTopEarlgreyPlicIrqIdUart2RxWatermark = 20, /**< uart2_rx_watermark */
1059 kTopEarlgreyPlicIrqIdUart2TxDone = 21, /**< uart2_tx_done */
1060 kTopEarlgreyPlicIrqIdUart2RxOverflow = 22, /**< uart2_rx_overflow */
1061 kTopEarlgreyPlicIrqIdUart2RxFrameErr = 23, /**< uart2_rx_frame_err */
1062 kTopEarlgreyPlicIrqIdUart2RxBreakErr = 24, /**< uart2_rx_break_err */
1063 kTopEarlgreyPlicIrqIdUart2RxTimeout = 25, /**< uart2_rx_timeout */
1064 kTopEarlgreyPlicIrqIdUart2RxParityErr = 26, /**< uart2_rx_parity_err */
1065 kTopEarlgreyPlicIrqIdUart2TxEmpty = 27, /**< uart2_tx_empty */
1066 kTopEarlgreyPlicIrqIdUart3TxWatermark = 28, /**< uart3_tx_watermark */
1067 kTopEarlgreyPlicIrqIdUart3RxWatermark = 29, /**< uart3_rx_watermark */
1068 kTopEarlgreyPlicIrqIdUart3TxDone = 30, /**< uart3_tx_done */
1069 kTopEarlgreyPlicIrqIdUart3RxOverflow = 31, /**< uart3_rx_overflow */
1070 kTopEarlgreyPlicIrqIdUart3RxFrameErr = 32, /**< uart3_rx_frame_err */
1071 kTopEarlgreyPlicIrqIdUart3RxBreakErr = 33, /**< uart3_rx_break_err */
1072 kTopEarlgreyPlicIrqIdUart3RxTimeout = 34, /**< uart3_rx_timeout */
1073 kTopEarlgreyPlicIrqIdUart3RxParityErr = 35, /**< uart3_rx_parity_err */
1074 kTopEarlgreyPlicIrqIdUart3TxEmpty = 36, /**< uart3_tx_empty */
1075 kTopEarlgreyPlicIrqIdGpio0Gpio0 = 37, /**< gpio0_gpio 0 */
1076 kTopEarlgreyPlicIrqIdGpio0Gpio1 = 38, /**< gpio0_gpio 1 */
1077 kTopEarlgreyPlicIrqIdGpio0Gpio2 = 39, /**< gpio0_gpio 2 */
1078 kTopEarlgreyPlicIrqIdGpio0Gpio3 = 40, /**< gpio0_gpio 3 */
1079 kTopEarlgreyPlicIrqIdGpio0Gpio4 = 41, /**< gpio0_gpio 4 */
1080 kTopEarlgreyPlicIrqIdGpio0Gpio5 = 42, /**< gpio0_gpio 5 */
1081 kTopEarlgreyPlicIrqIdGpio0Gpio6 = 43, /**< gpio0_gpio 6 */
1082 kTopEarlgreyPlicIrqIdGpio0Gpio7 = 44, /**< gpio0_gpio 7 */
1083 kTopEarlgreyPlicIrqIdGpio0Gpio8 = 45, /**< gpio0_gpio 8 */
1084 kTopEarlgreyPlicIrqIdGpio0Gpio9 = 46, /**< gpio0_gpio 9 */
1085 kTopEarlgreyPlicIrqIdGpio0Gpio10 = 47, /**< gpio0_gpio 10 */
1086 kTopEarlgreyPlicIrqIdGpio0Gpio11 = 48, /**< gpio0_gpio 11 */
1087 kTopEarlgreyPlicIrqIdGpio0Gpio12 = 49, /**< gpio0_gpio 12 */
1088 kTopEarlgreyPlicIrqIdGpio0Gpio13 = 50, /**< gpio0_gpio 13 */
1089 kTopEarlgreyPlicIrqIdGpio0Gpio14 = 51, /**< gpio0_gpio 14 */
1090 kTopEarlgreyPlicIrqIdGpio0Gpio15 = 52, /**< gpio0_gpio 15 */
1091 kTopEarlgreyPlicIrqIdGpio0Gpio16 = 53, /**< gpio0_gpio 16 */
1092 kTopEarlgreyPlicIrqIdGpio0Gpio17 = 54, /**< gpio0_gpio 17 */
1093 kTopEarlgreyPlicIrqIdGpio0Gpio18 = 55, /**< gpio0_gpio 18 */
1094 kTopEarlgreyPlicIrqIdGpio0Gpio19 = 56, /**< gpio0_gpio 19 */
1095 kTopEarlgreyPlicIrqIdGpio0Gpio20 = 57, /**< gpio0_gpio 20 */
1096 kTopEarlgreyPlicIrqIdGpio0Gpio21 = 58, /**< gpio0_gpio 21 */
1097 kTopEarlgreyPlicIrqIdGpio0Gpio22 = 59, /**< gpio0_gpio 22 */
1098 kTopEarlgreyPlicIrqIdGpio0Gpio23 = 60, /**< gpio0_gpio 23 */
1099 kTopEarlgreyPlicIrqIdGpio0Gpio24 = 61, /**< gpio0_gpio 24 */
1100 kTopEarlgreyPlicIrqIdGpio0Gpio25 = 62, /**< gpio0_gpio 25 */
1101 kTopEarlgreyPlicIrqIdGpio0Gpio26 = 63, /**< gpio0_gpio 26 */
1102 kTopEarlgreyPlicIrqIdGpio0Gpio27 = 64, /**< gpio0_gpio 27 */
1103 kTopEarlgreyPlicIrqIdGpio0Gpio28 = 65, /**< gpio0_gpio 28 */
1104 kTopEarlgreyPlicIrqIdGpio0Gpio29 = 66, /**< gpio0_gpio 29 */
1105 kTopEarlgreyPlicIrqIdGpio0Gpio30 = 67, /**< gpio0_gpio 30 */
1106 kTopEarlgreyPlicIrqIdGpio0Gpio31 = 68, /**< gpio0_gpio 31 */
1107 kTopEarlgreyPlicIrqIdGpio1Gpio0 = 69, /**< gpio1_gpio 0 */
1108 kTopEarlgreyPlicIrqIdGpio1Gpio1 = 70, /**< gpio1_gpio 1 */
1109 kTopEarlgreyPlicIrqIdGpio1Gpio2 = 71, /**< gpio1_gpio 2 */
1110 kTopEarlgreyPlicIrqIdGpio1Gpio3 = 72, /**< gpio1_gpio 3 */
1111 kTopEarlgreyPlicIrqIdGpio1Gpio4 = 73, /**< gpio1_gpio 4 */
1112 kTopEarlgreyPlicIrqIdGpio1Gpio5 = 74, /**< gpio1_gpio 5 */
1113 kTopEarlgreyPlicIrqIdGpio1Gpio6 = 75, /**< gpio1_gpio 6 */
1114 kTopEarlgreyPlicIrqIdGpio1Gpio7 = 76, /**< gpio1_gpio 7 */
1115 kTopEarlgreyPlicIrqIdGpio1Gpio8 = 77, /**< gpio1_gpio 8 */
1116 kTopEarlgreyPlicIrqIdGpio1Gpio9 = 78, /**< gpio1_gpio 9 */
1117 kTopEarlgreyPlicIrqIdGpio1Gpio10 = 79, /**< gpio1_gpio 10 */
1118 kTopEarlgreyPlicIrqIdGpio1Gpio11 = 80, /**< gpio1_gpio 11 */
1119 kTopEarlgreyPlicIrqIdGpio1Gpio12 = 81, /**< gpio1_gpio 12 */
1120 kTopEarlgreyPlicIrqIdGpio1Gpio13 = 82, /**< gpio1_gpio 13 */
1121 kTopEarlgreyPlicIrqIdGpio1Gpio14 = 83, /**< gpio1_gpio 14 */
1122 kTopEarlgreyPlicIrqIdGpio1Gpio15 = 84, /**< gpio1_gpio 15 */
1123 kTopEarlgreyPlicIrqIdGpio1Gpio16 = 85, /**< gpio1_gpio 16 */
1124 kTopEarlgreyPlicIrqIdGpio1Gpio17 = 86, /**< gpio1_gpio 17 */
1125 kTopEarlgreyPlicIrqIdGpio1Gpio18 = 87, /**< gpio1_gpio 18 */
1126 kTopEarlgreyPlicIrqIdGpio1Gpio19 = 88, /**< gpio1_gpio 19 */
1127 kTopEarlgreyPlicIrqIdGpio1Gpio20 = 89, /**< gpio1_gpio 20 */
1128 kTopEarlgreyPlicIrqIdGpio1Gpio21 = 90, /**< gpio1_gpio 21 */
1129 kTopEarlgreyPlicIrqIdGpio1Gpio22 = 91, /**< gpio1_gpio 22 */
1130 kTopEarlgreyPlicIrqIdGpio1Gpio23 = 92, /**< gpio1_gpio 23 */
1131 kTopEarlgreyPlicIrqIdGpio1Gpio24 = 93, /**< gpio1_gpio 24 */
1132 kTopEarlgreyPlicIrqIdGpio1Gpio25 = 94, /**< gpio1_gpio 25 */
1133 kTopEarlgreyPlicIrqIdGpio1Gpio26 = 95, /**< gpio1_gpio 26 */
1134 kTopEarlgreyPlicIrqIdGpio1Gpio27 = 96, /**< gpio1_gpio 27 */
1135 kTopEarlgreyPlicIrqIdGpio1Gpio28 = 97, /**< gpio1_gpio 28 */
1136 kTopEarlgreyPlicIrqIdGpio1Gpio29 = 98, /**< gpio1_gpio 29 */
1137 kTopEarlgreyPlicIrqIdGpio1Gpio30 = 99, /**< gpio1_gpio 30 */
1138 kTopEarlgreyPlicIrqIdGpio1Gpio31 = 100, /**< gpio1_gpio 31 */
1139 kTopEarlgreyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 101, /**< spi_device_upload_cmdfifo_not_empty */
1140 kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 102, /**< spi_device_upload_payload_not_empty */
1141 kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadOverflow = 103, /**< spi_device_upload_payload_overflow */
1142 kTopEarlgreyPlicIrqIdSpiDeviceReadbufWatermark = 104, /**< spi_device_readbuf_watermark */
1143 kTopEarlgreyPlicIrqIdSpiDeviceReadbufFlip = 105, /**< spi_device_readbuf_flip */
1144 kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 106, /**< spi_device_tpm_header_not_empty */
1145 kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 107, /**< spi_device_tpm_rdfifo_cmd_end */
1146 kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoDrop = 108, /**< spi_device_tpm_rdfifo_drop */
1147 kTopEarlgreyPlicIrqIdI2c0FmtThreshold = 109, /**< i2c0_fmt_threshold */
1148 kTopEarlgreyPlicIrqIdI2c0RxThreshold = 110, /**< i2c0_rx_threshold */
1149 kTopEarlgreyPlicIrqIdI2c0AcqThreshold = 111, /**< i2c0_acq_threshold */
1150 kTopEarlgreyPlicIrqIdI2c0RxOverflow = 112, /**< i2c0_rx_overflow */
1151 kTopEarlgreyPlicIrqIdI2c0ControllerHalt = 113, /**< i2c0_controller_halt */
1152 kTopEarlgreyPlicIrqIdI2c0SclInterference = 114, /**< i2c0_scl_interference */
1153 kTopEarlgreyPlicIrqIdI2c0SdaInterference = 115, /**< i2c0_sda_interference */
1154 kTopEarlgreyPlicIrqIdI2c0StretchTimeout = 116, /**< i2c0_stretch_timeout */
1155 kTopEarlgreyPlicIrqIdI2c0SdaUnstable = 117, /**< i2c0_sda_unstable */
1156 kTopEarlgreyPlicIrqIdI2c0CmdComplete = 118, /**< i2c0_cmd_complete */
1157 kTopEarlgreyPlicIrqIdI2c0TxStretch = 119, /**< i2c0_tx_stretch */
1158 kTopEarlgreyPlicIrqIdI2c0TxThreshold = 120, /**< i2c0_tx_threshold */
1159 kTopEarlgreyPlicIrqIdI2c0AcqStretch = 121, /**< i2c0_acq_stretch */
1160 kTopEarlgreyPlicIrqIdI2c0UnexpStop = 122, /**< i2c0_unexp_stop */
1161 kTopEarlgreyPlicIrqIdI2c0HostTimeout = 123, /**< i2c0_host_timeout */
1162 kTopEarlgreyPlicIrqIdI2c1FmtThreshold = 124, /**< i2c1_fmt_threshold */
1163 kTopEarlgreyPlicIrqIdI2c1RxThreshold = 125, /**< i2c1_rx_threshold */
1164 kTopEarlgreyPlicIrqIdI2c1AcqThreshold = 126, /**< i2c1_acq_threshold */
1165 kTopEarlgreyPlicIrqIdI2c1RxOverflow = 127, /**< i2c1_rx_overflow */
1166 kTopEarlgreyPlicIrqIdI2c1ControllerHalt = 128, /**< i2c1_controller_halt */
1167 kTopEarlgreyPlicIrqIdI2c1SclInterference = 129, /**< i2c1_scl_interference */
1168 kTopEarlgreyPlicIrqIdI2c1SdaInterference = 130, /**< i2c1_sda_interference */
1169 kTopEarlgreyPlicIrqIdI2c1StretchTimeout = 131, /**< i2c1_stretch_timeout */
1170 kTopEarlgreyPlicIrqIdI2c1SdaUnstable = 132, /**< i2c1_sda_unstable */
1171 kTopEarlgreyPlicIrqIdI2c1CmdComplete = 133, /**< i2c1_cmd_complete */
1172 kTopEarlgreyPlicIrqIdI2c1TxStretch = 134, /**< i2c1_tx_stretch */
1173 kTopEarlgreyPlicIrqIdI2c1TxThreshold = 135, /**< i2c1_tx_threshold */
1174 kTopEarlgreyPlicIrqIdI2c1AcqStretch = 136, /**< i2c1_acq_stretch */
1175 kTopEarlgreyPlicIrqIdI2c1UnexpStop = 137, /**< i2c1_unexp_stop */
1176 kTopEarlgreyPlicIrqIdI2c1HostTimeout = 138, /**< i2c1_host_timeout */
1177 kTopEarlgreyPlicIrqIdI2c2FmtThreshold = 139, /**< i2c2_fmt_threshold */
1178 kTopEarlgreyPlicIrqIdI2c2RxThreshold = 140, /**< i2c2_rx_threshold */
1179 kTopEarlgreyPlicIrqIdI2c2AcqThreshold = 141, /**< i2c2_acq_threshold */
1180 kTopEarlgreyPlicIrqIdI2c2RxOverflow = 142, /**< i2c2_rx_overflow */
1181 kTopEarlgreyPlicIrqIdI2c2ControllerHalt = 143, /**< i2c2_controller_halt */
1182 kTopEarlgreyPlicIrqIdI2c2SclInterference = 144, /**< i2c2_scl_interference */
1183 kTopEarlgreyPlicIrqIdI2c2SdaInterference = 145, /**< i2c2_sda_interference */
1184 kTopEarlgreyPlicIrqIdI2c2StretchTimeout = 146, /**< i2c2_stretch_timeout */
1185 kTopEarlgreyPlicIrqIdI2c2SdaUnstable = 147, /**< i2c2_sda_unstable */
1186 kTopEarlgreyPlicIrqIdI2c2CmdComplete = 148, /**< i2c2_cmd_complete */
1187 kTopEarlgreyPlicIrqIdI2c2TxStretch = 149, /**< i2c2_tx_stretch */
1188 kTopEarlgreyPlicIrqIdI2c2TxThreshold = 150, /**< i2c2_tx_threshold */
1189 kTopEarlgreyPlicIrqIdI2c2AcqStretch = 151, /**< i2c2_acq_stretch */
1190 kTopEarlgreyPlicIrqIdI2c2UnexpStop = 152, /**< i2c2_unexp_stop */
1191 kTopEarlgreyPlicIrqIdI2c2HostTimeout = 153, /**< i2c2_host_timeout */
1192 kTopEarlgreyPlicIrqIdI3c0Hci = 154, /**< i3c0_hci */
1193 kTopEarlgreyPlicIrqIdI3c0Targ = 155, /**< i3c0_targ */
1194 kTopEarlgreyPlicIrqIdI3c1Hci = 156, /**< i3c1_hci */
1195 kTopEarlgreyPlicIrqIdI3c1Targ = 157, /**< i3c1_targ */
1196 kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 158, /**< rv_timer_timer_expired_hart0_timer0 */
1197 kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 159, /**< otp_ctrl_otp_operation_done */
1198 kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 160, /**< otp_ctrl_otp_error */
1199 kTopEarlgreyPlicIrqIdAlertHandlerClassa = 161, /**< alert_handler_classa */
1200 kTopEarlgreyPlicIrqIdAlertHandlerClassb = 162, /**< alert_handler_classb */
1201 kTopEarlgreyPlicIrqIdAlertHandlerClassc = 163, /**< alert_handler_classc */
1202 kTopEarlgreyPlicIrqIdAlertHandlerClassd = 164, /**< alert_handler_classd */
1203 kTopEarlgreyPlicIrqIdSpiHost0Error = 165, /**< spi_host0_error */
1204 kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 166, /**< spi_host0_spi_event */
1205 kTopEarlgreyPlicIrqIdSpiHost1Error = 167, /**< spi_host1_error */
1206 kTopEarlgreyPlicIrqIdSpiHost1SpiEvent = 168, /**< spi_host1_spi_event */
1207 kTopEarlgreyPlicIrqIdUsbdevPktReceived = 169, /**< usbdev_pkt_received */
1208 kTopEarlgreyPlicIrqIdUsbdevPktSent = 170, /**< usbdev_pkt_sent */
1209 kTopEarlgreyPlicIrqIdUsbdevDisconnected = 171, /**< usbdev_disconnected */
1210 kTopEarlgreyPlicIrqIdUsbdevHostLost = 172, /**< usbdev_host_lost */
1211 kTopEarlgreyPlicIrqIdUsbdevLinkReset = 173, /**< usbdev_link_reset */
1212 kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 174, /**< usbdev_link_suspend */
1213 kTopEarlgreyPlicIrqIdUsbdevLinkResume = 175, /**< usbdev_link_resume */
1214 kTopEarlgreyPlicIrqIdUsbdevAvOutEmpty = 176, /**< usbdev_av_out_empty */
1215 kTopEarlgreyPlicIrqIdUsbdevRxFull = 177, /**< usbdev_rx_full */
1216 kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 178, /**< usbdev_av_overflow */
1217 kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 179, /**< usbdev_link_in_err */
1218 kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 180, /**< usbdev_rx_crc_err */
1219 kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 181, /**< usbdev_rx_pid_err */
1220 kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 182, /**< usbdev_rx_bitstuff_err */
1221 kTopEarlgreyPlicIrqIdUsbdevFrame = 183, /**< usbdev_frame */
1222 kTopEarlgreyPlicIrqIdUsbdevPowered = 184, /**< usbdev_powered */
1223 kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 185, /**< usbdev_link_out_err */
1224 kTopEarlgreyPlicIrqIdUsbdevAvSetupEmpty = 186, /**< usbdev_av_setup_empty */
1225 kTopEarlgreyPlicIrqIdPwrmgrWakeup = 187, /**< pwrmgr_wakeup */
1226 kTopEarlgreyPlicIrqIdSysrstCtrlEventDetected = 188, /**< sysrst_ctrl_event_detected */
1227 kTopEarlgreyPlicIrqIdAdcCtrlMatchPending = 189, /**< adc_ctrl_match_pending */
1228 kTopEarlgreyPlicIrqIdAonTimerWkupTimerExpired = 190, /**< aon_timer_wkup_timer_expired */
1229 kTopEarlgreyPlicIrqIdAonTimerWdogTimerBark = 191, /**< aon_timer_wdog_timer_bark */
1230 kTopEarlgreyPlicIrqIdSensorCtrlIoStatusChange = 192, /**< sensor_ctrl_io_status_change */
1231 kTopEarlgreyPlicIrqIdSensorCtrlInitStatusChange = 193, /**< sensor_ctrl_init_status_change */
1232 kTopEarlgreyPlicIrqIdRramCtrlWrEmpty = 194, /**< rram_ctrl_wr_empty */
1233 kTopEarlgreyPlicIrqIdRramCtrlWrLvl = 195, /**< rram_ctrl_wr_lvl */
1234 kTopEarlgreyPlicIrqIdRramCtrlRdFull = 196, /**< rram_ctrl_rd_full */
1235 kTopEarlgreyPlicIrqIdRramCtrlRdLvl = 197, /**< rram_ctrl_rd_lvl */
1236 kTopEarlgreyPlicIrqIdRramCtrlOpDone = 198, /**< rram_ctrl_op_done */
1237 kTopEarlgreyPlicIrqIdRramCtrlCorr1Err = 199, /**< rram_ctrl_corr1_err */
1238 kTopEarlgreyPlicIrqIdRramCtrlCorr2Err = 200, /**< rram_ctrl_corr2_err */
1239 kTopEarlgreyPlicIrqIdHmacHmacDone = 201, /**< hmac_hmac_done */
1240 kTopEarlgreyPlicIrqIdHmacFifoEmpty = 202, /**< hmac_fifo_empty */
1241 kTopEarlgreyPlicIrqIdHmacHmacErr = 203, /**< hmac_hmac_err */
1242 kTopEarlgreyPlicIrqIdKmacKmacDone = 204, /**< kmac_kmac_done */
1243 kTopEarlgreyPlicIrqIdKmacFifoEmpty = 205, /**< kmac_fifo_empty */
1244 kTopEarlgreyPlicIrqIdKmacKmacErr = 206, /**< kmac_kmac_err */
1245 kTopEarlgreyPlicIrqIdOtbnDone = 207, /**< otbn_done */
1246 kTopEarlgreyPlicIrqIdKeymgrDpeOpDone = 208, /**< keymgr_dpe_op_done */
1247 kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 209, /**< csrng_cs_cmd_req_done */
1248 kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 210, /**< csrng_cs_entropy_req */
1249 kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 211, /**< csrng_cs_hw_inst_exc */
1250 kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 212, /**< csrng_cs_fatal_err */
1251 kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 213, /**< entropy_src_es_entropy_valid */
1252 kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 214, /**< entropy_src_es_health_test_failed */
1253 kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 215, /**< entropy_src_es_observe_fifo_ready */
1254 kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 216, /**< entropy_src_es_fatal_err */
1255 kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 217, /**< edn0_edn_cmd_req_done */
1256 kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 218, /**< edn0_edn_fatal_err */
1257 kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 219, /**< edn1_edn_cmd_req_done */
1258 kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 220, /**< edn1_edn_fatal_err */
1259 kTopEarlgreyPlicIrqIdCheriotMemSysTbreDone = 221, /**< cheriot_mem_sys_tbre_done */
1260 kTopEarlgreyPlicIrqIdLast = 221, /**< \internal The Last Valid Interrupt ID. */
1261} top_earlgrey_plic_irq_id_t;
1262
1263/**
1264 * PLIC Interrupt Source to Peripheral Map
1265 *
1266 * This array is a mapping from `top_earlgrey_plic_irq_id_t` to
1267 * `top_earlgrey_plic_peripheral_t`.
1268 */
1269extern const top_earlgrey_plic_peripheral_t
1270 top_earlgrey_plic_interrupt_for_peripheral[222];
1271
1272/**
1273 * PLIC Interrupt Target.
1274 *
1275 * Enumeration used to determine which set of IE, CC, threshold registers to
1276 * access for a given interrupt target.
1277 */
1278typedef enum top_earlgrey_plic_target {
1279 kTopEarlgreyPlicTargetIbex0 = 0, /**< Ibex Core 0 */
1280 kTopEarlgreyPlicTargetLast = 0, /**< \internal Final PLIC target */
1281} top_earlgrey_plic_target_t;
1282
1283
1284/**
1285 * Alert Handler Source Peripheral.
1286 *
1287 * Enumeration used to determine which peripheral asserted the corresponding
1288 * alert.
1289 */
1290typedef enum top_earlgrey_alert_peripheral {
1291 kTopEarlgreyAlertPeripheralExternal = 0, /**< External Peripheral */
1292 kTopEarlgreyAlertPeripheralUart0 = 1, /**< uart0 */
1293 kTopEarlgreyAlertPeripheralUart1 = 2, /**< uart1 */
1294 kTopEarlgreyAlertPeripheralUart2 = 3, /**< uart2 */
1295 kTopEarlgreyAlertPeripheralUart3 = 4, /**< uart3 */
1296 kTopEarlgreyAlertPeripheralGpio0 = 5, /**< gpio0 */
1297 kTopEarlgreyAlertPeripheralGpio1 = 6, /**< gpio1 */
1298 kTopEarlgreyAlertPeripheralSpiDevice = 7, /**< spi_device */
1299 kTopEarlgreyAlertPeripheralI2c0 = 8, /**< i2c0 */
1300 kTopEarlgreyAlertPeripheralI2c1 = 9, /**< i2c1 */
1301 kTopEarlgreyAlertPeripheralI2c2 = 10, /**< i2c2 */
1302 kTopEarlgreyAlertPeripheralI3c0 = 11, /**< i3c0 */
1303 kTopEarlgreyAlertPeripheralI3c1 = 12, /**< i3c1 */
1304 kTopEarlgreyAlertPeripheralRvTimer = 13, /**< rv_timer */
1305 kTopEarlgreyAlertPeripheralOtpCtrl = 14, /**< otp_ctrl */
1306 kTopEarlgreyAlertPeripheralLcCtrl = 15, /**< lc_ctrl */
1307 kTopEarlgreyAlertPeripheralSpiHost0 = 16, /**< spi_host0 */
1308 kTopEarlgreyAlertPeripheralSpiHost1 = 17, /**< spi_host1 */
1309 kTopEarlgreyAlertPeripheralUsbdev = 18, /**< usbdev */
1310 kTopEarlgreyAlertPeripheralPwrmgr = 19, /**< pwrmgr */
1311 kTopEarlgreyAlertPeripheralRstmgr = 20, /**< rstmgr */
1312 kTopEarlgreyAlertPeripheralClkmgr = 21, /**< clkmgr */
1313 kTopEarlgreyAlertPeripheralSysrstCtrl = 22, /**< sysrst_ctrl */
1314 kTopEarlgreyAlertPeripheralAdcCtrl = 23, /**< adc_ctrl */
1315 kTopEarlgreyAlertPeripheralPinmux = 24, /**< pinmux */
1316 kTopEarlgreyAlertPeripheralAonTimer = 25, /**< aon_timer */
1317 kTopEarlgreyAlertPeripheralSensorCtrl = 26, /**< sensor_ctrl */
1318 kTopEarlgreyAlertPeripheralSramCtrlRet = 27, /**< sram_ctrl_ret */
1319 kTopEarlgreyAlertPeripheralRramCtrl = 28, /**< rram_ctrl */
1320 kTopEarlgreyAlertPeripheralRvDm = 29, /**< rv_dm */
1321 kTopEarlgreyAlertPeripheralRvPlic = 30, /**< rv_plic */
1322 kTopEarlgreyAlertPeripheralAes = 31, /**< aes */
1323 kTopEarlgreyAlertPeripheralHmac = 32, /**< hmac */
1324 kTopEarlgreyAlertPeripheralKmac = 33, /**< kmac */
1325 kTopEarlgreyAlertPeripheralOtbn = 34, /**< otbn */
1326 kTopEarlgreyAlertPeripheralKeymgrDpe = 35, /**< keymgr_dpe */
1327 kTopEarlgreyAlertPeripheralCsrng = 36, /**< csrng */
1328 kTopEarlgreyAlertPeripheralEntropySrc = 37, /**< entropy_src */
1329 kTopEarlgreyAlertPeripheralEdn0 = 38, /**< edn0 */
1330 kTopEarlgreyAlertPeripheralEdn1 = 39, /**< edn1 */
1331 kTopEarlgreyAlertPeripheralSramCtrlMain = 40, /**< sram_ctrl_main */
1332 kTopEarlgreyAlertPeripheralSramCtrlSec = 41, /**< sram_ctrl_sec */
1333 kTopEarlgreyAlertPeripheralRomCtrl = 42, /**< rom_ctrl */
1334 kTopEarlgreyAlertPeripheralRvCoreIbex = 43, /**< rv_core_ibex */
1335 kTopEarlgreyAlertPeripheralCheriotMemSys = 44, /**< cheriot_mem_sys */
1336 kTopEarlgreyAlertPeripheralSramCtrlMeta = 45, /**< sram_ctrl_meta */
1337 kTopEarlgreyAlertPeripheralLast = 45, /**< \internal Final Alert peripheral */
1338} top_earlgrey_alert_peripheral_t;
1339
1340/**
1341 * Alert Handler Alert Source.
1342 *
1343 * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
1344 * the same peripheral are guaranteed to be consecutive.
1345 */
1346typedef enum top_earlgrey_alert_id {
1347 kTopEarlgreyAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */
1348 kTopEarlgreyAlertIdUart1FatalFault = 1, /**< uart1_fatal_fault */
1349 kTopEarlgreyAlertIdUart2FatalFault = 2, /**< uart2_fatal_fault */
1350 kTopEarlgreyAlertIdUart3FatalFault = 3, /**< uart3_fatal_fault */
1351 kTopEarlgreyAlertIdGpio0FatalFault = 4, /**< gpio0_fatal_fault */
1352 kTopEarlgreyAlertIdGpio1FatalFault = 5, /**< gpio1_fatal_fault */
1353 kTopEarlgreyAlertIdSpiDeviceFatalFault = 6, /**< spi_device_fatal_fault */
1354 kTopEarlgreyAlertIdI2c0FatalFault = 7, /**< i2c0_fatal_fault */
1355 kTopEarlgreyAlertIdI2c1FatalFault = 8, /**< i2c1_fatal_fault */
1356 kTopEarlgreyAlertIdI2c2FatalFault = 9, /**< i2c2_fatal_fault */
1357 kTopEarlgreyAlertIdI3c0FatalFault = 10, /**< i3c0_fatal_fault */
1358 kTopEarlgreyAlertIdI3c1FatalFault = 11, /**< i3c1_fatal_fault */
1359 kTopEarlgreyAlertIdRvTimerFatalFault = 12, /**< rv_timer_fatal_fault */
1360 kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 13, /**< otp_ctrl_fatal_macro_error */
1361 kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 14, /**< otp_ctrl_fatal_check_error */
1362 kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 15, /**< otp_ctrl_fatal_bus_integ_error */
1363 kTopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert = 16, /**< otp_ctrl_fatal_prim_otp_alert */
1364 kTopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert = 17, /**< otp_ctrl_recov_prim_otp_alert */
1365 kTopEarlgreyAlertIdLcCtrlFatalProgError = 18, /**< lc_ctrl_fatal_prog_error */
1366 kTopEarlgreyAlertIdLcCtrlFatalStateError = 19, /**< lc_ctrl_fatal_state_error */
1367 kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 20, /**< lc_ctrl_fatal_bus_integ_error */
1368 kTopEarlgreyAlertIdSpiHost0FatalFault = 21, /**< spi_host0_fatal_fault */
1369 kTopEarlgreyAlertIdSpiHost1FatalFault = 22, /**< spi_host1_fatal_fault */
1370 kTopEarlgreyAlertIdUsbdevFatalFault = 23, /**< usbdev_fatal_fault */
1371 kTopEarlgreyAlertIdPwrmgrFatalFault = 24, /**< pwrmgr_fatal_fault */
1372 kTopEarlgreyAlertIdRstmgrFatalFault = 25, /**< rstmgr_fatal_fault */
1373 kTopEarlgreyAlertIdRstmgrFatalCnstyFault = 26, /**< rstmgr_fatal_cnsty_fault */
1374 kTopEarlgreyAlertIdClkmgrRecovFault = 27, /**< clkmgr_recov_fault */
1375 kTopEarlgreyAlertIdClkmgrFatalFault = 28, /**< clkmgr_fatal_fault */
1376 kTopEarlgreyAlertIdSysrstCtrlFatalFault = 29, /**< sysrst_ctrl_fatal_fault */
1377 kTopEarlgreyAlertIdAdcCtrlFatalFault = 30, /**< adc_ctrl_fatal_fault */
1378 kTopEarlgreyAlertIdPinmuxFatalFault = 31, /**< pinmux_fatal_fault */
1379 kTopEarlgreyAlertIdAonTimerFatalFault = 32, /**< aon_timer_fatal_fault */
1380 kTopEarlgreyAlertIdSensorCtrlRecovAlert = 33, /**< sensor_ctrl_recov_alert */
1381 kTopEarlgreyAlertIdSensorCtrlFatalAlert = 34, /**< sensor_ctrl_fatal_alert */
1382 kTopEarlgreyAlertIdSramCtrlRetFatalError = 35, /**< sram_ctrl_ret_fatal_error */
1383 kTopEarlgreyAlertIdRramCtrlRecovErr = 36, /**< rram_ctrl_recov_err */
1384 kTopEarlgreyAlertIdRramCtrlFatalStdErr = 37, /**< rram_ctrl_fatal_std_err */
1385 kTopEarlgreyAlertIdRramCtrlFatalErr = 38, /**< rram_ctrl_fatal_err */
1386 kTopEarlgreyAlertIdRramCtrlFatalMacroErr = 39, /**< rram_ctrl_fatal_macro_err */
1387 kTopEarlgreyAlertIdRramCtrlRecovMacroErr = 40, /**< rram_ctrl_recov_macro_err */
1388 kTopEarlgreyAlertIdRvDmFatalFault = 41, /**< rv_dm_fatal_fault */
1389 kTopEarlgreyAlertIdRvPlicFatalFault = 42, /**< rv_plic_fatal_fault */
1390 kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 43, /**< aes_recov_ctrl_update_err */
1391 kTopEarlgreyAlertIdAesFatalFault = 44, /**< aes_fatal_fault */
1392 kTopEarlgreyAlertIdHmacFatalFault = 45, /**< hmac_fatal_fault */
1393 kTopEarlgreyAlertIdKmacRecovOperationErr = 46, /**< kmac_recov_operation_err */
1394 kTopEarlgreyAlertIdKmacFatalFaultErr = 47, /**< kmac_fatal_fault_err */
1395 kTopEarlgreyAlertIdOtbnFatal = 48, /**< otbn_fatal */
1396 kTopEarlgreyAlertIdOtbnRecov = 49, /**< otbn_recov */
1397 kTopEarlgreyAlertIdKeymgrDpeRecovOperationErr = 50, /**< keymgr_dpe_recov_operation_err */
1398 kTopEarlgreyAlertIdKeymgrDpeFatalFaultErr = 51, /**< keymgr_dpe_fatal_fault_err */
1399 kTopEarlgreyAlertIdCsrngRecovAlert = 52, /**< csrng_recov_alert */
1400 kTopEarlgreyAlertIdCsrngFatalAlert = 53, /**< csrng_fatal_alert */
1401 kTopEarlgreyAlertIdEntropySrcRecovAlert = 54, /**< entropy_src_recov_alert */
1402 kTopEarlgreyAlertIdEntropySrcFatalAlert = 55, /**< entropy_src_fatal_alert */
1403 kTopEarlgreyAlertIdEdn0RecovAlert = 56, /**< edn0_recov_alert */
1404 kTopEarlgreyAlertIdEdn0FatalAlert = 57, /**< edn0_fatal_alert */
1405 kTopEarlgreyAlertIdEdn1RecovAlert = 58, /**< edn1_recov_alert */
1406 kTopEarlgreyAlertIdEdn1FatalAlert = 59, /**< edn1_fatal_alert */
1407 kTopEarlgreyAlertIdSramCtrlMainFatalError = 60, /**< sram_ctrl_main_fatal_error */
1408 kTopEarlgreyAlertIdSramCtrlSecFatalError = 61, /**< sram_ctrl_sec_fatal_error */
1409 kTopEarlgreyAlertIdRomCtrlFatal = 62, /**< rom_ctrl_fatal */
1410 kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 63, /**< rv_core_ibex_fatal_sw_err */
1411 kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 64, /**< rv_core_ibex_recov_sw_err */
1412 kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 65, /**< rv_core_ibex_fatal_hw_err */
1413 kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 66, /**< rv_core_ibex_recov_hw_err */
1414 kTopEarlgreyAlertIdCheriotMemSysFatalFault = 67, /**< cheriot_mem_sys_fatal_fault */
1415 kTopEarlgreyAlertIdSramCtrlMetaFatalError = 68, /**< sram_ctrl_meta_fatal_error */
1416 kTopEarlgreyAlertIdLast = 68, /**< \internal The Last Valid Alert ID. */
1417} top_earlgrey_alert_id_t;
1418
1419/**
1420 * Alert Handler Alert Source to Peripheral Map
1421 *
1422 * This array is a mapping from `top_earlgrey_alert_id_t` to
1423 * `top_earlgrey_alert_peripheral_t`.
1424 */
1425extern const top_earlgrey_alert_peripheral_t
1426 top_earlgrey_alert_for_peripheral[69];
1427
1428#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
1429
1430// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
1431// 0 and 1 are tied to value 0 and 1
1432#define NUM_MIO_PADS 47
1433#define NUM_DIO_PADS 16
1434
1435#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
1436
1437/**
1438 * Pinmux Peripheral Input.
1439 */
1440typedef enum top_earlgrey_pinmux_peripheral_in {
1441 kTopEarlgreyPinmuxPeripheralInGpio0Gpio0 = 0, /**< Peripheral Input 0 */
1442 kTopEarlgreyPinmuxPeripheralInGpio0Gpio1 = 1, /**< Peripheral Input 1 */
1443 kTopEarlgreyPinmuxPeripheralInGpio0Gpio2 = 2, /**< Peripheral Input 2 */
1444 kTopEarlgreyPinmuxPeripheralInGpio0Gpio3 = 3, /**< Peripheral Input 3 */
1445 kTopEarlgreyPinmuxPeripheralInGpio0Gpio4 = 4, /**< Peripheral Input 4 */
1446 kTopEarlgreyPinmuxPeripheralInGpio0Gpio5 = 5, /**< Peripheral Input 5 */
1447 kTopEarlgreyPinmuxPeripheralInGpio0Gpio6 = 6, /**< Peripheral Input 6 */
1448 kTopEarlgreyPinmuxPeripheralInGpio0Gpio7 = 7, /**< Peripheral Input 7 */
1449 kTopEarlgreyPinmuxPeripheralInGpio0Gpio8 = 8, /**< Peripheral Input 8 */
1450 kTopEarlgreyPinmuxPeripheralInGpio0Gpio9 = 9, /**< Peripheral Input 9 */
1451 kTopEarlgreyPinmuxPeripheralInGpio0Gpio10 = 10, /**< Peripheral Input 10 */
1452 kTopEarlgreyPinmuxPeripheralInGpio0Gpio11 = 11, /**< Peripheral Input 11 */
1453 kTopEarlgreyPinmuxPeripheralInGpio0Gpio12 = 12, /**< Peripheral Input 12 */
1454 kTopEarlgreyPinmuxPeripheralInGpio0Gpio13 = 13, /**< Peripheral Input 13 */
1455 kTopEarlgreyPinmuxPeripheralInGpio0Gpio14 = 14, /**< Peripheral Input 14 */
1456 kTopEarlgreyPinmuxPeripheralInGpio0Gpio15 = 15, /**< Peripheral Input 15 */
1457 kTopEarlgreyPinmuxPeripheralInGpio0Gpio16 = 16, /**< Peripheral Input 16 */
1458 kTopEarlgreyPinmuxPeripheralInGpio0Gpio17 = 17, /**< Peripheral Input 17 */
1459 kTopEarlgreyPinmuxPeripheralInGpio0Gpio18 = 18, /**< Peripheral Input 18 */
1460 kTopEarlgreyPinmuxPeripheralInGpio0Gpio19 = 19, /**< Peripheral Input 19 */
1461 kTopEarlgreyPinmuxPeripheralInGpio0Gpio20 = 20, /**< Peripheral Input 20 */
1462 kTopEarlgreyPinmuxPeripheralInGpio0Gpio21 = 21, /**< Peripheral Input 21 */
1463 kTopEarlgreyPinmuxPeripheralInGpio0Gpio22 = 22, /**< Peripheral Input 22 */
1464 kTopEarlgreyPinmuxPeripheralInGpio0Gpio23 = 23, /**< Peripheral Input 23 */
1465 kTopEarlgreyPinmuxPeripheralInGpio0Gpio24 = 24, /**< Peripheral Input 24 */
1466 kTopEarlgreyPinmuxPeripheralInGpio0Gpio25 = 25, /**< Peripheral Input 25 */
1467 kTopEarlgreyPinmuxPeripheralInGpio0Gpio26 = 26, /**< Peripheral Input 26 */
1468 kTopEarlgreyPinmuxPeripheralInGpio0Gpio27 = 27, /**< Peripheral Input 27 */
1469 kTopEarlgreyPinmuxPeripheralInGpio0Gpio28 = 28, /**< Peripheral Input 28 */
1470 kTopEarlgreyPinmuxPeripheralInGpio0Gpio29 = 29, /**< Peripheral Input 29 */
1471 kTopEarlgreyPinmuxPeripheralInGpio0Gpio30 = 30, /**< Peripheral Input 30 */
1472 kTopEarlgreyPinmuxPeripheralInGpio0Gpio31 = 31, /**< Peripheral Input 31 */
1473 kTopEarlgreyPinmuxPeripheralInGpio1Gpio0 = 32, /**< Peripheral Input 32 */
1474 kTopEarlgreyPinmuxPeripheralInGpio1Gpio1 = 33, /**< Peripheral Input 33 */
1475 kTopEarlgreyPinmuxPeripheralInGpio1Gpio2 = 34, /**< Peripheral Input 34 */
1476 kTopEarlgreyPinmuxPeripheralInGpio1Gpio3 = 35, /**< Peripheral Input 35 */
1477 kTopEarlgreyPinmuxPeripheralInGpio1Gpio4 = 36, /**< Peripheral Input 36 */
1478 kTopEarlgreyPinmuxPeripheralInGpio1Gpio5 = 37, /**< Peripheral Input 37 */
1479 kTopEarlgreyPinmuxPeripheralInGpio1Gpio6 = 38, /**< Peripheral Input 38 */
1480 kTopEarlgreyPinmuxPeripheralInGpio1Gpio7 = 39, /**< Peripheral Input 39 */
1481 kTopEarlgreyPinmuxPeripheralInGpio1Gpio8 = 40, /**< Peripheral Input 40 */
1482 kTopEarlgreyPinmuxPeripheralInGpio1Gpio9 = 41, /**< Peripheral Input 41 */
1483 kTopEarlgreyPinmuxPeripheralInGpio1Gpio10 = 42, /**< Peripheral Input 42 */
1484 kTopEarlgreyPinmuxPeripheralInGpio1Gpio11 = 43, /**< Peripheral Input 43 */
1485 kTopEarlgreyPinmuxPeripheralInGpio1Gpio12 = 44, /**< Peripheral Input 44 */
1486 kTopEarlgreyPinmuxPeripheralInGpio1Gpio13 = 45, /**< Peripheral Input 45 */
1487 kTopEarlgreyPinmuxPeripheralInGpio1Gpio14 = 46, /**< Peripheral Input 46 */
1488 kTopEarlgreyPinmuxPeripheralInGpio1Gpio15 = 47, /**< Peripheral Input 47 */
1489 kTopEarlgreyPinmuxPeripheralInGpio1Gpio16 = 48, /**< Peripheral Input 48 */
1490 kTopEarlgreyPinmuxPeripheralInGpio1Gpio17 = 49, /**< Peripheral Input 49 */
1491 kTopEarlgreyPinmuxPeripheralInGpio1Gpio18 = 50, /**< Peripheral Input 50 */
1492 kTopEarlgreyPinmuxPeripheralInGpio1Gpio19 = 51, /**< Peripheral Input 51 */
1493 kTopEarlgreyPinmuxPeripheralInGpio1Gpio20 = 52, /**< Peripheral Input 52 */
1494 kTopEarlgreyPinmuxPeripheralInGpio1Gpio21 = 53, /**< Peripheral Input 53 */
1495 kTopEarlgreyPinmuxPeripheralInGpio1Gpio22 = 54, /**< Peripheral Input 54 */
1496 kTopEarlgreyPinmuxPeripheralInGpio1Gpio23 = 55, /**< Peripheral Input 55 */
1497 kTopEarlgreyPinmuxPeripheralInGpio1Gpio24 = 56, /**< Peripheral Input 56 */
1498 kTopEarlgreyPinmuxPeripheralInGpio1Gpio25 = 57, /**< Peripheral Input 57 */
1499 kTopEarlgreyPinmuxPeripheralInGpio1Gpio26 = 58, /**< Peripheral Input 58 */
1500 kTopEarlgreyPinmuxPeripheralInGpio1Gpio27 = 59, /**< Peripheral Input 59 */
1501 kTopEarlgreyPinmuxPeripheralInGpio1Gpio28 = 60, /**< Peripheral Input 60 */
1502 kTopEarlgreyPinmuxPeripheralInGpio1Gpio29 = 61, /**< Peripheral Input 61 */
1503 kTopEarlgreyPinmuxPeripheralInGpio1Gpio30 = 62, /**< Peripheral Input 62 */
1504 kTopEarlgreyPinmuxPeripheralInGpio1Gpio31 = 63, /**< Peripheral Input 63 */
1505 kTopEarlgreyPinmuxPeripheralInI2c0Sda = 64, /**< Peripheral Input 64 */
1506 kTopEarlgreyPinmuxPeripheralInI2c0Scl = 65, /**< Peripheral Input 65 */
1507 kTopEarlgreyPinmuxPeripheralInI2c1Sda = 66, /**< Peripheral Input 66 */
1508 kTopEarlgreyPinmuxPeripheralInI2c1Scl = 67, /**< Peripheral Input 67 */
1509 kTopEarlgreyPinmuxPeripheralInI2c2Sda = 68, /**< Peripheral Input 68 */
1510 kTopEarlgreyPinmuxPeripheralInI2c2Scl = 69, /**< Peripheral Input 69 */
1511 kTopEarlgreyPinmuxPeripheralInI3c0Scl = 70, /**< Peripheral Input 70 */
1512 kTopEarlgreyPinmuxPeripheralInI3c0Sda = 71, /**< Peripheral Input 71 */
1513 kTopEarlgreyPinmuxPeripheralInI3c1Scl = 72, /**< Peripheral Input 72 */
1514 kTopEarlgreyPinmuxPeripheralInI3c1Sda = 73, /**< Peripheral Input 73 */
1515 kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0 = 74, /**< Peripheral Input 74 */
1516 kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1 = 75, /**< Peripheral Input 75 */
1517 kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2 = 76, /**< Peripheral Input 76 */
1518 kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3 = 77, /**< Peripheral Input 77 */
1519 kTopEarlgreyPinmuxPeripheralInUart0Rx = 78, /**< Peripheral Input 78 */
1520 kTopEarlgreyPinmuxPeripheralInUart1Rx = 79, /**< Peripheral Input 79 */
1521 kTopEarlgreyPinmuxPeripheralInUart2Rx = 80, /**< Peripheral Input 80 */
1522 kTopEarlgreyPinmuxPeripheralInUart3Rx = 81, /**< Peripheral Input 81 */
1523 kTopEarlgreyPinmuxPeripheralInI3c0RstdetScl = 82, /**< Peripheral Input 82 */
1524 kTopEarlgreyPinmuxPeripheralInI3c0RstdetSda = 83, /**< Peripheral Input 83 */
1525 kTopEarlgreyPinmuxPeripheralInI3c1RstdetScl = 84, /**< Peripheral Input 84 */
1526 kTopEarlgreyPinmuxPeripheralInI3c1RstdetSda = 85, /**< Peripheral Input 85 */
1527 kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb = 86, /**< Peripheral Input 86 */
1528 kTopEarlgreyPinmuxPeripheralInRramMacroTck = 87, /**< Peripheral Input 87 */
1529 kTopEarlgreyPinmuxPeripheralInRramMacroTms = 88, /**< Peripheral Input 88 */
1530 kTopEarlgreyPinmuxPeripheralInRramMacroTdi = 89, /**< Peripheral Input 89 */
1531 kTopEarlgreyPinmuxPeripheralInSysrstCtrlAcPresent = 90, /**< Peripheral Input 90 */
1532 kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey0In = 91, /**< Peripheral Input 91 */
1533 kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey1In = 92, /**< Peripheral Input 92 */
1534 kTopEarlgreyPinmuxPeripheralInSysrstCtrlKey2In = 93, /**< Peripheral Input 93 */
1535 kTopEarlgreyPinmuxPeripheralInSysrstCtrlPwrbIn = 94, /**< Peripheral Input 94 */
1536 kTopEarlgreyPinmuxPeripheralInSysrstCtrlLidOpen = 95, /**< Peripheral Input 95 */
1537 kTopEarlgreyPinmuxPeripheralInUsbdevSense = 96, /**< Peripheral Input 96 */
1538 kTopEarlgreyPinmuxPeripheralInLast = 96, /**< \internal Last valid peripheral input */
1539} top_earlgrey_pinmux_peripheral_in_t;
1540
1541/**
1542 * Pinmux MIO Input Selector.
1543 */
1544typedef enum top_earlgrey_pinmux_insel {
1545 kTopEarlgreyPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
1546 kTopEarlgreyPinmuxInselConstantOne = 1, /**< Tie constantly to one */
1547 kTopEarlgreyPinmuxInselIoa0 = 2, /**< MIO Pad 0 */
1548 kTopEarlgreyPinmuxInselIoa1 = 3, /**< MIO Pad 1 */
1549 kTopEarlgreyPinmuxInselIoa2 = 4, /**< MIO Pad 2 */
1550 kTopEarlgreyPinmuxInselIoa3 = 5, /**< MIO Pad 3 */
1551 kTopEarlgreyPinmuxInselIoa4 = 6, /**< MIO Pad 4 */
1552 kTopEarlgreyPinmuxInselIoa5 = 7, /**< MIO Pad 5 */
1553 kTopEarlgreyPinmuxInselIoa6 = 8, /**< MIO Pad 6 */
1554 kTopEarlgreyPinmuxInselIoa7 = 9, /**< MIO Pad 7 */
1555 kTopEarlgreyPinmuxInselIoa8 = 10, /**< MIO Pad 8 */
1556 kTopEarlgreyPinmuxInselIob0 = 11, /**< MIO Pad 9 */
1557 kTopEarlgreyPinmuxInselIob1 = 12, /**< MIO Pad 10 */
1558 kTopEarlgreyPinmuxInselIob2 = 13, /**< MIO Pad 11 */
1559 kTopEarlgreyPinmuxInselIob3 = 14, /**< MIO Pad 12 */
1560 kTopEarlgreyPinmuxInselIob4 = 15, /**< MIO Pad 13 */
1561 kTopEarlgreyPinmuxInselIob5 = 16, /**< MIO Pad 14 */
1562 kTopEarlgreyPinmuxInselIob6 = 17, /**< MIO Pad 15 */
1563 kTopEarlgreyPinmuxInselIob7 = 18, /**< MIO Pad 16 */
1564 kTopEarlgreyPinmuxInselIob8 = 19, /**< MIO Pad 17 */
1565 kTopEarlgreyPinmuxInselIob9 = 20, /**< MIO Pad 18 */
1566 kTopEarlgreyPinmuxInselIob10 = 21, /**< MIO Pad 19 */
1567 kTopEarlgreyPinmuxInselIob11 = 22, /**< MIO Pad 20 */
1568 kTopEarlgreyPinmuxInselIob12 = 23, /**< MIO Pad 21 */
1569 kTopEarlgreyPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
1570 kTopEarlgreyPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
1571 kTopEarlgreyPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
1572 kTopEarlgreyPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
1573 kTopEarlgreyPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
1574 kTopEarlgreyPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
1575 kTopEarlgreyPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
1576 kTopEarlgreyPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
1577 kTopEarlgreyPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
1578 kTopEarlgreyPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
1579 kTopEarlgreyPinmuxInselIoc10 = 34, /**< MIO Pad 32 */
1580 kTopEarlgreyPinmuxInselIoc11 = 35, /**< MIO Pad 33 */
1581 kTopEarlgreyPinmuxInselIoc12 = 36, /**< MIO Pad 34 */
1582 kTopEarlgreyPinmuxInselIor0 = 37, /**< MIO Pad 35 */
1583 kTopEarlgreyPinmuxInselIor1 = 38, /**< MIO Pad 36 */
1584 kTopEarlgreyPinmuxInselIor2 = 39, /**< MIO Pad 37 */
1585 kTopEarlgreyPinmuxInselIor3 = 40, /**< MIO Pad 38 */
1586 kTopEarlgreyPinmuxInselIor4 = 41, /**< MIO Pad 39 */
1587 kTopEarlgreyPinmuxInselIor5 = 42, /**< MIO Pad 40 */
1588 kTopEarlgreyPinmuxInselIor6 = 43, /**< MIO Pad 41 */
1589 kTopEarlgreyPinmuxInselIor7 = 44, /**< MIO Pad 42 */
1590 kTopEarlgreyPinmuxInselIor10 = 45, /**< MIO Pad 43 */
1591 kTopEarlgreyPinmuxInselIor11 = 46, /**< MIO Pad 44 */
1592 kTopEarlgreyPinmuxInselIor12 = 47, /**< MIO Pad 45 */
1593 kTopEarlgreyPinmuxInselIor13 = 48, /**< MIO Pad 46 */
1594 kTopEarlgreyPinmuxInselLast = 48, /**< \internal Last valid insel value */
1595} top_earlgrey_pinmux_insel_t;
1596
1597/**
1598 * Pinmux MIO Output.
1599 */
1600typedef enum top_earlgrey_pinmux_mio_out {
1601 kTopEarlgreyPinmuxMioOutIoa0 = 0, /**< MIO Pad 0 */
1602 kTopEarlgreyPinmuxMioOutIoa1 = 1, /**< MIO Pad 1 */
1603 kTopEarlgreyPinmuxMioOutIoa2 = 2, /**< MIO Pad 2 */
1604 kTopEarlgreyPinmuxMioOutIoa3 = 3, /**< MIO Pad 3 */
1605 kTopEarlgreyPinmuxMioOutIoa4 = 4, /**< MIO Pad 4 */
1606 kTopEarlgreyPinmuxMioOutIoa5 = 5, /**< MIO Pad 5 */
1607 kTopEarlgreyPinmuxMioOutIoa6 = 6, /**< MIO Pad 6 */
1608 kTopEarlgreyPinmuxMioOutIoa7 = 7, /**< MIO Pad 7 */
1609 kTopEarlgreyPinmuxMioOutIoa8 = 8, /**< MIO Pad 8 */
1610 kTopEarlgreyPinmuxMioOutIob0 = 9, /**< MIO Pad 9 */
1611 kTopEarlgreyPinmuxMioOutIob1 = 10, /**< MIO Pad 10 */
1612 kTopEarlgreyPinmuxMioOutIob2 = 11, /**< MIO Pad 11 */
1613 kTopEarlgreyPinmuxMioOutIob3 = 12, /**< MIO Pad 12 */
1614 kTopEarlgreyPinmuxMioOutIob4 = 13, /**< MIO Pad 13 */
1615 kTopEarlgreyPinmuxMioOutIob5 = 14, /**< MIO Pad 14 */
1616 kTopEarlgreyPinmuxMioOutIob6 = 15, /**< MIO Pad 15 */
1617 kTopEarlgreyPinmuxMioOutIob7 = 16, /**< MIO Pad 16 */
1618 kTopEarlgreyPinmuxMioOutIob8 = 17, /**< MIO Pad 17 */
1619 kTopEarlgreyPinmuxMioOutIob9 = 18, /**< MIO Pad 18 */
1620 kTopEarlgreyPinmuxMioOutIob10 = 19, /**< MIO Pad 19 */
1621 kTopEarlgreyPinmuxMioOutIob11 = 20, /**< MIO Pad 20 */
1622 kTopEarlgreyPinmuxMioOutIob12 = 21, /**< MIO Pad 21 */
1623 kTopEarlgreyPinmuxMioOutIoc0 = 22, /**< MIO Pad 22 */
1624 kTopEarlgreyPinmuxMioOutIoc1 = 23, /**< MIO Pad 23 */
1625 kTopEarlgreyPinmuxMioOutIoc2 = 24, /**< MIO Pad 24 */
1626 kTopEarlgreyPinmuxMioOutIoc3 = 25, /**< MIO Pad 25 */
1627 kTopEarlgreyPinmuxMioOutIoc4 = 26, /**< MIO Pad 26 */
1628 kTopEarlgreyPinmuxMioOutIoc5 = 27, /**< MIO Pad 27 */
1629 kTopEarlgreyPinmuxMioOutIoc6 = 28, /**< MIO Pad 28 */
1630 kTopEarlgreyPinmuxMioOutIoc7 = 29, /**< MIO Pad 29 */
1631 kTopEarlgreyPinmuxMioOutIoc8 = 30, /**< MIO Pad 30 */
1632 kTopEarlgreyPinmuxMioOutIoc9 = 31, /**< MIO Pad 31 */
1633 kTopEarlgreyPinmuxMioOutIoc10 = 32, /**< MIO Pad 32 */
1634 kTopEarlgreyPinmuxMioOutIoc11 = 33, /**< MIO Pad 33 */
1635 kTopEarlgreyPinmuxMioOutIoc12 = 34, /**< MIO Pad 34 */
1636 kTopEarlgreyPinmuxMioOutIor0 = 35, /**< MIO Pad 35 */
1637 kTopEarlgreyPinmuxMioOutIor1 = 36, /**< MIO Pad 36 */
1638 kTopEarlgreyPinmuxMioOutIor2 = 37, /**< MIO Pad 37 */
1639 kTopEarlgreyPinmuxMioOutIor3 = 38, /**< MIO Pad 38 */
1640 kTopEarlgreyPinmuxMioOutIor4 = 39, /**< MIO Pad 39 */
1641 kTopEarlgreyPinmuxMioOutIor5 = 40, /**< MIO Pad 40 */
1642 kTopEarlgreyPinmuxMioOutIor6 = 41, /**< MIO Pad 41 */
1643 kTopEarlgreyPinmuxMioOutIor7 = 42, /**< MIO Pad 42 */
1644 kTopEarlgreyPinmuxMioOutIor10 = 43, /**< MIO Pad 43 */
1645 kTopEarlgreyPinmuxMioOutIor11 = 44, /**< MIO Pad 44 */
1646 kTopEarlgreyPinmuxMioOutIor12 = 45, /**< MIO Pad 45 */
1647 kTopEarlgreyPinmuxMioOutIor13 = 46, /**< MIO Pad 46 */
1648 kTopEarlgreyPinmuxMioOutLast = 46, /**< \internal Last valid mio output */
1649} top_earlgrey_pinmux_mio_out_t;
1650
1651/**
1652 * Pinmux Peripheral Output Selector.
1653 */
1654typedef enum top_earlgrey_pinmux_outsel {
1655 kTopEarlgreyPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
1656 kTopEarlgreyPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
1657 kTopEarlgreyPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
1658 kTopEarlgreyPinmuxOutselGpio0Gpio0 = 3, /**< Peripheral Output 0 */
1659 kTopEarlgreyPinmuxOutselGpio0Gpio1 = 4, /**< Peripheral Output 1 */
1660 kTopEarlgreyPinmuxOutselGpio0Gpio2 = 5, /**< Peripheral Output 2 */
1661 kTopEarlgreyPinmuxOutselGpio0Gpio3 = 6, /**< Peripheral Output 3 */
1662 kTopEarlgreyPinmuxOutselGpio0Gpio4 = 7, /**< Peripheral Output 4 */
1663 kTopEarlgreyPinmuxOutselGpio0Gpio5 = 8, /**< Peripheral Output 5 */
1664 kTopEarlgreyPinmuxOutselGpio0Gpio6 = 9, /**< Peripheral Output 6 */
1665 kTopEarlgreyPinmuxOutselGpio0Gpio7 = 10, /**< Peripheral Output 7 */
1666 kTopEarlgreyPinmuxOutselGpio0Gpio8 = 11, /**< Peripheral Output 8 */
1667 kTopEarlgreyPinmuxOutselGpio0Gpio9 = 12, /**< Peripheral Output 9 */
1668 kTopEarlgreyPinmuxOutselGpio0Gpio10 = 13, /**< Peripheral Output 10 */
1669 kTopEarlgreyPinmuxOutselGpio0Gpio11 = 14, /**< Peripheral Output 11 */
1670 kTopEarlgreyPinmuxOutselGpio0Gpio12 = 15, /**< Peripheral Output 12 */
1671 kTopEarlgreyPinmuxOutselGpio0Gpio13 = 16, /**< Peripheral Output 13 */
1672 kTopEarlgreyPinmuxOutselGpio0Gpio14 = 17, /**< Peripheral Output 14 */
1673 kTopEarlgreyPinmuxOutselGpio0Gpio15 = 18, /**< Peripheral Output 15 */
1674 kTopEarlgreyPinmuxOutselGpio0Gpio16 = 19, /**< Peripheral Output 16 */
1675 kTopEarlgreyPinmuxOutselGpio0Gpio17 = 20, /**< Peripheral Output 17 */
1676 kTopEarlgreyPinmuxOutselGpio0Gpio18 = 21, /**< Peripheral Output 18 */
1677 kTopEarlgreyPinmuxOutselGpio0Gpio19 = 22, /**< Peripheral Output 19 */
1678 kTopEarlgreyPinmuxOutselGpio0Gpio20 = 23, /**< Peripheral Output 20 */
1679 kTopEarlgreyPinmuxOutselGpio0Gpio21 = 24, /**< Peripheral Output 21 */
1680 kTopEarlgreyPinmuxOutselGpio0Gpio22 = 25, /**< Peripheral Output 22 */
1681 kTopEarlgreyPinmuxOutselGpio0Gpio23 = 26, /**< Peripheral Output 23 */
1682 kTopEarlgreyPinmuxOutselGpio0Gpio24 = 27, /**< Peripheral Output 24 */
1683 kTopEarlgreyPinmuxOutselGpio0Gpio25 = 28, /**< Peripheral Output 25 */
1684 kTopEarlgreyPinmuxOutselGpio0Gpio26 = 29, /**< Peripheral Output 26 */
1685 kTopEarlgreyPinmuxOutselGpio0Gpio27 = 30, /**< Peripheral Output 27 */
1686 kTopEarlgreyPinmuxOutselGpio0Gpio28 = 31, /**< Peripheral Output 28 */
1687 kTopEarlgreyPinmuxOutselGpio0Gpio29 = 32, /**< Peripheral Output 29 */
1688 kTopEarlgreyPinmuxOutselGpio0Gpio30 = 33, /**< Peripheral Output 30 */
1689 kTopEarlgreyPinmuxOutselGpio0Gpio31 = 34, /**< Peripheral Output 31 */
1690 kTopEarlgreyPinmuxOutselGpio1Gpio0 = 35, /**< Peripheral Output 32 */
1691 kTopEarlgreyPinmuxOutselGpio1Gpio1 = 36, /**< Peripheral Output 33 */
1692 kTopEarlgreyPinmuxOutselGpio1Gpio2 = 37, /**< Peripheral Output 34 */
1693 kTopEarlgreyPinmuxOutselGpio1Gpio3 = 38, /**< Peripheral Output 35 */
1694 kTopEarlgreyPinmuxOutselGpio1Gpio4 = 39, /**< Peripheral Output 36 */
1695 kTopEarlgreyPinmuxOutselGpio1Gpio5 = 40, /**< Peripheral Output 37 */
1696 kTopEarlgreyPinmuxOutselGpio1Gpio6 = 41, /**< Peripheral Output 38 */
1697 kTopEarlgreyPinmuxOutselGpio1Gpio7 = 42, /**< Peripheral Output 39 */
1698 kTopEarlgreyPinmuxOutselGpio1Gpio8 = 43, /**< Peripheral Output 40 */
1699 kTopEarlgreyPinmuxOutselGpio1Gpio9 = 44, /**< Peripheral Output 41 */
1700 kTopEarlgreyPinmuxOutselGpio1Gpio10 = 45, /**< Peripheral Output 42 */
1701 kTopEarlgreyPinmuxOutselGpio1Gpio11 = 46, /**< Peripheral Output 43 */
1702 kTopEarlgreyPinmuxOutselGpio1Gpio12 = 47, /**< Peripheral Output 44 */
1703 kTopEarlgreyPinmuxOutselGpio1Gpio13 = 48, /**< Peripheral Output 45 */
1704 kTopEarlgreyPinmuxOutselGpio1Gpio14 = 49, /**< Peripheral Output 46 */
1705 kTopEarlgreyPinmuxOutselGpio1Gpio15 = 50, /**< Peripheral Output 47 */
1706 kTopEarlgreyPinmuxOutselGpio1Gpio16 = 51, /**< Peripheral Output 48 */
1707 kTopEarlgreyPinmuxOutselGpio1Gpio17 = 52, /**< Peripheral Output 49 */
1708 kTopEarlgreyPinmuxOutselGpio1Gpio18 = 53, /**< Peripheral Output 50 */
1709 kTopEarlgreyPinmuxOutselGpio1Gpio19 = 54, /**< Peripheral Output 51 */
1710 kTopEarlgreyPinmuxOutselGpio1Gpio20 = 55, /**< Peripheral Output 52 */
1711 kTopEarlgreyPinmuxOutselGpio1Gpio21 = 56, /**< Peripheral Output 53 */
1712 kTopEarlgreyPinmuxOutselGpio1Gpio22 = 57, /**< Peripheral Output 54 */
1713 kTopEarlgreyPinmuxOutselGpio1Gpio23 = 58, /**< Peripheral Output 55 */
1714 kTopEarlgreyPinmuxOutselGpio1Gpio24 = 59, /**< Peripheral Output 56 */
1715 kTopEarlgreyPinmuxOutselGpio1Gpio25 = 60, /**< Peripheral Output 57 */
1716 kTopEarlgreyPinmuxOutselGpio1Gpio26 = 61, /**< Peripheral Output 58 */
1717 kTopEarlgreyPinmuxOutselGpio1Gpio27 = 62, /**< Peripheral Output 59 */
1718 kTopEarlgreyPinmuxOutselGpio1Gpio28 = 63, /**< Peripheral Output 60 */
1719 kTopEarlgreyPinmuxOutselGpio1Gpio29 = 64, /**< Peripheral Output 61 */
1720 kTopEarlgreyPinmuxOutselGpio1Gpio30 = 65, /**< Peripheral Output 62 */
1721 kTopEarlgreyPinmuxOutselGpio1Gpio31 = 66, /**< Peripheral Output 63 */
1722 kTopEarlgreyPinmuxOutselI2c0Sda = 67, /**< Peripheral Output 64 */
1723 kTopEarlgreyPinmuxOutselI2c0Scl = 68, /**< Peripheral Output 65 */
1724 kTopEarlgreyPinmuxOutselI2c1Sda = 69, /**< Peripheral Output 66 */
1725 kTopEarlgreyPinmuxOutselI2c1Scl = 70, /**< Peripheral Output 67 */
1726 kTopEarlgreyPinmuxOutselI2c2Sda = 71, /**< Peripheral Output 68 */
1727 kTopEarlgreyPinmuxOutselI2c2Scl = 72, /**< Peripheral Output 69 */
1728 kTopEarlgreyPinmuxOutselI3c0Scl = 73, /**< Peripheral Output 70 */
1729 kTopEarlgreyPinmuxOutselI3c0Sda = 74, /**< Peripheral Output 71 */
1730 kTopEarlgreyPinmuxOutselI3c1Scl = 75, /**< Peripheral Output 72 */
1731 kTopEarlgreyPinmuxOutselI3c1Sda = 76, /**< Peripheral Output 73 */
1732 kTopEarlgreyPinmuxOutselSpiHost1Sd0 = 77, /**< Peripheral Output 74 */
1733 kTopEarlgreyPinmuxOutselSpiHost1Sd1 = 78, /**< Peripheral Output 75 */
1734 kTopEarlgreyPinmuxOutselSpiHost1Sd2 = 79, /**< Peripheral Output 76 */
1735 kTopEarlgreyPinmuxOutselSpiHost1Sd3 = 80, /**< Peripheral Output 77 */
1736 kTopEarlgreyPinmuxOutselUart0Tx = 81, /**< Peripheral Output 78 */
1737 kTopEarlgreyPinmuxOutselUart1Tx = 82, /**< Peripheral Output 79 */
1738 kTopEarlgreyPinmuxOutselUart2Tx = 83, /**< Peripheral Output 80 */
1739 kTopEarlgreyPinmuxOutselUart3Tx = 84, /**< Peripheral Output 81 */
1740 kTopEarlgreyPinmuxOutselI3c0CtrlSdaPu = 85, /**< Peripheral Output 82 */
1741 kTopEarlgreyPinmuxOutselI3c1CtrlSdaPu = 86, /**< Peripheral Output 83 */
1742 kTopEarlgreyPinmuxOutselSpiHost1Sck = 87, /**< Peripheral Output 84 */
1743 kTopEarlgreyPinmuxOutselSpiHost1Csb = 88, /**< Peripheral Output 85 */
1744 kTopEarlgreyPinmuxOutselRramMacroTdo = 89, /**< Peripheral Output 86 */
1745 kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut0 = 90, /**< Peripheral Output 87 */
1746 kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut1 = 91, /**< Peripheral Output 88 */
1747 kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut2 = 92, /**< Peripheral Output 89 */
1748 kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut3 = 93, /**< Peripheral Output 90 */
1749 kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut4 = 94, /**< Peripheral Output 91 */
1750 kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut5 = 95, /**< Peripheral Output 92 */
1751 kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut6 = 96, /**< Peripheral Output 93 */
1752 kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut7 = 97, /**< Peripheral Output 94 */
1753 kTopEarlgreyPinmuxOutselSensorCtrlAstDebugOut8 = 98, /**< Peripheral Output 95 */
1754 kTopEarlgreyPinmuxOutselSysrstCtrlBatDisable = 99, /**< Peripheral Output 96 */
1755 kTopEarlgreyPinmuxOutselSysrstCtrlKey0Out = 100, /**< Peripheral Output 97 */
1756 kTopEarlgreyPinmuxOutselSysrstCtrlKey1Out = 101, /**< Peripheral Output 98 */
1757 kTopEarlgreyPinmuxOutselSysrstCtrlKey2Out = 102, /**< Peripheral Output 99 */
1758 kTopEarlgreyPinmuxOutselSysrstCtrlPwrbOut = 103, /**< Peripheral Output 100 */
1759 kTopEarlgreyPinmuxOutselSysrstCtrlZ3Wakeup = 104, /**< Peripheral Output 101 */
1760 kTopEarlgreyPinmuxOutselLast = 104, /**< \internal Last valid outsel value */
1761} top_earlgrey_pinmux_outsel_t;
1762
1763/**
1764 * Dedicated Pad Selects
1765 */
1766typedef enum top_earlgrey_direct_pads {
1767 kTopEarlgreyDirectPadsUsbdevUsbDp = 0, /**< */
1768 kTopEarlgreyDirectPadsUsbdevUsbDn = 1, /**< */
1769 kTopEarlgreyDirectPadsSpiHost0Sd0 = 2, /**< */
1770 kTopEarlgreyDirectPadsSpiHost0Sd1 = 3, /**< */
1771 kTopEarlgreyDirectPadsSpiHost0Sd2 = 4, /**< */
1772 kTopEarlgreyDirectPadsSpiHost0Sd3 = 5, /**< */
1773 kTopEarlgreyDirectPadsSpiDeviceSd0 = 6, /**< */
1774 kTopEarlgreyDirectPadsSpiDeviceSd1 = 7, /**< */
1775 kTopEarlgreyDirectPadsSpiDeviceSd2 = 8, /**< */
1776 kTopEarlgreyDirectPadsSpiDeviceSd3 = 9, /**< */
1777 kTopEarlgreyDirectPadsSysrstCtrlEcRstL = 10, /**< */
1778 kTopEarlgreyDirectPadsSysrstCtrlFlashWpL = 11, /**< */
1779 kTopEarlgreyDirectPadsSpiDeviceSck = 12, /**< */
1780 kTopEarlgreyDirectPadsSpiDeviceCsb = 13, /**< */
1781 kTopEarlgreyDirectPadsSpiHost0Sck = 14, /**< */
1782 kTopEarlgreyDirectPadsSpiHost0Csb = 15, /**< */
1783 kTopEarlgreyDirectPadsLast = 15, /**< \internal Last valid direct pad */
1784} top_earlgrey_direct_pads_t;
1785
1786/**
1787 * Muxed Pad Selects
1788 */
1789typedef enum top_earlgrey_muxed_pads {
1790 kTopEarlgreyMuxedPadsIoa0 = 0, /**< */
1791 kTopEarlgreyMuxedPadsIoa1 = 1, /**< */
1792 kTopEarlgreyMuxedPadsIoa2 = 2, /**< */
1793 kTopEarlgreyMuxedPadsIoa3 = 3, /**< */
1794 kTopEarlgreyMuxedPadsIoa4 = 4, /**< */
1795 kTopEarlgreyMuxedPadsIoa5 = 5, /**< */
1796 kTopEarlgreyMuxedPadsIoa6 = 6, /**< */
1797 kTopEarlgreyMuxedPadsIoa7 = 7, /**< */
1798 kTopEarlgreyMuxedPadsIoa8 = 8, /**< */
1799 kTopEarlgreyMuxedPadsIob0 = 9, /**< */
1800 kTopEarlgreyMuxedPadsIob1 = 10, /**< */
1801 kTopEarlgreyMuxedPadsIob2 = 11, /**< */
1802 kTopEarlgreyMuxedPadsIob3 = 12, /**< */
1803 kTopEarlgreyMuxedPadsIob4 = 13, /**< */
1804 kTopEarlgreyMuxedPadsIob5 = 14, /**< */
1805 kTopEarlgreyMuxedPadsIob6 = 15, /**< */
1806 kTopEarlgreyMuxedPadsIob7 = 16, /**< */
1807 kTopEarlgreyMuxedPadsIob8 = 17, /**< */
1808 kTopEarlgreyMuxedPadsIob9 = 18, /**< */
1809 kTopEarlgreyMuxedPadsIob10 = 19, /**< */
1810 kTopEarlgreyMuxedPadsIob11 = 20, /**< */
1811 kTopEarlgreyMuxedPadsIob12 = 21, /**< */
1812 kTopEarlgreyMuxedPadsIoc0 = 22, /**< */
1813 kTopEarlgreyMuxedPadsIoc1 = 23, /**< */
1814 kTopEarlgreyMuxedPadsIoc2 = 24, /**< */
1815 kTopEarlgreyMuxedPadsIoc3 = 25, /**< */
1816 kTopEarlgreyMuxedPadsIoc4 = 26, /**< */
1817 kTopEarlgreyMuxedPadsIoc5 = 27, /**< */
1818 kTopEarlgreyMuxedPadsIoc6 = 28, /**< */
1819 kTopEarlgreyMuxedPadsIoc7 = 29, /**< */
1820 kTopEarlgreyMuxedPadsIoc8 = 30, /**< */
1821 kTopEarlgreyMuxedPadsIoc9 = 31, /**< */
1822 kTopEarlgreyMuxedPadsIoc10 = 32, /**< */
1823 kTopEarlgreyMuxedPadsIoc11 = 33, /**< */
1824 kTopEarlgreyMuxedPadsIoc12 = 34, /**< */
1825 kTopEarlgreyMuxedPadsIor0 = 35, /**< */
1826 kTopEarlgreyMuxedPadsIor1 = 36, /**< */
1827 kTopEarlgreyMuxedPadsIor2 = 37, /**< */
1828 kTopEarlgreyMuxedPadsIor3 = 38, /**< */
1829 kTopEarlgreyMuxedPadsIor4 = 39, /**< */
1830 kTopEarlgreyMuxedPadsIor5 = 40, /**< */
1831 kTopEarlgreyMuxedPadsIor6 = 41, /**< */
1832 kTopEarlgreyMuxedPadsIor7 = 42, /**< */
1833 kTopEarlgreyMuxedPadsIor10 = 43, /**< */
1834 kTopEarlgreyMuxedPadsIor11 = 44, /**< */
1835 kTopEarlgreyMuxedPadsIor12 = 45, /**< */
1836 kTopEarlgreyMuxedPadsIor13 = 46, /**< */
1837 kTopEarlgreyMuxedPadsLast = 46, /**< \internal Last valid muxed pad */
1838} top_earlgrey_muxed_pads_t;
1839
1840/**
1841 * Power Manager Wakeup Signals
1842 */
1843typedef enum top_earlgrey_power_manager_wake_ups {
1844 kTopEarlgreyPowerManagerWakeUpsI3c0RstdetWkupReq = 0, /**< */
1845 kTopEarlgreyPowerManagerWakeUpsI3c1RstdetWkupReq = 1, /**< */
1846 kTopEarlgreyPowerManagerWakeUpsSysrstCtrlWkupReq = 2, /**< */
1847 kTopEarlgreyPowerManagerWakeUpsAdcCtrlWkupReq = 3, /**< */
1848 kTopEarlgreyPowerManagerWakeUpsPinmuxPinWkupReq = 4, /**< */
1849 kTopEarlgreyPowerManagerWakeUpsPinmuxUsbWkupReq = 5, /**< */
1850 kTopEarlgreyPowerManagerWakeUpsAonTimerWkupReq = 6, /**< */
1851 kTopEarlgreyPowerManagerWakeUpsSensorCtrlWkupReq = 7, /**< */
1852 kTopEarlgreyPowerManagerWakeUpsLast = 7, /**< \internal Last valid pwrmgr wakeup signal */
1853} top_earlgrey_power_manager_wake_ups_t;
1854
1855/**
1856 * Reset Manager Software Controlled Resets
1857 */
1858typedef enum top_earlgrey_reset_manager_sw_resets {
1859 kTopEarlgreyResetManagerSwResetsSpiDevice = 0, /**< */
1860 kTopEarlgreyResetManagerSwResetsSpiHost0 = 1, /**< */
1861 kTopEarlgreyResetManagerSwResetsSpiHost1 = 2, /**< */
1862 kTopEarlgreyResetManagerSwResetsUsb = 3, /**< */
1863 kTopEarlgreyResetManagerSwResetsUsbAon = 4, /**< */
1864 kTopEarlgreyResetManagerSwResetsI2c0 = 5, /**< */
1865 kTopEarlgreyResetManagerSwResetsI2c1 = 6, /**< */
1866 kTopEarlgreyResetManagerSwResetsI2c2 = 7, /**< */
1867 kTopEarlgreyResetManagerSwResetsI3c0 = 8, /**< */
1868 kTopEarlgreyResetManagerSwResetsI3c1 = 9, /**< */
1869 kTopEarlgreyResetManagerSwResetsLast = 9, /**< \internal Last valid rstmgr software reset request */
1870} top_earlgrey_reset_manager_sw_resets_t;
1871
1872/**
1873 * Power Manager Reset Request Signals
1874 */
1875typedef enum top_earlgrey_power_manager_reset_requests {
1876 kTopEarlgreyPowerManagerResetRequestsSysrstCtrlRstReq = 0, /**< */
1877 kTopEarlgreyPowerManagerResetRequestsAonTimerAonTimerRstReq = 1, /**< */
1878 kTopEarlgreyPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */
1879} top_earlgrey_power_manager_reset_requests_t;
1880
1881/**
1882 * Clock Manager Software-Controlled ("Gated") Clocks.
1883 *
1884 * The Software has full control over these clocks.
1885 */
1886typedef enum top_earlgrey_gateable_clocks {
1887 kTopEarlgreyGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
1888 kTopEarlgreyGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
1889 kTopEarlgreyGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
1890 kTopEarlgreyGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
1891 kTopEarlgreyGateableClocksIoSpiHost1 = 4, /**< Clock clk_io_spi_host1 in group spi_host1 */
1892 kTopEarlgreyGateableClocksLast = 4, /**< \internal Last Valid Gateable Clock */
1893} top_earlgrey_gateable_clocks_t;
1894
1895/**
1896 * Clock Manager Software-Hinted Clocks.
1897 *
1898 * The Software has partial control over these clocks. It can ask them to stop,
1899 * but the clock manager is in control of whether the clock actually is stopped.
1900 */
1901typedef enum top_earlgrey_hintable_clocks {
1902 kTopEarlgreyHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */
1903 kTopEarlgreyHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */
1904 kTopEarlgreyHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */
1905 kTopEarlgreyHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */
1906 kTopEarlgreyHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */
1907} top_earlgrey_hintable_clocks_t;
1908
1909/**
1910 * MMIO Region
1911 *
1912 * MMIO region excludes any memory that is separate from the module
1913 * configuration space, i.e. ROM, main SRAM, and RRAM are excluded but retention
1914 * SRAM, spi_device memory, or usbdev memory are included.
1915 */
1916#define TOP_EARLGREY_MMIO_BASE_ADDR 0x40000000u
1917#define TOP_EARLGREY_MMIO_SIZE_BYTES 0x10000000u
1918
1919// Header Extern Guard
1920#ifdef __cplusplus
1921} // extern "C"
1922#endif
1923
1924#endif // OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_H_