Software APIs
top_earlgrey.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
6// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
7// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson
8// -o hw/top_earlgrey
9
10#ifndef OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_H_
11#define OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_H_
12
13/**
14 * @file
15 * @brief Top-specific Definitions
16 *
17 * This file contains preprocessor and type definitions for use within the
18 * device C/C++ codebase.
19 *
20 * These definitions are for information that depends on the top-specific chip
21 * configuration, which includes:
22 * - Device Memory Information (for Peripherals and Memory)
23 * - PLIC Interrupt ID Names and Source Mappings
24 * - Alert ID Names and Source Mappings
25 * - Pinmux Pin/Select Names
26 * - Power Manager Wakeups
27 */
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/**
34 * Peripheral base address for uart0 in top earlgrey.
35 *
36 * This should be used with #mmio_region_from_addr to access the memory-mapped
37 * registers associated with the peripheral (usually via a DIF).
38 */
39#define TOP_EARLGREY_UART0_BASE_ADDR 0x40000000u
40
41/**
42 * Peripheral size for uart0 in top earlgrey.
43 *
44 * This is the size (in bytes) of the peripheral's reserved memory area. All
45 * memory-mapped registers associated with this peripheral should have an
46 * address between #TOP_EARLGREY_UART0_BASE_ADDR and
47 * `TOP_EARLGREY_UART0_BASE_ADDR + TOP_EARLGREY_UART0_SIZE_BYTES`.
48 */
49#define TOP_EARLGREY_UART0_SIZE_BYTES 0x40u
50
51/**
52 * Peripheral base address for uart1 in top earlgrey.
53 *
54 * This should be used with #mmio_region_from_addr to access the memory-mapped
55 * registers associated with the peripheral (usually via a DIF).
56 */
57#define TOP_EARLGREY_UART1_BASE_ADDR 0x40010000u
58
59/**
60 * Peripheral size for uart1 in top earlgrey.
61 *
62 * This is the size (in bytes) of the peripheral's reserved memory area. All
63 * memory-mapped registers associated with this peripheral should have an
64 * address between #TOP_EARLGREY_UART1_BASE_ADDR and
65 * `TOP_EARLGREY_UART1_BASE_ADDR + TOP_EARLGREY_UART1_SIZE_BYTES`.
66 */
67#define TOP_EARLGREY_UART1_SIZE_BYTES 0x40u
68
69/**
70 * Peripheral base address for uart2 in top earlgrey.
71 *
72 * This should be used with #mmio_region_from_addr to access the memory-mapped
73 * registers associated with the peripheral (usually via a DIF).
74 */
75#define TOP_EARLGREY_UART2_BASE_ADDR 0x40020000u
76
77/**
78 * Peripheral size for uart2 in top earlgrey.
79 *
80 * This is the size (in bytes) of the peripheral's reserved memory area. All
81 * memory-mapped registers associated with this peripheral should have an
82 * address between #TOP_EARLGREY_UART2_BASE_ADDR and
83 * `TOP_EARLGREY_UART2_BASE_ADDR + TOP_EARLGREY_UART2_SIZE_BYTES`.
84 */
85#define TOP_EARLGREY_UART2_SIZE_BYTES 0x40u
86
87/**
88 * Peripheral base address for uart3 in top earlgrey.
89 *
90 * This should be used with #mmio_region_from_addr to access the memory-mapped
91 * registers associated with the peripheral (usually via a DIF).
92 */
93#define TOP_EARLGREY_UART3_BASE_ADDR 0x40030000u
94
95/**
96 * Peripheral size for uart3 in top earlgrey.
97 *
98 * This is the size (in bytes) of the peripheral's reserved memory area. All
99 * memory-mapped registers associated with this peripheral should have an
100 * address between #TOP_EARLGREY_UART3_BASE_ADDR and
101 * `TOP_EARLGREY_UART3_BASE_ADDR + TOP_EARLGREY_UART3_SIZE_BYTES`.
102 */
103#define TOP_EARLGREY_UART3_SIZE_BYTES 0x40u
104
105/**
106 * Peripheral base address for gpio in top earlgrey.
107 *
108 * This should be used with #mmio_region_from_addr to access the memory-mapped
109 * registers associated with the peripheral (usually via a DIF).
110 */
111#define TOP_EARLGREY_GPIO_BASE_ADDR 0x40040000u
112
113/**
114 * Peripheral size for gpio in top earlgrey.
115 *
116 * This is the size (in bytes) of the peripheral's reserved memory area. All
117 * memory-mapped registers associated with this peripheral should have an
118 * address between #TOP_EARLGREY_GPIO_BASE_ADDR and
119 * `TOP_EARLGREY_GPIO_BASE_ADDR + TOP_EARLGREY_GPIO_SIZE_BYTES`.
120 */
121#define TOP_EARLGREY_GPIO_SIZE_BYTES 0x80u
122
123/**
124 * Peripheral base address for spi_device in top earlgrey.
125 *
126 * This should be used with #mmio_region_from_addr to access the memory-mapped
127 * registers associated with the peripheral (usually via a DIF).
128 */
129#define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40050000u
130
131/**
132 * Peripheral size for spi_device in top earlgrey.
133 *
134 * This is the size (in bytes) of the peripheral's reserved memory area. All
135 * memory-mapped registers associated with this peripheral should have an
136 * address between #TOP_EARLGREY_SPI_DEVICE_BASE_ADDR and
137 * `TOP_EARLGREY_SPI_DEVICE_BASE_ADDR + TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES`.
138 */
139#define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x2000u
140
141/**
142 * Peripheral base address for i2c0 in top earlgrey.
143 *
144 * This should be used with #mmio_region_from_addr to access the memory-mapped
145 * registers associated with the peripheral (usually via a DIF).
146 */
147#define TOP_EARLGREY_I2C0_BASE_ADDR 0x40080000u
148
149/**
150 * Peripheral size for i2c0 in top earlgrey.
151 *
152 * This is the size (in bytes) of the peripheral's reserved memory area. All
153 * memory-mapped registers associated with this peripheral should have an
154 * address between #TOP_EARLGREY_I2C0_BASE_ADDR and
155 * `TOP_EARLGREY_I2C0_BASE_ADDR + TOP_EARLGREY_I2C0_SIZE_BYTES`.
156 */
157#define TOP_EARLGREY_I2C0_SIZE_BYTES 0x80u
158
159/**
160 * Peripheral base address for i2c1 in top earlgrey.
161 *
162 * This should be used with #mmio_region_from_addr to access the memory-mapped
163 * registers associated with the peripheral (usually via a DIF).
164 */
165#define TOP_EARLGREY_I2C1_BASE_ADDR 0x40090000u
166
167/**
168 * Peripheral size for i2c1 in top earlgrey.
169 *
170 * This is the size (in bytes) of the peripheral's reserved memory area. All
171 * memory-mapped registers associated with this peripheral should have an
172 * address between #TOP_EARLGREY_I2C1_BASE_ADDR and
173 * `TOP_EARLGREY_I2C1_BASE_ADDR + TOP_EARLGREY_I2C1_SIZE_BYTES`.
174 */
175#define TOP_EARLGREY_I2C1_SIZE_BYTES 0x80u
176
177/**
178 * Peripheral base address for i2c2 in top earlgrey.
179 *
180 * This should be used with #mmio_region_from_addr to access the memory-mapped
181 * registers associated with the peripheral (usually via a DIF).
182 */
183#define TOP_EARLGREY_I2C2_BASE_ADDR 0x400A0000u
184
185/**
186 * Peripheral size for i2c2 in top earlgrey.
187 *
188 * This is the size (in bytes) of the peripheral's reserved memory area. All
189 * memory-mapped registers associated with this peripheral should have an
190 * address between #TOP_EARLGREY_I2C2_BASE_ADDR and
191 * `TOP_EARLGREY_I2C2_BASE_ADDR + TOP_EARLGREY_I2C2_SIZE_BYTES`.
192 */
193#define TOP_EARLGREY_I2C2_SIZE_BYTES 0x80u
194
195/**
196 * Peripheral base address for pattgen in top earlgrey.
197 *
198 * This should be used with #mmio_region_from_addr to access the memory-mapped
199 * registers associated with the peripheral (usually via a DIF).
200 */
201#define TOP_EARLGREY_PATTGEN_BASE_ADDR 0x400E0000u
202
203/**
204 * Peripheral size for pattgen in top earlgrey.
205 *
206 * This is the size (in bytes) of the peripheral's reserved memory area. All
207 * memory-mapped registers associated with this peripheral should have an
208 * address between #TOP_EARLGREY_PATTGEN_BASE_ADDR and
209 * `TOP_EARLGREY_PATTGEN_BASE_ADDR + TOP_EARLGREY_PATTGEN_SIZE_BYTES`.
210 */
211#define TOP_EARLGREY_PATTGEN_SIZE_BYTES 0x40u
212
213/**
214 * Peripheral base address for rv_timer in top earlgrey.
215 *
216 * This should be used with #mmio_region_from_addr to access the memory-mapped
217 * registers associated with the peripheral (usually via a DIF).
218 */
219#define TOP_EARLGREY_RV_TIMER_BASE_ADDR 0x40100000u
220
221/**
222 * Peripheral size for rv_timer in top earlgrey.
223 *
224 * This is the size (in bytes) of the peripheral's reserved memory area. All
225 * memory-mapped registers associated with this peripheral should have an
226 * address between #TOP_EARLGREY_RV_TIMER_BASE_ADDR and
227 * `TOP_EARLGREY_RV_TIMER_BASE_ADDR + TOP_EARLGREY_RV_TIMER_SIZE_BYTES`.
228 */
229#define TOP_EARLGREY_RV_TIMER_SIZE_BYTES 0x200u
230
231/**
232 * Peripheral base address for core device on otp_ctrl in top earlgrey.
233 *
234 * This should be used with #mmio_region_from_addr to access the memory-mapped
235 * registers associated with the peripheral (usually via a DIF).
236 */
237#define TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR 0x40130000u
238
239/**
240 * Peripheral size for core device on otp_ctrl in top earlgrey.
241 *
242 * This is the size (in bytes) of the peripheral's reserved memory area. All
243 * memory-mapped registers associated with this peripheral should have an
244 * address between #TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR and
245 * `TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES`.
246 */
247#define TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES 0x1000u
248
249/**
250 * Peripheral base address for prim device on otp_macro in top earlgrey.
251 *
252 * This should be used with #mmio_region_from_addr to access the memory-mapped
253 * registers associated with the peripheral (usually via a DIF).
254 */
255#define TOP_EARLGREY_OTP_MACRO_PRIM_BASE_ADDR 0x40138000u
256
257/**
258 * Peripheral size for prim device on otp_macro in top earlgrey.
259 *
260 * This is the size (in bytes) of the peripheral's reserved memory area. All
261 * memory-mapped registers associated with this peripheral should have an
262 * address between #TOP_EARLGREY_OTP_MACRO_PRIM_BASE_ADDR and
263 * `TOP_EARLGREY_OTP_MACRO_PRIM_BASE_ADDR + TOP_EARLGREY_OTP_MACRO_PRIM_SIZE_BYTES`.
264 */
265#define TOP_EARLGREY_OTP_MACRO_PRIM_SIZE_BYTES 0x20u
266
267/**
268 * Peripheral base address for regs device on lc_ctrl in top earlgrey.
269 *
270 * This should be used with #mmio_region_from_addr to access the memory-mapped
271 * registers associated with the peripheral (usually via a DIF).
272 */
273#define TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR 0x40140000u
274
275/**
276 * Peripheral size for regs device on lc_ctrl in top earlgrey.
277 *
278 * This is the size (in bytes) of the peripheral's reserved memory area. All
279 * memory-mapped registers associated with this peripheral should have an
280 * address between #TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR and
281 * `TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES`.
282 */
283#define TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES 0x100u
284
285/**
286 * Peripheral base address for dmi device on lc_ctrl in top earlgrey.
287 *
288 * This should be used with #mmio_region_from_addr to access the memory-mapped
289 * registers associated with the peripheral (usually via a DIF).
290 */
291#define TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR 0x0u
292
293/**
294 * Peripheral size for dmi device on lc_ctrl in top earlgrey.
295 *
296 * This is the size (in bytes) of the peripheral's reserved memory area. All
297 * memory-mapped registers associated with this peripheral should have an
298 * address between #TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR and
299 * `TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR + TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES`.
300 */
301#define TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES 0x1000u
302
303/**
304 * Peripheral base address for alert_handler in top earlgrey.
305 *
306 * This should be used with #mmio_region_from_addr to access the memory-mapped
307 * registers associated with the peripheral (usually via a DIF).
308 */
309#define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x40150000u
310
311/**
312 * Peripheral size for alert_handler in top earlgrey.
313 *
314 * This is the size (in bytes) of the peripheral's reserved memory area. All
315 * memory-mapped registers associated with this peripheral should have an
316 * address between #TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR and
317 * `TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR + TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES`.
318 */
319#define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x800u
320
321/**
322 * Peripheral base address for spi_host0 in top earlgrey.
323 *
324 * This should be used with #mmio_region_from_addr to access the memory-mapped
325 * registers associated with the peripheral (usually via a DIF).
326 */
327#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40300000u
328
329/**
330 * Peripheral size for spi_host0 in top earlgrey.
331 *
332 * This is the size (in bytes) of the peripheral's reserved memory area. All
333 * memory-mapped registers associated with this peripheral should have an
334 * address between #TOP_EARLGREY_SPI_HOST0_BASE_ADDR and
335 * `TOP_EARLGREY_SPI_HOST0_BASE_ADDR + TOP_EARLGREY_SPI_HOST0_SIZE_BYTES`.
336 */
337#define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x40u
338
339/**
340 * Peripheral base address for spi_host1 in top earlgrey.
341 *
342 * This should be used with #mmio_region_from_addr to access the memory-mapped
343 * registers associated with the peripheral (usually via a DIF).
344 */
345#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40310000u
346
347/**
348 * Peripheral size for spi_host1 in top earlgrey.
349 *
350 * This is the size (in bytes) of the peripheral's reserved memory area. All
351 * memory-mapped registers associated with this peripheral should have an
352 * address between #TOP_EARLGREY_SPI_HOST1_BASE_ADDR and
353 * `TOP_EARLGREY_SPI_HOST1_BASE_ADDR + TOP_EARLGREY_SPI_HOST1_SIZE_BYTES`.
354 */
355#define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x40u
356
357/**
358 * Peripheral base address for usbdev in top earlgrey.
359 *
360 * This should be used with #mmio_region_from_addr to access the memory-mapped
361 * registers associated with the peripheral (usually via a DIF).
362 */
363#define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40320000u
364
365/**
366 * Peripheral size for usbdev in top earlgrey.
367 *
368 * This is the size (in bytes) of the peripheral's reserved memory area. All
369 * memory-mapped registers associated with this peripheral should have an
370 * address between #TOP_EARLGREY_USBDEV_BASE_ADDR and
371 * `TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES`.
372 */
373#define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000u
374
375/**
376 * Peripheral base address for pwrmgr_aon in top earlgrey.
377 *
378 * This should be used with #mmio_region_from_addr to access the memory-mapped
379 * registers associated with the peripheral (usually via a DIF).
380 */
381#define TOP_EARLGREY_PWRMGR_AON_BASE_ADDR 0x40400000u
382
383/**
384 * Peripheral size for pwrmgr_aon in top earlgrey.
385 *
386 * This is the size (in bytes) of the peripheral's reserved memory area. All
387 * memory-mapped registers associated with this peripheral should have an
388 * address between #TOP_EARLGREY_PWRMGR_AON_BASE_ADDR and
389 * `TOP_EARLGREY_PWRMGR_AON_BASE_ADDR + TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES`.
390 */
391#define TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES 0x80u
392
393/**
394 * Peripheral base address for rstmgr_aon in top earlgrey.
395 *
396 * This should be used with #mmio_region_from_addr to access the memory-mapped
397 * registers associated with the peripheral (usually via a DIF).
398 */
399#define TOP_EARLGREY_RSTMGR_AON_BASE_ADDR 0x40410000u
400
401/**
402 * Peripheral size for rstmgr_aon in top earlgrey.
403 *
404 * This is the size (in bytes) of the peripheral's reserved memory area. All
405 * memory-mapped registers associated with this peripheral should have an
406 * address between #TOP_EARLGREY_RSTMGR_AON_BASE_ADDR and
407 * `TOP_EARLGREY_RSTMGR_AON_BASE_ADDR + TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES`.
408 */
409#define TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES 0x80u
410
411/**
412 * Peripheral base address for clkmgr_aon in top earlgrey.
413 *
414 * This should be used with #mmio_region_from_addr to access the memory-mapped
415 * registers associated with the peripheral (usually via a DIF).
416 */
417#define TOP_EARLGREY_CLKMGR_AON_BASE_ADDR 0x40420000u
418
419/**
420 * Peripheral size for clkmgr_aon in top earlgrey.
421 *
422 * This is the size (in bytes) of the peripheral's reserved memory area. All
423 * memory-mapped registers associated with this peripheral should have an
424 * address between #TOP_EARLGREY_CLKMGR_AON_BASE_ADDR and
425 * `TOP_EARLGREY_CLKMGR_AON_BASE_ADDR + TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES`.
426 */
427#define TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES 0x80u
428
429/**
430 * Peripheral base address for sysrst_ctrl_aon in top earlgrey.
431 *
432 * This should be used with #mmio_region_from_addr to access the memory-mapped
433 * registers associated with the peripheral (usually via a DIF).
434 */
435#define TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
436
437/**
438 * Peripheral size for sysrst_ctrl_aon in top earlgrey.
439 *
440 * This is the size (in bytes) of the peripheral's reserved memory area. All
441 * memory-mapped registers associated with this peripheral should have an
442 * address between #TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR and
443 * `TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR + TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES`.
444 */
445#define TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES 0x100u
446
447/**
448 * Peripheral base address for adc_ctrl_aon in top earlgrey.
449 *
450 * This should be used with #mmio_region_from_addr to access the memory-mapped
451 * registers associated with the peripheral (usually via a DIF).
452 */
453#define TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR 0x40440000u
454
455/**
456 * Peripheral size for adc_ctrl_aon in top earlgrey.
457 *
458 * This is the size (in bytes) of the peripheral's reserved memory area. All
459 * memory-mapped registers associated with this peripheral should have an
460 * address between #TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR and
461 * `TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR + TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES`.
462 */
463#define TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES 0x80u
464
465/**
466 * Peripheral base address for pwm_aon in top earlgrey.
467 *
468 * This should be used with #mmio_region_from_addr to access the memory-mapped
469 * registers associated with the peripheral (usually via a DIF).
470 */
471#define TOP_EARLGREY_PWM_AON_BASE_ADDR 0x40450000u
472
473/**
474 * Peripheral size for pwm_aon in top earlgrey.
475 *
476 * This is the size (in bytes) of the peripheral's reserved memory area. All
477 * memory-mapped registers associated with this peripheral should have an
478 * address between #TOP_EARLGREY_PWM_AON_BASE_ADDR and
479 * `TOP_EARLGREY_PWM_AON_BASE_ADDR + TOP_EARLGREY_PWM_AON_SIZE_BYTES`.
480 */
481#define TOP_EARLGREY_PWM_AON_SIZE_BYTES 0x80u
482
483/**
484 * Peripheral base address for pinmux_aon in top earlgrey.
485 *
486 * This should be used with #mmio_region_from_addr to access the memory-mapped
487 * registers associated with the peripheral (usually via a DIF).
488 */
489#define TOP_EARLGREY_PINMUX_AON_BASE_ADDR 0x40460000u
490
491/**
492 * Peripheral size for pinmux_aon in top earlgrey.
493 *
494 * This is the size (in bytes) of the peripheral's reserved memory area. All
495 * memory-mapped registers associated with this peripheral should have an
496 * address between #TOP_EARLGREY_PINMUX_AON_BASE_ADDR and
497 * `TOP_EARLGREY_PINMUX_AON_BASE_ADDR + TOP_EARLGREY_PINMUX_AON_SIZE_BYTES`.
498 */
499#define TOP_EARLGREY_PINMUX_AON_SIZE_BYTES 0x1000u
500
501/**
502 * Peripheral base address for aon_timer_aon in top earlgrey.
503 *
504 * This should be used with #mmio_region_from_addr to access the memory-mapped
505 * registers associated with the peripheral (usually via a DIF).
506 */
507#define TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR 0x40470000u
508
509/**
510 * Peripheral size for aon_timer_aon in top earlgrey.
511 *
512 * This is the size (in bytes) of the peripheral's reserved memory area. All
513 * memory-mapped registers associated with this peripheral should have an
514 * address between #TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR and
515 * `TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR + TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES`.
516 */
517#define TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES 0x40u
518
519/**
520 * Peripheral base address for ast in top earlgrey.
521 *
522 * This should be used with #mmio_region_from_addr to access the memory-mapped
523 * registers associated with the peripheral (usually via a DIF).
524 */
525#define TOP_EARLGREY_AST_BASE_ADDR 0x40480000u
526
527/**
528 * Peripheral size for ast in top earlgrey.
529 *
530 * This is the size (in bytes) of the peripheral's reserved memory area. All
531 * memory-mapped registers associated with this peripheral should have an
532 * address between #TOP_EARLGREY_AST_BASE_ADDR and
533 * `TOP_EARLGREY_AST_BASE_ADDR + TOP_EARLGREY_AST_SIZE_BYTES`.
534 */
535#define TOP_EARLGREY_AST_SIZE_BYTES 0x400u
536
537/**
538 * Peripheral base address for sensor_ctrl_aon in top earlgrey.
539 *
540 * This should be used with #mmio_region_from_addr to access the memory-mapped
541 * registers associated with the peripheral (usually via a DIF).
542 */
543#define TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR 0x40490000u
544
545/**
546 * Peripheral size for sensor_ctrl_aon in top earlgrey.
547 *
548 * This is the size (in bytes) of the peripheral's reserved memory area. All
549 * memory-mapped registers associated with this peripheral should have an
550 * address between #TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR and
551 * `TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES`.
552 */
553#define TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES 0x80u
554
555/**
556 * Peripheral base address for regs device on sram_ctrl_ret_aon in top earlgrey.
557 *
558 * This should be used with #mmio_region_from_addr to access the memory-mapped
559 * registers associated with the peripheral (usually via a DIF).
560 */
561#define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
562
563/**
564 * Peripheral size for regs device on sram_ctrl_ret_aon in top earlgrey.
565 *
566 * This is the size (in bytes) of the peripheral's reserved memory area. All
567 * memory-mapped registers associated with this peripheral should have an
568 * address between #TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
569 * `TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
570 */
571#define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u
572
573/**
574 * Peripheral base address for ram device on sram_ctrl_ret_aon in top earlgrey.
575 *
576 * This should be used with #mmio_region_from_addr to access the memory-mapped
577 * registers associated with the peripheral (usually via a DIF).
578 */
579#define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
580
581/**
582 * Peripheral size for ram device on sram_ctrl_ret_aon in top earlgrey.
583 *
584 * This is the size (in bytes) of the peripheral's reserved memory area. All
585 * memory-mapped registers associated with this peripheral should have an
586 * address between #TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
587 * `TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
588 */
589#define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
590
591/**
592 * Peripheral base address for core device on flash_ctrl in top earlgrey.
593 *
594 * This should be used with #mmio_region_from_addr to access the memory-mapped
595 * registers associated with the peripheral (usually via a DIF).
596 */
597#define TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
598
599/**
600 * Peripheral size for core device on flash_ctrl in top earlgrey.
601 *
602 * This is the size (in bytes) of the peripheral's reserved memory area. All
603 * memory-mapped registers associated with this peripheral should have an
604 * address between #TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR and
605 * `TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES`.
606 */
607#define TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
608
609/**
610 * Peripheral base address for prim device on flash_ctrl in top earlgrey.
611 *
612 * This should be used with #mmio_region_from_addr to access the memory-mapped
613 * registers associated with the peripheral (usually via a DIF).
614 */
615#define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u
616
617/**
618 * Peripheral size for prim device on flash_ctrl in top earlgrey.
619 *
620 * This is the size (in bytes) of the peripheral's reserved memory area. All
621 * memory-mapped registers associated with this peripheral should have an
622 * address between #TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR and
623 * `TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES`.
624 */
625#define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u
626
627/**
628 * Peripheral base address for mem device on flash_ctrl in top earlgrey.
629 *
630 * This should be used with #mmio_region_from_addr to access the memory-mapped
631 * registers associated with the peripheral (usually via a DIF).
632 */
633#define TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
634
635/**
636 * Peripheral size for mem device on flash_ctrl in top earlgrey.
637 *
638 * This is the size (in bytes) of the peripheral's reserved memory area. All
639 * memory-mapped registers associated with this peripheral should have an
640 * address between #TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR and
641 * `TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES`.
642 */
643#define TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u
644
645/**
646 * Peripheral base address for regs device on rv_dm in top earlgrey.
647 *
648 * This should be used with #mmio_region_from_addr to access the memory-mapped
649 * registers associated with the peripheral (usually via a DIF).
650 */
651#define TOP_EARLGREY_RV_DM_REGS_BASE_ADDR 0x41200000u
652
653/**
654 * Peripheral size for regs device on rv_dm in top earlgrey.
655 *
656 * This is the size (in bytes) of the peripheral's reserved memory area. All
657 * memory-mapped registers associated with this peripheral should have an
658 * address between #TOP_EARLGREY_RV_DM_REGS_BASE_ADDR and
659 * `TOP_EARLGREY_RV_DM_REGS_BASE_ADDR + TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES`.
660 */
661#define TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES 0x10u
662
663/**
664 * Peripheral base address for mem device on rv_dm in top earlgrey.
665 *
666 * This should be used with #mmio_region_from_addr to access the memory-mapped
667 * registers associated with the peripheral (usually via a DIF).
668 */
669#define TOP_EARLGREY_RV_DM_MEM_BASE_ADDR 0x10000u
670
671/**
672 * Peripheral size for mem device on rv_dm in top earlgrey.
673 *
674 * This is the size (in bytes) of the peripheral's reserved memory area. All
675 * memory-mapped registers associated with this peripheral should have an
676 * address between #TOP_EARLGREY_RV_DM_MEM_BASE_ADDR and
677 * `TOP_EARLGREY_RV_DM_MEM_BASE_ADDR + TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES`.
678 */
679#define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000u
680
681/**
682 * Peripheral base address for dbg device on rv_dm in top earlgrey.
683 *
684 * This should be used with #mmio_region_from_addr to access the memory-mapped
685 * registers associated with the peripheral (usually via a DIF).
686 */
687#define TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000u
688
689/**
690 * Peripheral size for dbg device on rv_dm in top earlgrey.
691 *
692 * This is the size (in bytes) of the peripheral's reserved memory area. All
693 * memory-mapped registers associated with this peripheral should have an
694 * address between #TOP_EARLGREY_RV_DM_DBG_BASE_ADDR and
695 * `TOP_EARLGREY_RV_DM_DBG_BASE_ADDR + TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES`.
696 */
697#define TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200u
698
699/**
700 * Peripheral base address for rv_plic in top earlgrey.
701 *
702 * This should be used with #mmio_region_from_addr to access the memory-mapped
703 * registers associated with the peripheral (usually via a DIF).
704 */
705#define TOP_EARLGREY_RV_PLIC_BASE_ADDR 0x48000000u
706
707/**
708 * Peripheral size for rv_plic in top earlgrey.
709 *
710 * This is the size (in bytes) of the peripheral's reserved memory area. All
711 * memory-mapped registers associated with this peripheral should have an
712 * address between #TOP_EARLGREY_RV_PLIC_BASE_ADDR and
713 * `TOP_EARLGREY_RV_PLIC_BASE_ADDR + TOP_EARLGREY_RV_PLIC_SIZE_BYTES`.
714 */
715#define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x8000000u
716
717/**
718 * Peripheral base address for aes in top earlgrey.
719 *
720 * This should be used with #mmio_region_from_addr to access the memory-mapped
721 * registers associated with the peripheral (usually via a DIF).
722 */
723#define TOP_EARLGREY_AES_BASE_ADDR 0x41100000u
724
725/**
726 * Peripheral size for aes in top earlgrey.
727 *
728 * This is the size (in bytes) of the peripheral's reserved memory area. All
729 * memory-mapped registers associated with this peripheral should have an
730 * address between #TOP_EARLGREY_AES_BASE_ADDR and
731 * `TOP_EARLGREY_AES_BASE_ADDR + TOP_EARLGREY_AES_SIZE_BYTES`.
732 */
733#define TOP_EARLGREY_AES_SIZE_BYTES 0x100u
734
735/**
736 * Peripheral base address for hmac in top earlgrey.
737 *
738 * This should be used with #mmio_region_from_addr to access the memory-mapped
739 * registers associated with the peripheral (usually via a DIF).
740 */
741#define TOP_EARLGREY_HMAC_BASE_ADDR 0x41110000u
742
743/**
744 * Peripheral size for hmac in top earlgrey.
745 *
746 * This is the size (in bytes) of the peripheral's reserved memory area. All
747 * memory-mapped registers associated with this peripheral should have an
748 * address between #TOP_EARLGREY_HMAC_BASE_ADDR and
749 * `TOP_EARLGREY_HMAC_BASE_ADDR + TOP_EARLGREY_HMAC_SIZE_BYTES`.
750 */
751#define TOP_EARLGREY_HMAC_SIZE_BYTES 0x2000u
752
753/**
754 * Peripheral base address for kmac in top earlgrey.
755 *
756 * This should be used with #mmio_region_from_addr to access the memory-mapped
757 * registers associated with the peripheral (usually via a DIF).
758 */
759#define TOP_EARLGREY_KMAC_BASE_ADDR 0x41120000u
760
761/**
762 * Peripheral size for kmac in top earlgrey.
763 *
764 * This is the size (in bytes) of the peripheral's reserved memory area. All
765 * memory-mapped registers associated with this peripheral should have an
766 * address between #TOP_EARLGREY_KMAC_BASE_ADDR and
767 * `TOP_EARLGREY_KMAC_BASE_ADDR + TOP_EARLGREY_KMAC_SIZE_BYTES`.
768 */
769#define TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000u
770
771/**
772 * Peripheral base address for otbn in top earlgrey.
773 *
774 * This should be used with #mmio_region_from_addr to access the memory-mapped
775 * registers associated with the peripheral (usually via a DIF).
776 */
777#define TOP_EARLGREY_OTBN_BASE_ADDR 0x41130000u
778
779/**
780 * Peripheral size for otbn in top earlgrey.
781 *
782 * This is the size (in bytes) of the peripheral's reserved memory area. All
783 * memory-mapped registers associated with this peripheral should have an
784 * address between #TOP_EARLGREY_OTBN_BASE_ADDR and
785 * `TOP_EARLGREY_OTBN_BASE_ADDR + TOP_EARLGREY_OTBN_SIZE_BYTES`.
786 */
787#define TOP_EARLGREY_OTBN_SIZE_BYTES 0x10000u
788
789/**
790 * Peripheral base address for keymgr in top earlgrey.
791 *
792 * This should be used with #mmio_region_from_addr to access the memory-mapped
793 * registers associated with the peripheral (usually via a DIF).
794 */
795#define TOP_EARLGREY_KEYMGR_BASE_ADDR 0x41140000u
796
797/**
798 * Peripheral size for keymgr in top earlgrey.
799 *
800 * This is the size (in bytes) of the peripheral's reserved memory area. All
801 * memory-mapped registers associated with this peripheral should have an
802 * address between #TOP_EARLGREY_KEYMGR_BASE_ADDR and
803 * `TOP_EARLGREY_KEYMGR_BASE_ADDR + TOP_EARLGREY_KEYMGR_SIZE_BYTES`.
804 */
805#define TOP_EARLGREY_KEYMGR_SIZE_BYTES 0x100u
806
807/**
808 * Peripheral base address for csrng in top earlgrey.
809 *
810 * This should be used with #mmio_region_from_addr to access the memory-mapped
811 * registers associated with the peripheral (usually via a DIF).
812 */
813#define TOP_EARLGREY_CSRNG_BASE_ADDR 0x41150000u
814
815/**
816 * Peripheral size for csrng in top earlgrey.
817 *
818 * This is the size (in bytes) of the peripheral's reserved memory area. All
819 * memory-mapped registers associated with this peripheral should have an
820 * address between #TOP_EARLGREY_CSRNG_BASE_ADDR and
821 * `TOP_EARLGREY_CSRNG_BASE_ADDR + TOP_EARLGREY_CSRNG_SIZE_BYTES`.
822 */
823#define TOP_EARLGREY_CSRNG_SIZE_BYTES 0x80u
824
825/**
826 * Peripheral base address for entropy_src in top earlgrey.
827 *
828 * This should be used with #mmio_region_from_addr to access the memory-mapped
829 * registers associated with the peripheral (usually via a DIF).
830 */
831#define TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR 0x41160000u
832
833/**
834 * Peripheral size for entropy_src in top earlgrey.
835 *
836 * This is the size (in bytes) of the peripheral's reserved memory area. All
837 * memory-mapped registers associated with this peripheral should have an
838 * address between #TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR and
839 * `TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR + TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES`.
840 */
841#define TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES 0x100u
842
843/**
844 * Peripheral base address for edn0 in top earlgrey.
845 *
846 * This should be used with #mmio_region_from_addr to access the memory-mapped
847 * registers associated with the peripheral (usually via a DIF).
848 */
849#define TOP_EARLGREY_EDN0_BASE_ADDR 0x41170000u
850
851/**
852 * Peripheral size for edn0 in top earlgrey.
853 *
854 * This is the size (in bytes) of the peripheral's reserved memory area. All
855 * memory-mapped registers associated with this peripheral should have an
856 * address between #TOP_EARLGREY_EDN0_BASE_ADDR and
857 * `TOP_EARLGREY_EDN0_BASE_ADDR + TOP_EARLGREY_EDN0_SIZE_BYTES`.
858 */
859#define TOP_EARLGREY_EDN0_SIZE_BYTES 0x80u
860
861/**
862 * Peripheral base address for edn1 in top earlgrey.
863 *
864 * This should be used with #mmio_region_from_addr to access the memory-mapped
865 * registers associated with the peripheral (usually via a DIF).
866 */
867#define TOP_EARLGREY_EDN1_BASE_ADDR 0x41180000u
868
869/**
870 * Peripheral size for edn1 in top earlgrey.
871 *
872 * This is the size (in bytes) of the peripheral's reserved memory area. All
873 * memory-mapped registers associated with this peripheral should have an
874 * address between #TOP_EARLGREY_EDN1_BASE_ADDR and
875 * `TOP_EARLGREY_EDN1_BASE_ADDR + TOP_EARLGREY_EDN1_SIZE_BYTES`.
876 */
877#define TOP_EARLGREY_EDN1_SIZE_BYTES 0x80u
878
879/**
880 * Peripheral base address for regs device on sram_ctrl_main in top earlgrey.
881 *
882 * This should be used with #mmio_region_from_addr to access the memory-mapped
883 * registers associated with the peripheral (usually via a DIF).
884 */
885#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
886
887/**
888 * Peripheral size for regs device on sram_ctrl_main in top earlgrey.
889 *
890 * This is the size (in bytes) of the peripheral's reserved memory area. All
891 * memory-mapped registers associated with this peripheral should have an
892 * address between #TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
893 * `TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
894 */
895#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
896
897/**
898 * Peripheral base address for ram device on sram_ctrl_main in top earlgrey.
899 *
900 * This should be used with #mmio_region_from_addr to access the memory-mapped
901 * registers associated with the peripheral (usually via a DIF).
902 */
903#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
904
905/**
906 * Peripheral size for ram device on sram_ctrl_main in top earlgrey.
907 *
908 * This is the size (in bytes) of the peripheral's reserved memory area. All
909 * memory-mapped registers associated with this peripheral should have an
910 * address between #TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
911 * `TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
912 */
913#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
914
915/**
916 * Peripheral base address for regs device on rom_ctrl in top earlgrey.
917 *
918 * This should be used with #mmio_region_from_addr to access the memory-mapped
919 * registers associated with the peripheral (usually via a DIF).
920 */
921#define TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
922
923/**
924 * Peripheral size for regs device on rom_ctrl in top earlgrey.
925 *
926 * This is the size (in bytes) of the peripheral's reserved memory area. All
927 * memory-mapped registers associated with this peripheral should have an
928 * address between #TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR and
929 * `TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES`.
930 */
931#define TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES 0x80u
932
933/**
934 * Peripheral base address for rom device on rom_ctrl in top earlgrey.
935 *
936 * This should be used with #mmio_region_from_addr to access the memory-mapped
937 * registers associated with the peripheral (usually via a DIF).
938 */
939#define TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR 0x8000u
940
941/**
942 * Peripheral size for rom device on rom_ctrl in top earlgrey.
943 *
944 * This is the size (in bytes) of the peripheral's reserved memory area. All
945 * memory-mapped registers associated with this peripheral should have an
946 * address between #TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR and
947 * `TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES`.
948 */
949#define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
950
951/**
952 * Peripheral base address for cfg device on rv_core_ibex in top earlgrey.
953 *
954 * This should be used with #mmio_region_from_addr to access the memory-mapped
955 * registers associated with the peripheral (usually via a DIF).
956 */
957#define TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u
958
959/**
960 * Peripheral size for cfg device on rv_core_ibex in top earlgrey.
961 *
962 * This is the size (in bytes) of the peripheral's reserved memory area. All
963 * memory-mapped registers associated with this peripheral should have an
964 * address between #TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR and
965 * `TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES`.
966 */
967#define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u
968
969
970/**
971 * Memory base address for ram_ret_aon in top earlgrey.
972 */
973#define TOP_EARLGREY_RAM_RET_AON_BASE_ADDR 0x40600000u
974
975/**
976 * Memory size for ram_ret_aon in top earlgrey.
977 */
978#define TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES 0x1000u
979
980/**
981 * Memory base address for eflash in top earlgrey.
982 */
983#define TOP_EARLGREY_EFLASH_BASE_ADDR 0x20000000u
984
985/**
986 * Memory size for eflash in top earlgrey.
987 */
988#define TOP_EARLGREY_EFLASH_SIZE_BYTES 0x100000u
989
990/**
991 * Memory base address for ram_main in top earlgrey.
992 */
993#define TOP_EARLGREY_RAM_MAIN_BASE_ADDR 0x10000000u
994
995/**
996 * Memory size for ram_main in top earlgrey.
997 */
998#define TOP_EARLGREY_RAM_MAIN_SIZE_BYTES 0x20000u
999
1000/**
1001 * Memory base address for rom in top earlgrey.
1002 */
1003#define TOP_EARLGREY_ROM_BASE_ADDR 0x8000u
1004
1005/**
1006 * Memory size for rom in top earlgrey.
1007 */
1008#define TOP_EARLGREY_ROM_SIZE_BYTES 0x8000u
1009
1010
1011/**
1012 * PLIC Interrupt Source Peripheral.
1013 *
1014 * Enumeration used to determine which peripheral asserted the corresponding
1015 * interrupt.
1016 */
1017typedef enum top_earlgrey_plic_peripheral {
1018 kTopEarlgreyPlicPeripheralUnknown = 0, /**< Unknown Peripheral */
1019 kTopEarlgreyPlicPeripheralUart0 = 1, /**< uart0 */
1020 kTopEarlgreyPlicPeripheralUart1 = 2, /**< uart1 */
1021 kTopEarlgreyPlicPeripheralUart2 = 3, /**< uart2 */
1022 kTopEarlgreyPlicPeripheralUart3 = 4, /**< uart3 */
1023 kTopEarlgreyPlicPeripheralGpio = 5, /**< gpio */
1024 kTopEarlgreyPlicPeripheralSpiDevice = 6, /**< spi_device */
1025 kTopEarlgreyPlicPeripheralI2c0 = 7, /**< i2c0 */
1026 kTopEarlgreyPlicPeripheralI2c1 = 8, /**< i2c1 */
1027 kTopEarlgreyPlicPeripheralI2c2 = 9, /**< i2c2 */
1028 kTopEarlgreyPlicPeripheralPattgen = 10, /**< pattgen */
1029 kTopEarlgreyPlicPeripheralRvTimer = 11, /**< rv_timer */
1030 kTopEarlgreyPlicPeripheralOtpCtrl = 12, /**< otp_ctrl */
1031 kTopEarlgreyPlicPeripheralAlertHandler = 13, /**< alert_handler */
1032 kTopEarlgreyPlicPeripheralSpiHost0 = 14, /**< spi_host0 */
1033 kTopEarlgreyPlicPeripheralSpiHost1 = 15, /**< spi_host1 */
1034 kTopEarlgreyPlicPeripheralUsbdev = 16, /**< usbdev */
1035 kTopEarlgreyPlicPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
1036 kTopEarlgreyPlicPeripheralSysrstCtrlAon = 18, /**< sysrst_ctrl_aon */
1037 kTopEarlgreyPlicPeripheralAdcCtrlAon = 19, /**< adc_ctrl_aon */
1038 kTopEarlgreyPlicPeripheralAonTimerAon = 20, /**< aon_timer_aon */
1039 kTopEarlgreyPlicPeripheralSensorCtrlAon = 21, /**< sensor_ctrl_aon */
1040 kTopEarlgreyPlicPeripheralFlashCtrl = 22, /**< flash_ctrl */
1041 kTopEarlgreyPlicPeripheralHmac = 23, /**< hmac */
1042 kTopEarlgreyPlicPeripheralKmac = 24, /**< kmac */
1043 kTopEarlgreyPlicPeripheralOtbn = 25, /**< otbn */
1044 kTopEarlgreyPlicPeripheralKeymgr = 26, /**< keymgr */
1045 kTopEarlgreyPlicPeripheralCsrng = 27, /**< csrng */
1046 kTopEarlgreyPlicPeripheralEntropySrc = 28, /**< entropy_src */
1047 kTopEarlgreyPlicPeripheralEdn0 = 29, /**< edn0 */
1048 kTopEarlgreyPlicPeripheralEdn1 = 30, /**< edn1 */
1049 kTopEarlgreyPlicPeripheralLast = 30, /**< \internal Final PLIC peripheral */
1050} top_earlgrey_plic_peripheral_t;
1051
1052/**
1053 * PLIC Interrupt Source.
1054 *
1055 * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
1056 * the same peripheral are guaranteed to be consecutive.
1057 */
1058typedef enum top_earlgrey_plic_irq_id {
1059 kTopEarlgreyPlicIrqIdNone = 0, /**< No Interrupt */
1060 kTopEarlgreyPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
1061 kTopEarlgreyPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
1062 kTopEarlgreyPlicIrqIdUart0TxDone = 3, /**< uart0_tx_done */
1063 kTopEarlgreyPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
1064 kTopEarlgreyPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
1065 kTopEarlgreyPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
1066 kTopEarlgreyPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
1067 kTopEarlgreyPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
1068 kTopEarlgreyPlicIrqIdUart0TxEmpty = 9, /**< uart0_tx_empty */
1069 kTopEarlgreyPlicIrqIdUart1TxWatermark = 10, /**< uart1_tx_watermark */
1070 kTopEarlgreyPlicIrqIdUart1RxWatermark = 11, /**< uart1_rx_watermark */
1071 kTopEarlgreyPlicIrqIdUart1TxDone = 12, /**< uart1_tx_done */
1072 kTopEarlgreyPlicIrqIdUart1RxOverflow = 13, /**< uart1_rx_overflow */
1073 kTopEarlgreyPlicIrqIdUart1RxFrameErr = 14, /**< uart1_rx_frame_err */
1074 kTopEarlgreyPlicIrqIdUart1RxBreakErr = 15, /**< uart1_rx_break_err */
1075 kTopEarlgreyPlicIrqIdUart1RxTimeout = 16, /**< uart1_rx_timeout */
1076 kTopEarlgreyPlicIrqIdUart1RxParityErr = 17, /**< uart1_rx_parity_err */
1077 kTopEarlgreyPlicIrqIdUart1TxEmpty = 18, /**< uart1_tx_empty */
1078 kTopEarlgreyPlicIrqIdUart2TxWatermark = 19, /**< uart2_tx_watermark */
1079 kTopEarlgreyPlicIrqIdUart2RxWatermark = 20, /**< uart2_rx_watermark */
1080 kTopEarlgreyPlicIrqIdUart2TxDone = 21, /**< uart2_tx_done */
1081 kTopEarlgreyPlicIrqIdUart2RxOverflow = 22, /**< uart2_rx_overflow */
1082 kTopEarlgreyPlicIrqIdUart2RxFrameErr = 23, /**< uart2_rx_frame_err */
1083 kTopEarlgreyPlicIrqIdUart2RxBreakErr = 24, /**< uart2_rx_break_err */
1084 kTopEarlgreyPlicIrqIdUart2RxTimeout = 25, /**< uart2_rx_timeout */
1085 kTopEarlgreyPlicIrqIdUart2RxParityErr = 26, /**< uart2_rx_parity_err */
1086 kTopEarlgreyPlicIrqIdUart2TxEmpty = 27, /**< uart2_tx_empty */
1087 kTopEarlgreyPlicIrqIdUart3TxWatermark = 28, /**< uart3_tx_watermark */
1088 kTopEarlgreyPlicIrqIdUart3RxWatermark = 29, /**< uart3_rx_watermark */
1089 kTopEarlgreyPlicIrqIdUart3TxDone = 30, /**< uart3_tx_done */
1090 kTopEarlgreyPlicIrqIdUart3RxOverflow = 31, /**< uart3_rx_overflow */
1091 kTopEarlgreyPlicIrqIdUart3RxFrameErr = 32, /**< uart3_rx_frame_err */
1092 kTopEarlgreyPlicIrqIdUart3RxBreakErr = 33, /**< uart3_rx_break_err */
1093 kTopEarlgreyPlicIrqIdUart3RxTimeout = 34, /**< uart3_rx_timeout */
1094 kTopEarlgreyPlicIrqIdUart3RxParityErr = 35, /**< uart3_rx_parity_err */
1095 kTopEarlgreyPlicIrqIdUart3TxEmpty = 36, /**< uart3_tx_empty */
1096 kTopEarlgreyPlicIrqIdGpioGpio0 = 37, /**< gpio_gpio 0 */
1097 kTopEarlgreyPlicIrqIdGpioGpio1 = 38, /**< gpio_gpio 1 */
1098 kTopEarlgreyPlicIrqIdGpioGpio2 = 39, /**< gpio_gpio 2 */
1099 kTopEarlgreyPlicIrqIdGpioGpio3 = 40, /**< gpio_gpio 3 */
1100 kTopEarlgreyPlicIrqIdGpioGpio4 = 41, /**< gpio_gpio 4 */
1101 kTopEarlgreyPlicIrqIdGpioGpio5 = 42, /**< gpio_gpio 5 */
1102 kTopEarlgreyPlicIrqIdGpioGpio6 = 43, /**< gpio_gpio 6 */
1103 kTopEarlgreyPlicIrqIdGpioGpio7 = 44, /**< gpio_gpio 7 */
1104 kTopEarlgreyPlicIrqIdGpioGpio8 = 45, /**< gpio_gpio 8 */
1105 kTopEarlgreyPlicIrqIdGpioGpio9 = 46, /**< gpio_gpio 9 */
1106 kTopEarlgreyPlicIrqIdGpioGpio10 = 47, /**< gpio_gpio 10 */
1107 kTopEarlgreyPlicIrqIdGpioGpio11 = 48, /**< gpio_gpio 11 */
1108 kTopEarlgreyPlicIrqIdGpioGpio12 = 49, /**< gpio_gpio 12 */
1109 kTopEarlgreyPlicIrqIdGpioGpio13 = 50, /**< gpio_gpio 13 */
1110 kTopEarlgreyPlicIrqIdGpioGpio14 = 51, /**< gpio_gpio 14 */
1111 kTopEarlgreyPlicIrqIdGpioGpio15 = 52, /**< gpio_gpio 15 */
1112 kTopEarlgreyPlicIrqIdGpioGpio16 = 53, /**< gpio_gpio 16 */
1113 kTopEarlgreyPlicIrqIdGpioGpio17 = 54, /**< gpio_gpio 17 */
1114 kTopEarlgreyPlicIrqIdGpioGpio18 = 55, /**< gpio_gpio 18 */
1115 kTopEarlgreyPlicIrqIdGpioGpio19 = 56, /**< gpio_gpio 19 */
1116 kTopEarlgreyPlicIrqIdGpioGpio20 = 57, /**< gpio_gpio 20 */
1117 kTopEarlgreyPlicIrqIdGpioGpio21 = 58, /**< gpio_gpio 21 */
1118 kTopEarlgreyPlicIrqIdGpioGpio22 = 59, /**< gpio_gpio 22 */
1119 kTopEarlgreyPlicIrqIdGpioGpio23 = 60, /**< gpio_gpio 23 */
1120 kTopEarlgreyPlicIrqIdGpioGpio24 = 61, /**< gpio_gpio 24 */
1121 kTopEarlgreyPlicIrqIdGpioGpio25 = 62, /**< gpio_gpio 25 */
1122 kTopEarlgreyPlicIrqIdGpioGpio26 = 63, /**< gpio_gpio 26 */
1123 kTopEarlgreyPlicIrqIdGpioGpio27 = 64, /**< gpio_gpio 27 */
1124 kTopEarlgreyPlicIrqIdGpioGpio28 = 65, /**< gpio_gpio 28 */
1125 kTopEarlgreyPlicIrqIdGpioGpio29 = 66, /**< gpio_gpio 29 */
1126 kTopEarlgreyPlicIrqIdGpioGpio30 = 67, /**< gpio_gpio 30 */
1127 kTopEarlgreyPlicIrqIdGpioGpio31 = 68, /**< gpio_gpio 31 */
1128 kTopEarlgreyPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 69, /**< spi_device_upload_cmdfifo_not_empty */
1129 kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 70, /**< spi_device_upload_payload_not_empty */
1130 kTopEarlgreyPlicIrqIdSpiDeviceUploadPayloadOverflow = 71, /**< spi_device_upload_payload_overflow */
1131 kTopEarlgreyPlicIrqIdSpiDeviceReadbufWatermark = 72, /**< spi_device_readbuf_watermark */
1132 kTopEarlgreyPlicIrqIdSpiDeviceReadbufFlip = 73, /**< spi_device_readbuf_flip */
1133 kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 74, /**< spi_device_tpm_header_not_empty */
1134 kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 75, /**< spi_device_tpm_rdfifo_cmd_end */
1135 kTopEarlgreyPlicIrqIdSpiDeviceTpmRdfifoDrop = 76, /**< spi_device_tpm_rdfifo_drop */
1136 kTopEarlgreyPlicIrqIdI2c0FmtThreshold = 77, /**< i2c0_fmt_threshold */
1137 kTopEarlgreyPlicIrqIdI2c0RxThreshold = 78, /**< i2c0_rx_threshold */
1138 kTopEarlgreyPlicIrqIdI2c0AcqThreshold = 79, /**< i2c0_acq_threshold */
1139 kTopEarlgreyPlicIrqIdI2c0RxOverflow = 80, /**< i2c0_rx_overflow */
1140 kTopEarlgreyPlicIrqIdI2c0ControllerHalt = 81, /**< i2c0_controller_halt */
1141 kTopEarlgreyPlicIrqIdI2c0SclInterference = 82, /**< i2c0_scl_interference */
1142 kTopEarlgreyPlicIrqIdI2c0SdaInterference = 83, /**< i2c0_sda_interference */
1143 kTopEarlgreyPlicIrqIdI2c0StretchTimeout = 84, /**< i2c0_stretch_timeout */
1144 kTopEarlgreyPlicIrqIdI2c0SdaUnstable = 85, /**< i2c0_sda_unstable */
1145 kTopEarlgreyPlicIrqIdI2c0CmdComplete = 86, /**< i2c0_cmd_complete */
1146 kTopEarlgreyPlicIrqIdI2c0TxStretch = 87, /**< i2c0_tx_stretch */
1147 kTopEarlgreyPlicIrqIdI2c0TxThreshold = 88, /**< i2c0_tx_threshold */
1148 kTopEarlgreyPlicIrqIdI2c0AcqStretch = 89, /**< i2c0_acq_stretch */
1149 kTopEarlgreyPlicIrqIdI2c0UnexpStop = 90, /**< i2c0_unexp_stop */
1150 kTopEarlgreyPlicIrqIdI2c0HostTimeout = 91, /**< i2c0_host_timeout */
1151 kTopEarlgreyPlicIrqIdI2c1FmtThreshold = 92, /**< i2c1_fmt_threshold */
1152 kTopEarlgreyPlicIrqIdI2c1RxThreshold = 93, /**< i2c1_rx_threshold */
1153 kTopEarlgreyPlicIrqIdI2c1AcqThreshold = 94, /**< i2c1_acq_threshold */
1154 kTopEarlgreyPlicIrqIdI2c1RxOverflow = 95, /**< i2c1_rx_overflow */
1155 kTopEarlgreyPlicIrqIdI2c1ControllerHalt = 96, /**< i2c1_controller_halt */
1156 kTopEarlgreyPlicIrqIdI2c1SclInterference = 97, /**< i2c1_scl_interference */
1157 kTopEarlgreyPlicIrqIdI2c1SdaInterference = 98, /**< i2c1_sda_interference */
1158 kTopEarlgreyPlicIrqIdI2c1StretchTimeout = 99, /**< i2c1_stretch_timeout */
1159 kTopEarlgreyPlicIrqIdI2c1SdaUnstable = 100, /**< i2c1_sda_unstable */
1160 kTopEarlgreyPlicIrqIdI2c1CmdComplete = 101, /**< i2c1_cmd_complete */
1161 kTopEarlgreyPlicIrqIdI2c1TxStretch = 102, /**< i2c1_tx_stretch */
1162 kTopEarlgreyPlicIrqIdI2c1TxThreshold = 103, /**< i2c1_tx_threshold */
1163 kTopEarlgreyPlicIrqIdI2c1AcqStretch = 104, /**< i2c1_acq_stretch */
1164 kTopEarlgreyPlicIrqIdI2c1UnexpStop = 105, /**< i2c1_unexp_stop */
1165 kTopEarlgreyPlicIrqIdI2c1HostTimeout = 106, /**< i2c1_host_timeout */
1166 kTopEarlgreyPlicIrqIdI2c2FmtThreshold = 107, /**< i2c2_fmt_threshold */
1167 kTopEarlgreyPlicIrqIdI2c2RxThreshold = 108, /**< i2c2_rx_threshold */
1168 kTopEarlgreyPlicIrqIdI2c2AcqThreshold = 109, /**< i2c2_acq_threshold */
1169 kTopEarlgreyPlicIrqIdI2c2RxOverflow = 110, /**< i2c2_rx_overflow */
1170 kTopEarlgreyPlicIrqIdI2c2ControllerHalt = 111, /**< i2c2_controller_halt */
1171 kTopEarlgreyPlicIrqIdI2c2SclInterference = 112, /**< i2c2_scl_interference */
1172 kTopEarlgreyPlicIrqIdI2c2SdaInterference = 113, /**< i2c2_sda_interference */
1173 kTopEarlgreyPlicIrqIdI2c2StretchTimeout = 114, /**< i2c2_stretch_timeout */
1174 kTopEarlgreyPlicIrqIdI2c2SdaUnstable = 115, /**< i2c2_sda_unstable */
1175 kTopEarlgreyPlicIrqIdI2c2CmdComplete = 116, /**< i2c2_cmd_complete */
1176 kTopEarlgreyPlicIrqIdI2c2TxStretch = 117, /**< i2c2_tx_stretch */
1177 kTopEarlgreyPlicIrqIdI2c2TxThreshold = 118, /**< i2c2_tx_threshold */
1178 kTopEarlgreyPlicIrqIdI2c2AcqStretch = 119, /**< i2c2_acq_stretch */
1179 kTopEarlgreyPlicIrqIdI2c2UnexpStop = 120, /**< i2c2_unexp_stop */
1180 kTopEarlgreyPlicIrqIdI2c2HostTimeout = 121, /**< i2c2_host_timeout */
1181 kTopEarlgreyPlicIrqIdPattgenDoneCh0 = 122, /**< pattgen_done_ch0 */
1182 kTopEarlgreyPlicIrqIdPattgenDoneCh1 = 123, /**< pattgen_done_ch1 */
1183 kTopEarlgreyPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 124, /**< rv_timer_timer_expired_hart0_timer0 */
1184 kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 125, /**< otp_ctrl_otp_operation_done */
1185 kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 126, /**< otp_ctrl_otp_error */
1186 kTopEarlgreyPlicIrqIdAlertHandlerClassa = 127, /**< alert_handler_classa */
1187 kTopEarlgreyPlicIrqIdAlertHandlerClassb = 128, /**< alert_handler_classb */
1188 kTopEarlgreyPlicIrqIdAlertHandlerClassc = 129, /**< alert_handler_classc */
1189 kTopEarlgreyPlicIrqIdAlertHandlerClassd = 130, /**< alert_handler_classd */
1190 kTopEarlgreyPlicIrqIdSpiHost0Error = 131, /**< spi_host0_error */
1191 kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 132, /**< spi_host0_spi_event */
1192 kTopEarlgreyPlicIrqIdSpiHost1Error = 133, /**< spi_host1_error */
1193 kTopEarlgreyPlicIrqIdSpiHost1SpiEvent = 134, /**< spi_host1_spi_event */
1194 kTopEarlgreyPlicIrqIdUsbdevPktReceived = 135, /**< usbdev_pkt_received */
1195 kTopEarlgreyPlicIrqIdUsbdevPktSent = 136, /**< usbdev_pkt_sent */
1196 kTopEarlgreyPlicIrqIdUsbdevDisconnected = 137, /**< usbdev_disconnected */
1197 kTopEarlgreyPlicIrqIdUsbdevHostLost = 138, /**< usbdev_host_lost */
1198 kTopEarlgreyPlicIrqIdUsbdevLinkReset = 139, /**< usbdev_link_reset */
1199 kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 140, /**< usbdev_link_suspend */
1200 kTopEarlgreyPlicIrqIdUsbdevLinkResume = 141, /**< usbdev_link_resume */
1201 kTopEarlgreyPlicIrqIdUsbdevAvOutEmpty = 142, /**< usbdev_av_out_empty */
1202 kTopEarlgreyPlicIrqIdUsbdevRxFull = 143, /**< usbdev_rx_full */
1203 kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 144, /**< usbdev_av_overflow */
1204 kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 145, /**< usbdev_link_in_err */
1205 kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 146, /**< usbdev_rx_crc_err */
1206 kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 147, /**< usbdev_rx_pid_err */
1207 kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 148, /**< usbdev_rx_bitstuff_err */
1208 kTopEarlgreyPlicIrqIdUsbdevFrame = 149, /**< usbdev_frame */
1209 kTopEarlgreyPlicIrqIdUsbdevPowered = 150, /**< usbdev_powered */
1210 kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 151, /**< usbdev_link_out_err */
1211 kTopEarlgreyPlicIrqIdUsbdevAvSetupEmpty = 152, /**< usbdev_av_setup_empty */
1212 kTopEarlgreyPlicIrqIdPwrmgrAonWakeup = 153, /**< pwrmgr_aon_wakeup */
1213 kTopEarlgreyPlicIrqIdSysrstCtrlAonEventDetected = 154, /**< sysrst_ctrl_aon_event_detected */
1214 kTopEarlgreyPlicIrqIdAdcCtrlAonMatchPending = 155, /**< adc_ctrl_aon_match_pending */
1215 kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired = 156, /**< aon_timer_aon_wkup_timer_expired */
1216 kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark = 157, /**< aon_timer_aon_wdog_timer_bark */
1217 kTopEarlgreyPlicIrqIdSensorCtrlAonIoStatusChange = 158, /**< sensor_ctrl_aon_io_status_change */
1218 kTopEarlgreyPlicIrqIdSensorCtrlAonInitStatusChange = 159, /**< sensor_ctrl_aon_init_status_change */
1219 kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 160, /**< flash_ctrl_prog_empty */
1220 kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 161, /**< flash_ctrl_prog_lvl */
1221 kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 162, /**< flash_ctrl_rd_full */
1222 kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 163, /**< flash_ctrl_rd_lvl */
1223 kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 164, /**< flash_ctrl_op_done */
1224 kTopEarlgreyPlicIrqIdFlashCtrlCorrErr = 165, /**< flash_ctrl_corr_err */
1225 kTopEarlgreyPlicIrqIdHmacHmacDone = 166, /**< hmac_hmac_done */
1226 kTopEarlgreyPlicIrqIdHmacFifoEmpty = 167, /**< hmac_fifo_empty */
1227 kTopEarlgreyPlicIrqIdHmacHmacErr = 168, /**< hmac_hmac_err */
1228 kTopEarlgreyPlicIrqIdKmacKmacDone = 169, /**< kmac_kmac_done */
1229 kTopEarlgreyPlicIrqIdKmacFifoEmpty = 170, /**< kmac_fifo_empty */
1230 kTopEarlgreyPlicIrqIdKmacKmacErr = 171, /**< kmac_kmac_err */
1231 kTopEarlgreyPlicIrqIdOtbnDone = 172, /**< otbn_done */
1232 kTopEarlgreyPlicIrqIdKeymgrOpDone = 173, /**< keymgr_op_done */
1233 kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 174, /**< csrng_cs_cmd_req_done */
1234 kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 175, /**< csrng_cs_entropy_req */
1235 kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 176, /**< csrng_cs_hw_inst_exc */
1236 kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 177, /**< csrng_cs_fatal_err */
1237 kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 178, /**< entropy_src_es_entropy_valid */
1238 kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 179, /**< entropy_src_es_health_test_failed */
1239 kTopEarlgreyPlicIrqIdEntropySrcEsObserveFifoReady = 180, /**< entropy_src_es_observe_fifo_ready */
1240 kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 181, /**< entropy_src_es_fatal_err */
1241 kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 182, /**< edn0_edn_cmd_req_done */
1242 kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 183, /**< edn0_edn_fatal_err */
1243 kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 184, /**< edn1_edn_cmd_req_done */
1244 kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 185, /**< edn1_edn_fatal_err */
1245 kTopEarlgreyPlicIrqIdLast = 185, /**< \internal The Last Valid Interrupt ID. */
1246} top_earlgrey_plic_irq_id_t;
1247
1248/**
1249 * PLIC Interrupt Source to Peripheral Map
1250 *
1251 * This array is a mapping from `top_earlgrey_plic_irq_id_t` to
1252 * `top_earlgrey_plic_peripheral_t`.
1253 */
1254extern const top_earlgrey_plic_peripheral_t
1255 top_earlgrey_plic_interrupt_for_peripheral[186];
1256
1257/**
1258 * PLIC Interrupt Target.
1259 *
1260 * Enumeration used to determine which set of IE, CC, threshold registers to
1261 * access for a given interrupt target.
1262 */
1263typedef enum top_earlgrey_plic_target {
1264 kTopEarlgreyPlicTargetIbex0 = 0, /**< Ibex Core 0 */
1265 kTopEarlgreyPlicTargetLast = 0, /**< \internal Final PLIC target */
1266} top_earlgrey_plic_target_t;
1267
1268
1269/**
1270 * Alert Handler Source Peripheral.
1271 *
1272 * Enumeration used to determine which peripheral asserted the corresponding
1273 * alert.
1274 */
1275typedef enum top_earlgrey_alert_peripheral {
1276 kTopEarlgreyAlertPeripheralExternal = 0, /**< External Peripheral */
1277 kTopEarlgreyAlertPeripheralUart0 = 1, /**< uart0 */
1278 kTopEarlgreyAlertPeripheralUart1 = 2, /**< uart1 */
1279 kTopEarlgreyAlertPeripheralUart2 = 3, /**< uart2 */
1280 kTopEarlgreyAlertPeripheralUart3 = 4, /**< uart3 */
1281 kTopEarlgreyAlertPeripheralGpio = 5, /**< gpio */
1282 kTopEarlgreyAlertPeripheralSpiDevice = 6, /**< spi_device */
1283 kTopEarlgreyAlertPeripheralI2c0 = 7, /**< i2c0 */
1284 kTopEarlgreyAlertPeripheralI2c1 = 8, /**< i2c1 */
1285 kTopEarlgreyAlertPeripheralI2c2 = 9, /**< i2c2 */
1286 kTopEarlgreyAlertPeripheralPattgen = 10, /**< pattgen */
1287 kTopEarlgreyAlertPeripheralRvTimer = 11, /**< rv_timer */
1288 kTopEarlgreyAlertPeripheralOtpCtrl = 12, /**< otp_ctrl */
1289 kTopEarlgreyAlertPeripheralLcCtrl = 13, /**< lc_ctrl */
1290 kTopEarlgreyAlertPeripheralSpiHost0 = 14, /**< spi_host0 */
1291 kTopEarlgreyAlertPeripheralSpiHost1 = 15, /**< spi_host1 */
1292 kTopEarlgreyAlertPeripheralUsbdev = 16, /**< usbdev */
1293 kTopEarlgreyAlertPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
1294 kTopEarlgreyAlertPeripheralRstmgrAon = 18, /**< rstmgr_aon */
1295 kTopEarlgreyAlertPeripheralClkmgrAon = 19, /**< clkmgr_aon */
1296 kTopEarlgreyAlertPeripheralSysrstCtrlAon = 20, /**< sysrst_ctrl_aon */
1297 kTopEarlgreyAlertPeripheralAdcCtrlAon = 21, /**< adc_ctrl_aon */
1298 kTopEarlgreyAlertPeripheralPwmAon = 22, /**< pwm_aon */
1299 kTopEarlgreyAlertPeripheralPinmuxAon = 23, /**< pinmux_aon */
1300 kTopEarlgreyAlertPeripheralAonTimerAon = 24, /**< aon_timer_aon */
1301 kTopEarlgreyAlertPeripheralSensorCtrlAon = 25, /**< sensor_ctrl_aon */
1302 kTopEarlgreyAlertPeripheralSramCtrlRetAon = 26, /**< sram_ctrl_ret_aon */
1303 kTopEarlgreyAlertPeripheralFlashCtrl = 27, /**< flash_ctrl */
1304 kTopEarlgreyAlertPeripheralRvDm = 28, /**< rv_dm */
1305 kTopEarlgreyAlertPeripheralRvPlic = 29, /**< rv_plic */
1306 kTopEarlgreyAlertPeripheralAes = 30, /**< aes */
1307 kTopEarlgreyAlertPeripheralHmac = 31, /**< hmac */
1308 kTopEarlgreyAlertPeripheralKmac = 32, /**< kmac */
1309 kTopEarlgreyAlertPeripheralOtbn = 33, /**< otbn */
1310 kTopEarlgreyAlertPeripheralKeymgr = 34, /**< keymgr */
1311 kTopEarlgreyAlertPeripheralCsrng = 35, /**< csrng */
1312 kTopEarlgreyAlertPeripheralEntropySrc = 36, /**< entropy_src */
1313 kTopEarlgreyAlertPeripheralEdn0 = 37, /**< edn0 */
1314 kTopEarlgreyAlertPeripheralEdn1 = 38, /**< edn1 */
1315 kTopEarlgreyAlertPeripheralSramCtrlMain = 39, /**< sram_ctrl_main */
1316 kTopEarlgreyAlertPeripheralRomCtrl = 40, /**< rom_ctrl */
1317 kTopEarlgreyAlertPeripheralRvCoreIbex = 41, /**< rv_core_ibex */
1318 kTopEarlgreyAlertPeripheralLast = 41, /**< \internal Final Alert peripheral */
1319} top_earlgrey_alert_peripheral_t;
1320
1321/**
1322 * Alert Handler Alert Source.
1323 *
1324 * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
1325 * the same peripheral are guaranteed to be consecutive.
1326 */
1327typedef enum top_earlgrey_alert_id {
1328 kTopEarlgreyAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */
1329 kTopEarlgreyAlertIdUart1FatalFault = 1, /**< uart1_fatal_fault */
1330 kTopEarlgreyAlertIdUart2FatalFault = 2, /**< uart2_fatal_fault */
1331 kTopEarlgreyAlertIdUart3FatalFault = 3, /**< uart3_fatal_fault */
1332 kTopEarlgreyAlertIdGpioFatalFault = 4, /**< gpio_fatal_fault */
1333 kTopEarlgreyAlertIdSpiDeviceFatalFault = 5, /**< spi_device_fatal_fault */
1334 kTopEarlgreyAlertIdI2c0FatalFault = 6, /**< i2c0_fatal_fault */
1335 kTopEarlgreyAlertIdI2c1FatalFault = 7, /**< i2c1_fatal_fault */
1336 kTopEarlgreyAlertIdI2c2FatalFault = 8, /**< i2c2_fatal_fault */
1337 kTopEarlgreyAlertIdPattgenFatalFault = 9, /**< pattgen_fatal_fault */
1338 kTopEarlgreyAlertIdRvTimerFatalFault = 10, /**< rv_timer_fatal_fault */
1339 kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 11, /**< otp_ctrl_fatal_macro_error */
1340 kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 12, /**< otp_ctrl_fatal_check_error */
1341 kTopEarlgreyAlertIdOtpCtrlFatalBusIntegError = 13, /**< otp_ctrl_fatal_bus_integ_error */
1342 kTopEarlgreyAlertIdOtpCtrlFatalPrimOtpAlert = 14, /**< otp_ctrl_fatal_prim_otp_alert */
1343 kTopEarlgreyAlertIdOtpCtrlRecovPrimOtpAlert = 15, /**< otp_ctrl_recov_prim_otp_alert */
1344 kTopEarlgreyAlertIdLcCtrlFatalProgError = 16, /**< lc_ctrl_fatal_prog_error */
1345 kTopEarlgreyAlertIdLcCtrlFatalStateError = 17, /**< lc_ctrl_fatal_state_error */
1346 kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 18, /**< lc_ctrl_fatal_bus_integ_error */
1347 kTopEarlgreyAlertIdSpiHost0FatalFault = 19, /**< spi_host0_fatal_fault */
1348 kTopEarlgreyAlertIdSpiHost1FatalFault = 20, /**< spi_host1_fatal_fault */
1349 kTopEarlgreyAlertIdUsbdevFatalFault = 21, /**< usbdev_fatal_fault */
1350 kTopEarlgreyAlertIdPwrmgrAonFatalFault = 22, /**< pwrmgr_aon_fatal_fault */
1351 kTopEarlgreyAlertIdRstmgrAonFatalFault = 23, /**< rstmgr_aon_fatal_fault */
1352 kTopEarlgreyAlertIdRstmgrAonFatalCnstyFault = 24, /**< rstmgr_aon_fatal_cnsty_fault */
1353 kTopEarlgreyAlertIdClkmgrAonRecovFault = 25, /**< clkmgr_aon_recov_fault */
1354 kTopEarlgreyAlertIdClkmgrAonFatalFault = 26, /**< clkmgr_aon_fatal_fault */
1355 kTopEarlgreyAlertIdSysrstCtrlAonFatalFault = 27, /**< sysrst_ctrl_aon_fatal_fault */
1356 kTopEarlgreyAlertIdAdcCtrlAonFatalFault = 28, /**< adc_ctrl_aon_fatal_fault */
1357 kTopEarlgreyAlertIdPwmAonFatalFault = 29, /**< pwm_aon_fatal_fault */
1358 kTopEarlgreyAlertIdPinmuxAonFatalFault = 30, /**< pinmux_aon_fatal_fault */
1359 kTopEarlgreyAlertIdAonTimerAonFatalFault = 31, /**< aon_timer_aon_fatal_fault */
1360 kTopEarlgreyAlertIdSensorCtrlAonRecovAlert = 32, /**< sensor_ctrl_aon_recov_alert */
1361 kTopEarlgreyAlertIdSensorCtrlAonFatalAlert = 33, /**< sensor_ctrl_aon_fatal_alert */
1362 kTopEarlgreyAlertIdSramCtrlRetAonFatalError = 34, /**< sram_ctrl_ret_aon_fatal_error */
1363 kTopEarlgreyAlertIdFlashCtrlRecovErr = 35, /**< flash_ctrl_recov_err */
1364 kTopEarlgreyAlertIdFlashCtrlFatalStdErr = 36, /**< flash_ctrl_fatal_std_err */
1365 kTopEarlgreyAlertIdFlashCtrlFatalErr = 37, /**< flash_ctrl_fatal_err */
1366 kTopEarlgreyAlertIdFlashCtrlFatalPrimFlashAlert = 38, /**< flash_ctrl_fatal_prim_flash_alert */
1367 kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 39, /**< flash_ctrl_recov_prim_flash_alert */
1368 kTopEarlgreyAlertIdRvDmFatalFault = 40, /**< rv_dm_fatal_fault */
1369 kTopEarlgreyAlertIdRvPlicFatalFault = 41, /**< rv_plic_fatal_fault */
1370 kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 42, /**< aes_recov_ctrl_update_err */
1371 kTopEarlgreyAlertIdAesFatalFault = 43, /**< aes_fatal_fault */
1372 kTopEarlgreyAlertIdHmacFatalFault = 44, /**< hmac_fatal_fault */
1373 kTopEarlgreyAlertIdKmacRecovOperationErr = 45, /**< kmac_recov_operation_err */
1374 kTopEarlgreyAlertIdKmacFatalFaultErr = 46, /**< kmac_fatal_fault_err */
1375 kTopEarlgreyAlertIdOtbnFatal = 47, /**< otbn_fatal */
1376 kTopEarlgreyAlertIdOtbnRecov = 48, /**< otbn_recov */
1377 kTopEarlgreyAlertIdKeymgrRecovOperationErr = 49, /**< keymgr_recov_operation_err */
1378 kTopEarlgreyAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */
1379 kTopEarlgreyAlertIdCsrngRecovAlert = 51, /**< csrng_recov_alert */
1380 kTopEarlgreyAlertIdCsrngFatalAlert = 52, /**< csrng_fatal_alert */
1381 kTopEarlgreyAlertIdEntropySrcRecovAlert = 53, /**< entropy_src_recov_alert */
1382 kTopEarlgreyAlertIdEntropySrcFatalAlert = 54, /**< entropy_src_fatal_alert */
1383 kTopEarlgreyAlertIdEdn0RecovAlert = 55, /**< edn0_recov_alert */
1384 kTopEarlgreyAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */
1385 kTopEarlgreyAlertIdEdn1RecovAlert = 57, /**< edn1_recov_alert */
1386 kTopEarlgreyAlertIdEdn1FatalAlert = 58, /**< edn1_fatal_alert */
1387 kTopEarlgreyAlertIdSramCtrlMainFatalError = 59, /**< sram_ctrl_main_fatal_error */
1388 kTopEarlgreyAlertIdRomCtrlFatal = 60, /**< rom_ctrl_fatal */
1389 kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 61, /**< rv_core_ibex_fatal_sw_err */
1390 kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 62, /**< rv_core_ibex_recov_sw_err */
1391 kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 63, /**< rv_core_ibex_fatal_hw_err */
1392 kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 64, /**< rv_core_ibex_recov_hw_err */
1393 kTopEarlgreyAlertIdLast = 64, /**< \internal The Last Valid Alert ID. */
1394} top_earlgrey_alert_id_t;
1395
1396/**
1397 * Alert Handler Alert Source to Peripheral Map
1398 *
1399 * This array is a mapping from `top_earlgrey_alert_id_t` to
1400 * `top_earlgrey_alert_peripheral_t`.
1401 */
1402extern const top_earlgrey_alert_peripheral_t
1403 top_earlgrey_alert_for_peripheral[65];
1404
1405#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
1406
1407// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
1408// 0 and 1 are tied to value 0 and 1
1409#define NUM_MIO_PADS 47
1410#define NUM_DIO_PADS 16
1411
1412#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
1413
1414/**
1415 * Pinmux Peripheral Input.
1416 */
1417typedef enum top_earlgrey_pinmux_peripheral_in {
1418 kTopEarlgreyPinmuxPeripheralInGpioGpio0 = 0, /**< Peripheral Input 0 */
1419 kTopEarlgreyPinmuxPeripheralInGpioGpio1 = 1, /**< Peripheral Input 1 */
1420 kTopEarlgreyPinmuxPeripheralInGpioGpio2 = 2, /**< Peripheral Input 2 */
1421 kTopEarlgreyPinmuxPeripheralInGpioGpio3 = 3, /**< Peripheral Input 3 */
1422 kTopEarlgreyPinmuxPeripheralInGpioGpio4 = 4, /**< Peripheral Input 4 */
1423 kTopEarlgreyPinmuxPeripheralInGpioGpio5 = 5, /**< Peripheral Input 5 */
1424 kTopEarlgreyPinmuxPeripheralInGpioGpio6 = 6, /**< Peripheral Input 6 */
1425 kTopEarlgreyPinmuxPeripheralInGpioGpio7 = 7, /**< Peripheral Input 7 */
1426 kTopEarlgreyPinmuxPeripheralInGpioGpio8 = 8, /**< Peripheral Input 8 */
1427 kTopEarlgreyPinmuxPeripheralInGpioGpio9 = 9, /**< Peripheral Input 9 */
1428 kTopEarlgreyPinmuxPeripheralInGpioGpio10 = 10, /**< Peripheral Input 10 */
1429 kTopEarlgreyPinmuxPeripheralInGpioGpio11 = 11, /**< Peripheral Input 11 */
1430 kTopEarlgreyPinmuxPeripheralInGpioGpio12 = 12, /**< Peripheral Input 12 */
1431 kTopEarlgreyPinmuxPeripheralInGpioGpio13 = 13, /**< Peripheral Input 13 */
1432 kTopEarlgreyPinmuxPeripheralInGpioGpio14 = 14, /**< Peripheral Input 14 */
1433 kTopEarlgreyPinmuxPeripheralInGpioGpio15 = 15, /**< Peripheral Input 15 */
1434 kTopEarlgreyPinmuxPeripheralInGpioGpio16 = 16, /**< Peripheral Input 16 */
1435 kTopEarlgreyPinmuxPeripheralInGpioGpio17 = 17, /**< Peripheral Input 17 */
1436 kTopEarlgreyPinmuxPeripheralInGpioGpio18 = 18, /**< Peripheral Input 18 */
1437 kTopEarlgreyPinmuxPeripheralInGpioGpio19 = 19, /**< Peripheral Input 19 */
1438 kTopEarlgreyPinmuxPeripheralInGpioGpio20 = 20, /**< Peripheral Input 20 */
1439 kTopEarlgreyPinmuxPeripheralInGpioGpio21 = 21, /**< Peripheral Input 21 */
1440 kTopEarlgreyPinmuxPeripheralInGpioGpio22 = 22, /**< Peripheral Input 22 */
1441 kTopEarlgreyPinmuxPeripheralInGpioGpio23 = 23, /**< Peripheral Input 23 */
1442 kTopEarlgreyPinmuxPeripheralInGpioGpio24 = 24, /**< Peripheral Input 24 */
1443 kTopEarlgreyPinmuxPeripheralInGpioGpio25 = 25, /**< Peripheral Input 25 */
1444 kTopEarlgreyPinmuxPeripheralInGpioGpio26 = 26, /**< Peripheral Input 26 */
1445 kTopEarlgreyPinmuxPeripheralInGpioGpio27 = 27, /**< Peripheral Input 27 */
1446 kTopEarlgreyPinmuxPeripheralInGpioGpio28 = 28, /**< Peripheral Input 28 */
1447 kTopEarlgreyPinmuxPeripheralInGpioGpio29 = 29, /**< Peripheral Input 29 */
1448 kTopEarlgreyPinmuxPeripheralInGpioGpio30 = 30, /**< Peripheral Input 30 */
1449 kTopEarlgreyPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */
1450 kTopEarlgreyPinmuxPeripheralInI2c0Sda = 32, /**< Peripheral Input 32 */
1451 kTopEarlgreyPinmuxPeripheralInI2c0Scl = 33, /**< Peripheral Input 33 */
1452 kTopEarlgreyPinmuxPeripheralInI2c1Sda = 34, /**< Peripheral Input 34 */
1453 kTopEarlgreyPinmuxPeripheralInI2c1Scl = 35, /**< Peripheral Input 35 */
1454 kTopEarlgreyPinmuxPeripheralInI2c2Sda = 36, /**< Peripheral Input 36 */
1455 kTopEarlgreyPinmuxPeripheralInI2c2Scl = 37, /**< Peripheral Input 37 */
1456 kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0 = 38, /**< Peripheral Input 38 */
1457 kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1 = 39, /**< Peripheral Input 39 */
1458 kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2 = 40, /**< Peripheral Input 40 */
1459 kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3 = 41, /**< Peripheral Input 41 */
1460 kTopEarlgreyPinmuxPeripheralInUart0Rx = 42, /**< Peripheral Input 42 */
1461 kTopEarlgreyPinmuxPeripheralInUart1Rx = 43, /**< Peripheral Input 43 */
1462 kTopEarlgreyPinmuxPeripheralInUart2Rx = 44, /**< Peripheral Input 44 */
1463 kTopEarlgreyPinmuxPeripheralInUart3Rx = 45, /**< Peripheral Input 45 */
1464 kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb = 46, /**< Peripheral Input 46 */
1465 kTopEarlgreyPinmuxPeripheralInFlashCtrlTck = 47, /**< Peripheral Input 47 */
1466 kTopEarlgreyPinmuxPeripheralInFlashCtrlTms = 48, /**< Peripheral Input 48 */
1467 kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi = 49, /**< Peripheral Input 49 */
1468 kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonAcPresent = 50, /**< Peripheral Input 50 */
1469 kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey0In = 51, /**< Peripheral Input 51 */
1470 kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey1In = 52, /**< Peripheral Input 52 */
1471 kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey2In = 53, /**< Peripheral Input 53 */
1472 kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonPwrbIn = 54, /**< Peripheral Input 54 */
1473 kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonLidOpen = 55, /**< Peripheral Input 55 */
1474 kTopEarlgreyPinmuxPeripheralInUsbdevSense = 56, /**< Peripheral Input 56 */
1475 kTopEarlgreyPinmuxPeripheralInLast = 56, /**< \internal Last valid peripheral input */
1476} top_earlgrey_pinmux_peripheral_in_t;
1477
1478/**
1479 * Pinmux MIO Input Selector.
1480 */
1481typedef enum top_earlgrey_pinmux_insel {
1482 kTopEarlgreyPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
1483 kTopEarlgreyPinmuxInselConstantOne = 1, /**< Tie constantly to one */
1484 kTopEarlgreyPinmuxInselIoa0 = 2, /**< MIO Pad 0 */
1485 kTopEarlgreyPinmuxInselIoa1 = 3, /**< MIO Pad 1 */
1486 kTopEarlgreyPinmuxInselIoa2 = 4, /**< MIO Pad 2 */
1487 kTopEarlgreyPinmuxInselIoa3 = 5, /**< MIO Pad 3 */
1488 kTopEarlgreyPinmuxInselIoa4 = 6, /**< MIO Pad 4 */
1489 kTopEarlgreyPinmuxInselIoa5 = 7, /**< MIO Pad 5 */
1490 kTopEarlgreyPinmuxInselIoa6 = 8, /**< MIO Pad 6 */
1491 kTopEarlgreyPinmuxInselIoa7 = 9, /**< MIO Pad 7 */
1492 kTopEarlgreyPinmuxInselIoa8 = 10, /**< MIO Pad 8 */
1493 kTopEarlgreyPinmuxInselIob0 = 11, /**< MIO Pad 9 */
1494 kTopEarlgreyPinmuxInselIob1 = 12, /**< MIO Pad 10 */
1495 kTopEarlgreyPinmuxInselIob2 = 13, /**< MIO Pad 11 */
1496 kTopEarlgreyPinmuxInselIob3 = 14, /**< MIO Pad 12 */
1497 kTopEarlgreyPinmuxInselIob4 = 15, /**< MIO Pad 13 */
1498 kTopEarlgreyPinmuxInselIob5 = 16, /**< MIO Pad 14 */
1499 kTopEarlgreyPinmuxInselIob6 = 17, /**< MIO Pad 15 */
1500 kTopEarlgreyPinmuxInselIob7 = 18, /**< MIO Pad 16 */
1501 kTopEarlgreyPinmuxInselIob8 = 19, /**< MIO Pad 17 */
1502 kTopEarlgreyPinmuxInselIob9 = 20, /**< MIO Pad 18 */
1503 kTopEarlgreyPinmuxInselIob10 = 21, /**< MIO Pad 19 */
1504 kTopEarlgreyPinmuxInselIob11 = 22, /**< MIO Pad 20 */
1505 kTopEarlgreyPinmuxInselIob12 = 23, /**< MIO Pad 21 */
1506 kTopEarlgreyPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
1507 kTopEarlgreyPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
1508 kTopEarlgreyPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
1509 kTopEarlgreyPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
1510 kTopEarlgreyPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
1511 kTopEarlgreyPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
1512 kTopEarlgreyPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
1513 kTopEarlgreyPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
1514 kTopEarlgreyPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
1515 kTopEarlgreyPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
1516 kTopEarlgreyPinmuxInselIoc10 = 34, /**< MIO Pad 32 */
1517 kTopEarlgreyPinmuxInselIoc11 = 35, /**< MIO Pad 33 */
1518 kTopEarlgreyPinmuxInselIoc12 = 36, /**< MIO Pad 34 */
1519 kTopEarlgreyPinmuxInselIor0 = 37, /**< MIO Pad 35 */
1520 kTopEarlgreyPinmuxInselIor1 = 38, /**< MIO Pad 36 */
1521 kTopEarlgreyPinmuxInselIor2 = 39, /**< MIO Pad 37 */
1522 kTopEarlgreyPinmuxInselIor3 = 40, /**< MIO Pad 38 */
1523 kTopEarlgreyPinmuxInselIor4 = 41, /**< MIO Pad 39 */
1524 kTopEarlgreyPinmuxInselIor5 = 42, /**< MIO Pad 40 */
1525 kTopEarlgreyPinmuxInselIor6 = 43, /**< MIO Pad 41 */
1526 kTopEarlgreyPinmuxInselIor7 = 44, /**< MIO Pad 42 */
1527 kTopEarlgreyPinmuxInselIor10 = 45, /**< MIO Pad 43 */
1528 kTopEarlgreyPinmuxInselIor11 = 46, /**< MIO Pad 44 */
1529 kTopEarlgreyPinmuxInselIor12 = 47, /**< MIO Pad 45 */
1530 kTopEarlgreyPinmuxInselIor13 = 48, /**< MIO Pad 46 */
1531 kTopEarlgreyPinmuxInselLast = 48, /**< \internal Last valid insel value */
1532} top_earlgrey_pinmux_insel_t;
1533
1534/**
1535 * Pinmux MIO Output.
1536 */
1537typedef enum top_earlgrey_pinmux_mio_out {
1538 kTopEarlgreyPinmuxMioOutIoa0 = 0, /**< MIO Pad 0 */
1539 kTopEarlgreyPinmuxMioOutIoa1 = 1, /**< MIO Pad 1 */
1540 kTopEarlgreyPinmuxMioOutIoa2 = 2, /**< MIO Pad 2 */
1541 kTopEarlgreyPinmuxMioOutIoa3 = 3, /**< MIO Pad 3 */
1542 kTopEarlgreyPinmuxMioOutIoa4 = 4, /**< MIO Pad 4 */
1543 kTopEarlgreyPinmuxMioOutIoa5 = 5, /**< MIO Pad 5 */
1544 kTopEarlgreyPinmuxMioOutIoa6 = 6, /**< MIO Pad 6 */
1545 kTopEarlgreyPinmuxMioOutIoa7 = 7, /**< MIO Pad 7 */
1546 kTopEarlgreyPinmuxMioOutIoa8 = 8, /**< MIO Pad 8 */
1547 kTopEarlgreyPinmuxMioOutIob0 = 9, /**< MIO Pad 9 */
1548 kTopEarlgreyPinmuxMioOutIob1 = 10, /**< MIO Pad 10 */
1549 kTopEarlgreyPinmuxMioOutIob2 = 11, /**< MIO Pad 11 */
1550 kTopEarlgreyPinmuxMioOutIob3 = 12, /**< MIO Pad 12 */
1551 kTopEarlgreyPinmuxMioOutIob4 = 13, /**< MIO Pad 13 */
1552 kTopEarlgreyPinmuxMioOutIob5 = 14, /**< MIO Pad 14 */
1553 kTopEarlgreyPinmuxMioOutIob6 = 15, /**< MIO Pad 15 */
1554 kTopEarlgreyPinmuxMioOutIob7 = 16, /**< MIO Pad 16 */
1555 kTopEarlgreyPinmuxMioOutIob8 = 17, /**< MIO Pad 17 */
1556 kTopEarlgreyPinmuxMioOutIob9 = 18, /**< MIO Pad 18 */
1557 kTopEarlgreyPinmuxMioOutIob10 = 19, /**< MIO Pad 19 */
1558 kTopEarlgreyPinmuxMioOutIob11 = 20, /**< MIO Pad 20 */
1559 kTopEarlgreyPinmuxMioOutIob12 = 21, /**< MIO Pad 21 */
1560 kTopEarlgreyPinmuxMioOutIoc0 = 22, /**< MIO Pad 22 */
1561 kTopEarlgreyPinmuxMioOutIoc1 = 23, /**< MIO Pad 23 */
1562 kTopEarlgreyPinmuxMioOutIoc2 = 24, /**< MIO Pad 24 */
1563 kTopEarlgreyPinmuxMioOutIoc3 = 25, /**< MIO Pad 25 */
1564 kTopEarlgreyPinmuxMioOutIoc4 = 26, /**< MIO Pad 26 */
1565 kTopEarlgreyPinmuxMioOutIoc5 = 27, /**< MIO Pad 27 */
1566 kTopEarlgreyPinmuxMioOutIoc6 = 28, /**< MIO Pad 28 */
1567 kTopEarlgreyPinmuxMioOutIoc7 = 29, /**< MIO Pad 29 */
1568 kTopEarlgreyPinmuxMioOutIoc8 = 30, /**< MIO Pad 30 */
1569 kTopEarlgreyPinmuxMioOutIoc9 = 31, /**< MIO Pad 31 */
1570 kTopEarlgreyPinmuxMioOutIoc10 = 32, /**< MIO Pad 32 */
1571 kTopEarlgreyPinmuxMioOutIoc11 = 33, /**< MIO Pad 33 */
1572 kTopEarlgreyPinmuxMioOutIoc12 = 34, /**< MIO Pad 34 */
1573 kTopEarlgreyPinmuxMioOutIor0 = 35, /**< MIO Pad 35 */
1574 kTopEarlgreyPinmuxMioOutIor1 = 36, /**< MIO Pad 36 */
1575 kTopEarlgreyPinmuxMioOutIor2 = 37, /**< MIO Pad 37 */
1576 kTopEarlgreyPinmuxMioOutIor3 = 38, /**< MIO Pad 38 */
1577 kTopEarlgreyPinmuxMioOutIor4 = 39, /**< MIO Pad 39 */
1578 kTopEarlgreyPinmuxMioOutIor5 = 40, /**< MIO Pad 40 */
1579 kTopEarlgreyPinmuxMioOutIor6 = 41, /**< MIO Pad 41 */
1580 kTopEarlgreyPinmuxMioOutIor7 = 42, /**< MIO Pad 42 */
1581 kTopEarlgreyPinmuxMioOutIor10 = 43, /**< MIO Pad 43 */
1582 kTopEarlgreyPinmuxMioOutIor11 = 44, /**< MIO Pad 44 */
1583 kTopEarlgreyPinmuxMioOutIor12 = 45, /**< MIO Pad 45 */
1584 kTopEarlgreyPinmuxMioOutIor13 = 46, /**< MIO Pad 46 */
1585 kTopEarlgreyPinmuxMioOutLast = 46, /**< \internal Last valid mio output */
1586} top_earlgrey_pinmux_mio_out_t;
1587
1588/**
1589 * Pinmux Peripheral Output Selector.
1590 */
1591typedef enum top_earlgrey_pinmux_outsel {
1592 kTopEarlgreyPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
1593 kTopEarlgreyPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
1594 kTopEarlgreyPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
1595 kTopEarlgreyPinmuxOutselGpioGpio0 = 3, /**< Peripheral Output 0 */
1596 kTopEarlgreyPinmuxOutselGpioGpio1 = 4, /**< Peripheral Output 1 */
1597 kTopEarlgreyPinmuxOutselGpioGpio2 = 5, /**< Peripheral Output 2 */
1598 kTopEarlgreyPinmuxOutselGpioGpio3 = 6, /**< Peripheral Output 3 */
1599 kTopEarlgreyPinmuxOutselGpioGpio4 = 7, /**< Peripheral Output 4 */
1600 kTopEarlgreyPinmuxOutselGpioGpio5 = 8, /**< Peripheral Output 5 */
1601 kTopEarlgreyPinmuxOutselGpioGpio6 = 9, /**< Peripheral Output 6 */
1602 kTopEarlgreyPinmuxOutselGpioGpio7 = 10, /**< Peripheral Output 7 */
1603 kTopEarlgreyPinmuxOutselGpioGpio8 = 11, /**< Peripheral Output 8 */
1604 kTopEarlgreyPinmuxOutselGpioGpio9 = 12, /**< Peripheral Output 9 */
1605 kTopEarlgreyPinmuxOutselGpioGpio10 = 13, /**< Peripheral Output 10 */
1606 kTopEarlgreyPinmuxOutselGpioGpio11 = 14, /**< Peripheral Output 11 */
1607 kTopEarlgreyPinmuxOutselGpioGpio12 = 15, /**< Peripheral Output 12 */
1608 kTopEarlgreyPinmuxOutselGpioGpio13 = 16, /**< Peripheral Output 13 */
1609 kTopEarlgreyPinmuxOutselGpioGpio14 = 17, /**< Peripheral Output 14 */
1610 kTopEarlgreyPinmuxOutselGpioGpio15 = 18, /**< Peripheral Output 15 */
1611 kTopEarlgreyPinmuxOutselGpioGpio16 = 19, /**< Peripheral Output 16 */
1612 kTopEarlgreyPinmuxOutselGpioGpio17 = 20, /**< Peripheral Output 17 */
1613 kTopEarlgreyPinmuxOutselGpioGpio18 = 21, /**< Peripheral Output 18 */
1614 kTopEarlgreyPinmuxOutselGpioGpio19 = 22, /**< Peripheral Output 19 */
1615 kTopEarlgreyPinmuxOutselGpioGpio20 = 23, /**< Peripheral Output 20 */
1616 kTopEarlgreyPinmuxOutselGpioGpio21 = 24, /**< Peripheral Output 21 */
1617 kTopEarlgreyPinmuxOutselGpioGpio22 = 25, /**< Peripheral Output 22 */
1618 kTopEarlgreyPinmuxOutselGpioGpio23 = 26, /**< Peripheral Output 23 */
1619 kTopEarlgreyPinmuxOutselGpioGpio24 = 27, /**< Peripheral Output 24 */
1620 kTopEarlgreyPinmuxOutselGpioGpio25 = 28, /**< Peripheral Output 25 */
1621 kTopEarlgreyPinmuxOutselGpioGpio26 = 29, /**< Peripheral Output 26 */
1622 kTopEarlgreyPinmuxOutselGpioGpio27 = 30, /**< Peripheral Output 27 */
1623 kTopEarlgreyPinmuxOutselGpioGpio28 = 31, /**< Peripheral Output 28 */
1624 kTopEarlgreyPinmuxOutselGpioGpio29 = 32, /**< Peripheral Output 29 */
1625 kTopEarlgreyPinmuxOutselGpioGpio30 = 33, /**< Peripheral Output 30 */
1626 kTopEarlgreyPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */
1627 kTopEarlgreyPinmuxOutselI2c0Sda = 35, /**< Peripheral Output 32 */
1628 kTopEarlgreyPinmuxOutselI2c0Scl = 36, /**< Peripheral Output 33 */
1629 kTopEarlgreyPinmuxOutselI2c1Sda = 37, /**< Peripheral Output 34 */
1630 kTopEarlgreyPinmuxOutselI2c1Scl = 38, /**< Peripheral Output 35 */
1631 kTopEarlgreyPinmuxOutselI2c2Sda = 39, /**< Peripheral Output 36 */
1632 kTopEarlgreyPinmuxOutselI2c2Scl = 40, /**< Peripheral Output 37 */
1633 kTopEarlgreyPinmuxOutselSpiHost1Sd0 = 41, /**< Peripheral Output 38 */
1634 kTopEarlgreyPinmuxOutselSpiHost1Sd1 = 42, /**< Peripheral Output 39 */
1635 kTopEarlgreyPinmuxOutselSpiHost1Sd2 = 43, /**< Peripheral Output 40 */
1636 kTopEarlgreyPinmuxOutselSpiHost1Sd3 = 44, /**< Peripheral Output 41 */
1637 kTopEarlgreyPinmuxOutselUart0Tx = 45, /**< Peripheral Output 42 */
1638 kTopEarlgreyPinmuxOutselUart1Tx = 46, /**< Peripheral Output 43 */
1639 kTopEarlgreyPinmuxOutselUart2Tx = 47, /**< Peripheral Output 44 */
1640 kTopEarlgreyPinmuxOutselUart3Tx = 48, /**< Peripheral Output 45 */
1641 kTopEarlgreyPinmuxOutselPattgenPda0Tx = 49, /**< Peripheral Output 46 */
1642 kTopEarlgreyPinmuxOutselPattgenPcl0Tx = 50, /**< Peripheral Output 47 */
1643 kTopEarlgreyPinmuxOutselPattgenPda1Tx = 51, /**< Peripheral Output 48 */
1644 kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 52, /**< Peripheral Output 49 */
1645 kTopEarlgreyPinmuxOutselSpiHost1Sck = 53, /**< Peripheral Output 50 */
1646 kTopEarlgreyPinmuxOutselSpiHost1Csb = 54, /**< Peripheral Output 51 */
1647 kTopEarlgreyPinmuxOutselFlashCtrlTdo = 55, /**< Peripheral Output 52 */
1648 kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0 = 56, /**< Peripheral Output 53 */
1649 kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1 = 57, /**< Peripheral Output 54 */
1650 kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2 = 58, /**< Peripheral Output 55 */
1651 kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut3 = 59, /**< Peripheral Output 56 */
1652 kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut4 = 60, /**< Peripheral Output 57 */
1653 kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut5 = 61, /**< Peripheral Output 58 */
1654 kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut6 = 62, /**< Peripheral Output 59 */
1655 kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut7 = 63, /**< Peripheral Output 60 */
1656 kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut8 = 64, /**< Peripheral Output 61 */
1657 kTopEarlgreyPinmuxOutselPwmAonPwm0 = 65, /**< Peripheral Output 62 */
1658 kTopEarlgreyPinmuxOutselPwmAonPwm1 = 66, /**< Peripheral Output 63 */
1659 kTopEarlgreyPinmuxOutselPwmAonPwm2 = 67, /**< Peripheral Output 64 */
1660 kTopEarlgreyPinmuxOutselPwmAonPwm3 = 68, /**< Peripheral Output 65 */
1661 kTopEarlgreyPinmuxOutselPwmAonPwm4 = 69, /**< Peripheral Output 66 */
1662 kTopEarlgreyPinmuxOutselPwmAonPwm5 = 70, /**< Peripheral Output 67 */
1663 kTopEarlgreyPinmuxOutselOtpMacroTest0 = 71, /**< Peripheral Output 68 */
1664 kTopEarlgreyPinmuxOutselSysrstCtrlAonBatDisable = 72, /**< Peripheral Output 69 */
1665 kTopEarlgreyPinmuxOutselSysrstCtrlAonKey0Out = 73, /**< Peripheral Output 70 */
1666 kTopEarlgreyPinmuxOutselSysrstCtrlAonKey1Out = 74, /**< Peripheral Output 71 */
1667 kTopEarlgreyPinmuxOutselSysrstCtrlAonKey2Out = 75, /**< Peripheral Output 72 */
1668 kTopEarlgreyPinmuxOutselSysrstCtrlAonPwrbOut = 76, /**< Peripheral Output 73 */
1669 kTopEarlgreyPinmuxOutselSysrstCtrlAonZ3Wakeup = 77, /**< Peripheral Output 74 */
1670 kTopEarlgreyPinmuxOutselLast = 77, /**< \internal Last valid outsel value */
1671} top_earlgrey_pinmux_outsel_t;
1672
1673/**
1674 * Dedicated Pad Selects
1675 */
1676typedef enum top_earlgrey_direct_pads {
1677 kTopEarlgreyDirectPadsUsbdevUsbDp = 0, /**< */
1678 kTopEarlgreyDirectPadsUsbdevUsbDn = 1, /**< */
1679 kTopEarlgreyDirectPadsSpiHost0Sd0 = 2, /**< */
1680 kTopEarlgreyDirectPadsSpiHost0Sd1 = 3, /**< */
1681 kTopEarlgreyDirectPadsSpiHost0Sd2 = 4, /**< */
1682 kTopEarlgreyDirectPadsSpiHost0Sd3 = 5, /**< */
1683 kTopEarlgreyDirectPadsSpiDeviceSd0 = 6, /**< */
1684 kTopEarlgreyDirectPadsSpiDeviceSd1 = 7, /**< */
1685 kTopEarlgreyDirectPadsSpiDeviceSd2 = 8, /**< */
1686 kTopEarlgreyDirectPadsSpiDeviceSd3 = 9, /**< */
1687 kTopEarlgreyDirectPadsSysrstCtrlAonEcRstL = 10, /**< */
1688 kTopEarlgreyDirectPadsSysrstCtrlAonFlashWpL = 11, /**< */
1689 kTopEarlgreyDirectPadsSpiDeviceSck = 12, /**< */
1690 kTopEarlgreyDirectPadsSpiDeviceCsb = 13, /**< */
1691 kTopEarlgreyDirectPadsSpiHost0Sck = 14, /**< */
1692 kTopEarlgreyDirectPadsSpiHost0Csb = 15, /**< */
1693 kTopEarlgreyDirectPadsLast = 15, /**< \internal Last valid direct pad */
1694} top_earlgrey_direct_pads_t;
1695
1696/**
1697 * Muxed Pad Selects
1698 */
1699typedef enum top_earlgrey_muxed_pads {
1700 kTopEarlgreyMuxedPadsIoa0 = 0, /**< */
1701 kTopEarlgreyMuxedPadsIoa1 = 1, /**< */
1702 kTopEarlgreyMuxedPadsIoa2 = 2, /**< */
1703 kTopEarlgreyMuxedPadsIoa3 = 3, /**< */
1704 kTopEarlgreyMuxedPadsIoa4 = 4, /**< */
1705 kTopEarlgreyMuxedPadsIoa5 = 5, /**< */
1706 kTopEarlgreyMuxedPadsIoa6 = 6, /**< */
1707 kTopEarlgreyMuxedPadsIoa7 = 7, /**< */
1708 kTopEarlgreyMuxedPadsIoa8 = 8, /**< */
1709 kTopEarlgreyMuxedPadsIob0 = 9, /**< */
1710 kTopEarlgreyMuxedPadsIob1 = 10, /**< */
1711 kTopEarlgreyMuxedPadsIob2 = 11, /**< */
1712 kTopEarlgreyMuxedPadsIob3 = 12, /**< */
1713 kTopEarlgreyMuxedPadsIob4 = 13, /**< */
1714 kTopEarlgreyMuxedPadsIob5 = 14, /**< */
1715 kTopEarlgreyMuxedPadsIob6 = 15, /**< */
1716 kTopEarlgreyMuxedPadsIob7 = 16, /**< */
1717 kTopEarlgreyMuxedPadsIob8 = 17, /**< */
1718 kTopEarlgreyMuxedPadsIob9 = 18, /**< */
1719 kTopEarlgreyMuxedPadsIob10 = 19, /**< */
1720 kTopEarlgreyMuxedPadsIob11 = 20, /**< */
1721 kTopEarlgreyMuxedPadsIob12 = 21, /**< */
1722 kTopEarlgreyMuxedPadsIoc0 = 22, /**< */
1723 kTopEarlgreyMuxedPadsIoc1 = 23, /**< */
1724 kTopEarlgreyMuxedPadsIoc2 = 24, /**< */
1725 kTopEarlgreyMuxedPadsIoc3 = 25, /**< */
1726 kTopEarlgreyMuxedPadsIoc4 = 26, /**< */
1727 kTopEarlgreyMuxedPadsIoc5 = 27, /**< */
1728 kTopEarlgreyMuxedPadsIoc6 = 28, /**< */
1729 kTopEarlgreyMuxedPadsIoc7 = 29, /**< */
1730 kTopEarlgreyMuxedPadsIoc8 = 30, /**< */
1731 kTopEarlgreyMuxedPadsIoc9 = 31, /**< */
1732 kTopEarlgreyMuxedPadsIoc10 = 32, /**< */
1733 kTopEarlgreyMuxedPadsIoc11 = 33, /**< */
1734 kTopEarlgreyMuxedPadsIoc12 = 34, /**< */
1735 kTopEarlgreyMuxedPadsIor0 = 35, /**< */
1736 kTopEarlgreyMuxedPadsIor1 = 36, /**< */
1737 kTopEarlgreyMuxedPadsIor2 = 37, /**< */
1738 kTopEarlgreyMuxedPadsIor3 = 38, /**< */
1739 kTopEarlgreyMuxedPadsIor4 = 39, /**< */
1740 kTopEarlgreyMuxedPadsIor5 = 40, /**< */
1741 kTopEarlgreyMuxedPadsIor6 = 41, /**< */
1742 kTopEarlgreyMuxedPadsIor7 = 42, /**< */
1743 kTopEarlgreyMuxedPadsIor10 = 43, /**< */
1744 kTopEarlgreyMuxedPadsIor11 = 44, /**< */
1745 kTopEarlgreyMuxedPadsIor12 = 45, /**< */
1746 kTopEarlgreyMuxedPadsIor13 = 46, /**< */
1747 kTopEarlgreyMuxedPadsLast = 46, /**< \internal Last valid muxed pad */
1748} top_earlgrey_muxed_pads_t;
1749
1750/**
1751 * Power Manager Wakeup Signals
1752 */
1753typedef enum top_earlgrey_power_manager_wake_ups {
1754 kTopEarlgreyPowerManagerWakeUpsSysrstCtrlAonWkupReq = 0, /**< */
1755 kTopEarlgreyPowerManagerWakeUpsAdcCtrlAonWkupReq = 1, /**< */
1756 kTopEarlgreyPowerManagerWakeUpsPinmuxAonPinWkupReq = 2, /**< */
1757 kTopEarlgreyPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3, /**< */
1758 kTopEarlgreyPowerManagerWakeUpsAonTimerAonWkupReq = 4, /**< */
1759 kTopEarlgreyPowerManagerWakeUpsSensorCtrlAonWkupReq = 5, /**< */
1760 kTopEarlgreyPowerManagerWakeUpsLast = 5, /**< \internal Last valid pwrmgr wakeup signal */
1761} top_earlgrey_power_manager_wake_ups_t;
1762
1763/**
1764 * Reset Manager Software Controlled Resets
1765 */
1766typedef enum top_earlgrey_reset_manager_sw_resets {
1767 kTopEarlgreyResetManagerSwResetsSpiDevice = 0, /**< */
1768 kTopEarlgreyResetManagerSwResetsSpiHost0 = 1, /**< */
1769 kTopEarlgreyResetManagerSwResetsSpiHost1 = 2, /**< */
1770 kTopEarlgreyResetManagerSwResetsUsb = 3, /**< */
1771 kTopEarlgreyResetManagerSwResetsUsbAon = 4, /**< */
1772 kTopEarlgreyResetManagerSwResetsI2c0 = 5, /**< */
1773 kTopEarlgreyResetManagerSwResetsI2c1 = 6, /**< */
1774 kTopEarlgreyResetManagerSwResetsI2c2 = 7, /**< */
1775 kTopEarlgreyResetManagerSwResetsLast = 7, /**< \internal Last valid rstmgr software reset request */
1776} top_earlgrey_reset_manager_sw_resets_t;
1777
1778/**
1779 * Power Manager Reset Request Signals
1780 */
1781typedef enum top_earlgrey_power_manager_reset_requests {
1782 kTopEarlgreyPowerManagerResetRequestsSysrstCtrlAonRstReq = 0, /**< */
1783 kTopEarlgreyPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1, /**< */
1784 kTopEarlgreyPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */
1785} top_earlgrey_power_manager_reset_requests_t;
1786
1787/**
1788 * Clock Manager Software-Controlled ("Gated") Clocks.
1789 *
1790 * The Software has full control over these clocks.
1791 */
1792typedef enum top_earlgrey_gateable_clocks {
1793 kTopEarlgreyGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
1794 kTopEarlgreyGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
1795 kTopEarlgreyGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
1796 kTopEarlgreyGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
1797 kTopEarlgreyGateableClocksLast = 3, /**< \internal Last Valid Gateable Clock */
1798} top_earlgrey_gateable_clocks_t;
1799
1800/**
1801 * Clock Manager Software-Hinted Clocks.
1802 *
1803 * The Software has partial control over these clocks. It can ask them to stop,
1804 * but the clock manager is in control of whether the clock actually is stopped.
1805 */
1806typedef enum top_earlgrey_hintable_clocks {
1807 kTopEarlgreyHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */
1808 kTopEarlgreyHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */
1809 kTopEarlgreyHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */
1810 kTopEarlgreyHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */
1811 kTopEarlgreyHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */
1812} top_earlgrey_hintable_clocks_t;
1813
1814/**
1815 * MMIO Region
1816 *
1817 * MMIO region excludes any memory that is separate from the module
1818 * configuration space, i.e. ROM, main SRAM, and flash are excluded but
1819 * retention SRAM, spi_device memory, or usbdev memory are included.
1820 */
1821#define TOP_EARLGREY_MMIO_BASE_ADDR 0x40000000u
1822#define TOP_EARLGREY_MMIO_SIZE_BYTES 0x10000000u
1823
1824// Header Extern Guard
1825#ifdef __cplusplus
1826} // extern "C"
1827#endif
1828
1829#endif // OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_H_