10 #ifndef OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_H_
11 #define OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_H_
39 #define TOP_EARLGREY_UART0_BASE_ADDR 0x40000000u
49 #define TOP_EARLGREY_UART0_SIZE_BYTES 0x40u
57 #define TOP_EARLGREY_UART1_BASE_ADDR 0x40010000u
67 #define TOP_EARLGREY_UART1_SIZE_BYTES 0x40u
75 #define TOP_EARLGREY_UART2_BASE_ADDR 0x40020000u
85 #define TOP_EARLGREY_UART2_SIZE_BYTES 0x40u
93 #define TOP_EARLGREY_UART3_BASE_ADDR 0x40030000u
103 #define TOP_EARLGREY_UART3_SIZE_BYTES 0x40u
111 #define TOP_EARLGREY_GPIO_BASE_ADDR 0x40040000u
121 #define TOP_EARLGREY_GPIO_SIZE_BYTES 0x80u
129 #define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40050000u
139 #define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x2000u
147 #define TOP_EARLGREY_I2C0_BASE_ADDR 0x40080000u
157 #define TOP_EARLGREY_I2C0_SIZE_BYTES 0x80u
165 #define TOP_EARLGREY_I2C1_BASE_ADDR 0x40090000u
175 #define TOP_EARLGREY_I2C1_SIZE_BYTES 0x80u
183 #define TOP_EARLGREY_I2C2_BASE_ADDR 0x400A0000u
193 #define TOP_EARLGREY_I2C2_SIZE_BYTES 0x80u
201 #define TOP_EARLGREY_PATTGEN_BASE_ADDR 0x400E0000u
211 #define TOP_EARLGREY_PATTGEN_SIZE_BYTES 0x40u
219 #define TOP_EARLGREY_RV_TIMER_BASE_ADDR 0x40100000u
229 #define TOP_EARLGREY_RV_TIMER_SIZE_BYTES 0x200u
237 #define TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR 0x40130000u
247 #define TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES 0x1000u
255 #define TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR 0x40138000u
265 #define TOP_EARLGREY_OTP_CTRL_PRIM_SIZE_BYTES 0x20u
273 #define TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR 0x40140000u
283 #define TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES 0x100u
291 #define TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR 0x0u
301 #define TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES 0x1000u
309 #define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x40150000u
319 #define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x800u
327 #define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40300000u
337 #define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x40u
345 #define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40310000u
355 #define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x40u
363 #define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40320000u
373 #define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000u
381 #define TOP_EARLGREY_PWRMGR_AON_BASE_ADDR 0x40400000u
391 #define TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES 0x80u
399 #define TOP_EARLGREY_RSTMGR_AON_BASE_ADDR 0x40410000u
409 #define TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES 0x80u
417 #define TOP_EARLGREY_CLKMGR_AON_BASE_ADDR 0x40420000u
427 #define TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES 0x80u
435 #define TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
445 #define TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES 0x100u
453 #define TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR 0x40440000u
463 #define TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES 0x80u
471 #define TOP_EARLGREY_PWM_AON_BASE_ADDR 0x40450000u
481 #define TOP_EARLGREY_PWM_AON_SIZE_BYTES 0x80u
489 #define TOP_EARLGREY_PINMUX_AON_BASE_ADDR 0x40460000u
499 #define TOP_EARLGREY_PINMUX_AON_SIZE_BYTES 0x1000u
507 #define TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR 0x40470000u
517 #define TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES 0x40u
525 #define TOP_EARLGREY_AST_BASE_ADDR 0x40480000u
535 #define TOP_EARLGREY_AST_SIZE_BYTES 0x400u
543 #define TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR 0x40490000u
553 #define TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES 0x80u
561 #define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
571 #define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u
579 #define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
589 #define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
597 #define TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
607 #define TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
615 #define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u
625 #define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u
633 #define TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
643 #define TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u
651 #define TOP_EARLGREY_RV_DM_REGS_BASE_ADDR 0x41200000u
661 #define TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES 0x10u
669 #define TOP_EARLGREY_RV_DM_MEM_BASE_ADDR 0x10000u
679 #define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000u
687 #define TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000u
697 #define TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200u
705 #define TOP_EARLGREY_RV_PLIC_BASE_ADDR 0x48000000u
715 #define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x8000000u
723 #define TOP_EARLGREY_AES_BASE_ADDR 0x41100000u
733 #define TOP_EARLGREY_AES_SIZE_BYTES 0x100u
741 #define TOP_EARLGREY_HMAC_BASE_ADDR 0x41110000u
751 #define TOP_EARLGREY_HMAC_SIZE_BYTES 0x2000u
759 #define TOP_EARLGREY_KMAC_BASE_ADDR 0x41120000u
769 #define TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000u
777 #define TOP_EARLGREY_OTBN_BASE_ADDR 0x41130000u
787 #define TOP_EARLGREY_OTBN_SIZE_BYTES 0x10000u
795 #define TOP_EARLGREY_KEYMGR_BASE_ADDR 0x41140000u
805 #define TOP_EARLGREY_KEYMGR_SIZE_BYTES 0x100u
813 #define TOP_EARLGREY_CSRNG_BASE_ADDR 0x41150000u
823 #define TOP_EARLGREY_CSRNG_SIZE_BYTES 0x80u
831 #define TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR 0x41160000u
841 #define TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES 0x100u
849 #define TOP_EARLGREY_EDN0_BASE_ADDR 0x41170000u
859 #define TOP_EARLGREY_EDN0_SIZE_BYTES 0x80u
867 #define TOP_EARLGREY_EDN1_BASE_ADDR 0x41180000u
877 #define TOP_EARLGREY_EDN1_SIZE_BYTES 0x80u
885 #define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
895 #define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
903 #define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
913 #define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
921 #define TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
931 #define TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES 0x80u
939 #define TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR 0x8000u
949 #define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
957 #define TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000u
967 #define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u
973 #define TOP_EARLGREY_RAM_RET_AON_BASE_ADDR 0x40600000u
978 #define TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES 0x1000u
983 #define TOP_EARLGREY_EFLASH_BASE_ADDR 0x20000000u
988 #define TOP_EARLGREY_EFLASH_SIZE_BYTES 0x100000u
993 #define TOP_EARLGREY_RAM_MAIN_BASE_ADDR 0x10000000u
998 #define TOP_EARLGREY_RAM_MAIN_SIZE_BYTES 0x20000u
1003 #define TOP_EARLGREY_ROM_BASE_ADDR 0x8000u
1008 #define TOP_EARLGREY_ROM_SIZE_BYTES 0x8000u
1049 kTopEarlgreyPlicPeripheralLast = 30,
1245 kTopEarlgreyPlicIrqIdLast = 185,
1265 kTopEarlgreyPlicTargetLast = 0,
1316 kTopEarlgreyAlertPeripheralLast = 40,
1391 kTopEarlgreyAlertIdLast = 64,
1403 #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
1407 #define NUM_MIO_PADS 47
1408 #define NUM_DIO_PADS 16
1410 #define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
1473 kTopEarlgreyPinmuxPeripheralInLast = 56,
1529 kTopEarlgreyPinmuxInselLast = 48,
1583 kTopEarlgreyPinmuxMioOutLast = 46,
1668 kTopEarlgreyPinmuxOutselLast = 77,
1675 kTopEarlgreyDirectPadsUsbdevUsbDp = 0,
1676 kTopEarlgreyDirectPadsUsbdevUsbDn = 1,
1677 kTopEarlgreyDirectPadsSpiHost0Sd0 = 2,
1678 kTopEarlgreyDirectPadsSpiHost0Sd1 = 3,
1679 kTopEarlgreyDirectPadsSpiHost0Sd2 = 4,
1680 kTopEarlgreyDirectPadsSpiHost0Sd3 = 5,
1681 kTopEarlgreyDirectPadsSpiDeviceSd0 = 6,
1682 kTopEarlgreyDirectPadsSpiDeviceSd1 = 7,
1683 kTopEarlgreyDirectPadsSpiDeviceSd2 = 8,
1684 kTopEarlgreyDirectPadsSpiDeviceSd3 = 9,
1685 kTopEarlgreyDirectPadsSysrstCtrlAonEcRstL = 10,
1686 kTopEarlgreyDirectPadsSysrstCtrlAonFlashWpL = 11,
1687 kTopEarlgreyDirectPadsSpiDeviceSck = 12,
1688 kTopEarlgreyDirectPadsSpiDeviceCsb = 13,
1689 kTopEarlgreyDirectPadsSpiHost0Sck = 14,
1690 kTopEarlgreyDirectPadsSpiHost0Csb = 15,
1691 kTopEarlgreyDirectPadsLast = 15,
1698 kTopEarlgreyMuxedPadsIoa0 = 0,
1699 kTopEarlgreyMuxedPadsIoa1 = 1,
1700 kTopEarlgreyMuxedPadsIoa2 = 2,
1701 kTopEarlgreyMuxedPadsIoa3 = 3,
1702 kTopEarlgreyMuxedPadsIoa4 = 4,
1703 kTopEarlgreyMuxedPadsIoa5 = 5,
1704 kTopEarlgreyMuxedPadsIoa6 = 6,
1705 kTopEarlgreyMuxedPadsIoa7 = 7,
1706 kTopEarlgreyMuxedPadsIoa8 = 8,
1707 kTopEarlgreyMuxedPadsIob0 = 9,
1708 kTopEarlgreyMuxedPadsIob1 = 10,
1709 kTopEarlgreyMuxedPadsIob2 = 11,
1710 kTopEarlgreyMuxedPadsIob3 = 12,
1711 kTopEarlgreyMuxedPadsIob4 = 13,
1712 kTopEarlgreyMuxedPadsIob5 = 14,
1713 kTopEarlgreyMuxedPadsIob6 = 15,
1714 kTopEarlgreyMuxedPadsIob7 = 16,
1715 kTopEarlgreyMuxedPadsIob8 = 17,
1716 kTopEarlgreyMuxedPadsIob9 = 18,
1717 kTopEarlgreyMuxedPadsIob10 = 19,
1718 kTopEarlgreyMuxedPadsIob11 = 20,
1719 kTopEarlgreyMuxedPadsIob12 = 21,
1720 kTopEarlgreyMuxedPadsIoc0 = 22,
1721 kTopEarlgreyMuxedPadsIoc1 = 23,
1722 kTopEarlgreyMuxedPadsIoc2 = 24,
1723 kTopEarlgreyMuxedPadsIoc3 = 25,
1724 kTopEarlgreyMuxedPadsIoc4 = 26,
1725 kTopEarlgreyMuxedPadsIoc5 = 27,
1726 kTopEarlgreyMuxedPadsIoc6 = 28,
1727 kTopEarlgreyMuxedPadsIoc7 = 29,
1728 kTopEarlgreyMuxedPadsIoc8 = 30,
1729 kTopEarlgreyMuxedPadsIoc9 = 31,
1730 kTopEarlgreyMuxedPadsIoc10 = 32,
1731 kTopEarlgreyMuxedPadsIoc11 = 33,
1732 kTopEarlgreyMuxedPadsIoc12 = 34,
1733 kTopEarlgreyMuxedPadsIor0 = 35,
1734 kTopEarlgreyMuxedPadsIor1 = 36,
1735 kTopEarlgreyMuxedPadsIor2 = 37,
1736 kTopEarlgreyMuxedPadsIor3 = 38,
1737 kTopEarlgreyMuxedPadsIor4 = 39,
1738 kTopEarlgreyMuxedPadsIor5 = 40,
1739 kTopEarlgreyMuxedPadsIor6 = 41,
1740 kTopEarlgreyMuxedPadsIor7 = 42,
1741 kTopEarlgreyMuxedPadsIor10 = 43,
1742 kTopEarlgreyMuxedPadsIor11 = 44,
1743 kTopEarlgreyMuxedPadsIor12 = 45,
1744 kTopEarlgreyMuxedPadsIor13 = 46,
1745 kTopEarlgreyMuxedPadsLast = 46,
1752 kTopEarlgreyPowerManagerWakeUpsSysrstCtrlAonWkupReq = 0,
1753 kTopEarlgreyPowerManagerWakeUpsAdcCtrlAonWkupReq = 1,
1754 kTopEarlgreyPowerManagerWakeUpsPinmuxAonPinWkupReq = 2,
1755 kTopEarlgreyPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3,
1756 kTopEarlgreyPowerManagerWakeUpsAonTimerAonWkupReq = 4,
1757 kTopEarlgreyPowerManagerWakeUpsSensorCtrlAonWkupReq = 5,
1758 kTopEarlgreyPowerManagerWakeUpsLast = 5,
1765 kTopEarlgreyResetManagerSwResetsSpiDevice = 0,
1766 kTopEarlgreyResetManagerSwResetsSpiHost0 = 1,
1767 kTopEarlgreyResetManagerSwResetsSpiHost1 = 2,
1768 kTopEarlgreyResetManagerSwResetsUsb = 3,
1769 kTopEarlgreyResetManagerSwResetsUsbAon = 4,
1770 kTopEarlgreyResetManagerSwResetsI2c0 = 5,
1771 kTopEarlgreyResetManagerSwResetsI2c1 = 6,
1772 kTopEarlgreyResetManagerSwResetsI2c2 = 7,
1773 kTopEarlgreyResetManagerSwResetsLast = 7,
1780 kTopEarlgreyPowerManagerResetRequestsSysrstCtrlAonRstReq = 0,
1781 kTopEarlgreyPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1,
1782 kTopEarlgreyPowerManagerResetRequestsLast = 1,
1795 kTopEarlgreyGateableClocksLast = 3,
1809 kTopEarlgreyHintableClocksLast = 3,
1819 #define TOP_EARLGREY_MMIO_BASE_ADDR 0x40000000u
1820 #define TOP_EARLGREY_MMIO_SIZE_BYTES 0x10000000u