Software APIs
top_darjeeling.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
6// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
7// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson
8// -o hw/top_darjeeling
9
10#ifndef OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_
11#define OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_
12
13/**
14 * @file
15 * @brief Top-specific Definitions
16 *
17 * This file contains preprocessor and type definitions for use within the
18 * device C/C++ codebase.
19 *
20 * These definitions are for information that depends on the top-specific chip
21 * configuration, which includes:
22 * - Device Memory Information (for Peripherals and Memory)
23 * - PLIC Interrupt ID Names and Source Mappings
24 * - Alert ID Names and Source Mappings
25 * - Pinmux Pin/Select Names
26 * - Power Manager Wakeups
27 */
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/**
34 * Peripheral base address for uart0 in top darjeeling.
35 *
36 * This should be used with #mmio_region_from_addr to access the memory-mapped
37 * registers associated with the peripheral (usually via a DIF).
38 */
39#define TOP_DARJEELING_UART0_BASE_ADDR 0x30010000u
40
41/**
42 * Peripheral size for uart0 in top darjeeling.
43 *
44 * This is the size (in bytes) of the peripheral's reserved memory area. All
45 * memory-mapped registers associated with this peripheral should have an
46 * address between #TOP_DARJEELING_UART0_BASE_ADDR and
47 * `TOP_DARJEELING_UART0_BASE_ADDR + TOP_DARJEELING_UART0_SIZE_BYTES`.
48 */
49#define TOP_DARJEELING_UART0_SIZE_BYTES 0x40u
50
51/**
52 * Peripheral base address for gpio in top darjeeling.
53 *
54 * This should be used with #mmio_region_from_addr to access the memory-mapped
55 * registers associated with the peripheral (usually via a DIF).
56 */
57#define TOP_DARJEELING_GPIO_BASE_ADDR 0x30000000u
58
59/**
60 * Peripheral size for gpio in top darjeeling.
61 *
62 * This is the size (in bytes) of the peripheral's reserved memory area. All
63 * memory-mapped registers associated with this peripheral should have an
64 * address between #TOP_DARJEELING_GPIO_BASE_ADDR and
65 * `TOP_DARJEELING_GPIO_BASE_ADDR + TOP_DARJEELING_GPIO_SIZE_BYTES`.
66 */
67#define TOP_DARJEELING_GPIO_SIZE_BYTES 0x100u
68
69/**
70 * Peripheral base address for spi_device in top darjeeling.
71 *
72 * This should be used with #mmio_region_from_addr to access the memory-mapped
73 * registers associated with the peripheral (usually via a DIF).
74 */
75#define TOP_DARJEELING_SPI_DEVICE_BASE_ADDR 0x30310000u
76
77/**
78 * Peripheral size for spi_device in top darjeeling.
79 *
80 * This is the size (in bytes) of the peripheral's reserved memory area. All
81 * memory-mapped registers associated with this peripheral should have an
82 * address between #TOP_DARJEELING_SPI_DEVICE_BASE_ADDR and
83 * `TOP_DARJEELING_SPI_DEVICE_BASE_ADDR + TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES`.
84 */
85#define TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES 0x2000u
86
87/**
88 * Peripheral base address for i2c0 in top darjeeling.
89 *
90 * This should be used with #mmio_region_from_addr to access the memory-mapped
91 * registers associated with the peripheral (usually via a DIF).
92 */
93#define TOP_DARJEELING_I2C0_BASE_ADDR 0x30080000u
94
95/**
96 * Peripheral size for i2c0 in top darjeeling.
97 *
98 * This is the size (in bytes) of the peripheral's reserved memory area. All
99 * memory-mapped registers associated with this peripheral should have an
100 * address between #TOP_DARJEELING_I2C0_BASE_ADDR and
101 * `TOP_DARJEELING_I2C0_BASE_ADDR + TOP_DARJEELING_I2C0_SIZE_BYTES`.
102 */
103#define TOP_DARJEELING_I2C0_SIZE_BYTES 0x80u
104
105/**
106 * Peripheral base address for rv_timer in top darjeeling.
107 *
108 * This should be used with #mmio_region_from_addr to access the memory-mapped
109 * registers associated with the peripheral (usually via a DIF).
110 */
111#define TOP_DARJEELING_RV_TIMER_BASE_ADDR 0x30100000u
112
113/**
114 * Peripheral size for rv_timer in top darjeeling.
115 *
116 * This is the size (in bytes) of the peripheral's reserved memory area. All
117 * memory-mapped registers associated with this peripheral should have an
118 * address between #TOP_DARJEELING_RV_TIMER_BASE_ADDR and
119 * `TOP_DARJEELING_RV_TIMER_BASE_ADDR + TOP_DARJEELING_RV_TIMER_SIZE_BYTES`.
120 */
121#define TOP_DARJEELING_RV_TIMER_SIZE_BYTES 0x200u
122
123/**
124 * Peripheral base address for core device on otp_ctrl in top darjeeling.
125 *
126 * This should be used with #mmio_region_from_addr to access the memory-mapped
127 * registers associated with the peripheral (usually via a DIF).
128 */
129#define TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR 0x30130000u
130
131/**
132 * Peripheral size for core device on otp_ctrl in top darjeeling.
133 *
134 * This is the size (in bytes) of the peripheral's reserved memory area. All
135 * memory-mapped registers associated with this peripheral should have an
136 * address between #TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR and
137 * `TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES`.
138 */
139#define TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES 0x8000u
140
141/**
142 * Peripheral base address for prim device on otp_macro in top darjeeling.
143 *
144 * This should be used with #mmio_region_from_addr to access the memory-mapped
145 * registers associated with the peripheral (usually via a DIF).
146 */
147#define TOP_DARJEELING_OTP_MACRO_PRIM_BASE_ADDR 0x30140000u
148
149/**
150 * Peripheral size for prim device on otp_macro in top darjeeling.
151 *
152 * This is the size (in bytes) of the peripheral's reserved memory area. All
153 * memory-mapped registers associated with this peripheral should have an
154 * address between #TOP_DARJEELING_OTP_MACRO_PRIM_BASE_ADDR and
155 * `TOP_DARJEELING_OTP_MACRO_PRIM_BASE_ADDR + TOP_DARJEELING_OTP_MACRO_PRIM_SIZE_BYTES`.
156 */
157#define TOP_DARJEELING_OTP_MACRO_PRIM_SIZE_BYTES 0x20u
158
159/**
160 * Peripheral base address for regs device on lc_ctrl in top darjeeling.
161 *
162 * This should be used with #mmio_region_from_addr to access the memory-mapped
163 * registers associated with the peripheral (usually via a DIF).
164 */
165#define TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR 0x30150000u
166
167/**
168 * Peripheral size for regs device on lc_ctrl in top darjeeling.
169 *
170 * This is the size (in bytes) of the peripheral's reserved memory area. All
171 * memory-mapped registers associated with this peripheral should have an
172 * address between #TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR and
173 * `TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR + TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES`.
174 */
175#define TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES 0x100u
176
177/**
178 * Peripheral base address for alert_handler in top darjeeling.
179 *
180 * This should be used with #mmio_region_from_addr to access the memory-mapped
181 * registers associated with the peripheral (usually via a DIF).
182 */
183#define TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR 0x30160000u
184
185/**
186 * Peripheral size for alert_handler in top darjeeling.
187 *
188 * This is the size (in bytes) of the peripheral's reserved memory area. All
189 * memory-mapped registers associated with this peripheral should have an
190 * address between #TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR and
191 * `TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR + TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES`.
192 */
193#define TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES 0x800u
194
195/**
196 * Peripheral base address for spi_host0 in top darjeeling.
197 *
198 * This should be used with #mmio_region_from_addr to access the memory-mapped
199 * registers associated with the peripheral (usually via a DIF).
200 */
201#define TOP_DARJEELING_SPI_HOST0_BASE_ADDR 0x30300000u
202
203/**
204 * Peripheral size for spi_host0 in top darjeeling.
205 *
206 * This is the size (in bytes) of the peripheral's reserved memory area. All
207 * memory-mapped registers associated with this peripheral should have an
208 * address between #TOP_DARJEELING_SPI_HOST0_BASE_ADDR and
209 * `TOP_DARJEELING_SPI_HOST0_BASE_ADDR + TOP_DARJEELING_SPI_HOST0_SIZE_BYTES`.
210 */
211#define TOP_DARJEELING_SPI_HOST0_SIZE_BYTES 0x40u
212
213/**
214 * Peripheral base address for pwrmgr_aon in top darjeeling.
215 *
216 * This should be used with #mmio_region_from_addr to access the memory-mapped
217 * registers associated with the peripheral (usually via a DIF).
218 */
219#define TOP_DARJEELING_PWRMGR_AON_BASE_ADDR 0x30400000u
220
221/**
222 * Peripheral size for pwrmgr_aon in top darjeeling.
223 *
224 * This is the size (in bytes) of the peripheral's reserved memory area. All
225 * memory-mapped registers associated with this peripheral should have an
226 * address between #TOP_DARJEELING_PWRMGR_AON_BASE_ADDR and
227 * `TOP_DARJEELING_PWRMGR_AON_BASE_ADDR + TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES`.
228 */
229#define TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES 0x80u
230
231/**
232 * Peripheral base address for rstmgr_aon in top darjeeling.
233 *
234 * This should be used with #mmio_region_from_addr to access the memory-mapped
235 * registers associated with the peripheral (usually via a DIF).
236 */
237#define TOP_DARJEELING_RSTMGR_AON_BASE_ADDR 0x30410000u
238
239/**
240 * Peripheral size for rstmgr_aon in top darjeeling.
241 *
242 * This is the size (in bytes) of the peripheral's reserved memory area. All
243 * memory-mapped registers associated with this peripheral should have an
244 * address between #TOP_DARJEELING_RSTMGR_AON_BASE_ADDR and
245 * `TOP_DARJEELING_RSTMGR_AON_BASE_ADDR + TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES`.
246 */
247#define TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES 0x80u
248
249/**
250 * Peripheral base address for clkmgr_aon in top darjeeling.
251 *
252 * This should be used with #mmio_region_from_addr to access the memory-mapped
253 * registers associated with the peripheral (usually via a DIF).
254 */
255#define TOP_DARJEELING_CLKMGR_AON_BASE_ADDR 0x30420000u
256
257/**
258 * Peripheral size for clkmgr_aon in top darjeeling.
259 *
260 * This is the size (in bytes) of the peripheral's reserved memory area. All
261 * memory-mapped registers associated with this peripheral should have an
262 * address between #TOP_DARJEELING_CLKMGR_AON_BASE_ADDR and
263 * `TOP_DARJEELING_CLKMGR_AON_BASE_ADDR + TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES`.
264 */
265#define TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES 0x40u
266
267/**
268 * Peripheral base address for pinmux_aon in top darjeeling.
269 *
270 * This should be used with #mmio_region_from_addr to access the memory-mapped
271 * registers associated with the peripheral (usually via a DIF).
272 */
273#define TOP_DARJEELING_PINMUX_AON_BASE_ADDR 0x30460000u
274
275/**
276 * Peripheral size for pinmux_aon in top darjeeling.
277 *
278 * This is the size (in bytes) of the peripheral's reserved memory area. All
279 * memory-mapped registers associated with this peripheral should have an
280 * address between #TOP_DARJEELING_PINMUX_AON_BASE_ADDR and
281 * `TOP_DARJEELING_PINMUX_AON_BASE_ADDR + TOP_DARJEELING_PINMUX_AON_SIZE_BYTES`.
282 */
283#define TOP_DARJEELING_PINMUX_AON_SIZE_BYTES 0x800u
284
285/**
286 * Peripheral base address for aon_timer_aon in top darjeeling.
287 *
288 * This should be used with #mmio_region_from_addr to access the memory-mapped
289 * registers associated with the peripheral (usually via a DIF).
290 */
291#define TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR 0x30470000u
292
293/**
294 * Peripheral size for aon_timer_aon in top darjeeling.
295 *
296 * This is the size (in bytes) of the peripheral's reserved memory area. All
297 * memory-mapped registers associated with this peripheral should have an
298 * address between #TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR and
299 * `TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR + TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES`.
300 */
301#define TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES 0x40u
302
303/**
304 * Peripheral base address for ast in top darjeeling.
305 *
306 * This should be used with #mmio_region_from_addr to access the memory-mapped
307 * registers associated with the peripheral (usually via a DIF).
308 */
309#define TOP_DARJEELING_AST_BASE_ADDR 0x30480000u
310
311/**
312 * Peripheral size for ast in top darjeeling.
313 *
314 * This is the size (in bytes) of the peripheral's reserved memory area. All
315 * memory-mapped registers associated with this peripheral should have an
316 * address between #TOP_DARJEELING_AST_BASE_ADDR and
317 * `TOP_DARJEELING_AST_BASE_ADDR + TOP_DARJEELING_AST_SIZE_BYTES`.
318 */
319#define TOP_DARJEELING_AST_SIZE_BYTES 0x400u
320
321/**
322 * Peripheral base address for core device on soc_proxy in top darjeeling.
323 *
324 * This should be used with #mmio_region_from_addr to access the memory-mapped
325 * registers associated with the peripheral (usually via a DIF).
326 */
327#define TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR 0x22030000u
328
329/**
330 * Peripheral size for core device on soc_proxy in top darjeeling.
331 *
332 * This is the size (in bytes) of the peripheral's reserved memory area. All
333 * memory-mapped registers associated with this peripheral should have an
334 * address between #TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR and
335 * `TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES`.
336 */
337#define TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES 0x10u
338
339/**
340 * Peripheral base address for ctn device on soc_proxy in top darjeeling.
341 *
342 * This should be used with #mmio_region_from_addr to access the memory-mapped
343 * registers associated with the peripheral (usually via a DIF).
344 */
345#define TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR 0x40000000u
346
347/**
348 * Peripheral size for ctn device on soc_proxy in top darjeeling.
349 *
350 * This is the size (in bytes) of the peripheral's reserved memory area. All
351 * memory-mapped registers associated with this peripheral should have an
352 * address between #TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR and
353 * `TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES`.
354 */
355#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x40000000u
356
357/**
358 * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.
359 *
360 * This should be used with #mmio_region_from_addr to access the memory-mapped
361 * registers associated with the peripheral (usually via a DIF).
362 */
363#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x30500000u
364
365/**
366 * Peripheral size for regs device on sram_ctrl_ret_aon in top darjeeling.
367 *
368 * This is the size (in bytes) of the peripheral's reserved memory area. All
369 * memory-mapped registers associated with this peripheral should have an
370 * address between #TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
371 * `TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
372 */
373#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u
374
375/**
376 * Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling.
377 *
378 * This should be used with #mmio_region_from_addr to access the memory-mapped
379 * registers associated with the peripheral (usually via a DIF).
380 */
381#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x30600000u
382
383/**
384 * Peripheral size for ram device on sram_ctrl_ret_aon in top darjeeling.
385 *
386 * This is the size (in bytes) of the peripheral's reserved memory area. All
387 * memory-mapped registers associated with this peripheral should have an
388 * address between #TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
389 * `TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
390 */
391#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
392
393/**
394 * Peripheral base address for regs device on rv_dm in top darjeeling.
395 *
396 * This should be used with #mmio_region_from_addr to access the memory-mapped
397 * registers associated with the peripheral (usually via a DIF).
398 */
399#define TOP_DARJEELING_RV_DM_REGS_BASE_ADDR 0x21200000u
400
401/**
402 * Peripheral size for regs device on rv_dm in top darjeeling.
403 *
404 * This is the size (in bytes) of the peripheral's reserved memory area. All
405 * memory-mapped registers associated with this peripheral should have an
406 * address between #TOP_DARJEELING_RV_DM_REGS_BASE_ADDR and
407 * `TOP_DARJEELING_RV_DM_REGS_BASE_ADDR + TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES`.
408 */
409#define TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES 0x10u
410
411/**
412 * Peripheral base address for mem device on rv_dm in top darjeeling.
413 *
414 * This should be used with #mmio_region_from_addr to access the memory-mapped
415 * registers associated with the peripheral (usually via a DIF).
416 */
417#define TOP_DARJEELING_RV_DM_MEM_BASE_ADDR 0x40000u
418
419/**
420 * Peripheral size for mem device on rv_dm in top darjeeling.
421 *
422 * This is the size (in bytes) of the peripheral's reserved memory area. All
423 * memory-mapped registers associated with this peripheral should have an
424 * address between #TOP_DARJEELING_RV_DM_MEM_BASE_ADDR and
425 * `TOP_DARJEELING_RV_DM_MEM_BASE_ADDR + TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES`.
426 */
427#define TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES 0x1000u
428
429/**
430 * Peripheral base address for rv_plic in top darjeeling.
431 *
432 * This should be used with #mmio_region_from_addr to access the memory-mapped
433 * registers associated with the peripheral (usually via a DIF).
434 */
435#define TOP_DARJEELING_RV_PLIC_BASE_ADDR 0x28000000u
436
437/**
438 * Peripheral size for rv_plic in top darjeeling.
439 *
440 * This is the size (in bytes) of the peripheral's reserved memory area. All
441 * memory-mapped registers associated with this peripheral should have an
442 * address between #TOP_DARJEELING_RV_PLIC_BASE_ADDR and
443 * `TOP_DARJEELING_RV_PLIC_BASE_ADDR + TOP_DARJEELING_RV_PLIC_SIZE_BYTES`.
444 */
445#define TOP_DARJEELING_RV_PLIC_SIZE_BYTES 0x8000000u
446
447/**
448 * Peripheral base address for aes in top darjeeling.
449 *
450 * This should be used with #mmio_region_from_addr to access the memory-mapped
451 * registers associated with the peripheral (usually via a DIF).
452 */
453#define TOP_DARJEELING_AES_BASE_ADDR 0x21100000u
454
455/**
456 * Peripheral size for aes in top darjeeling.
457 *
458 * This is the size (in bytes) of the peripheral's reserved memory area. All
459 * memory-mapped registers associated with this peripheral should have an
460 * address between #TOP_DARJEELING_AES_BASE_ADDR and
461 * `TOP_DARJEELING_AES_BASE_ADDR + TOP_DARJEELING_AES_SIZE_BYTES`.
462 */
463#define TOP_DARJEELING_AES_SIZE_BYTES 0x100u
464
465/**
466 * Peripheral base address for hmac in top darjeeling.
467 *
468 * This should be used with #mmio_region_from_addr to access the memory-mapped
469 * registers associated with the peripheral (usually via a DIF).
470 */
471#define TOP_DARJEELING_HMAC_BASE_ADDR 0x21110000u
472
473/**
474 * Peripheral size for hmac in top darjeeling.
475 *
476 * This is the size (in bytes) of the peripheral's reserved memory area. All
477 * memory-mapped registers associated with this peripheral should have an
478 * address between #TOP_DARJEELING_HMAC_BASE_ADDR and
479 * `TOP_DARJEELING_HMAC_BASE_ADDR + TOP_DARJEELING_HMAC_SIZE_BYTES`.
480 */
481#define TOP_DARJEELING_HMAC_SIZE_BYTES 0x2000u
482
483/**
484 * Peripheral base address for kmac in top darjeeling.
485 *
486 * This should be used with #mmio_region_from_addr to access the memory-mapped
487 * registers associated with the peripheral (usually via a DIF).
488 */
489#define TOP_DARJEELING_KMAC_BASE_ADDR 0x21120000u
490
491/**
492 * Peripheral size for kmac in top darjeeling.
493 *
494 * This is the size (in bytes) of the peripheral's reserved memory area. All
495 * memory-mapped registers associated with this peripheral should have an
496 * address between #TOP_DARJEELING_KMAC_BASE_ADDR and
497 * `TOP_DARJEELING_KMAC_BASE_ADDR + TOP_DARJEELING_KMAC_SIZE_BYTES`.
498 */
499#define TOP_DARJEELING_KMAC_SIZE_BYTES 0x1000u
500
501/**
502 * Peripheral base address for otbn in top darjeeling.
503 *
504 * This should be used with #mmio_region_from_addr to access the memory-mapped
505 * registers associated with the peripheral (usually via a DIF).
506 */
507#define TOP_DARJEELING_OTBN_BASE_ADDR 0x21130000u
508
509/**
510 * Peripheral size for otbn in top darjeeling.
511 *
512 * This is the size (in bytes) of the peripheral's reserved memory area. All
513 * memory-mapped registers associated with this peripheral should have an
514 * address between #TOP_DARJEELING_OTBN_BASE_ADDR and
515 * `TOP_DARJEELING_OTBN_BASE_ADDR + TOP_DARJEELING_OTBN_SIZE_BYTES`.
516 */
517#define TOP_DARJEELING_OTBN_SIZE_BYTES 0x10000u
518
519/**
520 * Peripheral base address for keymgr_dpe in top darjeeling.
521 *
522 * This should be used with #mmio_region_from_addr to access the memory-mapped
523 * registers associated with the peripheral (usually via a DIF).
524 */
525#define TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR 0x21140000u
526
527/**
528 * Peripheral size for keymgr_dpe in top darjeeling.
529 *
530 * This is the size (in bytes) of the peripheral's reserved memory area. All
531 * memory-mapped registers associated with this peripheral should have an
532 * address between #TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR and
533 * `TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR + TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES`.
534 */
535#define TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES 0x100u
536
537/**
538 * Peripheral base address for csrng in top darjeeling.
539 *
540 * This should be used with #mmio_region_from_addr to access the memory-mapped
541 * registers associated with the peripheral (usually via a DIF).
542 */
543#define TOP_DARJEELING_CSRNG_BASE_ADDR 0x21150000u
544
545/**
546 * Peripheral size for csrng in top darjeeling.
547 *
548 * This is the size (in bytes) of the peripheral's reserved memory area. All
549 * memory-mapped registers associated with this peripheral should have an
550 * address between #TOP_DARJEELING_CSRNG_BASE_ADDR and
551 * `TOP_DARJEELING_CSRNG_BASE_ADDR + TOP_DARJEELING_CSRNG_SIZE_BYTES`.
552 */
553#define TOP_DARJEELING_CSRNG_SIZE_BYTES 0x80u
554
555/**
556 * Peripheral base address for entropy_src in top darjeeling.
557 *
558 * This should be used with #mmio_region_from_addr to access the memory-mapped
559 * registers associated with the peripheral (usually via a DIF).
560 */
561#define TOP_DARJEELING_ENTROPY_SRC_BASE_ADDR 0x21160000u
562
563/**
564 * Peripheral size for entropy_src in top darjeeling.
565 *
566 * This is the size (in bytes) of the peripheral's reserved memory area. All
567 * memory-mapped registers associated with this peripheral should have an
568 * address between #TOP_DARJEELING_ENTROPY_SRC_BASE_ADDR and
569 * `TOP_DARJEELING_ENTROPY_SRC_BASE_ADDR + TOP_DARJEELING_ENTROPY_SRC_SIZE_BYTES`.
570 */
571#define TOP_DARJEELING_ENTROPY_SRC_SIZE_BYTES 0x100u
572
573/**
574 * Peripheral base address for edn0 in top darjeeling.
575 *
576 * This should be used with #mmio_region_from_addr to access the memory-mapped
577 * registers associated with the peripheral (usually via a DIF).
578 */
579#define TOP_DARJEELING_EDN0_BASE_ADDR 0x21170000u
580
581/**
582 * Peripheral size for edn0 in top darjeeling.
583 *
584 * This is the size (in bytes) of the peripheral's reserved memory area. All
585 * memory-mapped registers associated with this peripheral should have an
586 * address between #TOP_DARJEELING_EDN0_BASE_ADDR and
587 * `TOP_DARJEELING_EDN0_BASE_ADDR + TOP_DARJEELING_EDN0_SIZE_BYTES`.
588 */
589#define TOP_DARJEELING_EDN0_SIZE_BYTES 0x80u
590
591/**
592 * Peripheral base address for edn1 in top darjeeling.
593 *
594 * This should be used with #mmio_region_from_addr to access the memory-mapped
595 * registers associated with the peripheral (usually via a DIF).
596 */
597#define TOP_DARJEELING_EDN1_BASE_ADDR 0x21180000u
598
599/**
600 * Peripheral size for edn1 in top darjeeling.
601 *
602 * This is the size (in bytes) of the peripheral's reserved memory area. All
603 * memory-mapped registers associated with this peripheral should have an
604 * address between #TOP_DARJEELING_EDN1_BASE_ADDR and
605 * `TOP_DARJEELING_EDN1_BASE_ADDR + TOP_DARJEELING_EDN1_SIZE_BYTES`.
606 */
607#define TOP_DARJEELING_EDN1_SIZE_BYTES 0x80u
608
609/**
610 * Peripheral base address for regs device on sram_ctrl_main in top darjeeling.
611 *
612 * This should be used with #mmio_region_from_addr to access the memory-mapped
613 * registers associated with the peripheral (usually via a DIF).
614 */
615#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x211C0000u
616
617/**
618 * Peripheral size for regs device on sram_ctrl_main in top darjeeling.
619 *
620 * This is the size (in bytes) of the peripheral's reserved memory area. All
621 * memory-mapped registers associated with this peripheral should have an
622 * address between #TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
623 * `TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
624 */
625#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u
626
627/**
628 * Peripheral base address for ram device on sram_ctrl_main in top darjeeling.
629 *
630 * This should be used with #mmio_region_from_addr to access the memory-mapped
631 * registers associated with the peripheral (usually via a DIF).
632 */
633#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
634
635/**
636 * Peripheral size for ram device on sram_ctrl_main in top darjeeling.
637 *
638 * This is the size (in bytes) of the peripheral's reserved memory area. All
639 * memory-mapped registers associated with this peripheral should have an
640 * address between #TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
641 * `TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
642 */
643#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x10000u
644
645/**
646 * Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling.
647 *
648 * This should be used with #mmio_region_from_addr to access the memory-mapped
649 * registers associated with the peripheral (usually via a DIF).
650 */
651#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR 0x211D0000u
652
653/**
654 * Peripheral size for regs device on sram_ctrl_mbox in top darjeeling.
655 *
656 * This is the size (in bytes) of the peripheral's reserved memory area. All
657 * memory-mapped registers associated with this peripheral should have an
658 * address between #TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR and
659 * `TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES`.
660 */
661#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES 0x40u
662
663/**
664 * Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling.
665 *
666 * This should be used with #mmio_region_from_addr to access the memory-mapped
667 * registers associated with the peripheral (usually via a DIF).
668 */
669#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR 0x11000000u
670
671/**
672 * Peripheral size for ram device on sram_ctrl_mbox in top darjeeling.
673 *
674 * This is the size (in bytes) of the peripheral's reserved memory area. All
675 * memory-mapped registers associated with this peripheral should have an
676 * address between #TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR and
677 * `TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES`.
678 */
679#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES 0x1000u
680
681/**
682 * Peripheral base address for regs device on rom_ctrl0 in top darjeeling.
683 *
684 * This should be used with #mmio_region_from_addr to access the memory-mapped
685 * registers associated with the peripheral (usually via a DIF).
686 */
687#define TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR 0x211E0000u
688
689/**
690 * Peripheral size for regs device on rom_ctrl0 in top darjeeling.
691 *
692 * This is the size (in bytes) of the peripheral's reserved memory area. All
693 * memory-mapped registers associated with this peripheral should have an
694 * address between #TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR and
695 * `TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR + TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES`.
696 */
697#define TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES 0x80u
698
699/**
700 * Peripheral base address for rom device on rom_ctrl0 in top darjeeling.
701 *
702 * This should be used with #mmio_region_from_addr to access the memory-mapped
703 * registers associated with the peripheral (usually via a DIF).
704 */
705#define TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR 0x8000u
706
707/**
708 * Peripheral size for rom device on rom_ctrl0 in top darjeeling.
709 *
710 * This is the size (in bytes) of the peripheral's reserved memory area. All
711 * memory-mapped registers associated with this peripheral should have an
712 * address between #TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR and
713 * `TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR + TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES`.
714 */
715#define TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES 0x8000u
716
717/**
718 * Peripheral base address for regs device on rom_ctrl1 in top darjeeling.
719 *
720 * This should be used with #mmio_region_from_addr to access the memory-mapped
721 * registers associated with the peripheral (usually via a DIF).
722 */
723#define TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR 0x211E1000u
724
725/**
726 * Peripheral size for regs device on rom_ctrl1 in top darjeeling.
727 *
728 * This is the size (in bytes) of the peripheral's reserved memory area. All
729 * memory-mapped registers associated with this peripheral should have an
730 * address between #TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR and
731 * `TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR + TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES`.
732 */
733#define TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES 0x80u
734
735/**
736 * Peripheral base address for rom device on rom_ctrl1 in top darjeeling.
737 *
738 * This should be used with #mmio_region_from_addr to access the memory-mapped
739 * registers associated with the peripheral (usually via a DIF).
740 */
741#define TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR 0x20000u
742
743/**
744 * Peripheral size for rom device on rom_ctrl1 in top darjeeling.
745 *
746 * This is the size (in bytes) of the peripheral's reserved memory area. All
747 * memory-mapped registers associated with this peripheral should have an
748 * address between #TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR and
749 * `TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR + TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES`.
750 */
751#define TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES 0x10000u
752
753/**
754 * Peripheral base address for dma in top darjeeling.
755 *
756 * This should be used with #mmio_region_from_addr to access the memory-mapped
757 * registers associated with the peripheral (usually via a DIF).
758 */
759#define TOP_DARJEELING_DMA_BASE_ADDR 0x22010000u
760
761/**
762 * Peripheral size for dma in top darjeeling.
763 *
764 * This is the size (in bytes) of the peripheral's reserved memory area. All
765 * memory-mapped registers associated with this peripheral should have an
766 * address between #TOP_DARJEELING_DMA_BASE_ADDR and
767 * `TOP_DARJEELING_DMA_BASE_ADDR + TOP_DARJEELING_DMA_SIZE_BYTES`.
768 */
769#define TOP_DARJEELING_DMA_SIZE_BYTES 0x200u
770
771/**
772 * Peripheral base address for core device on mbx0 in top darjeeling.
773 *
774 * This should be used with #mmio_region_from_addr to access the memory-mapped
775 * registers associated with the peripheral (usually via a DIF).
776 */
777#define TOP_DARJEELING_MBX0_CORE_BASE_ADDR 0x22000000u
778
779/**
780 * Peripheral size for core device on mbx0 in top darjeeling.
781 *
782 * This is the size (in bytes) of the peripheral's reserved memory area. All
783 * memory-mapped registers associated with this peripheral should have an
784 * address between #TOP_DARJEELING_MBX0_CORE_BASE_ADDR and
785 * `TOP_DARJEELING_MBX0_CORE_BASE_ADDR + TOP_DARJEELING_MBX0_CORE_SIZE_BYTES`.
786 */
787#define TOP_DARJEELING_MBX0_CORE_SIZE_BYTES 0x80u
788
789/**
790 * Peripheral base address for core device on mbx1 in top darjeeling.
791 *
792 * This should be used with #mmio_region_from_addr to access the memory-mapped
793 * registers associated with the peripheral (usually via a DIF).
794 */
795#define TOP_DARJEELING_MBX1_CORE_BASE_ADDR 0x22000100u
796
797/**
798 * Peripheral size for core device on mbx1 in top darjeeling.
799 *
800 * This is the size (in bytes) of the peripheral's reserved memory area. All
801 * memory-mapped registers associated with this peripheral should have an
802 * address between #TOP_DARJEELING_MBX1_CORE_BASE_ADDR and
803 * `TOP_DARJEELING_MBX1_CORE_BASE_ADDR + TOP_DARJEELING_MBX1_CORE_SIZE_BYTES`.
804 */
805#define TOP_DARJEELING_MBX1_CORE_SIZE_BYTES 0x80u
806
807/**
808 * Peripheral base address for core device on mbx2 in top darjeeling.
809 *
810 * This should be used with #mmio_region_from_addr to access the memory-mapped
811 * registers associated with the peripheral (usually via a DIF).
812 */
813#define TOP_DARJEELING_MBX2_CORE_BASE_ADDR 0x22000200u
814
815/**
816 * Peripheral size for core device on mbx2 in top darjeeling.
817 *
818 * This is the size (in bytes) of the peripheral's reserved memory area. All
819 * memory-mapped registers associated with this peripheral should have an
820 * address between #TOP_DARJEELING_MBX2_CORE_BASE_ADDR and
821 * `TOP_DARJEELING_MBX2_CORE_BASE_ADDR + TOP_DARJEELING_MBX2_CORE_SIZE_BYTES`.
822 */
823#define TOP_DARJEELING_MBX2_CORE_SIZE_BYTES 0x80u
824
825/**
826 * Peripheral base address for core device on mbx3 in top darjeeling.
827 *
828 * This should be used with #mmio_region_from_addr to access the memory-mapped
829 * registers associated with the peripheral (usually via a DIF).
830 */
831#define TOP_DARJEELING_MBX3_CORE_BASE_ADDR 0x22000300u
832
833/**
834 * Peripheral size for core device on mbx3 in top darjeeling.
835 *
836 * This is the size (in bytes) of the peripheral's reserved memory area. All
837 * memory-mapped registers associated with this peripheral should have an
838 * address between #TOP_DARJEELING_MBX3_CORE_BASE_ADDR and
839 * `TOP_DARJEELING_MBX3_CORE_BASE_ADDR + TOP_DARJEELING_MBX3_CORE_SIZE_BYTES`.
840 */
841#define TOP_DARJEELING_MBX3_CORE_SIZE_BYTES 0x80u
842
843/**
844 * Peripheral base address for core device on mbx4 in top darjeeling.
845 *
846 * This should be used with #mmio_region_from_addr to access the memory-mapped
847 * registers associated with the peripheral (usually via a DIF).
848 */
849#define TOP_DARJEELING_MBX4_CORE_BASE_ADDR 0x22000400u
850
851/**
852 * Peripheral size for core device on mbx4 in top darjeeling.
853 *
854 * This is the size (in bytes) of the peripheral's reserved memory area. All
855 * memory-mapped registers associated with this peripheral should have an
856 * address between #TOP_DARJEELING_MBX4_CORE_BASE_ADDR and
857 * `TOP_DARJEELING_MBX4_CORE_BASE_ADDR + TOP_DARJEELING_MBX4_CORE_SIZE_BYTES`.
858 */
859#define TOP_DARJEELING_MBX4_CORE_SIZE_BYTES 0x80u
860
861/**
862 * Peripheral base address for core device on mbx5 in top darjeeling.
863 *
864 * This should be used with #mmio_region_from_addr to access the memory-mapped
865 * registers associated with the peripheral (usually via a DIF).
866 */
867#define TOP_DARJEELING_MBX5_CORE_BASE_ADDR 0x22000500u
868
869/**
870 * Peripheral size for core device on mbx5 in top darjeeling.
871 *
872 * This is the size (in bytes) of the peripheral's reserved memory area. All
873 * memory-mapped registers associated with this peripheral should have an
874 * address between #TOP_DARJEELING_MBX5_CORE_BASE_ADDR and
875 * `TOP_DARJEELING_MBX5_CORE_BASE_ADDR + TOP_DARJEELING_MBX5_CORE_SIZE_BYTES`.
876 */
877#define TOP_DARJEELING_MBX5_CORE_SIZE_BYTES 0x80u
878
879/**
880 * Peripheral base address for core device on mbx6 in top darjeeling.
881 *
882 * This should be used with #mmio_region_from_addr to access the memory-mapped
883 * registers associated with the peripheral (usually via a DIF).
884 */
885#define TOP_DARJEELING_MBX6_CORE_BASE_ADDR 0x22000600u
886
887/**
888 * Peripheral size for core device on mbx6 in top darjeeling.
889 *
890 * This is the size (in bytes) of the peripheral's reserved memory area. All
891 * memory-mapped registers associated with this peripheral should have an
892 * address between #TOP_DARJEELING_MBX6_CORE_BASE_ADDR and
893 * `TOP_DARJEELING_MBX6_CORE_BASE_ADDR + TOP_DARJEELING_MBX6_CORE_SIZE_BYTES`.
894 */
895#define TOP_DARJEELING_MBX6_CORE_SIZE_BYTES 0x80u
896
897/**
898 * Peripheral base address for core device on mbx_jtag in top darjeeling.
899 *
900 * This should be used with #mmio_region_from_addr to access the memory-mapped
901 * registers associated with the peripheral (usually via a DIF).
902 */
903#define TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR 0x22000800u
904
905/**
906 * Peripheral size for core device on mbx_jtag in top darjeeling.
907 *
908 * This is the size (in bytes) of the peripheral's reserved memory area. All
909 * memory-mapped registers associated with this peripheral should have an
910 * address between #TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR and
911 * `TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES`.
912 */
913#define TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES 0x80u
914
915/**
916 * Peripheral base address for core device on mbx_pcie0 in top darjeeling.
917 *
918 * This should be used with #mmio_region_from_addr to access the memory-mapped
919 * registers associated with the peripheral (usually via a DIF).
920 */
921#define TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR 0x22040000u
922
923/**
924 * Peripheral size for core device on mbx_pcie0 in top darjeeling.
925 *
926 * This is the size (in bytes) of the peripheral's reserved memory area. All
927 * memory-mapped registers associated with this peripheral should have an
928 * address between #TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR and
929 * `TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES`.
930 */
931#define TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES 0x80u
932
933/**
934 * Peripheral base address for core device on mbx_pcie1 in top darjeeling.
935 *
936 * This should be used with #mmio_region_from_addr to access the memory-mapped
937 * registers associated with the peripheral (usually via a DIF).
938 */
939#define TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR 0x22040100u
940
941/**
942 * Peripheral size for core device on mbx_pcie1 in top darjeeling.
943 *
944 * This is the size (in bytes) of the peripheral's reserved memory area. All
945 * memory-mapped registers associated with this peripheral should have an
946 * address between #TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR and
947 * `TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES`.
948 */
949#define TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES 0x80u
950
951/**
952 * Peripheral base address for core device on soc_dbg_ctrl in top darjeeling.
953 *
954 * This should be used with #mmio_region_from_addr to access the memory-mapped
955 * registers associated with the peripheral (usually via a DIF).
956 */
957#define TOP_DARJEELING_SOC_DBG_CTRL_CORE_BASE_ADDR 0x30170000u
958
959/**
960 * Peripheral size for core device on soc_dbg_ctrl in top darjeeling.
961 *
962 * This is the size (in bytes) of the peripheral's reserved memory area. All
963 * memory-mapped registers associated with this peripheral should have an
964 * address between #TOP_DARJEELING_SOC_DBG_CTRL_CORE_BASE_ADDR and
965 * `TOP_DARJEELING_SOC_DBG_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_SOC_DBG_CTRL_CORE_SIZE_BYTES`.
966 */
967#define TOP_DARJEELING_SOC_DBG_CTRL_CORE_SIZE_BYTES 0x20u
968
969/**
970 * Peripheral base address for cfg device on rv_core_ibex in top darjeeling.
971 *
972 * This should be used with #mmio_region_from_addr to access the memory-mapped
973 * registers associated with the peripheral (usually via a DIF).
974 */
975#define TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR 0x211F0000u
976
977/**
978 * Peripheral size for cfg device on rv_core_ibex in top darjeeling.
979 *
980 * This is the size (in bytes) of the peripheral's reserved memory area. All
981 * memory-mapped registers associated with this peripheral should have an
982 * address between #TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR and
983 * `TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES`.
984 */
985#define TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES 0x800u
986
987
988/**
989 * Memory base address for ctn in top darjeeling.
990 */
991#define TOP_DARJEELING_CTN_BASE_ADDR 0x40000000u
992
993/**
994 * Memory size for ctn in top darjeeling.
995 */
996#define TOP_DARJEELING_CTN_SIZE_BYTES 0x40000000u
997
998/**
999 * Memory base address for ram_ret_aon in top darjeeling.
1000 */
1001#define TOP_DARJEELING_RAM_RET_AON_BASE_ADDR 0x30600000u
1002
1003/**
1004 * Memory size for ram_ret_aon in top darjeeling.
1005 */
1006#define TOP_DARJEELING_RAM_RET_AON_SIZE_BYTES 0x1000u
1007
1008/**
1009 * Memory base address for ram_main in top darjeeling.
1010 */
1011#define TOP_DARJEELING_RAM_MAIN_BASE_ADDR 0x10000000u
1012
1013/**
1014 * Memory size for ram_main in top darjeeling.
1015 */
1016#define TOP_DARJEELING_RAM_MAIN_SIZE_BYTES 0x10000u
1017
1018/**
1019 * Memory base address for ram_mbox in top darjeeling.
1020 */
1021#define TOP_DARJEELING_RAM_MBOX_BASE_ADDR 0x11000000u
1022
1023/**
1024 * Memory size for ram_mbox in top darjeeling.
1025 */
1026#define TOP_DARJEELING_RAM_MBOX_SIZE_BYTES 0x1000u
1027
1028/**
1029 * Memory base address for rom0 in top darjeeling.
1030 */
1031#define TOP_DARJEELING_ROM0_BASE_ADDR 0x8000u
1032
1033/**
1034 * Memory size for rom0 in top darjeeling.
1035 */
1036#define TOP_DARJEELING_ROM0_SIZE_BYTES 0x8000u
1037
1038/**
1039 * Memory base address for rom1 in top darjeeling.
1040 */
1041#define TOP_DARJEELING_ROM1_BASE_ADDR 0x20000u
1042
1043/**
1044 * Memory size for rom1 in top darjeeling.
1045 */
1046#define TOP_DARJEELING_ROM1_SIZE_BYTES 0x10000u
1047
1048
1049/**
1050 * PLIC Interrupt Source Peripheral.
1051 *
1052 * Enumeration used to determine which peripheral asserted the corresponding
1053 * interrupt.
1054 */
1056 kTopDarjeelingPlicPeripheralUnknown = 0, /**< Unknown Peripheral */
1088 kTopDarjeelingPlicPeripheralAcRangeCheck = 32, /**< ac_range_check */
1089 kTopDarjeelingPlicPeripheralLast = 32, /**< \internal Final PLIC peripheral */
1091
1092/**
1093 * PLIC Interrupt Source.
1094 *
1095 * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
1096 * the same peripheral are guaranteed to be consecutive.
1097 */
1099 kTopDarjeelingPlicIrqIdNone = 0, /**< No Interrupt */
1100 kTopDarjeelingPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
1101 kTopDarjeelingPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
1102 kTopDarjeelingPlicIrqIdUart0TxDone = 3, /**< uart0_tx_done */
1103 kTopDarjeelingPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
1104 kTopDarjeelingPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
1105 kTopDarjeelingPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
1106 kTopDarjeelingPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
1107 kTopDarjeelingPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
1108 kTopDarjeelingPlicIrqIdUart0TxEmpty = 9, /**< uart0_tx_empty */
1109 kTopDarjeelingPlicIrqIdGpioGpio0 = 10, /**< gpio_gpio 0 */
1110 kTopDarjeelingPlicIrqIdGpioGpio1 = 11, /**< gpio_gpio 1 */
1111 kTopDarjeelingPlicIrqIdGpioGpio2 = 12, /**< gpio_gpio 2 */
1112 kTopDarjeelingPlicIrqIdGpioGpio3 = 13, /**< gpio_gpio 3 */
1113 kTopDarjeelingPlicIrqIdGpioGpio4 = 14, /**< gpio_gpio 4 */
1114 kTopDarjeelingPlicIrqIdGpioGpio5 = 15, /**< gpio_gpio 5 */
1115 kTopDarjeelingPlicIrqIdGpioGpio6 = 16, /**< gpio_gpio 6 */
1116 kTopDarjeelingPlicIrqIdGpioGpio7 = 17, /**< gpio_gpio 7 */
1117 kTopDarjeelingPlicIrqIdGpioGpio8 = 18, /**< gpio_gpio 8 */
1118 kTopDarjeelingPlicIrqIdGpioGpio9 = 19, /**< gpio_gpio 9 */
1119 kTopDarjeelingPlicIrqIdGpioGpio10 = 20, /**< gpio_gpio 10 */
1120 kTopDarjeelingPlicIrqIdGpioGpio11 = 21, /**< gpio_gpio 11 */
1121 kTopDarjeelingPlicIrqIdGpioGpio12 = 22, /**< gpio_gpio 12 */
1122 kTopDarjeelingPlicIrqIdGpioGpio13 = 23, /**< gpio_gpio 13 */
1123 kTopDarjeelingPlicIrqIdGpioGpio14 = 24, /**< gpio_gpio 14 */
1124 kTopDarjeelingPlicIrqIdGpioGpio15 = 25, /**< gpio_gpio 15 */
1125 kTopDarjeelingPlicIrqIdGpioGpio16 = 26, /**< gpio_gpio 16 */
1126 kTopDarjeelingPlicIrqIdGpioGpio17 = 27, /**< gpio_gpio 17 */
1127 kTopDarjeelingPlicIrqIdGpioGpio18 = 28, /**< gpio_gpio 18 */
1128 kTopDarjeelingPlicIrqIdGpioGpio19 = 29, /**< gpio_gpio 19 */
1129 kTopDarjeelingPlicIrqIdGpioGpio20 = 30, /**< gpio_gpio 20 */
1130 kTopDarjeelingPlicIrqIdGpioGpio21 = 31, /**< gpio_gpio 21 */
1131 kTopDarjeelingPlicIrqIdGpioGpio22 = 32, /**< gpio_gpio 22 */
1132 kTopDarjeelingPlicIrqIdGpioGpio23 = 33, /**< gpio_gpio 23 */
1133 kTopDarjeelingPlicIrqIdGpioGpio24 = 34, /**< gpio_gpio 24 */
1134 kTopDarjeelingPlicIrqIdGpioGpio25 = 35, /**< gpio_gpio 25 */
1135 kTopDarjeelingPlicIrqIdGpioGpio26 = 36, /**< gpio_gpio 26 */
1136 kTopDarjeelingPlicIrqIdGpioGpio27 = 37, /**< gpio_gpio 27 */
1137 kTopDarjeelingPlicIrqIdGpioGpio28 = 38, /**< gpio_gpio 28 */
1138 kTopDarjeelingPlicIrqIdGpioGpio29 = 39, /**< gpio_gpio 29 */
1139 kTopDarjeelingPlicIrqIdGpioGpio30 = 40, /**< gpio_gpio 30 */
1140 kTopDarjeelingPlicIrqIdGpioGpio31 = 41, /**< gpio_gpio 31 */
1141 kTopDarjeelingPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 42, /**< spi_device_upload_cmdfifo_not_empty */
1142 kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 43, /**< spi_device_upload_payload_not_empty */
1143 kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadOverflow = 44, /**< spi_device_upload_payload_overflow */
1144 kTopDarjeelingPlicIrqIdSpiDeviceReadbufWatermark = 45, /**< spi_device_readbuf_watermark */
1145 kTopDarjeelingPlicIrqIdSpiDeviceReadbufFlip = 46, /**< spi_device_readbuf_flip */
1146 kTopDarjeelingPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 47, /**< spi_device_tpm_header_not_empty */
1147 kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 48, /**< spi_device_tpm_rdfifo_cmd_end */
1148 kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoDrop = 49, /**< spi_device_tpm_rdfifo_drop */
1149 kTopDarjeelingPlicIrqIdI2c0FmtThreshold = 50, /**< i2c0_fmt_threshold */
1150 kTopDarjeelingPlicIrqIdI2c0RxThreshold = 51, /**< i2c0_rx_threshold */
1151 kTopDarjeelingPlicIrqIdI2c0AcqThreshold = 52, /**< i2c0_acq_threshold */
1152 kTopDarjeelingPlicIrqIdI2c0RxOverflow = 53, /**< i2c0_rx_overflow */
1153 kTopDarjeelingPlicIrqIdI2c0ControllerHalt = 54, /**< i2c0_controller_halt */
1154 kTopDarjeelingPlicIrqIdI2c0SclInterference = 55, /**< i2c0_scl_interference */
1155 kTopDarjeelingPlicIrqIdI2c0SdaInterference = 56, /**< i2c0_sda_interference */
1156 kTopDarjeelingPlicIrqIdI2c0StretchTimeout = 57, /**< i2c0_stretch_timeout */
1157 kTopDarjeelingPlicIrqIdI2c0SdaUnstable = 58, /**< i2c0_sda_unstable */
1158 kTopDarjeelingPlicIrqIdI2c0CmdComplete = 59, /**< i2c0_cmd_complete */
1159 kTopDarjeelingPlicIrqIdI2c0TxStretch = 60, /**< i2c0_tx_stretch */
1160 kTopDarjeelingPlicIrqIdI2c0TxThreshold = 61, /**< i2c0_tx_threshold */
1161 kTopDarjeelingPlicIrqIdI2c0AcqStretch = 62, /**< i2c0_acq_stretch */
1162 kTopDarjeelingPlicIrqIdI2c0UnexpStop = 63, /**< i2c0_unexp_stop */
1163 kTopDarjeelingPlicIrqIdI2c0HostTimeout = 64, /**< i2c0_host_timeout */
1164 kTopDarjeelingPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 65, /**< rv_timer_timer_expired_hart0_timer0 */
1165 kTopDarjeelingPlicIrqIdOtpCtrlOtpOperationDone = 66, /**< otp_ctrl_otp_operation_done */
1166 kTopDarjeelingPlicIrqIdOtpCtrlOtpError = 67, /**< otp_ctrl_otp_error */
1167 kTopDarjeelingPlicIrqIdAlertHandlerClassa = 68, /**< alert_handler_classa */
1168 kTopDarjeelingPlicIrqIdAlertHandlerClassb = 69, /**< alert_handler_classb */
1169 kTopDarjeelingPlicIrqIdAlertHandlerClassc = 70, /**< alert_handler_classc */
1170 kTopDarjeelingPlicIrqIdAlertHandlerClassd = 71, /**< alert_handler_classd */
1171 kTopDarjeelingPlicIrqIdSpiHost0Error = 72, /**< spi_host0_error */
1172 kTopDarjeelingPlicIrqIdSpiHost0SpiEvent = 73, /**< spi_host0_spi_event */
1173 kTopDarjeelingPlicIrqIdPwrmgrAonWakeup = 74, /**< pwrmgr_aon_wakeup */
1174 kTopDarjeelingPlicIrqIdAonTimerAonWkupTimerExpired = 75, /**< aon_timer_aon_wkup_timer_expired */
1175 kTopDarjeelingPlicIrqIdAonTimerAonWdogTimerBark = 76, /**< aon_timer_aon_wdog_timer_bark */
1176 kTopDarjeelingPlicIrqIdSocProxyExternal0 = 77, /**< soc_proxy_external 0 */
1177 kTopDarjeelingPlicIrqIdSocProxyExternal1 = 78, /**< soc_proxy_external 1 */
1178 kTopDarjeelingPlicIrqIdSocProxyExternal2 = 79, /**< soc_proxy_external 2 */
1179 kTopDarjeelingPlicIrqIdSocProxyExternal3 = 80, /**< soc_proxy_external 3 */
1180 kTopDarjeelingPlicIrqIdSocProxyExternal4 = 81, /**< soc_proxy_external 4 */
1181 kTopDarjeelingPlicIrqIdSocProxyExternal5 = 82, /**< soc_proxy_external 5 */
1182 kTopDarjeelingPlicIrqIdSocProxyExternal6 = 83, /**< soc_proxy_external 6 */
1183 kTopDarjeelingPlicIrqIdSocProxyExternal7 = 84, /**< soc_proxy_external 7 */
1184 kTopDarjeelingPlicIrqIdSocProxyExternal8 = 85, /**< soc_proxy_external 8 */
1185 kTopDarjeelingPlicIrqIdSocProxyExternal9 = 86, /**< soc_proxy_external 9 */
1186 kTopDarjeelingPlicIrqIdSocProxyExternal10 = 87, /**< soc_proxy_external 10 */
1187 kTopDarjeelingPlicIrqIdSocProxyExternal11 = 88, /**< soc_proxy_external 11 */
1188 kTopDarjeelingPlicIrqIdSocProxyExternal12 = 89, /**< soc_proxy_external 12 */
1189 kTopDarjeelingPlicIrqIdSocProxyExternal13 = 90, /**< soc_proxy_external 13 */
1190 kTopDarjeelingPlicIrqIdSocProxyExternal14 = 91, /**< soc_proxy_external 14 */
1191 kTopDarjeelingPlicIrqIdSocProxyExternal15 = 92, /**< soc_proxy_external 15 */
1192 kTopDarjeelingPlicIrqIdSocProxyExternal16 = 93, /**< soc_proxy_external 16 */
1193 kTopDarjeelingPlicIrqIdSocProxyExternal17 = 94, /**< soc_proxy_external 17 */
1194 kTopDarjeelingPlicIrqIdSocProxyExternal18 = 95, /**< soc_proxy_external 18 */
1195 kTopDarjeelingPlicIrqIdSocProxyExternal19 = 96, /**< soc_proxy_external 19 */
1196 kTopDarjeelingPlicIrqIdSocProxyExternal20 = 97, /**< soc_proxy_external 20 */
1197 kTopDarjeelingPlicIrqIdSocProxyExternal21 = 98, /**< soc_proxy_external 21 */
1198 kTopDarjeelingPlicIrqIdSocProxyExternal22 = 99, /**< soc_proxy_external 22 */
1199 kTopDarjeelingPlicIrqIdSocProxyExternal23 = 100, /**< soc_proxy_external 23 */
1200 kTopDarjeelingPlicIrqIdSocProxyExternal24 = 101, /**< soc_proxy_external 24 */
1201 kTopDarjeelingPlicIrqIdSocProxyExternal25 = 102, /**< soc_proxy_external 25 */
1202 kTopDarjeelingPlicIrqIdSocProxyExternal26 = 103, /**< soc_proxy_external 26 */
1203 kTopDarjeelingPlicIrqIdSocProxyExternal27 = 104, /**< soc_proxy_external 27 */
1204 kTopDarjeelingPlicIrqIdSocProxyExternal28 = 105, /**< soc_proxy_external 28 */
1205 kTopDarjeelingPlicIrqIdSocProxyExternal29 = 106, /**< soc_proxy_external 29 */
1206 kTopDarjeelingPlicIrqIdSocProxyExternal30 = 107, /**< soc_proxy_external 30 */
1207 kTopDarjeelingPlicIrqIdSocProxyExternal31 = 108, /**< soc_proxy_external 31 */
1208 kTopDarjeelingPlicIrqIdHmacHmacDone = 109, /**< hmac_hmac_done */
1209 kTopDarjeelingPlicIrqIdHmacFifoEmpty = 110, /**< hmac_fifo_empty */
1210 kTopDarjeelingPlicIrqIdHmacHmacErr = 111, /**< hmac_hmac_err */
1211 kTopDarjeelingPlicIrqIdKmacKmacDone = 112, /**< kmac_kmac_done */
1212 kTopDarjeelingPlicIrqIdKmacFifoEmpty = 113, /**< kmac_fifo_empty */
1213 kTopDarjeelingPlicIrqIdKmacKmacErr = 114, /**< kmac_kmac_err */
1214 kTopDarjeelingPlicIrqIdOtbnDone = 115, /**< otbn_done */
1215 kTopDarjeelingPlicIrqIdKeymgrDpeOpDone = 116, /**< keymgr_dpe_op_done */
1216 kTopDarjeelingPlicIrqIdCsrngCsCmdReqDone = 117, /**< csrng_cs_cmd_req_done */
1217 kTopDarjeelingPlicIrqIdCsrngCsEntropyReq = 118, /**< csrng_cs_entropy_req */
1218 kTopDarjeelingPlicIrqIdCsrngCsHwInstExc = 119, /**< csrng_cs_hw_inst_exc */
1219 kTopDarjeelingPlicIrqIdCsrngCsFatalErr = 120, /**< csrng_cs_fatal_err */
1220 kTopDarjeelingPlicIrqIdEntropySrcEsEntropyValid = 121, /**< entropy_src_es_entropy_valid */
1221 kTopDarjeelingPlicIrqIdEntropySrcEsHealthTestFailed = 122, /**< entropy_src_es_health_test_failed */
1222 kTopDarjeelingPlicIrqIdEntropySrcEsObserveFifoReady = 123, /**< entropy_src_es_observe_fifo_ready */
1223 kTopDarjeelingPlicIrqIdEntropySrcEsFatalErr = 124, /**< entropy_src_es_fatal_err */
1224 kTopDarjeelingPlicIrqIdEdn0EdnCmdReqDone = 125, /**< edn0_edn_cmd_req_done */
1225 kTopDarjeelingPlicIrqIdEdn0EdnFatalErr = 126, /**< edn0_edn_fatal_err */
1226 kTopDarjeelingPlicIrqIdEdn1EdnCmdReqDone = 127, /**< edn1_edn_cmd_req_done */
1227 kTopDarjeelingPlicIrqIdEdn1EdnFatalErr = 128, /**< edn1_edn_fatal_err */
1228 kTopDarjeelingPlicIrqIdDmaDmaDone = 129, /**< dma_dma_done */
1229 kTopDarjeelingPlicIrqIdDmaDmaChunkDone = 130, /**< dma_dma_chunk_done */
1230 kTopDarjeelingPlicIrqIdDmaDmaError = 131, /**< dma_dma_error */
1231 kTopDarjeelingPlicIrqIdMbx0MbxReady = 132, /**< mbx0_mbx_ready */
1232 kTopDarjeelingPlicIrqIdMbx0MbxAbort = 133, /**< mbx0_mbx_abort */
1233 kTopDarjeelingPlicIrqIdMbx0MbxError = 134, /**< mbx0_mbx_error */
1234 kTopDarjeelingPlicIrqIdMbx1MbxReady = 135, /**< mbx1_mbx_ready */
1235 kTopDarjeelingPlicIrqIdMbx1MbxAbort = 136, /**< mbx1_mbx_abort */
1236 kTopDarjeelingPlicIrqIdMbx1MbxError = 137, /**< mbx1_mbx_error */
1237 kTopDarjeelingPlicIrqIdMbx2MbxReady = 138, /**< mbx2_mbx_ready */
1238 kTopDarjeelingPlicIrqIdMbx2MbxAbort = 139, /**< mbx2_mbx_abort */
1239 kTopDarjeelingPlicIrqIdMbx2MbxError = 140, /**< mbx2_mbx_error */
1240 kTopDarjeelingPlicIrqIdMbx3MbxReady = 141, /**< mbx3_mbx_ready */
1241 kTopDarjeelingPlicIrqIdMbx3MbxAbort = 142, /**< mbx3_mbx_abort */
1242 kTopDarjeelingPlicIrqIdMbx3MbxError = 143, /**< mbx3_mbx_error */
1243 kTopDarjeelingPlicIrqIdMbx4MbxReady = 144, /**< mbx4_mbx_ready */
1244 kTopDarjeelingPlicIrqIdMbx4MbxAbort = 145, /**< mbx4_mbx_abort */
1245 kTopDarjeelingPlicIrqIdMbx4MbxError = 146, /**< mbx4_mbx_error */
1246 kTopDarjeelingPlicIrqIdMbx5MbxReady = 147, /**< mbx5_mbx_ready */
1247 kTopDarjeelingPlicIrqIdMbx5MbxAbort = 148, /**< mbx5_mbx_abort */
1248 kTopDarjeelingPlicIrqIdMbx5MbxError = 149, /**< mbx5_mbx_error */
1249 kTopDarjeelingPlicIrqIdMbx6MbxReady = 150, /**< mbx6_mbx_ready */
1250 kTopDarjeelingPlicIrqIdMbx6MbxAbort = 151, /**< mbx6_mbx_abort */
1251 kTopDarjeelingPlicIrqIdMbx6MbxError = 152, /**< mbx6_mbx_error */
1252 kTopDarjeelingPlicIrqIdMbxJtagMbxReady = 153, /**< mbx_jtag_mbx_ready */
1253 kTopDarjeelingPlicIrqIdMbxJtagMbxAbort = 154, /**< mbx_jtag_mbx_abort */
1254 kTopDarjeelingPlicIrqIdMbxJtagMbxError = 155, /**< mbx_jtag_mbx_error */
1255 kTopDarjeelingPlicIrqIdMbxPcie0MbxReady = 156, /**< mbx_pcie0_mbx_ready */
1256 kTopDarjeelingPlicIrqIdMbxPcie0MbxAbort = 157, /**< mbx_pcie0_mbx_abort */
1257 kTopDarjeelingPlicIrqIdMbxPcie0MbxError = 158, /**< mbx_pcie0_mbx_error */
1258 kTopDarjeelingPlicIrqIdMbxPcie1MbxReady = 159, /**< mbx_pcie1_mbx_ready */
1259 kTopDarjeelingPlicIrqIdMbxPcie1MbxAbort = 160, /**< mbx_pcie1_mbx_abort */
1260 kTopDarjeelingPlicIrqIdMbxPcie1MbxError = 161, /**< mbx_pcie1_mbx_error */
1261 kTopDarjeelingPlicIrqIdRaclCtrlRaclError = 162, /**< racl_ctrl_racl_error */
1262 kTopDarjeelingPlicIrqIdAcRangeCheckDenyCntReached = 163, /**< ac_range_check_deny_cnt_reached */
1263 kTopDarjeelingPlicIrqIdLast = 163, /**< \internal The Last Valid Interrupt ID. */
1265
1266/**
1267 * PLIC Interrupt Source to Peripheral Map
1268 *
1269 * This array is a mapping from `top_darjeeling_plic_irq_id_t` to
1270 * `top_darjeeling_plic_peripheral_t`.
1271 */
1273 top_darjeeling_plic_interrupt_for_peripheral[164];
1274
1275/**
1276 * PLIC Interrupt Target.
1277 *
1278 * Enumeration used to determine which set of IE, CC, threshold registers to
1279 * access for a given interrupt target.
1280 */
1282 kTopDarjeelingPlicTargetIbex0 = 0, /**< Ibex Core 0 */
1283 kTopDarjeelingPlicTargetLast = 0, /**< \internal Final PLIC target */
1285
1286
1287/**
1288 * Alert Handler Source Peripheral.
1289 *
1290 * Enumeration used to determine which peripheral asserted the corresponding
1291 * alert.
1292 */
1294 kTopDarjeelingAlertPeripheralExternal = 0, /**< External Peripheral */
1309 kTopDarjeelingAlertPeripheralSramCtrlRetAon = 15, /**< sram_ctrl_ret_aon */
1340 kTopDarjeelingAlertPeripheralLast = 45, /**< \internal Final Alert peripheral */
1342
1343/**
1344 * Alert Handler Alert Source.
1345 *
1346 * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
1347 * the same peripheral are guaranteed to be consecutive.
1348 */
1350 kTopDarjeelingAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */
1351 kTopDarjeelingAlertIdGpioFatalFault = 1, /**< gpio_fatal_fault */
1352 kTopDarjeelingAlertIdSpiDeviceFatalFault = 2, /**< spi_device_fatal_fault */
1353 kTopDarjeelingAlertIdI2c0FatalFault = 3, /**< i2c0_fatal_fault */
1354 kTopDarjeelingAlertIdRvTimerFatalFault = 4, /**< rv_timer_fatal_fault */
1355 kTopDarjeelingAlertIdOtpCtrlFatalMacroError = 5, /**< otp_ctrl_fatal_macro_error */
1356 kTopDarjeelingAlertIdOtpCtrlFatalCheckError = 6, /**< otp_ctrl_fatal_check_error */
1357 kTopDarjeelingAlertIdOtpCtrlFatalBusIntegError = 7, /**< otp_ctrl_fatal_bus_integ_error */
1358 kTopDarjeelingAlertIdOtpCtrlFatalPrimOtpAlert = 8, /**< otp_ctrl_fatal_prim_otp_alert */
1359 kTopDarjeelingAlertIdOtpCtrlRecovPrimOtpAlert = 9, /**< otp_ctrl_recov_prim_otp_alert */
1360 kTopDarjeelingAlertIdLcCtrlFatalProgError = 10, /**< lc_ctrl_fatal_prog_error */
1361 kTopDarjeelingAlertIdLcCtrlFatalStateError = 11, /**< lc_ctrl_fatal_state_error */
1362 kTopDarjeelingAlertIdLcCtrlFatalBusIntegError = 12, /**< lc_ctrl_fatal_bus_integ_error */
1363 kTopDarjeelingAlertIdSpiHost0FatalFault = 13, /**< spi_host0_fatal_fault */
1364 kTopDarjeelingAlertIdPwrmgrAonFatalFault = 14, /**< pwrmgr_aon_fatal_fault */
1365 kTopDarjeelingAlertIdRstmgrAonFatalFault = 15, /**< rstmgr_aon_fatal_fault */
1366 kTopDarjeelingAlertIdRstmgrAonFatalCnstyFault = 16, /**< rstmgr_aon_fatal_cnsty_fault */
1367 kTopDarjeelingAlertIdClkmgrAonRecovFault = 17, /**< clkmgr_aon_recov_fault */
1368 kTopDarjeelingAlertIdClkmgrAonFatalFault = 18, /**< clkmgr_aon_fatal_fault */
1369 kTopDarjeelingAlertIdPinmuxAonFatalFault = 19, /**< pinmux_aon_fatal_fault */
1370 kTopDarjeelingAlertIdAonTimerAonFatalFault = 20, /**< aon_timer_aon_fatal_fault */
1371 kTopDarjeelingAlertIdSocProxyFatalAlertIntg = 21, /**< soc_proxy_fatal_alert_intg */
1372 kTopDarjeelingAlertIdSocProxyFatalAlertExternal0 = 22, /**< soc_proxy_fatal_alert_external_0 */
1373 kTopDarjeelingAlertIdSocProxyFatalAlertExternal1 = 23, /**< soc_proxy_fatal_alert_external_1 */
1374 kTopDarjeelingAlertIdSocProxyFatalAlertExternal2 = 24, /**< soc_proxy_fatal_alert_external_2 */
1375 kTopDarjeelingAlertIdSocProxyFatalAlertExternal3 = 25, /**< soc_proxy_fatal_alert_external_3 */
1376 kTopDarjeelingAlertIdSocProxyFatalAlertExternal4 = 26, /**< soc_proxy_fatal_alert_external_4 */
1377 kTopDarjeelingAlertIdSocProxyFatalAlertExternal5 = 27, /**< soc_proxy_fatal_alert_external_5 */
1378 kTopDarjeelingAlertIdSocProxyFatalAlertExternal6 = 28, /**< soc_proxy_fatal_alert_external_6 */
1379 kTopDarjeelingAlertIdSocProxyFatalAlertExternal7 = 29, /**< soc_proxy_fatal_alert_external_7 */
1380 kTopDarjeelingAlertIdSocProxyFatalAlertExternal8 = 30, /**< soc_proxy_fatal_alert_external_8 */
1381 kTopDarjeelingAlertIdSocProxyFatalAlertExternal9 = 31, /**< soc_proxy_fatal_alert_external_9 */
1382 kTopDarjeelingAlertIdSocProxyFatalAlertExternal10 = 32, /**< soc_proxy_fatal_alert_external_10 */
1383 kTopDarjeelingAlertIdSocProxyFatalAlertExternal11 = 33, /**< soc_proxy_fatal_alert_external_11 */
1384 kTopDarjeelingAlertIdSocProxyFatalAlertExternal12 = 34, /**< soc_proxy_fatal_alert_external_12 */
1385 kTopDarjeelingAlertIdSocProxyFatalAlertExternal13 = 35, /**< soc_proxy_fatal_alert_external_13 */
1386 kTopDarjeelingAlertIdSocProxyFatalAlertExternal14 = 36, /**< soc_proxy_fatal_alert_external_14 */
1387 kTopDarjeelingAlertIdSocProxyFatalAlertExternal15 = 37, /**< soc_proxy_fatal_alert_external_15 */
1388 kTopDarjeelingAlertIdSocProxyFatalAlertExternal16 = 38, /**< soc_proxy_fatal_alert_external_16 */
1389 kTopDarjeelingAlertIdSocProxyFatalAlertExternal17 = 39, /**< soc_proxy_fatal_alert_external_17 */
1390 kTopDarjeelingAlertIdSocProxyFatalAlertExternal18 = 40, /**< soc_proxy_fatal_alert_external_18 */
1391 kTopDarjeelingAlertIdSocProxyFatalAlertExternal19 = 41, /**< soc_proxy_fatal_alert_external_19 */
1392 kTopDarjeelingAlertIdSocProxyFatalAlertExternal20 = 42, /**< soc_proxy_fatal_alert_external_20 */
1393 kTopDarjeelingAlertIdSocProxyFatalAlertExternal21 = 43, /**< soc_proxy_fatal_alert_external_21 */
1394 kTopDarjeelingAlertIdSocProxyFatalAlertExternal22 = 44, /**< soc_proxy_fatal_alert_external_22 */
1395 kTopDarjeelingAlertIdSocProxyFatalAlertExternal23 = 45, /**< soc_proxy_fatal_alert_external_23 */
1396 kTopDarjeelingAlertIdSocProxyRecovAlertExternal0 = 46, /**< soc_proxy_recov_alert_external_0 */
1397 kTopDarjeelingAlertIdSocProxyRecovAlertExternal1 = 47, /**< soc_proxy_recov_alert_external_1 */
1398 kTopDarjeelingAlertIdSocProxyRecovAlertExternal2 = 48, /**< soc_proxy_recov_alert_external_2 */
1399 kTopDarjeelingAlertIdSocProxyRecovAlertExternal3 = 49, /**< soc_proxy_recov_alert_external_3 */
1400 kTopDarjeelingAlertIdSramCtrlRetAonFatalError = 50, /**< sram_ctrl_ret_aon_fatal_error */
1401 kTopDarjeelingAlertIdRvDmFatalFault = 51, /**< rv_dm_fatal_fault */
1402 kTopDarjeelingAlertIdRvPlicFatalFault = 52, /**< rv_plic_fatal_fault */
1403 kTopDarjeelingAlertIdAesRecovCtrlUpdateErr = 53, /**< aes_recov_ctrl_update_err */
1404 kTopDarjeelingAlertIdAesFatalFault = 54, /**< aes_fatal_fault */
1405 kTopDarjeelingAlertIdHmacFatalFault = 55, /**< hmac_fatal_fault */
1406 kTopDarjeelingAlertIdKmacRecovOperationErr = 56, /**< kmac_recov_operation_err */
1407 kTopDarjeelingAlertIdKmacFatalFaultErr = 57, /**< kmac_fatal_fault_err */
1408 kTopDarjeelingAlertIdOtbnFatal = 58, /**< otbn_fatal */
1409 kTopDarjeelingAlertIdOtbnRecov = 59, /**< otbn_recov */
1410 kTopDarjeelingAlertIdKeymgrDpeRecovOperationErr = 60, /**< keymgr_dpe_recov_operation_err */
1411 kTopDarjeelingAlertIdKeymgrDpeFatalFaultErr = 61, /**< keymgr_dpe_fatal_fault_err */
1412 kTopDarjeelingAlertIdCsrngRecovAlert = 62, /**< csrng_recov_alert */
1413 kTopDarjeelingAlertIdCsrngFatalAlert = 63, /**< csrng_fatal_alert */
1414 kTopDarjeelingAlertIdEntropySrcRecovAlert = 64, /**< entropy_src_recov_alert */
1415 kTopDarjeelingAlertIdEntropySrcFatalAlert = 65, /**< entropy_src_fatal_alert */
1416 kTopDarjeelingAlertIdEdn0RecovAlert = 66, /**< edn0_recov_alert */
1417 kTopDarjeelingAlertIdEdn0FatalAlert = 67, /**< edn0_fatal_alert */
1418 kTopDarjeelingAlertIdEdn1RecovAlert = 68, /**< edn1_recov_alert */
1419 kTopDarjeelingAlertIdEdn1FatalAlert = 69, /**< edn1_fatal_alert */
1420 kTopDarjeelingAlertIdSramCtrlMainFatalError = 70, /**< sram_ctrl_main_fatal_error */
1421 kTopDarjeelingAlertIdSramCtrlMboxFatalError = 71, /**< sram_ctrl_mbox_fatal_error */
1422 kTopDarjeelingAlertIdRomCtrl0Fatal = 72, /**< rom_ctrl0_fatal */
1423 kTopDarjeelingAlertIdRomCtrl1Fatal = 73, /**< rom_ctrl1_fatal */
1424 kTopDarjeelingAlertIdDmaFatalFault = 74, /**< dma_fatal_fault */
1425 kTopDarjeelingAlertIdMbx0FatalFault = 75, /**< mbx0_fatal_fault */
1426 kTopDarjeelingAlertIdMbx0RecovFault = 76, /**< mbx0_recov_fault */
1427 kTopDarjeelingAlertIdMbx1FatalFault = 77, /**< mbx1_fatal_fault */
1428 kTopDarjeelingAlertIdMbx1RecovFault = 78, /**< mbx1_recov_fault */
1429 kTopDarjeelingAlertIdMbx2FatalFault = 79, /**< mbx2_fatal_fault */
1430 kTopDarjeelingAlertIdMbx2RecovFault = 80, /**< mbx2_recov_fault */
1431 kTopDarjeelingAlertIdMbx3FatalFault = 81, /**< mbx3_fatal_fault */
1432 kTopDarjeelingAlertIdMbx3RecovFault = 82, /**< mbx3_recov_fault */
1433 kTopDarjeelingAlertIdMbx4FatalFault = 83, /**< mbx4_fatal_fault */
1434 kTopDarjeelingAlertIdMbx4RecovFault = 84, /**< mbx4_recov_fault */
1435 kTopDarjeelingAlertIdMbx5FatalFault = 85, /**< mbx5_fatal_fault */
1436 kTopDarjeelingAlertIdMbx5RecovFault = 86, /**< mbx5_recov_fault */
1437 kTopDarjeelingAlertIdMbx6FatalFault = 87, /**< mbx6_fatal_fault */
1438 kTopDarjeelingAlertIdMbx6RecovFault = 88, /**< mbx6_recov_fault */
1439 kTopDarjeelingAlertIdMbxJtagFatalFault = 89, /**< mbx_jtag_fatal_fault */
1440 kTopDarjeelingAlertIdMbxJtagRecovFault = 90, /**< mbx_jtag_recov_fault */
1441 kTopDarjeelingAlertIdMbxPcie0FatalFault = 91, /**< mbx_pcie0_fatal_fault */
1442 kTopDarjeelingAlertIdMbxPcie0RecovFault = 92, /**< mbx_pcie0_recov_fault */
1443 kTopDarjeelingAlertIdMbxPcie1FatalFault = 93, /**< mbx_pcie1_fatal_fault */
1444 kTopDarjeelingAlertIdMbxPcie1RecovFault = 94, /**< mbx_pcie1_recov_fault */
1445 kTopDarjeelingAlertIdSocDbgCtrlFatalFault = 95, /**< soc_dbg_ctrl_fatal_fault */
1446 kTopDarjeelingAlertIdSocDbgCtrlRecovCtrlUpdateErr = 96, /**< soc_dbg_ctrl_recov_ctrl_update_err */
1447 kTopDarjeelingAlertIdRaclCtrlFatalFault = 97, /**< racl_ctrl_fatal_fault */
1448 kTopDarjeelingAlertIdRaclCtrlRecovCtrlUpdateErr = 98, /**< racl_ctrl_recov_ctrl_update_err */
1449 kTopDarjeelingAlertIdAcRangeCheckRecovCtrlUpdateErr = 99, /**< ac_range_check_recov_ctrl_update_err */
1450 kTopDarjeelingAlertIdAcRangeCheckFatalFault = 100, /**< ac_range_check_fatal_fault */
1451 kTopDarjeelingAlertIdRvCoreIbexFatalSwErr = 101, /**< rv_core_ibex_fatal_sw_err */
1452 kTopDarjeelingAlertIdRvCoreIbexRecovSwErr = 102, /**< rv_core_ibex_recov_sw_err */
1453 kTopDarjeelingAlertIdRvCoreIbexFatalHwErr = 103, /**< rv_core_ibex_fatal_hw_err */
1454 kTopDarjeelingAlertIdRvCoreIbexRecovHwErr = 104, /**< rv_core_ibex_recov_hw_err */
1455 kTopDarjeelingAlertIdLast = 104, /**< \internal The Last Valid Alert ID. */
1457
1458/**
1459 * Alert Handler Alert Source to Peripheral Map
1460 *
1461 * This array is a mapping from `top_darjeeling_alert_id_t` to
1462 * `top_darjeeling_alert_peripheral_t`.
1463 */
1465 top_darjeeling_alert_for_peripheral[105];
1466
1467#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
1468
1469// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
1470// 0 and 1 are tied to value 0 and 1
1471#define NUM_MIO_PADS 12
1472#define NUM_DIO_PADS 73
1473
1474#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
1475
1476/**
1477 * Pinmux Peripheral Input.
1478 */
1484 kTopDarjeelingPinmuxPeripheralInLast = 3, /**< \internal Last valid peripheral input */
1486
1487/**
1488 * Pinmux MIO Input Selector.
1489 */
1491 kTopDarjeelingPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
1492 kTopDarjeelingPinmuxInselConstantOne = 1, /**< Tie constantly to one */
1493 kTopDarjeelingPinmuxInselMio0 = 2, /**< MIO Pad 0 */
1494 kTopDarjeelingPinmuxInselMio1 = 3, /**< MIO Pad 1 */
1495 kTopDarjeelingPinmuxInselMio2 = 4, /**< MIO Pad 2 */
1496 kTopDarjeelingPinmuxInselMio3 = 5, /**< MIO Pad 3 */
1497 kTopDarjeelingPinmuxInselMio4 = 6, /**< MIO Pad 4 */
1498 kTopDarjeelingPinmuxInselMio5 = 7, /**< MIO Pad 5 */
1499 kTopDarjeelingPinmuxInselMio6 = 8, /**< MIO Pad 6 */
1500 kTopDarjeelingPinmuxInselMio7 = 9, /**< MIO Pad 7 */
1501 kTopDarjeelingPinmuxInselMio8 = 10, /**< MIO Pad 8 */
1502 kTopDarjeelingPinmuxInselMio9 = 11, /**< MIO Pad 9 */
1503 kTopDarjeelingPinmuxInselMio10 = 12, /**< MIO Pad 10 */
1504 kTopDarjeelingPinmuxInselMio11 = 13, /**< MIO Pad 11 */
1505 kTopDarjeelingPinmuxInselLast = 13, /**< \internal Last valid insel value */
1507
1508/**
1509 * Pinmux MIO Output.
1510 */
1512 kTopDarjeelingPinmuxMioOutMio0 = 0, /**< MIO Pad 0 */
1513 kTopDarjeelingPinmuxMioOutMio1 = 1, /**< MIO Pad 1 */
1514 kTopDarjeelingPinmuxMioOutMio2 = 2, /**< MIO Pad 2 */
1515 kTopDarjeelingPinmuxMioOutMio3 = 3, /**< MIO Pad 3 */
1516 kTopDarjeelingPinmuxMioOutMio4 = 4, /**< MIO Pad 4 */
1517 kTopDarjeelingPinmuxMioOutMio5 = 5, /**< MIO Pad 5 */
1518 kTopDarjeelingPinmuxMioOutMio6 = 6, /**< MIO Pad 6 */
1519 kTopDarjeelingPinmuxMioOutMio7 = 7, /**< MIO Pad 7 */
1520 kTopDarjeelingPinmuxMioOutMio8 = 8, /**< MIO Pad 8 */
1521 kTopDarjeelingPinmuxMioOutMio9 = 9, /**< MIO Pad 9 */
1522 kTopDarjeelingPinmuxMioOutMio10 = 10, /**< MIO Pad 10 */
1523 kTopDarjeelingPinmuxMioOutMio11 = 11, /**< MIO Pad 11 */
1524 kTopDarjeelingPinmuxMioOutLast = 11, /**< \internal Last valid mio output */
1526
1527/**
1528 * Pinmux Peripheral Output Selector.
1529 */
1531 kTopDarjeelingPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
1532 kTopDarjeelingPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
1533 kTopDarjeelingPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
1534 kTopDarjeelingPinmuxOutselSocProxySocGpo12 = 3, /**< Peripheral Output 0 */
1535 kTopDarjeelingPinmuxOutselSocProxySocGpo13 = 4, /**< Peripheral Output 1 */
1536 kTopDarjeelingPinmuxOutselSocProxySocGpo14 = 5, /**< Peripheral Output 2 */
1537 kTopDarjeelingPinmuxOutselSocProxySocGpo15 = 6, /**< Peripheral Output 3 */
1538 kTopDarjeelingPinmuxOutselOtpMacroTest0 = 7, /**< Peripheral Output 4 */
1539 kTopDarjeelingPinmuxOutselLast = 7, /**< \internal Last valid outsel value */
1541
1542/**
1543 * Dedicated Pad Selects
1544 */
1546 kTopDarjeelingDirectPadsSpiHost0Sd0 = 0, /**< */
1547 kTopDarjeelingDirectPadsSpiHost0Sd1 = 1, /**< */
1548 kTopDarjeelingDirectPadsSpiHost0Sd2 = 2, /**< */
1549 kTopDarjeelingDirectPadsSpiHost0Sd3 = 3, /**< */
1550 kTopDarjeelingDirectPadsSpiDeviceSd0 = 4, /**< */
1551 kTopDarjeelingDirectPadsSpiDeviceSd1 = 5, /**< */
1552 kTopDarjeelingDirectPadsSpiDeviceSd2 = 6, /**< */
1553 kTopDarjeelingDirectPadsSpiDeviceSd3 = 7, /**< */
1554 kTopDarjeelingDirectPadsI2c0Scl = 8, /**< */
1555 kTopDarjeelingDirectPadsI2c0Sda = 9, /**< */
1556 kTopDarjeelingDirectPadsGpioGpio0 = 10, /**< */
1557 kTopDarjeelingDirectPadsGpioGpio1 = 11, /**< */
1558 kTopDarjeelingDirectPadsGpioGpio2 = 12, /**< */
1559 kTopDarjeelingDirectPadsGpioGpio3 = 13, /**< */
1560 kTopDarjeelingDirectPadsGpioGpio4 = 14, /**< */
1561 kTopDarjeelingDirectPadsGpioGpio5 = 15, /**< */
1562 kTopDarjeelingDirectPadsGpioGpio6 = 16, /**< */
1563 kTopDarjeelingDirectPadsGpioGpio7 = 17, /**< */
1564 kTopDarjeelingDirectPadsGpioGpio8 = 18, /**< */
1565 kTopDarjeelingDirectPadsGpioGpio9 = 19, /**< */
1566 kTopDarjeelingDirectPadsGpioGpio10 = 20, /**< */
1567 kTopDarjeelingDirectPadsGpioGpio11 = 21, /**< */
1568 kTopDarjeelingDirectPadsGpioGpio12 = 22, /**< */
1569 kTopDarjeelingDirectPadsGpioGpio13 = 23, /**< */
1570 kTopDarjeelingDirectPadsGpioGpio14 = 24, /**< */
1571 kTopDarjeelingDirectPadsGpioGpio15 = 25, /**< */
1572 kTopDarjeelingDirectPadsGpioGpio16 = 26, /**< */
1573 kTopDarjeelingDirectPadsGpioGpio17 = 27, /**< */
1574 kTopDarjeelingDirectPadsGpioGpio18 = 28, /**< */
1575 kTopDarjeelingDirectPadsGpioGpio19 = 29, /**< */
1576 kTopDarjeelingDirectPadsGpioGpio20 = 30, /**< */
1577 kTopDarjeelingDirectPadsGpioGpio21 = 31, /**< */
1578 kTopDarjeelingDirectPadsGpioGpio22 = 32, /**< */
1579 kTopDarjeelingDirectPadsGpioGpio23 = 33, /**< */
1580 kTopDarjeelingDirectPadsGpioGpio24 = 34, /**< */
1581 kTopDarjeelingDirectPadsGpioGpio25 = 35, /**< */
1582 kTopDarjeelingDirectPadsGpioGpio26 = 36, /**< */
1583 kTopDarjeelingDirectPadsGpioGpio27 = 37, /**< */
1584 kTopDarjeelingDirectPadsGpioGpio28 = 38, /**< */
1585 kTopDarjeelingDirectPadsGpioGpio29 = 39, /**< */
1586 kTopDarjeelingDirectPadsGpioGpio30 = 40, /**< */
1587 kTopDarjeelingDirectPadsGpioGpio31 = 41, /**< */
1588 kTopDarjeelingDirectPadsSpiDeviceSck = 42, /**< */
1589 kTopDarjeelingDirectPadsSpiDeviceCsb = 43, /**< */
1590 kTopDarjeelingDirectPadsSpiDeviceTpmCsb = 44, /**< */
1591 kTopDarjeelingDirectPadsUart0Rx = 45, /**< */
1592 kTopDarjeelingDirectPadsSocProxySocGpi0 = 46, /**< */
1593 kTopDarjeelingDirectPadsSocProxySocGpi1 = 47, /**< */
1594 kTopDarjeelingDirectPadsSocProxySocGpi2 = 48, /**< */
1595 kTopDarjeelingDirectPadsSocProxySocGpi3 = 49, /**< */
1596 kTopDarjeelingDirectPadsSocProxySocGpi4 = 50, /**< */
1597 kTopDarjeelingDirectPadsSocProxySocGpi5 = 51, /**< */
1598 kTopDarjeelingDirectPadsSocProxySocGpi6 = 52, /**< */
1599 kTopDarjeelingDirectPadsSocProxySocGpi7 = 53, /**< */
1600 kTopDarjeelingDirectPadsSocProxySocGpi8 = 54, /**< */
1601 kTopDarjeelingDirectPadsSocProxySocGpi9 = 55, /**< */
1602 kTopDarjeelingDirectPadsSocProxySocGpi10 = 56, /**< */
1603 kTopDarjeelingDirectPadsSocProxySocGpi11 = 57, /**< */
1604 kTopDarjeelingDirectPadsSpiHost0Sck = 58, /**< */
1605 kTopDarjeelingDirectPadsSpiHost0Csb = 59, /**< */
1606 kTopDarjeelingDirectPadsUart0Tx = 60, /**< */
1607 kTopDarjeelingDirectPadsSocProxySocGpo0 = 61, /**< */
1608 kTopDarjeelingDirectPadsSocProxySocGpo1 = 62, /**< */
1609 kTopDarjeelingDirectPadsSocProxySocGpo2 = 63, /**< */
1610 kTopDarjeelingDirectPadsSocProxySocGpo3 = 64, /**< */
1611 kTopDarjeelingDirectPadsSocProxySocGpo4 = 65, /**< */
1612 kTopDarjeelingDirectPadsSocProxySocGpo5 = 66, /**< */
1613 kTopDarjeelingDirectPadsSocProxySocGpo6 = 67, /**< */
1614 kTopDarjeelingDirectPadsSocProxySocGpo7 = 68, /**< */
1615 kTopDarjeelingDirectPadsSocProxySocGpo8 = 69, /**< */
1616 kTopDarjeelingDirectPadsSocProxySocGpo9 = 70, /**< */
1617 kTopDarjeelingDirectPadsSocProxySocGpo10 = 71, /**< */
1618 kTopDarjeelingDirectPadsSocProxySocGpo11 = 72, /**< */
1619 kTopDarjeelingDirectPadsLast = 72, /**< \internal Last valid direct pad */
1621
1622/**
1623 * Muxed Pad Selects
1624 */
1626 kTopDarjeelingMuxedPadsMio0 = 0, /**< */
1627 kTopDarjeelingMuxedPadsMio1 = 1, /**< */
1628 kTopDarjeelingMuxedPadsMio2 = 2, /**< */
1629 kTopDarjeelingMuxedPadsMio3 = 3, /**< */
1630 kTopDarjeelingMuxedPadsMio4 = 4, /**< */
1631 kTopDarjeelingMuxedPadsMio5 = 5, /**< */
1632 kTopDarjeelingMuxedPadsMio6 = 6, /**< */
1633 kTopDarjeelingMuxedPadsMio7 = 7, /**< */
1634 kTopDarjeelingMuxedPadsMio8 = 8, /**< */
1635 kTopDarjeelingMuxedPadsMio9 = 9, /**< */
1636 kTopDarjeelingMuxedPadsMio10 = 10, /**< */
1637 kTopDarjeelingMuxedPadsMio11 = 11, /**< */
1638 kTopDarjeelingMuxedPadsLast = 11, /**< \internal Last valid muxed pad */
1640
1641/**
1642 * Power Manager Wakeup Signals
1643 */
1645 kTopDarjeelingPowerManagerWakeUpsPinmuxAonPinWkupReq = 0, /**< */
1646 kTopDarjeelingPowerManagerWakeUpsAonTimerAonWkupReq = 1, /**< */
1647 kTopDarjeelingPowerManagerWakeUpsSocProxyWkupInternalReq = 2, /**< */
1648 kTopDarjeelingPowerManagerWakeUpsSocProxyWkupExternalReq = 3, /**< */
1649 kTopDarjeelingPowerManagerWakeUpsLast = 3, /**< \internal Last valid pwrmgr wakeup signal */
1651
1652/**
1653 * Reset Manager Software Controlled Resets
1654 */
1656 kTopDarjeelingResetManagerSwResetsSpiDevice = 0, /**< */
1657 kTopDarjeelingResetManagerSwResetsSpiHost0 = 1, /**< */
1658 kTopDarjeelingResetManagerSwResetsI2c0 = 2, /**< */
1659 kTopDarjeelingResetManagerSwResetsLast = 2, /**< \internal Last valid rstmgr software reset request */
1661
1662/**
1663 * Power Manager Reset Request Signals
1664 */
1666 kTopDarjeelingPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 0, /**< */
1667 kTopDarjeelingPowerManagerResetRequestsSocProxyRstReqExternal = 1, /**< */
1668 kTopDarjeelingPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */
1670
1671/**
1672 * Clock Manager Software-Controlled ("Gated") Clocks.
1673 *
1674 * The Software has full control over these clocks.
1675 */
1677 kTopDarjeelingGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
1678 kTopDarjeelingGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
1679 kTopDarjeelingGateableClocksLast = 1, /**< \internal Last Valid Gateable Clock */
1681
1682/**
1683 * Clock Manager Software-Hinted Clocks.
1684 *
1685 * The Software has partial control over these clocks. It can ask them to stop,
1686 * but the clock manager is in control of whether the clock actually is stopped.
1687 */
1689 kTopDarjeelingHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */
1690 kTopDarjeelingHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */
1691 kTopDarjeelingHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */
1692 kTopDarjeelingHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */
1693 kTopDarjeelingHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */
1695
1696/**
1697 * MMIO Region
1698 *
1699 * MMIO region excludes any memory that is separate from the module
1700 * configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but
1701 * retention SRAM or spi_device are included.
1702 */
1703#define TOP_DARJEELING_MMIO_BASE_ADDR 0x21100000u
1704#define TOP_DARJEELING_MMIO_SIZE_BYTES 0xF501000u
1705
1706// Header Extern Guard
1707#ifdef __cplusplus
1708} // extern "C"
1709#endif
1710
1711#endif // OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_