rram_ctrl_regs.h File Reference

Generated register defines for rram_ctrl. More...

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Macros
#define	RRAM_CTRL_PARAM_EXEC_EN   2724870391
#define	RRAM_CTRL_PARAM_NUM_REGIONS   10
#define	RRAM_CTRL_PARAM_NUM_INFO_PAGES   8
#define	RRAM_CTRL_PARAM_NUM_EMUL_INFO_REGIONS   2
#define	RRAM_CTRL_PARAM_NUM_EMUL_INFO_SUBREGIONS   24
#define	RRAM_CTRL_PARAM_NUM_DATA_PAGES   4096
#define	RRAM_CTRL_PARAM_NUM_OTP_PAGES   6
#define	RRAM_CTRL_PARAM_WORDS_PER_PAGE   32
#define	RRAM_CTRL_PARAM_BYTES_PER_WORD   16
#define	RRAM_CTRL_PARAM_BYTES_PER_PAGE   512
#define	RRAM_CTRL_PARAM_NUM_ALERTS   5
#define	RRAM_CTRL_PARAM_REG_WIDTH   32
#define	RRAM_CTRL_INTR_COMMON_WR_EMPTY_BIT   0
#define	RRAM_CTRL_INTR_COMMON_WR_LVL_BIT   1
#define	RRAM_CTRL_INTR_COMMON_RD_FULL_BIT   2
#define	RRAM_CTRL_INTR_COMMON_RD_LVL_BIT   3
#define	RRAM_CTRL_INTR_COMMON_OP_DONE_BIT   4
#define	RRAM_CTRL_INTR_COMMON_CORR1_ERR_BIT   5
#define	RRAM_CTRL_INTR_COMMON_CORR2_ERR_BIT   6
#define	RRAM_CTRL_INTR_STATE_REG_OFFSET   0x0
#define	RRAM_CTRL_INTR_STATE_REG_RESVAL   0x3u
#define	RRAM_CTRL_INTR_STATE_WR_EMPTY_BIT   0
#define	RRAM_CTRL_INTR_STATE_WR_LVL_BIT   1
#define	RRAM_CTRL_INTR_STATE_RD_FULL_BIT   2
#define	RRAM_CTRL_INTR_STATE_RD_LVL_BIT   3
#define	RRAM_CTRL_INTR_STATE_OP_DONE_BIT   4
#define	RRAM_CTRL_INTR_STATE_CORR1_ERR_BIT   5
#define	RRAM_CTRL_INTR_STATE_CORR2_ERR_BIT   6
#define	RRAM_CTRL_INTR_ENABLE_REG_OFFSET   0x4
#define	RRAM_CTRL_INTR_ENABLE_REG_RESVAL   0x0u
#define	RRAM_CTRL_INTR_ENABLE_WR_EMPTY_BIT   0
#define	RRAM_CTRL_INTR_ENABLE_WR_LVL_BIT   1
#define	RRAM_CTRL_INTR_ENABLE_RD_FULL_BIT   2
#define	RRAM_CTRL_INTR_ENABLE_RD_LVL_BIT   3
#define	RRAM_CTRL_INTR_ENABLE_OP_DONE_BIT   4
#define	RRAM_CTRL_INTR_ENABLE_CORR1_ERR_BIT   5
#define	RRAM_CTRL_INTR_ENABLE_CORR2_ERR_BIT   6
#define	RRAM_CTRL_INTR_TEST_REG_OFFSET   0x8
#define	RRAM_CTRL_INTR_TEST_REG_RESVAL   0x0u
#define	RRAM_CTRL_INTR_TEST_WR_EMPTY_BIT   0
#define	RRAM_CTRL_INTR_TEST_WR_LVL_BIT   1
#define	RRAM_CTRL_INTR_TEST_RD_FULL_BIT   2
#define	RRAM_CTRL_INTR_TEST_RD_LVL_BIT   3
#define	RRAM_CTRL_INTR_TEST_OP_DONE_BIT   4
#define	RRAM_CTRL_INTR_TEST_CORR1_ERR_BIT   5
#define	RRAM_CTRL_INTR_TEST_CORR2_ERR_BIT   6
#define	RRAM_CTRL_ALERT_TEST_REG_OFFSET   0xc
#define	RRAM_CTRL_ALERT_TEST_REG_RESVAL   0x80000000u
#define	RRAM_CTRL_ALERT_TEST_RECOV_ERR_BIT   0
#define	RRAM_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT   1
#define	RRAM_CTRL_ALERT_TEST_FATAL_ERR_BIT   2
#define	RRAM_CTRL_ALERT_TEST_FATAL_MACRO_ERR_BIT   3
#define	RRAM_CTRL_ALERT_TEST_RECOV_MACRO_ERR_BIT   4
#define	RRAM_CTRL_ALERT_TEST_REGWEN_BIT   31
#define	RRAM_CTRL_DIS_REG_OFFSET   0x10
#define	RRAM_CTRL_DIS_REG_RESVAL   0x99u
#define	RRAM_CTRL_DIS_SW_DIS_MASK   0xfu
#define	RRAM_CTRL_DIS_SW_DIS_OFFSET   0
#define	RRAM_CTRL_DIS_SW_DIS_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DIS_SW_DIS_MASK, .index = RRAM_CTRL_DIS_SW_DIS_OFFSET })
#define	RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_MASK   0xfu
#define	RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_OFFSET   4
#define	RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_MASK, .index = RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_OFFSET })
#define	RRAM_CTRL_EXEC_REG_OFFSET   0x14
#define	RRAM_CTRL_EXEC_REG_RESVAL   0x0u
#define	RRAM_CTRL_INIT_REG_OFFSET   0x18
#define	RRAM_CTRL_INIT_REG_RESVAL   0x0u
#define	RRAM_CTRL_INIT_VAL_BIT   0
#define	RRAM_CTRL_CTRL_REGWEN_REG_OFFSET   0x1c
#define	RRAM_CTRL_CTRL_REGWEN_REG_RESVAL   0x1u
#define	RRAM_CTRL_CTRL_REGWEN_EN_BIT   0
#define	RRAM_CTRL_CONTROL_REG_OFFSET   0x20
#define	RRAM_CTRL_CONTROL_REG_RESVAL   0x0u
#define	RRAM_CTRL_CONTROL_START_BIT   0
#define	RRAM_CTRL_CONTROL_OP_MASK   0x3u
#define	RRAM_CTRL_CONTROL_OP_OFFSET   4
#define	RRAM_CTRL_CONTROL_OP_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CONTROL_OP_MASK, .index = RRAM_CTRL_CONTROL_OP_OFFSET })
#define	RRAM_CTRL_CONTROL_OP_VALUE_READ   0x0
#define	RRAM_CTRL_CONTROL_OP_VALUE_WRITE   0x1
#define	RRAM_CTRL_CONTROL_OP_VALUE_REWRITE   0x2
#define	RRAM_CTRL_CONTROL_PARTITION_BIT   8
#define	RRAM_CTRL_CONTROL_NUM_MASK   0x3ffu
#define	RRAM_CTRL_CONTROL_NUM_OFFSET   16
#define	RRAM_CTRL_CONTROL_NUM_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CONTROL_NUM_MASK, .index = RRAM_CTRL_CONTROL_NUM_OFFSET })
#define	RRAM_CTRL_ADDR_REG_OFFSET   0x24
#define	RRAM_CTRL_ADDR_REG_RESVAL   0x0u
#define	RRAM_CTRL_ADDR_START_MASK   0x1fffffu
#define	RRAM_CTRL_ADDR_START_OFFSET   0
#define	RRAM_CTRL_ADDR_START_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_ADDR_START_MASK, .index = RRAM_CTRL_ADDR_START_OFFSET })
#define	RRAM_CTRL_REGION_CFG_REGWEN_REGION_FIELD_WIDTH   1
#define	RRAM_CTRL_REGION_CFG_REGWEN_MULTIREG_COUNT   10
#define	RRAM_CTRL_REGION_CFG_REGWEN_0_REG_OFFSET   0x28
#define	RRAM_CTRL_REGION_CFG_REGWEN_0_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT   0
#define	RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_LOCKED   0x0
#define	RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_ENABLED   0x1
#define	RRAM_CTRL_REGION_CFG_REGWEN_1_REG_OFFSET   0x2c
#define	RRAM_CTRL_REGION_CFG_REGWEN_1_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_1_REGION_1_BIT   0
#define	RRAM_CTRL_REGION_CFG_REGWEN_2_REG_OFFSET   0x30
#define	RRAM_CTRL_REGION_CFG_REGWEN_2_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_2_REGION_2_BIT   0
#define	RRAM_CTRL_REGION_CFG_REGWEN_3_REG_OFFSET   0x34
#define	RRAM_CTRL_REGION_CFG_REGWEN_3_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_3_REGION_3_BIT   0
#define	RRAM_CTRL_REGION_CFG_REGWEN_4_REG_OFFSET   0x38
#define	RRAM_CTRL_REGION_CFG_REGWEN_4_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_4_REGION_4_BIT   0
#define	RRAM_CTRL_REGION_CFG_REGWEN_5_REG_OFFSET   0x3c
#define	RRAM_CTRL_REGION_CFG_REGWEN_5_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_5_REGION_5_BIT   0
#define	RRAM_CTRL_REGION_CFG_REGWEN_6_REG_OFFSET   0x40
#define	RRAM_CTRL_REGION_CFG_REGWEN_6_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_6_REGION_6_BIT   0
#define	RRAM_CTRL_REGION_CFG_REGWEN_7_REG_OFFSET   0x44
#define	RRAM_CTRL_REGION_CFG_REGWEN_7_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_7_REGION_7_BIT   0
#define	RRAM_CTRL_REGION_CFG_REGWEN_8_REG_OFFSET   0x48
#define	RRAM_CTRL_REGION_CFG_REGWEN_8_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_8_REGION_8_BIT   0
#define	RRAM_CTRL_REGION_CFG_REGWEN_9_REG_OFFSET   0x4c
#define	RRAM_CTRL_REGION_CFG_REGWEN_9_REG_RESVAL   0x1u
#define	RRAM_CTRL_REGION_CFG_REGWEN_9_REGION_9_BIT   0
#define	RRAM_CTRL_MP_REGION_CFG_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_MP_REGION_CFG_RD_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_MP_REGION_CFG_WR_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_MP_REGION_CFG_SCRAMBLE_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_MP_REGION_CFG_ECC_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_MP_REGION_CFG_MULTIREG_COUNT   10
#define	RRAM_CTRL_MP_REGION_CFG_0_REG_OFFSET   0x50
#define	RRAM_CTRL_MP_REGION_CFG_0_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_0_EN_0_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_0_EN_0_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_0_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_EN_0_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_1_REG_OFFSET   0x54
#define	RRAM_CTRL_MP_REGION_CFG_1_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_1_EN_1_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_1_EN_1_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_1_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_EN_1_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_2_REG_OFFSET   0x58
#define	RRAM_CTRL_MP_REGION_CFG_2_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_2_EN_2_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_2_EN_2_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_2_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_EN_2_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_3_REG_OFFSET   0x5c
#define	RRAM_CTRL_MP_REGION_CFG_3_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_3_EN_3_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_3_EN_3_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_3_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_EN_3_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_4_REG_OFFSET   0x60
#define	RRAM_CTRL_MP_REGION_CFG_4_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_4_EN_4_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_4_EN_4_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_4_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_EN_4_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_5_REG_OFFSET   0x64
#define	RRAM_CTRL_MP_REGION_CFG_5_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_5_EN_5_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_5_EN_5_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_5_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_EN_5_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_6_REG_OFFSET   0x68
#define	RRAM_CTRL_MP_REGION_CFG_6_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_6_EN_6_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_6_EN_6_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_6_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_EN_6_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_7_REG_OFFSET   0x6c
#define	RRAM_CTRL_MP_REGION_CFG_7_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_7_EN_7_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_7_EN_7_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_7_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_EN_7_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_8_REG_OFFSET   0x70
#define	RRAM_CTRL_MP_REGION_CFG_8_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_8_EN_8_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_8_EN_8_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_8_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_EN_8_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_9_REG_OFFSET   0x74
#define	RRAM_CTRL_MP_REGION_CFG_9_REG_RESVAL   0x99999u
#define	RRAM_CTRL_MP_REGION_CFG_9_EN_9_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_9_EN_9_OFFSET   0
#define	RRAM_CTRL_MP_REGION_CFG_9_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_EN_9_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_OFFSET   4
#define	RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_OFFSET   8
#define	RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_OFFSET   12
#define	RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_OFFSET })
#define	RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_MASK   0xfu
#define	RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_OFFSET   16
#define	RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_OFFSET })
#define	RRAM_CTRL_MP_REGION_BASE_FIELD_WIDTH   12
#define	RRAM_CTRL_MP_REGION_SIZE_FIELD_WIDTH   12
#define	RRAM_CTRL_MP_REGION_MULTIREG_COUNT   10
#define	RRAM_CTRL_MP_REGION_0_REG_OFFSET   0x78
#define	RRAM_CTRL_MP_REGION_0_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_0_BASE_0_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_0_BASE_0_OFFSET   0
#define	RRAM_CTRL_MP_REGION_0_BASE_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_0_BASE_0_MASK, .index = RRAM_CTRL_MP_REGION_0_BASE_0_OFFSET })
#define	RRAM_CTRL_MP_REGION_0_SIZE_0_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_0_SIZE_0_OFFSET   12
#define	RRAM_CTRL_MP_REGION_0_SIZE_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_0_SIZE_0_MASK, .index = RRAM_CTRL_MP_REGION_0_SIZE_0_OFFSET })
#define	RRAM_CTRL_MP_REGION_1_REG_OFFSET   0x7c
#define	RRAM_CTRL_MP_REGION_1_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_1_BASE_1_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_1_BASE_1_OFFSET   0
#define	RRAM_CTRL_MP_REGION_1_BASE_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_1_BASE_1_MASK, .index = RRAM_CTRL_MP_REGION_1_BASE_1_OFFSET })
#define	RRAM_CTRL_MP_REGION_1_SIZE_1_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_1_SIZE_1_OFFSET   12
#define	RRAM_CTRL_MP_REGION_1_SIZE_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_1_SIZE_1_MASK, .index = RRAM_CTRL_MP_REGION_1_SIZE_1_OFFSET })
#define	RRAM_CTRL_MP_REGION_2_REG_OFFSET   0x80
#define	RRAM_CTRL_MP_REGION_2_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_2_BASE_2_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_2_BASE_2_OFFSET   0
#define	RRAM_CTRL_MP_REGION_2_BASE_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_2_BASE_2_MASK, .index = RRAM_CTRL_MP_REGION_2_BASE_2_OFFSET })
#define	RRAM_CTRL_MP_REGION_2_SIZE_2_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_2_SIZE_2_OFFSET   12
#define	RRAM_CTRL_MP_REGION_2_SIZE_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_2_SIZE_2_MASK, .index = RRAM_CTRL_MP_REGION_2_SIZE_2_OFFSET })
#define	RRAM_CTRL_MP_REGION_3_REG_OFFSET   0x84
#define	RRAM_CTRL_MP_REGION_3_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_3_BASE_3_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_3_BASE_3_OFFSET   0
#define	RRAM_CTRL_MP_REGION_3_BASE_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_3_BASE_3_MASK, .index = RRAM_CTRL_MP_REGION_3_BASE_3_OFFSET })
#define	RRAM_CTRL_MP_REGION_3_SIZE_3_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_3_SIZE_3_OFFSET   12
#define	RRAM_CTRL_MP_REGION_3_SIZE_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_3_SIZE_3_MASK, .index = RRAM_CTRL_MP_REGION_3_SIZE_3_OFFSET })
#define	RRAM_CTRL_MP_REGION_4_REG_OFFSET   0x88
#define	RRAM_CTRL_MP_REGION_4_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_4_BASE_4_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_4_BASE_4_OFFSET   0
#define	RRAM_CTRL_MP_REGION_4_BASE_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_4_BASE_4_MASK, .index = RRAM_CTRL_MP_REGION_4_BASE_4_OFFSET })
#define	RRAM_CTRL_MP_REGION_4_SIZE_4_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_4_SIZE_4_OFFSET   12
#define	RRAM_CTRL_MP_REGION_4_SIZE_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_4_SIZE_4_MASK, .index = RRAM_CTRL_MP_REGION_4_SIZE_4_OFFSET })
#define	RRAM_CTRL_MP_REGION_5_REG_OFFSET   0x8c
#define	RRAM_CTRL_MP_REGION_5_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_5_BASE_5_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_5_BASE_5_OFFSET   0
#define	RRAM_CTRL_MP_REGION_5_BASE_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_5_BASE_5_MASK, .index = RRAM_CTRL_MP_REGION_5_BASE_5_OFFSET })
#define	RRAM_CTRL_MP_REGION_5_SIZE_5_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_5_SIZE_5_OFFSET   12
#define	RRAM_CTRL_MP_REGION_5_SIZE_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_5_SIZE_5_MASK, .index = RRAM_CTRL_MP_REGION_5_SIZE_5_OFFSET })
#define	RRAM_CTRL_MP_REGION_6_REG_OFFSET   0x90
#define	RRAM_CTRL_MP_REGION_6_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_6_BASE_6_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_6_BASE_6_OFFSET   0
#define	RRAM_CTRL_MP_REGION_6_BASE_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_6_BASE_6_MASK, .index = RRAM_CTRL_MP_REGION_6_BASE_6_OFFSET })
#define	RRAM_CTRL_MP_REGION_6_SIZE_6_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_6_SIZE_6_OFFSET   12
#define	RRAM_CTRL_MP_REGION_6_SIZE_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_6_SIZE_6_MASK, .index = RRAM_CTRL_MP_REGION_6_SIZE_6_OFFSET })
#define	RRAM_CTRL_MP_REGION_7_REG_OFFSET   0x94
#define	RRAM_CTRL_MP_REGION_7_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_7_BASE_7_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_7_BASE_7_OFFSET   0
#define	RRAM_CTRL_MP_REGION_7_BASE_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_7_BASE_7_MASK, .index = RRAM_CTRL_MP_REGION_7_BASE_7_OFFSET })
#define	RRAM_CTRL_MP_REGION_7_SIZE_7_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_7_SIZE_7_OFFSET   12
#define	RRAM_CTRL_MP_REGION_7_SIZE_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_7_SIZE_7_MASK, .index = RRAM_CTRL_MP_REGION_7_SIZE_7_OFFSET })
#define	RRAM_CTRL_MP_REGION_8_REG_OFFSET   0x98
#define	RRAM_CTRL_MP_REGION_8_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_8_BASE_8_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_8_BASE_8_OFFSET   0
#define	RRAM_CTRL_MP_REGION_8_BASE_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_8_BASE_8_MASK, .index = RRAM_CTRL_MP_REGION_8_BASE_8_OFFSET })
#define	RRAM_CTRL_MP_REGION_8_SIZE_8_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_8_SIZE_8_OFFSET   12
#define	RRAM_CTRL_MP_REGION_8_SIZE_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_8_SIZE_8_MASK, .index = RRAM_CTRL_MP_REGION_8_SIZE_8_OFFSET })
#define	RRAM_CTRL_MP_REGION_9_REG_OFFSET   0x9c
#define	RRAM_CTRL_MP_REGION_9_REG_RESVAL   0x0u
#define	RRAM_CTRL_MP_REGION_9_BASE_9_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_9_BASE_9_OFFSET   0
#define	RRAM_CTRL_MP_REGION_9_BASE_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_9_BASE_9_MASK, .index = RRAM_CTRL_MP_REGION_9_BASE_9_OFFSET })
#define	RRAM_CTRL_MP_REGION_9_SIZE_9_MASK   0xfffu
#define	RRAM_CTRL_MP_REGION_9_SIZE_9_OFFSET   12
#define	RRAM_CTRL_MP_REGION_9_SIZE_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_9_SIZE_9_MASK, .index = RRAM_CTRL_MP_REGION_9_SIZE_9_OFFSET })
#define	RRAM_CTRL_DEFAULT_REGION_REG_OFFSET   0xa0
#define	RRAM_CTRL_DEFAULT_REGION_REG_RESVAL   0x9999u
#define	RRAM_CTRL_DEFAULT_REGION_RD_EN_MASK   0xfu
#define	RRAM_CTRL_DEFAULT_REGION_RD_EN_OFFSET   0
#define	RRAM_CTRL_DEFAULT_REGION_RD_EN_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_RD_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_RD_EN_OFFSET })
#define	RRAM_CTRL_DEFAULT_REGION_WR_EN_MASK   0xfu
#define	RRAM_CTRL_DEFAULT_REGION_WR_EN_OFFSET   4
#define	RRAM_CTRL_DEFAULT_REGION_WR_EN_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_WR_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_WR_EN_OFFSET })
#define	RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK   0xfu
#define	RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET   8
#define	RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET })
#define	RRAM_CTRL_DEFAULT_REGION_ECC_EN_MASK   0xfu
#define	RRAM_CTRL_DEFAULT_REGION_ECC_EN_OFFSET   12
#define	RRAM_CTRL_DEFAULT_REGION_ECC_EN_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_ECC_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_ECC_EN_OFFSET })
#define	RRAM_CTRL_INFO_REGWEN_REGION_FIELD_WIDTH   1
#define	RRAM_CTRL_INFO_REGWEN_MULTIREG_COUNT   8
#define	RRAM_CTRL_INFO_REGWEN_0_REG_OFFSET   0xa4
#define	RRAM_CTRL_INFO_REGWEN_0_REG_RESVAL   0x1u
#define	RRAM_CTRL_INFO_REGWEN_0_REGION_0_BIT   0
#define	RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_LOCKED   0x0
#define	RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_ENABLED   0x1
#define	RRAM_CTRL_INFO_REGWEN_1_REG_OFFSET   0xa8
#define	RRAM_CTRL_INFO_REGWEN_1_REG_RESVAL   0x1u
#define	RRAM_CTRL_INFO_REGWEN_1_REGION_1_BIT   0
#define	RRAM_CTRL_INFO_REGWEN_2_REG_OFFSET   0xac
#define	RRAM_CTRL_INFO_REGWEN_2_REG_RESVAL   0x1u
#define	RRAM_CTRL_INFO_REGWEN_2_REGION_2_BIT   0
#define	RRAM_CTRL_INFO_REGWEN_3_REG_OFFSET   0xb0
#define	RRAM_CTRL_INFO_REGWEN_3_REG_RESVAL   0x1u
#define	RRAM_CTRL_INFO_REGWEN_3_REGION_3_BIT   0
#define	RRAM_CTRL_INFO_REGWEN_4_REG_OFFSET   0xb4
#define	RRAM_CTRL_INFO_REGWEN_4_REG_RESVAL   0x1u
#define	RRAM_CTRL_INFO_REGWEN_4_REGION_4_BIT   0
#define	RRAM_CTRL_INFO_REGWEN_5_REG_OFFSET   0xb8
#define	RRAM_CTRL_INFO_REGWEN_5_REG_RESVAL   0x1u
#define	RRAM_CTRL_INFO_REGWEN_5_REGION_5_BIT   0
#define	RRAM_CTRL_INFO_REGWEN_6_REG_OFFSET   0xbc
#define	RRAM_CTRL_INFO_REGWEN_6_REG_RESVAL   0x1u
#define	RRAM_CTRL_INFO_REGWEN_6_REGION_6_BIT   0
#define	RRAM_CTRL_INFO_REGWEN_7_REG_OFFSET   0xc0
#define	RRAM_CTRL_INFO_REGWEN_7_REG_RESVAL   0x1u
#define	RRAM_CTRL_INFO_REGWEN_7_REGION_7_BIT   0
#define	RRAM_CTRL_INFO_PAGE_CFG_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_INFO_PAGE_CFG_RD_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_INFO_PAGE_CFG_WR_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_INFO_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_INFO_PAGE_CFG_ECC_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_INFO_PAGE_CFG_MULTIREG_COUNT   8
#define	RRAM_CTRL_INFO_PAGE_CFG_0_REG_OFFSET   0xc4
#define	RRAM_CTRL_INFO_PAGE_CFG_0_REG_RESVAL   0x99999u
#define	RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_OFFSET   0
#define	RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_OFFSET   4
#define	RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_OFFSET   8
#define	RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET   12
#define	RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_OFFSET   16
#define	RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_1_REG_OFFSET   0xc8
#define	RRAM_CTRL_INFO_PAGE_CFG_1_REG_RESVAL   0x99999u
#define	RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_OFFSET   0
#define	RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_OFFSET   4
#define	RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_OFFSET   8
#define	RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET   12
#define	RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_OFFSET   16
#define	RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_2_REG_OFFSET   0xcc
#define	RRAM_CTRL_INFO_PAGE_CFG_2_REG_RESVAL   0x99999u
#define	RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_OFFSET   0
#define	RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_OFFSET   4
#define	RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_OFFSET   8
#define	RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET   12
#define	RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_OFFSET   16
#define	RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_3_REG_OFFSET   0xd0
#define	RRAM_CTRL_INFO_PAGE_CFG_3_REG_RESVAL   0x99999u
#define	RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_OFFSET   0
#define	RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_OFFSET   4
#define	RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_OFFSET   8
#define	RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET   12
#define	RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_OFFSET   16
#define	RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_4_REG_OFFSET   0xd4
#define	RRAM_CTRL_INFO_PAGE_CFG_4_REG_RESVAL   0x99999u
#define	RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_OFFSET   0
#define	RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_OFFSET   4
#define	RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_OFFSET   8
#define	RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET   12
#define	RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_OFFSET   16
#define	RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_5_REG_OFFSET   0xd8
#define	RRAM_CTRL_INFO_PAGE_CFG_5_REG_RESVAL   0x99999u
#define	RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_OFFSET   0
#define	RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_OFFSET   4
#define	RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_OFFSET   8
#define	RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET   12
#define	RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_OFFSET   16
#define	RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_6_REG_OFFSET   0xdc
#define	RRAM_CTRL_INFO_PAGE_CFG_6_REG_RESVAL   0x99999u
#define	RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_OFFSET   0
#define	RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_OFFSET   4
#define	RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_OFFSET   8
#define	RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET   12
#define	RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_OFFSET   16
#define	RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_7_REG_OFFSET   0xe0
#define	RRAM_CTRL_INFO_PAGE_CFG_7_REG_RESVAL   0x99999u
#define	RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_OFFSET   0
#define	RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_OFFSET   4
#define	RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_OFFSET   8
#define	RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET   12
#define	RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define	RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_MASK   0xfu
#define	RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_OFFSET   16
#define	RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_REGWEN_REGION_FIELD_WIDTH   1
#define	RRAM_CTRL_EMUL_INFO_REGWEN_MULTIREG_COUNT   2
#define	RRAM_CTRL_EMUL_INFO_REGWEN_0_REG_OFFSET   0xe4
#define	RRAM_CTRL_EMUL_INFO_REGWEN_0_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_BIT   0
#define	RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_VALUE_REGION_LOCKED   0x0
#define	RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_VALUE_REGION_ENABLED   0x1
#define	RRAM_CTRL_EMUL_INFO_REGWEN_1_REG_OFFSET   0xe8
#define	RRAM_CTRL_EMUL_INFO_REGWEN_1_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_REGWEN_1_REGION_1_BIT   0
#define	RRAM_CTRL_EMUL_INFO_REGION_BASE_FIELD_WIDTH   12
#define	RRAM_CTRL_EMUL_INFO_REGION_SIZE_FIELD_WIDTH   12
#define	RRAM_CTRL_EMUL_INFO_REGION_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_EMUL_INFO_REGION_MULTIREG_COUNT   2
#define	RRAM_CTRL_EMUL_INFO_REGION_0_REG_OFFSET   0xec
#define	RRAM_CTRL_EMUL_INFO_REGION_0_REG_RESVAL   0x9000000u
#define	RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_MASK   0xfffu
#define	RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_MASK   0xfffu
#define	RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_OFFSET   24
#define	RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_REGION_1_REG_OFFSET   0xf0
#define	RRAM_CTRL_EMUL_INFO_REGION_1_REG_RESVAL   0x9000000u
#define	RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_MASK   0xfffu
#define	RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_MASK   0xfffu
#define	RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_OFFSET   24
#define	RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_REGION_FIELD_WIDTH   1
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_MULTIREG_COUNT   24
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REG_OFFSET   0xf4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_VALUE_SUBREGION_LOCKED    0x0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_VALUE_SUBREGION_ENABLED    0x1
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REG_OFFSET   0xf8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REGION_1_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REG_OFFSET   0xfc
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REGION_2_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REG_OFFSET   0x100
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REGION_3_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REG_OFFSET   0x104
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REGION_4_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REG_OFFSET   0x108
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REGION_5_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REG_OFFSET   0x10c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REGION_6_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REG_OFFSET   0x110
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REGION_7_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REG_OFFSET   0x114
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REGION_8_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REG_OFFSET   0x118
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REGION_9_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REG_OFFSET   0x11c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REGION_10_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REG_OFFSET   0x120
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REGION_11_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REG_OFFSET   0x124
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REGION_12_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REG_OFFSET   0x128
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REGION_13_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REG_OFFSET   0x12c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REGION_14_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REG_OFFSET   0x130
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REGION_15_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REG_OFFSET   0x134
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REGION_16_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REG_OFFSET   0x138
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REGION_17_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REG_OFFSET   0x13c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REGION_18_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REG_OFFSET   0x140
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REGION_19_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REG_OFFSET   0x144
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REGION_20_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REG_OFFSET   0x148
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REGION_21_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REG_OFFSET   0x14c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REGION_22_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REG_OFFSET   0x150
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REGION_23_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_TOP_FIELD_WIDTH   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_MULTIREG_COUNT   24
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_0_REG_OFFSET   0x154
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_0_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_1_REG_OFFSET   0x158
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_1_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_2_REG_OFFSET   0x15c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_2_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_3_REG_OFFSET   0x160
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_3_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_4_REG_OFFSET   0x164
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_4_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_5_REG_OFFSET   0x168
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_5_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_6_REG_OFFSET   0x16c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_6_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_7_REG_OFFSET   0x170
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_7_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_8_REG_OFFSET   0x174
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_8_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_9_REG_OFFSET   0x178
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_9_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_10_REG_OFFSET   0x17c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_10_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_11_REG_OFFSET   0x180
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_11_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_12_REG_OFFSET   0x184
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_12_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_13_REG_OFFSET   0x188
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_13_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_14_REG_OFFSET   0x18c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_14_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_15_REG_OFFSET   0x190
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_15_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_16_REG_OFFSET   0x194
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_16_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_17_REG_OFFSET   0x198
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_17_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_18_REG_OFFSET   0x19c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_18_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_19_REG_OFFSET   0x1a0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_19_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_20_REG_OFFSET   0x1a4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_20_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_21_REG_OFFSET   0x1a8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_21_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_22_REG_OFFSET   0x1ac
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_22_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_23_REG_OFFSET   0x1b0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_23_REG_RESVAL   0x0u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_MASK   0xffu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_OFFSET   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_REGION_FIELD_WIDTH   1
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_MULTIREG_COUNT   24
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REG_OFFSET   0x1b4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_VALUE_SUBREGION_LOCKED    0x0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_VALUE_SUBREGION_ENABLED    0x1
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REG_OFFSET   0x1b8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REGION_1_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REG_OFFSET   0x1bc
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REGION_2_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REG_OFFSET   0x1c0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REGION_3_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REG_OFFSET   0x1c4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REGION_4_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REG_OFFSET   0x1c8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REGION_5_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REG_OFFSET   0x1cc
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REGION_6_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REG_OFFSET   0x1d0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REGION_7_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REG_OFFSET   0x1d4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REGION_8_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REG_OFFSET   0x1d8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REGION_9_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REG_OFFSET   0x1dc
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REGION_10_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REG_OFFSET   0x1e0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REGION_11_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REG_OFFSET   0x1e4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REGION_12_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REG_OFFSET   0x1e8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REGION_13_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REG_OFFSET   0x1ec
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REGION_14_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REG_OFFSET   0x1f0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REGION_15_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REG_OFFSET   0x1f4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REGION_16_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REG_OFFSET   0x1f8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REGION_17_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REG_OFFSET   0x1fc
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REGION_18_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REG_OFFSET   0x200
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REGION_19_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REG_OFFSET   0x204
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REGION_20_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REG_OFFSET   0x208
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REGION_21_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REG_OFFSET   0x20c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REGION_22_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REG_OFFSET   0x210
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REG_RESVAL   0x1u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REGION_23_BIT   0
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_RD_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_WR_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_SCRAMBLE_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_ECC_EN_FIELD_WIDTH   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_MULTIREG_COUNT   24
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_REG_OFFSET   0x214
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_REG_OFFSET   0x218
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_REG_OFFSET   0x21c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_REG_OFFSET   0x220
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_REG_OFFSET   0x224
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_REG_OFFSET   0x228
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_REG_OFFSET   0x22c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_REG_OFFSET   0x230
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_REG_OFFSET   0x234
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_REG_OFFSET   0x238
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_REG_OFFSET   0x23c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_REG_OFFSET   0x240
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_REG_OFFSET   0x244
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_REG_OFFSET   0x248
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_REG_OFFSET   0x24c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_REG_OFFSET   0x250
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_REG_OFFSET   0x254
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_REG_OFFSET   0x258
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_REG_OFFSET   0x25c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_REG_OFFSET   0x260
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_REG_OFFSET   0x264
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_REG_OFFSET   0x268
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_REG_OFFSET   0x26c
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_REG_OFFSET   0x270
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_REG_RESVAL   0x99990u
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_OFFSET   4
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_OFFSET   8
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_OFFSET   12
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_OFFSET })
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_MASK   0xfu
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_OFFSET   16
#define	RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_OFFSET })
#define	RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_OFFSET   0x274
#define	RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_RESVAL   0x99u
#define	RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK   0xfu
#define	RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET   0
#define	RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK, .index = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET })
#define	RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK   0xfu
#define	RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET   4
#define	RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK, .index = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET })
#define	RRAM_CTRL_OP_STATUS_REG_OFFSET   0x278
#define	RRAM_CTRL_OP_STATUS_REG_RESVAL   0x0u
#define	RRAM_CTRL_OP_STATUS_DONE_BIT   0
#define	RRAM_CTRL_OP_STATUS_ERR_BIT   1
#define	RRAM_CTRL_STATUS_REG_OFFSET   0x27c
#define	RRAM_CTRL_STATUS_REG_RESVAL   0xau
#define	RRAM_CTRL_STATUS_RD_FULL_BIT   0
#define	RRAM_CTRL_STATUS_RD_EMPTY_BIT   1
#define	RRAM_CTRL_STATUS_WR_FULL_BIT   2
#define	RRAM_CTRL_STATUS_WR_EMPTY_BIT   3
#define	RRAM_CTRL_STATUS_INIT_DONE_BIT   4
#define	RRAM_CTRL_STATUS_KEYS_VALID_BIT   5
#define	RRAM_CTRL_ERR_CODE_REG_OFFSET   0x280
#define	RRAM_CTRL_ERR_CODE_REG_RESVAL   0x0u
#define	RRAM_CTRL_ERR_CODE_OP_ERR_BIT   0
#define	RRAM_CTRL_ERR_CODE_MP_ERR_BIT   1
#define	RRAM_CTRL_ERR_CODE_RD_ERR_BIT   2
#define	RRAM_CTRL_ERR_CODE_WR_ERR_BIT   3
#define	RRAM_CTRL_STD_FAULT_STATUS_REG_OFFSET   0x284
#define	RRAM_CTRL_STD_FAULT_STATUS_REG_RESVAL   0x0u
#define	RRAM_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT   0
#define	RRAM_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT   1
#define	RRAM_CTRL_STD_FAULT_STATUS_LCMGR_INTG_ERR_BIT   2
#define	RRAM_CTRL_STD_FAULT_STATUS_OTP_ERR_BIT   3
#define	RRAM_CTRL_STD_FAULT_STATUS_OTP_INTG_ERR_BIT   4
#define	RRAM_CTRL_STD_FAULT_STATUS_PHY_WR_INTG_ERR_BIT   5
#define	RRAM_CTRL_STD_FAULT_STATUS_PHY_FIFO_ERR_BIT   6
#define	RRAM_CTRL_STD_FAULT_STATUS_PHY_FSM_ERR_BIT   7
#define	RRAM_CTRL_STD_FAULT_STATUS_PHY_CNT_ERR_BIT   8
#define	RRAM_CTRL_STD_FAULT_STATUS_PHY_ARB_ERR_BIT   9
#define	RRAM_CTRL_STD_FAULT_STATUS_CTRL_FSM_ERR_BIT   10
#define	RRAM_CTRL_STD_FAULT_STATUS_CTRL_CNT_ERR_BIT   11
#define	RRAM_CTRL_STD_FAULT_STATUS_CTRL_FIFO_ERR_BIT   12
#define	RRAM_CTRL_FAULT_STATUS_REG_OFFSET   0x288
#define	RRAM_CTRL_FAULT_STATUS_REG_RESVAL   0x0u
#define	RRAM_CTRL_FAULT_STATUS_LCMGR_OP_ERR_BIT   0
#define	RRAM_CTRL_FAULT_STATUS_LCMGR_MP_ERR_BIT   1
#define	RRAM_CTRL_FAULT_STATUS_LCMGR_RD_ERR_BIT   2
#define	RRAM_CTRL_FAULT_STATUS_LCMGR_WR_ERR_BIT   3
#define	RRAM_CTRL_FAULT_STATUS_OTP_OP_ERR_BIT   4
#define	RRAM_CTRL_FAULT_STATUS_OTP_MP_ERR_BIT   5
#define	RRAM_CTRL_FAULT_STATUS_OTP_RD_ERR_BIT   6
#define	RRAM_CTRL_FAULT_STATUS_OTP_WR_ERR_BIT   7
#define	RRAM_CTRL_FAULT_STATUS_SEED_ERR_BIT   8
#define	RRAM_CTRL_FAULT_STATUS_PHY_RELBL_ERR_BIT   9
#define	RRAM_CTRL_FAULT_STATUS_PHY_RD_INTG_ERR_BIT   10
#define	RRAM_CTRL_FAULT_STATUS_PHY_RD_CTRL_ERR_BIT   11
#define	RRAM_CTRL_FAULT_STATUS_SPURIOUS_DONE_BIT   12
#define	RRAM_CTRL_FAULT_STATUS_HOST_GNT_ERR_BIT   13
#define	RRAM_CTRL_ERR_ADDR_REG_OFFSET   0x28c
#define	RRAM_CTRL_ERR_ADDR_REG_RESVAL   0x0u
#define	RRAM_CTRL_ERR_ADDR_ERR_ADDR_MASK   0x1fffffu
#define	RRAM_CTRL_ERR_ADDR_ERR_ADDR_OFFSET   0
#define	RRAM_CTRL_ERR_ADDR_ERR_ADDR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_ERR_ADDR_ERR_ADDR_MASK, .index = RRAM_CTRL_ERR_ADDR_ERR_ADDR_OFFSET })
#define	RRAM_CTRL_CORR1_ERR_CNT_REG_OFFSET   0x290
#define	RRAM_CTRL_CORR1_ERR_CNT_REG_RESVAL   0x0u
#define	RRAM_CTRL_CORR1_ERR_CNT_VAL_MASK   0xffu
#define	RRAM_CTRL_CORR1_ERR_CNT_VAL_OFFSET   0
#define	RRAM_CTRL_CORR1_ERR_CNT_VAL_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR1_ERR_CNT_VAL_MASK, .index = RRAM_CTRL_CORR1_ERR_CNT_VAL_OFFSET })
#define	RRAM_CTRL_CORR2_ERR_CNT_REG_OFFSET   0x294
#define	RRAM_CTRL_CORR2_ERR_CNT_REG_RESVAL   0x0u
#define	RRAM_CTRL_CORR2_ERR_CNT_VAL_MASK   0xffu
#define	RRAM_CTRL_CORR2_ERR_CNT_VAL_OFFSET   0
#define	RRAM_CTRL_CORR2_ERR_CNT_VAL_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR2_ERR_CNT_VAL_MASK, .index = RRAM_CTRL_CORR2_ERR_CNT_VAL_OFFSET })
#define	RRAM_CTRL_CORR1_ERR_LOC_REG_OFFSET   0x298
#define	RRAM_CTRL_CORR1_ERR_LOC_REG_RESVAL   0x0u
#define	RRAM_CTRL_CORR1_ERR_LOC_ADDR_MASK   0x1fffffu
#define	RRAM_CTRL_CORR1_ERR_LOC_ADDR_OFFSET   0
#define	RRAM_CTRL_CORR1_ERR_LOC_ADDR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR1_ERR_LOC_ADDR_MASK, .index = RRAM_CTRL_CORR1_ERR_LOC_ADDR_OFFSET })
#define	RRAM_CTRL_CORR1_ERR_LOC_PART_BIT   24
#define	RRAM_CTRL_CORR2_ERR_LOC_REG_OFFSET   0x29c
#define	RRAM_CTRL_CORR2_ERR_LOC_REG_RESVAL   0x0u
#define	RRAM_CTRL_CORR2_ERR_LOC_ADDR_MASK   0x1fffffu
#define	RRAM_CTRL_CORR2_ERR_LOC_ADDR_OFFSET   0
#define	RRAM_CTRL_CORR2_ERR_LOC_ADDR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR2_ERR_LOC_ADDR_MASK, .index = RRAM_CTRL_CORR2_ERR_LOC_ADDR_OFFSET })
#define	RRAM_CTRL_CORR2_ERR_LOC_PART_BIT   24
#define	RRAM_CTRL_PHY_STATUS_REG_OFFSET   0x2a0
#define	RRAM_CTRL_PHY_STATUS_REG_RESVAL   0x0u
#define	RRAM_CTRL_PHY_STATUS_WR_BUSY_BIT   0
#define	RRAM_CTRL_PHY_STATUS_INIT_DONE_BIT   1
#define	RRAM_CTRL_SCRATCH_REG_OFFSET   0x2a4
#define	RRAM_CTRL_SCRATCH_REG_RESVAL   0x0u
#define	RRAM_CTRL_FIFO_LVL_REG_OFFSET   0x2a8
#define	RRAM_CTRL_FIFO_LVL_REG_RESVAL   0xf0fu
#define	RRAM_CTRL_FIFO_LVL_WR_MASK   0x1fu
#define	RRAM_CTRL_FIFO_LVL_WR_OFFSET   0
#define	RRAM_CTRL_FIFO_LVL_WR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_FIFO_LVL_WR_MASK, .index = RRAM_CTRL_FIFO_LVL_WR_OFFSET })
#define	RRAM_CTRL_FIFO_LVL_RD_MASK   0x1fu
#define	RRAM_CTRL_FIFO_LVL_RD_OFFSET   8
#define	RRAM_CTRL_FIFO_LVL_RD_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_FIFO_LVL_RD_MASK, .index = RRAM_CTRL_FIFO_LVL_RD_OFFSET })
#define	RRAM_CTRL_FIFO_CLR_REG_OFFSET   0x2ac
#define	RRAM_CTRL_FIFO_CLR_REG_RESVAL   0x0u
#define	RRAM_CTRL_FIFO_CLR_WR_BIT   0
#define	RRAM_CTRL_FIFO_CLR_RD_BIT   1
#define	RRAM_CTRL_CURR_FIFO_LVL_REG_OFFSET   0x2b0
#define	RRAM_CTRL_CURR_FIFO_LVL_REG_RESVAL   0x0u
#define	RRAM_CTRL_CURR_FIFO_LVL_WR_MASK   0x1fu
#define	RRAM_CTRL_CURR_FIFO_LVL_WR_OFFSET   0
#define	RRAM_CTRL_CURR_FIFO_LVL_WR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CURR_FIFO_LVL_WR_MASK, .index = RRAM_CTRL_CURR_FIFO_LVL_WR_OFFSET })
#define	RRAM_CTRL_CURR_FIFO_LVL_RD_MASK   0x1fu
#define	RRAM_CTRL_CURR_FIFO_LVL_RD_OFFSET   8
#define	RRAM_CTRL_CURR_FIFO_LVL_RD_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CURR_FIFO_LVL_RD_MASK, .index = RRAM_CTRL_CURR_FIFO_LVL_RD_OFFSET })
#define	RRAM_CTRL_WR_FIFO_REG_OFFSET   0x2b4
#define	RRAM_CTRL_WR_FIFO_SIZE_WORDS   1
#define	RRAM_CTRL_WR_FIFO_SIZE_BYTES   4
#define	RRAM_CTRL_RD_FIFO_REG_OFFSET   0x2b8
#define	RRAM_CTRL_RD_FIFO_SIZE_WORDS   1
#define	RRAM_CTRL_RD_FIFO_SIZE_BYTES   4

Detailed Description

Generated register defines for rram_ctrl.

Definition in file rram_ctrl_regs.h.

Macro Definition Documentation

RRAM_CTRL_ADDR_REG_OFFSET

#define RRAM_CTRL_ADDR_REG_OFFSET   0x24

Definition at line 151 of file rram_ctrl_regs.h.

RRAM_CTRL_ADDR_REG_RESVAL

#define RRAM_CTRL_ADDR_REG_RESVAL   0x0u

Definition at line 152 of file rram_ctrl_regs.h.

RRAM_CTRL_ADDR_START_FIELD

#define RRAM_CTRL_ADDR_START_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_ADDR_START_MASK, .index = RRAM_CTRL_ADDR_START_OFFSET })

Definition at line 155 of file rram_ctrl_regs.h.

RRAM_CTRL_ADDR_START_MASK

#define RRAM_CTRL_ADDR_START_MASK   0x1fffffu

Definition at line 153 of file rram_ctrl_regs.h.

RRAM_CTRL_ADDR_START_OFFSET

#define RRAM_CTRL_ADDR_START_OFFSET   0

Definition at line 154 of file rram_ctrl_regs.h.

RRAM_CTRL_ALERT_TEST_FATAL_ERR_BIT

#define RRAM_CTRL_ALERT_TEST_FATAL_ERR_BIT   2

Definition at line 102 of file rram_ctrl_regs.h.

RRAM_CTRL_ALERT_TEST_FATAL_MACRO_ERR_BIT

#define RRAM_CTRL_ALERT_TEST_FATAL_MACRO_ERR_BIT   3

Definition at line 103 of file rram_ctrl_regs.h.

RRAM_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT

#define RRAM_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT   1

Definition at line 101 of file rram_ctrl_regs.h.

RRAM_CTRL_ALERT_TEST_RECOV_ERR_BIT

#define RRAM_CTRL_ALERT_TEST_RECOV_ERR_BIT   0

Definition at line 100 of file rram_ctrl_regs.h.

RRAM_CTRL_ALERT_TEST_RECOV_MACRO_ERR_BIT

#define RRAM_CTRL_ALERT_TEST_RECOV_MACRO_ERR_BIT   4

Definition at line 104 of file rram_ctrl_regs.h.

RRAM_CTRL_ALERT_TEST_REG_OFFSET

#define RRAM_CTRL_ALERT_TEST_REG_OFFSET   0xc

Definition at line 98 of file rram_ctrl_regs.h.

RRAM_CTRL_ALERT_TEST_REG_RESVAL

#define RRAM_CTRL_ALERT_TEST_REG_RESVAL   0x80000000u

Definition at line 99 of file rram_ctrl_regs.h.

RRAM_CTRL_ALERT_TEST_REGWEN_BIT

#define RRAM_CTRL_ALERT_TEST_REGWEN_BIT   31

Definition at line 105 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_NUM_FIELD

#define RRAM_CTRL_CONTROL_NUM_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CONTROL_NUM_MASK, .index = RRAM_CTRL_CONTROL_NUM_OFFSET })

Definition at line 147 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_NUM_MASK

#define RRAM_CTRL_CONTROL_NUM_MASK   0x3ffu

Definition at line 145 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_NUM_OFFSET

#define RRAM_CTRL_CONTROL_NUM_OFFSET   16

Definition at line 146 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_OP_FIELD

#define RRAM_CTRL_CONTROL_OP_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CONTROL_OP_MASK, .index = RRAM_CTRL_CONTROL_OP_OFFSET })

Definition at line 139 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_OP_MASK

#define RRAM_CTRL_CONTROL_OP_MASK   0x3u

Definition at line 137 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_OP_OFFSET

#define RRAM_CTRL_CONTROL_OP_OFFSET   4

Definition at line 138 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_OP_VALUE_READ

#define RRAM_CTRL_CONTROL_OP_VALUE_READ   0x0

Definition at line 141 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_OP_VALUE_REWRITE

#define RRAM_CTRL_CONTROL_OP_VALUE_REWRITE   0x2

Definition at line 143 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_OP_VALUE_WRITE

#define RRAM_CTRL_CONTROL_OP_VALUE_WRITE   0x1

Definition at line 142 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_PARTITION_BIT

#define RRAM_CTRL_CONTROL_PARTITION_BIT   8

Definition at line 144 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_REG_OFFSET

#define RRAM_CTRL_CONTROL_REG_OFFSET   0x20

Definition at line 134 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_REG_RESVAL

#define RRAM_CTRL_CONTROL_REG_RESVAL   0x0u

Definition at line 135 of file rram_ctrl_regs.h.

RRAM_CTRL_CONTROL_START_BIT

#define RRAM_CTRL_CONTROL_START_BIT   0

Definition at line 136 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_CNT_REG_OFFSET

#define RRAM_CTRL_CORR1_ERR_CNT_REG_OFFSET   0x290

Definition at line 1951 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_CNT_REG_RESVAL

#define RRAM_CTRL_CORR1_ERR_CNT_REG_RESVAL   0x0u

Definition at line 1952 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_CNT_VAL_FIELD

#define RRAM_CTRL_CORR1_ERR_CNT_VAL_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR1_ERR_CNT_VAL_MASK, .index = RRAM_CTRL_CORR1_ERR_CNT_VAL_OFFSET })

Definition at line 1955 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_CNT_VAL_MASK

#define RRAM_CTRL_CORR1_ERR_CNT_VAL_MASK   0xffu

Definition at line 1953 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_CNT_VAL_OFFSET

#define RRAM_CTRL_CORR1_ERR_CNT_VAL_OFFSET   0

Definition at line 1954 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_LOC_ADDR_FIELD

#define RRAM_CTRL_CORR1_ERR_LOC_ADDR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR1_ERR_LOC_ADDR_MASK, .index = RRAM_CTRL_CORR1_ERR_LOC_ADDR_OFFSET })

Definition at line 1971 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_LOC_ADDR_MASK

#define RRAM_CTRL_CORR1_ERR_LOC_ADDR_MASK   0x1fffffu

Definition at line 1969 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_LOC_ADDR_OFFSET

#define RRAM_CTRL_CORR1_ERR_LOC_ADDR_OFFSET   0

Definition at line 1970 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_LOC_PART_BIT

#define RRAM_CTRL_CORR1_ERR_LOC_PART_BIT   24

Definition at line 1973 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_LOC_REG_OFFSET

#define RRAM_CTRL_CORR1_ERR_LOC_REG_OFFSET   0x298

Definition at line 1967 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR1_ERR_LOC_REG_RESVAL

#define RRAM_CTRL_CORR1_ERR_LOC_REG_RESVAL   0x0u

Definition at line 1968 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_CNT_REG_OFFSET

#define RRAM_CTRL_CORR2_ERR_CNT_REG_OFFSET   0x294

Definition at line 1959 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_CNT_REG_RESVAL

#define RRAM_CTRL_CORR2_ERR_CNT_REG_RESVAL   0x0u

Definition at line 1960 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_CNT_VAL_FIELD

#define RRAM_CTRL_CORR2_ERR_CNT_VAL_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR2_ERR_CNT_VAL_MASK, .index = RRAM_CTRL_CORR2_ERR_CNT_VAL_OFFSET })

Definition at line 1963 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_CNT_VAL_MASK

#define RRAM_CTRL_CORR2_ERR_CNT_VAL_MASK   0xffu

Definition at line 1961 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_CNT_VAL_OFFSET

#define RRAM_CTRL_CORR2_ERR_CNT_VAL_OFFSET   0

Definition at line 1962 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_LOC_ADDR_FIELD

#define RRAM_CTRL_CORR2_ERR_LOC_ADDR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR2_ERR_LOC_ADDR_MASK, .index = RRAM_CTRL_CORR2_ERR_LOC_ADDR_OFFSET })

Definition at line 1980 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_LOC_ADDR_MASK

#define RRAM_CTRL_CORR2_ERR_LOC_ADDR_MASK   0x1fffffu

Definition at line 1978 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_LOC_ADDR_OFFSET

#define RRAM_CTRL_CORR2_ERR_LOC_ADDR_OFFSET   0

Definition at line 1979 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_LOC_PART_BIT

#define RRAM_CTRL_CORR2_ERR_LOC_PART_BIT   24

Definition at line 1982 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_LOC_REG_OFFSET

#define RRAM_CTRL_CORR2_ERR_LOC_REG_OFFSET   0x29c

Definition at line 1976 of file rram_ctrl_regs.h.

RRAM_CTRL_CORR2_ERR_LOC_REG_RESVAL

#define RRAM_CTRL_CORR2_ERR_LOC_REG_RESVAL   0x0u

Definition at line 1977 of file rram_ctrl_regs.h.

RRAM_CTRL_CTRL_REGWEN_EN_BIT

#define RRAM_CTRL_CTRL_REGWEN_EN_BIT   0

Definition at line 131 of file rram_ctrl_regs.h.

RRAM_CTRL_CTRL_REGWEN_REG_OFFSET

#define RRAM_CTRL_CTRL_REGWEN_REG_OFFSET   0x1c

Definition at line 129 of file rram_ctrl_regs.h.

RRAM_CTRL_CTRL_REGWEN_REG_RESVAL

#define RRAM_CTRL_CTRL_REGWEN_REG_RESVAL   0x1u

Definition at line 130 of file rram_ctrl_regs.h.

RRAM_CTRL_CURR_FIFO_LVL_RD_FIELD

#define RRAM_CTRL_CURR_FIFO_LVL_RD_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CURR_FIFO_LVL_RD_MASK, .index = RRAM_CTRL_CURR_FIFO_LVL_RD_OFFSET })

Definition at line 2021 of file rram_ctrl_regs.h.

RRAM_CTRL_CURR_FIFO_LVL_RD_MASK

#define RRAM_CTRL_CURR_FIFO_LVL_RD_MASK   0x1fu

Definition at line 2019 of file rram_ctrl_regs.h.

RRAM_CTRL_CURR_FIFO_LVL_RD_OFFSET

#define RRAM_CTRL_CURR_FIFO_LVL_RD_OFFSET   8

Definition at line 2020 of file rram_ctrl_regs.h.

RRAM_CTRL_CURR_FIFO_LVL_REG_OFFSET

#define RRAM_CTRL_CURR_FIFO_LVL_REG_OFFSET   0x2b0

Definition at line 2013 of file rram_ctrl_regs.h.

RRAM_CTRL_CURR_FIFO_LVL_REG_RESVAL

#define RRAM_CTRL_CURR_FIFO_LVL_REG_RESVAL   0x0u

Definition at line 2014 of file rram_ctrl_regs.h.

RRAM_CTRL_CURR_FIFO_LVL_WR_FIELD

#define RRAM_CTRL_CURR_FIFO_LVL_WR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_CURR_FIFO_LVL_WR_MASK, .index = RRAM_CTRL_CURR_FIFO_LVL_WR_OFFSET })

Definition at line 2017 of file rram_ctrl_regs.h.

RRAM_CTRL_CURR_FIFO_LVL_WR_MASK

#define RRAM_CTRL_CURR_FIFO_LVL_WR_MASK   0x1fu

Definition at line 2015 of file rram_ctrl_regs.h.

RRAM_CTRL_CURR_FIFO_LVL_WR_OFFSET

#define RRAM_CTRL_CURR_FIFO_LVL_WR_OFFSET   0

Definition at line 2016 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_ECC_EN_FIELD

#define RRAM_CTRL_DEFAULT_REGION_ECC_EN_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_ECC_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_ECC_EN_OFFSET })

Definition at line 604 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_ECC_EN_MASK

#define RRAM_CTRL_DEFAULT_REGION_ECC_EN_MASK   0xfu

Definition at line 602 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_ECC_EN_OFFSET

#define RRAM_CTRL_DEFAULT_REGION_ECC_EN_OFFSET   12

Definition at line 603 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_RD_EN_FIELD

#define RRAM_CTRL_DEFAULT_REGION_RD_EN_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_RD_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_RD_EN_OFFSET })

Definition at line 592 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_RD_EN_MASK

#define RRAM_CTRL_DEFAULT_REGION_RD_EN_MASK   0xfu

Definition at line 590 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_RD_EN_OFFSET

#define RRAM_CTRL_DEFAULT_REGION_RD_EN_OFFSET   0

Definition at line 591 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_REG_OFFSET

#define RRAM_CTRL_DEFAULT_REGION_REG_OFFSET   0xa0

Definition at line 588 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_REG_RESVAL

#define RRAM_CTRL_DEFAULT_REGION_REG_RESVAL   0x9999u

Definition at line 589 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD

#define RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET })

Definition at line 600 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK

#define RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK   0xfu

Definition at line 598 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET

#define RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET   8

Definition at line 599 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_WR_EN_FIELD

#define RRAM_CTRL_DEFAULT_REGION_WR_EN_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_WR_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_WR_EN_OFFSET })

Definition at line 596 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_WR_EN_MASK

#define RRAM_CTRL_DEFAULT_REGION_WR_EN_MASK   0xfu

Definition at line 594 of file rram_ctrl_regs.h.

RRAM_CTRL_DEFAULT_REGION_WR_EN_OFFSET

#define RRAM_CTRL_DEFAULT_REGION_WR_EN_OFFSET   4

Definition at line 595 of file rram_ctrl_regs.h.

RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_FIELD

#define RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_MASK, .index = RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_OFFSET })

Definition at line 116 of file rram_ctrl_regs.h.

RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_MASK

#define RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_MASK   0xfu

Definition at line 114 of file rram_ctrl_regs.h.

RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_OFFSET

#define RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_OFFSET   4

Definition at line 115 of file rram_ctrl_regs.h.

RRAM_CTRL_DIS_REG_OFFSET

#define RRAM_CTRL_DIS_REG_OFFSET   0x10

Definition at line 108 of file rram_ctrl_regs.h.

RRAM_CTRL_DIS_REG_RESVAL

#define RRAM_CTRL_DIS_REG_RESVAL   0x99u

Definition at line 109 of file rram_ctrl_regs.h.

RRAM_CTRL_DIS_SW_DIS_FIELD

#define RRAM_CTRL_DIS_SW_DIS_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_DIS_SW_DIS_MASK, .index = RRAM_CTRL_DIS_SW_DIS_OFFSET })

Definition at line 112 of file rram_ctrl_regs.h.

RRAM_CTRL_DIS_SW_DIS_MASK

#define RRAM_CTRL_DIS_SW_DIS_MASK   0xfu

Definition at line 110 of file rram_ctrl_regs.h.

RRAM_CTRL_DIS_SW_DIS_OFFSET

#define RRAM_CTRL_DIS_SW_DIS_OFFSET   0

Definition at line 111 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_FIELD

#define RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_OFFSET })

Definition at line 880 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_MASK

#define RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_MASK   0xfffu

Definition at line 878 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_OFFSET   0

Definition at line 879 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_FIELD

#define RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_OFFSET })

Definition at line 888 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_MASK

#define RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_MASK   0xfu

Definition at line 886 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_OFFSET   24

Definition at line 887 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGION_0_REG_OFFSET   0xec

Definition at line 876 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_REGION_0_REG_RESVAL   0x9000000u

Definition at line 877 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_FIELD

#define RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_OFFSET })

Definition at line 884 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_MASK

#define RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_MASK   0xfffu

Definition at line 882 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_OFFSET   12

Definition at line 883 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_FIELD

#define RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_OFFSET })

Definition at line 896 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_MASK

#define RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_MASK   0xfffu

Definition at line 894 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_OFFSET   0

Definition at line 895 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_FIELD

#define RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_OFFSET })

Definition at line 904 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_MASK

#define RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_MASK   0xfu

Definition at line 902 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_OFFSET   24

Definition at line 903 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGION_1_REG_OFFSET   0xf0

Definition at line 892 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_REGION_1_REG_RESVAL   0x9000000u

Definition at line 893 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_FIELD

#define RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_OFFSET })

Definition at line 900 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_MASK

#define RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_MASK   0xfffu

Definition at line 898 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_OFFSET   12

Definition at line 899 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_BASE_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_REGION_BASE_FIELD_WIDTH   12

Definition at line 870 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_EN_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_REGION_EN_FIELD_WIDTH   4

Definition at line 872 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_MULTIREG_COUNT

#define RRAM_CTRL_EMUL_INFO_REGION_MULTIREG_COUNT   2

Definition at line 873 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGION_SIZE_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_REGION_SIZE_FIELD_WIDTH   12

Definition at line 871 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_0_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REG_OFFSET   0xe4

Definition at line 858 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_0_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REG_RESVAL   0x1u

Definition at line 859 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_BIT

#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_BIT   0

Definition at line 860 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_VALUE_REGION_ENABLED

#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_VALUE_REGION_ENABLED   0x1

Definition at line 862 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_VALUE_REGION_LOCKED

#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_VALUE_REGION_LOCKED   0x0

Definition at line 861 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_1_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_REGWEN_1_REG_OFFSET   0xe8

Definition at line 865 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_1_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_REGWEN_1_REG_RESVAL   0x1u

Definition at line 866 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_1_REGION_1_BIT

#define RRAM_CTRL_EMUL_INFO_REGWEN_1_REGION_1_BIT   0

Definition at line 867 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_MULTIREG_COUNT

#define RRAM_CTRL_EMUL_INFO_REGWEN_MULTIREG_COUNT   2

Definition at line 855 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_REGWEN_REGION_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_REGWEN_REGION_FIELD_WIDTH   1

Definition at line 854 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_0_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_REG_OFFSET   0x154

Definition at line 1042 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_0_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_REG_RESVAL   0x0u

Definition at line 1043 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_OFFSET })

Definition at line 1046 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_MASK   0xffu

Definition at line 1044 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_OFFSET   0

Definition at line 1045 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_10_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_REG_OFFSET   0x17c

Definition at line 1132 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_10_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_REG_RESVAL   0x0u

Definition at line 1133 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_OFFSET })

Definition at line 1136 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_MASK   0xffu

Definition at line 1134 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_OFFSET   0

Definition at line 1135 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_11_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_REG_OFFSET   0x180

Definition at line 1141 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_11_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_REG_RESVAL   0x0u

Definition at line 1142 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_OFFSET })

Definition at line 1145 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_MASK   0xffu

Definition at line 1143 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_OFFSET   0

Definition at line 1144 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_12_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_REG_OFFSET   0x184

Definition at line 1150 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_12_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_REG_RESVAL   0x0u

Definition at line 1151 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_OFFSET })

Definition at line 1154 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_MASK   0xffu

Definition at line 1152 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_OFFSET   0

Definition at line 1153 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_13_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_REG_OFFSET   0x188

Definition at line 1159 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_13_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_REG_RESVAL   0x0u

Definition at line 1160 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_OFFSET })

Definition at line 1163 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_MASK   0xffu

Definition at line 1161 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_OFFSET   0

Definition at line 1162 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_14_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_REG_OFFSET   0x18c

Definition at line 1168 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_14_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_REG_RESVAL   0x0u

Definition at line 1169 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_OFFSET })

Definition at line 1172 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_MASK   0xffu

Definition at line 1170 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_OFFSET   0

Definition at line 1171 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_15_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_REG_OFFSET   0x190

Definition at line 1177 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_15_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_REG_RESVAL   0x0u

Definition at line 1178 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_OFFSET })

Definition at line 1181 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_MASK   0xffu

Definition at line 1179 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_OFFSET   0

Definition at line 1180 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_16_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_REG_OFFSET   0x194

Definition at line 1186 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_16_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_REG_RESVAL   0x0u

Definition at line 1187 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_OFFSET })

Definition at line 1190 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_MASK   0xffu

Definition at line 1188 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_OFFSET   0

Definition at line 1189 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_17_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_REG_OFFSET   0x198

Definition at line 1195 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_17_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_REG_RESVAL   0x0u

Definition at line 1196 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_OFFSET })

Definition at line 1199 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_MASK   0xffu

Definition at line 1197 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_OFFSET   0

Definition at line 1198 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_18_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_REG_OFFSET   0x19c

Definition at line 1204 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_18_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_REG_RESVAL   0x0u

Definition at line 1205 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_OFFSET })

Definition at line 1208 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_MASK   0xffu

Definition at line 1206 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_OFFSET   0

Definition at line 1207 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_19_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_REG_OFFSET   0x1a0

Definition at line 1213 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_19_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_REG_RESVAL   0x0u

Definition at line 1214 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_OFFSET })

Definition at line 1217 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_MASK   0xffu

Definition at line 1215 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_OFFSET   0

Definition at line 1216 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_1_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_REG_OFFSET   0x158

Definition at line 1051 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_1_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_REG_RESVAL   0x0u

Definition at line 1052 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_OFFSET })

Definition at line 1055 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_MASK   0xffu

Definition at line 1053 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_OFFSET   0

Definition at line 1054 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_20_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_REG_OFFSET   0x1a4

Definition at line 1222 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_20_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_REG_RESVAL   0x0u

Definition at line 1223 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_OFFSET })

Definition at line 1226 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_MASK   0xffu

Definition at line 1224 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_OFFSET   0

Definition at line 1225 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_21_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_REG_OFFSET   0x1a8

Definition at line 1231 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_21_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_REG_RESVAL   0x0u

Definition at line 1232 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_OFFSET })

Definition at line 1235 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_MASK   0xffu

Definition at line 1233 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_OFFSET   0

Definition at line 1234 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_22_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_REG_OFFSET   0x1ac

Definition at line 1240 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_22_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_REG_RESVAL   0x0u

Definition at line 1241 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_OFFSET })

Definition at line 1244 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_MASK   0xffu

Definition at line 1242 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_OFFSET   0

Definition at line 1243 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_23_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_REG_OFFSET   0x1b0

Definition at line 1249 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_23_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_REG_RESVAL   0x0u

Definition at line 1250 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_OFFSET })

Definition at line 1253 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_MASK   0xffu

Definition at line 1251 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_OFFSET   0

Definition at line 1252 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_2_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_REG_OFFSET   0x15c

Definition at line 1060 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_2_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_REG_RESVAL   0x0u

Definition at line 1061 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_OFFSET })

Definition at line 1064 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_MASK   0xffu

Definition at line 1062 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_OFFSET   0

Definition at line 1063 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_3_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_REG_OFFSET   0x160

Definition at line 1069 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_3_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_REG_RESVAL   0x0u

Definition at line 1070 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_OFFSET })

Definition at line 1073 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_MASK   0xffu

Definition at line 1071 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_OFFSET   0

Definition at line 1072 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_4_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_REG_OFFSET   0x164

Definition at line 1078 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_4_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_REG_RESVAL   0x0u

Definition at line 1079 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_OFFSET })

Definition at line 1082 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_MASK   0xffu

Definition at line 1080 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_OFFSET   0

Definition at line 1081 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_5_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_REG_OFFSET   0x168

Definition at line 1087 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_5_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_REG_RESVAL   0x0u

Definition at line 1088 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_OFFSET })

Definition at line 1091 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_MASK   0xffu

Definition at line 1089 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_OFFSET   0

Definition at line 1090 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_6_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_REG_OFFSET   0x16c

Definition at line 1096 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_6_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_REG_RESVAL   0x0u

Definition at line 1097 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_OFFSET })

Definition at line 1100 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_MASK   0xffu

Definition at line 1098 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_OFFSET   0

Definition at line 1099 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_7_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_REG_OFFSET   0x170

Definition at line 1105 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_7_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_REG_RESVAL   0x0u

Definition at line 1106 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_OFFSET })

Definition at line 1109 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_MASK   0xffu

Definition at line 1107 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_OFFSET   0

Definition at line 1108 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_8_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_REG_OFFSET   0x174

Definition at line 1114 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_8_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_REG_RESVAL   0x0u

Definition at line 1115 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_OFFSET })

Definition at line 1118 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_MASK   0xffu

Definition at line 1116 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_OFFSET   0

Definition at line 1117 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_9_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_REG_OFFSET   0x178

Definition at line 1123 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_9_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_REG_RESVAL   0x0u

Definition at line 1124 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_OFFSET })

Definition at line 1127 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_MASK   0xffu

Definition at line 1125 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_OFFSET   0

Definition at line 1126 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_OFFSET })

Definition at line 1408 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_MASK   0xfu

Definition at line 1406 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_OFFSET   16

Definition at line 1407 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_OFFSET })

Definition at line 1396 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_MASK   0xfu

Definition at line 1394 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_OFFSET   4

Definition at line 1395 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_REG_OFFSET   0x214

Definition at line 1392 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_REG_RESVAL   0x99990u

Definition at line 1393 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_OFFSET })

Definition at line 1404 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_MASK   0xfu

Definition at line 1402 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_OFFSET   12

Definition at line 1403 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_OFFSET })

Definition at line 1400 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_MASK   0xfu

Definition at line 1398 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_OFFSET   8

Definition at line 1399 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_OFFSET })

Definition at line 1608 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_MASK   0xfu

Definition at line 1606 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_OFFSET   16

Definition at line 1607 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_OFFSET })

Definition at line 1596 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_MASK   0xfu

Definition at line 1594 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_OFFSET   4

Definition at line 1595 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_REG_OFFSET   0x23c

Definition at line 1592 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_REG_RESVAL   0x99990u

Definition at line 1593 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_OFFSET })

Definition at line 1604 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_MASK   0xfu

Definition at line 1602 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_OFFSET   12

Definition at line 1603 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_OFFSET })

Definition at line 1600 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_MASK   0xfu

Definition at line 1598 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_OFFSET   8

Definition at line 1599 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_OFFSET })

Definition at line 1628 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_MASK   0xfu

Definition at line 1626 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_OFFSET   16

Definition at line 1627 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_OFFSET })

Definition at line 1616 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_MASK   0xfu

Definition at line 1614 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_OFFSET   4

Definition at line 1615 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_REG_OFFSET   0x240

Definition at line 1612 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_REG_RESVAL   0x99990u

Definition at line 1613 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_OFFSET })

Definition at line 1624 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_MASK   0xfu

Definition at line 1622 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_OFFSET   12

Definition at line 1623 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_OFFSET })

Definition at line 1620 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_MASK   0xfu

Definition at line 1618 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_OFFSET   8

Definition at line 1619 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_OFFSET })

Definition at line 1648 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_MASK   0xfu

Definition at line 1646 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_OFFSET   16

Definition at line 1647 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_OFFSET })

Definition at line 1636 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_MASK   0xfu

Definition at line 1634 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_OFFSET   4

Definition at line 1635 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_REG_OFFSET   0x244

Definition at line 1632 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_REG_RESVAL   0x99990u

Definition at line 1633 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_OFFSET })

Definition at line 1644 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_MASK   0xfu

Definition at line 1642 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_OFFSET   12

Definition at line 1643 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_OFFSET })

Definition at line 1640 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_MASK   0xfu

Definition at line 1638 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_OFFSET   8

Definition at line 1639 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_OFFSET })

Definition at line 1668 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_MASK   0xfu

Definition at line 1666 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_OFFSET   16

Definition at line 1667 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_OFFSET })

Definition at line 1656 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_MASK   0xfu

Definition at line 1654 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_OFFSET   4

Definition at line 1655 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_REG_OFFSET   0x248

Definition at line 1652 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_REG_RESVAL   0x99990u

Definition at line 1653 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_OFFSET })

Definition at line 1664 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_MASK   0xfu

Definition at line 1662 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_OFFSET   12

Definition at line 1663 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_OFFSET })

Definition at line 1660 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_MASK   0xfu

Definition at line 1658 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_OFFSET   8

Definition at line 1659 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_OFFSET })

Definition at line 1688 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_MASK   0xfu

Definition at line 1686 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_OFFSET   16

Definition at line 1687 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_OFFSET })

Definition at line 1676 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_MASK   0xfu

Definition at line 1674 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_OFFSET   4

Definition at line 1675 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_REG_OFFSET   0x24c

Definition at line 1672 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_REG_RESVAL   0x99990u

Definition at line 1673 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_OFFSET })

Definition at line 1684 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_MASK   0xfu

Definition at line 1682 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_OFFSET   12

Definition at line 1683 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_OFFSET })

Definition at line 1680 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_MASK   0xfu

Definition at line 1678 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_OFFSET   8

Definition at line 1679 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_OFFSET })

Definition at line 1708 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_MASK   0xfu

Definition at line 1706 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_OFFSET   16

Definition at line 1707 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_OFFSET })

Definition at line 1696 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_MASK   0xfu

Definition at line 1694 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_OFFSET   4

Definition at line 1695 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_REG_OFFSET   0x250

Definition at line 1692 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_REG_RESVAL   0x99990u

Definition at line 1693 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_OFFSET })

Definition at line 1704 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_MASK   0xfu

Definition at line 1702 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_OFFSET   12

Definition at line 1703 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_OFFSET })

Definition at line 1700 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_MASK   0xfu

Definition at line 1698 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_OFFSET   8

Definition at line 1699 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_OFFSET })

Definition at line 1728 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_MASK   0xfu

Definition at line 1726 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_OFFSET   16

Definition at line 1727 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_OFFSET })

Definition at line 1716 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_MASK   0xfu

Definition at line 1714 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_OFFSET   4

Definition at line 1715 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_REG_OFFSET   0x254

Definition at line 1712 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_REG_RESVAL   0x99990u

Definition at line 1713 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_OFFSET })

Definition at line 1724 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_MASK   0xfu

Definition at line 1722 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_OFFSET   12

Definition at line 1723 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_OFFSET })

Definition at line 1720 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_MASK   0xfu

Definition at line 1718 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_OFFSET   8

Definition at line 1719 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_OFFSET })

Definition at line 1748 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_MASK   0xfu

Definition at line 1746 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_OFFSET   16

Definition at line 1747 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_OFFSET })

Definition at line 1736 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_MASK   0xfu

Definition at line 1734 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_OFFSET   4

Definition at line 1735 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_REG_OFFSET   0x258

Definition at line 1732 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_REG_RESVAL   0x99990u

Definition at line 1733 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_OFFSET })

Definition at line 1744 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_MASK   0xfu

Definition at line 1742 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_OFFSET   12

Definition at line 1743 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_OFFSET })

Definition at line 1740 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_MASK   0xfu

Definition at line 1738 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_OFFSET   8

Definition at line 1739 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_OFFSET })

Definition at line 1768 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_MASK   0xfu

Definition at line 1766 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_OFFSET   16

Definition at line 1767 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_OFFSET })

Definition at line 1756 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_MASK   0xfu

Definition at line 1754 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_OFFSET   4

Definition at line 1755 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_REG_OFFSET   0x25c

Definition at line 1752 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_REG_RESVAL   0x99990u

Definition at line 1753 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_OFFSET })

Definition at line 1764 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_MASK   0xfu

Definition at line 1762 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_OFFSET   12

Definition at line 1763 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_OFFSET })

Definition at line 1760 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_MASK   0xfu

Definition at line 1758 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_OFFSET   8

Definition at line 1759 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_OFFSET })

Definition at line 1788 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_MASK   0xfu

Definition at line 1786 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_OFFSET   16

Definition at line 1787 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_OFFSET })

Definition at line 1776 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_MASK   0xfu

Definition at line 1774 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_OFFSET   4

Definition at line 1775 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_REG_OFFSET   0x260

Definition at line 1772 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_REG_RESVAL   0x99990u

Definition at line 1773 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_OFFSET })

Definition at line 1784 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_MASK   0xfu

Definition at line 1782 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_OFFSET   12

Definition at line 1783 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_OFFSET })

Definition at line 1780 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_MASK   0xfu

Definition at line 1778 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_OFFSET   8

Definition at line 1779 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_OFFSET })

Definition at line 1428 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_MASK   0xfu

Definition at line 1426 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_OFFSET   16

Definition at line 1427 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_OFFSET })

Definition at line 1416 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_MASK   0xfu

Definition at line 1414 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_OFFSET   4

Definition at line 1415 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_REG_OFFSET   0x218

Definition at line 1412 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_REG_RESVAL   0x99990u

Definition at line 1413 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_OFFSET })

Definition at line 1424 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_MASK   0xfu

Definition at line 1422 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_OFFSET   12

Definition at line 1423 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_OFFSET })

Definition at line 1420 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_MASK   0xfu

Definition at line 1418 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_OFFSET   8

Definition at line 1419 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_OFFSET })

Definition at line 1808 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_MASK   0xfu

Definition at line 1806 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_OFFSET   16

Definition at line 1807 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_OFFSET })

Definition at line 1796 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_MASK   0xfu

Definition at line 1794 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_OFFSET   4

Definition at line 1795 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_REG_OFFSET   0x264

Definition at line 1792 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_REG_RESVAL   0x99990u

Definition at line 1793 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_OFFSET })

Definition at line 1804 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_MASK   0xfu

Definition at line 1802 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_OFFSET   12

Definition at line 1803 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_OFFSET })

Definition at line 1800 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_MASK   0xfu

Definition at line 1798 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_OFFSET   8

Definition at line 1799 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_OFFSET })

Definition at line 1828 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_MASK   0xfu

Definition at line 1826 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_OFFSET   16

Definition at line 1827 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_OFFSET })

Definition at line 1816 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_MASK   0xfu

Definition at line 1814 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_OFFSET   4

Definition at line 1815 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_REG_OFFSET   0x268

Definition at line 1812 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_REG_RESVAL   0x99990u

Definition at line 1813 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_OFFSET })

Definition at line 1824 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_MASK   0xfu

Definition at line 1822 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_OFFSET   12

Definition at line 1823 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_OFFSET })

Definition at line 1820 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_MASK   0xfu

Definition at line 1818 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_OFFSET   8

Definition at line 1819 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_OFFSET })

Definition at line 1848 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_MASK   0xfu

Definition at line 1846 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_OFFSET   16

Definition at line 1847 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_OFFSET })

Definition at line 1836 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_MASK   0xfu

Definition at line 1834 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_OFFSET   4

Definition at line 1835 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_REG_OFFSET   0x26c

Definition at line 1832 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_REG_RESVAL   0x99990u

Definition at line 1833 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_OFFSET })

Definition at line 1844 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_MASK   0xfu

Definition at line 1842 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_OFFSET   12

Definition at line 1843 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_OFFSET })

Definition at line 1840 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_MASK   0xfu

Definition at line 1838 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_OFFSET   8

Definition at line 1839 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_OFFSET })

Definition at line 1868 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_MASK   0xfu

Definition at line 1866 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_OFFSET   16

Definition at line 1867 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_OFFSET })

Definition at line 1856 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_MASK   0xfu

Definition at line 1854 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_OFFSET   4

Definition at line 1855 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_REG_OFFSET   0x270

Definition at line 1852 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_REG_RESVAL   0x99990u

Definition at line 1853 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_OFFSET })

Definition at line 1864 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_MASK   0xfu

Definition at line 1862 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_OFFSET   12

Definition at line 1863 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_OFFSET })

Definition at line 1860 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_MASK   0xfu

Definition at line 1858 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_OFFSET   8

Definition at line 1859 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_OFFSET })

Definition at line 1448 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_MASK   0xfu

Definition at line 1446 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_OFFSET   16

Definition at line 1447 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_OFFSET })

Definition at line 1436 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_MASK   0xfu

Definition at line 1434 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_OFFSET   4

Definition at line 1435 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_REG_OFFSET   0x21c

Definition at line 1432 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_REG_RESVAL   0x99990u

Definition at line 1433 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_OFFSET })

Definition at line 1444 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_MASK   0xfu

Definition at line 1442 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_OFFSET   12

Definition at line 1443 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_OFFSET })

Definition at line 1440 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_MASK   0xfu

Definition at line 1438 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_OFFSET   8

Definition at line 1439 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_OFFSET })

Definition at line 1468 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_MASK   0xfu

Definition at line 1466 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_OFFSET   16

Definition at line 1467 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_OFFSET })

Definition at line 1456 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_MASK   0xfu

Definition at line 1454 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_OFFSET   4

Definition at line 1455 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_REG_OFFSET   0x220

Definition at line 1452 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_REG_RESVAL   0x99990u

Definition at line 1453 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_OFFSET })

Definition at line 1464 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_MASK   0xfu

Definition at line 1462 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_OFFSET   12

Definition at line 1463 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_OFFSET })

Definition at line 1460 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_MASK   0xfu

Definition at line 1458 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_OFFSET   8

Definition at line 1459 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_OFFSET })

Definition at line 1488 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_MASK   0xfu

Definition at line 1486 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_OFFSET   16

Definition at line 1487 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_OFFSET })

Definition at line 1476 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_MASK   0xfu

Definition at line 1474 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_OFFSET   4

Definition at line 1475 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_REG_OFFSET   0x224

Definition at line 1472 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_REG_RESVAL   0x99990u

Definition at line 1473 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_OFFSET })

Definition at line 1484 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_MASK   0xfu

Definition at line 1482 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_OFFSET   12

Definition at line 1483 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_OFFSET })

Definition at line 1480 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_MASK   0xfu

Definition at line 1478 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_OFFSET   8

Definition at line 1479 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_OFFSET })

Definition at line 1508 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_MASK   0xfu

Definition at line 1506 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_OFFSET   16

Definition at line 1507 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_OFFSET })

Definition at line 1496 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_MASK   0xfu

Definition at line 1494 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_OFFSET   4

Definition at line 1495 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_REG_OFFSET   0x228

Definition at line 1492 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_REG_RESVAL   0x99990u

Definition at line 1493 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_OFFSET })

Definition at line 1504 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_MASK   0xfu

Definition at line 1502 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_OFFSET   12

Definition at line 1503 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_OFFSET })

Definition at line 1500 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_MASK   0xfu

Definition at line 1498 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_OFFSET   8

Definition at line 1499 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_OFFSET })

Definition at line 1528 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_MASK   0xfu

Definition at line 1526 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_OFFSET   16

Definition at line 1527 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_OFFSET })

Definition at line 1516 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_MASK   0xfu

Definition at line 1514 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_OFFSET   4

Definition at line 1515 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_REG_OFFSET   0x22c

Definition at line 1512 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_REG_RESVAL   0x99990u

Definition at line 1513 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_OFFSET })

Definition at line 1524 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_MASK   0xfu

Definition at line 1522 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_OFFSET   12

Definition at line 1523 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_OFFSET })

Definition at line 1520 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_MASK   0xfu

Definition at line 1518 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_OFFSET   8

Definition at line 1519 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_OFFSET })

Definition at line 1548 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_MASK   0xfu

Definition at line 1546 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_OFFSET   16

Definition at line 1547 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_OFFSET })

Definition at line 1536 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_MASK   0xfu

Definition at line 1534 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_OFFSET   4

Definition at line 1535 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_REG_OFFSET   0x230

Definition at line 1532 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_REG_RESVAL   0x99990u

Definition at line 1533 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_OFFSET })

Definition at line 1544 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_MASK   0xfu

Definition at line 1542 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_OFFSET   12

Definition at line 1543 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_OFFSET })

Definition at line 1540 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_MASK   0xfu

Definition at line 1538 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_OFFSET   8

Definition at line 1539 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_OFFSET })

Definition at line 1568 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_MASK   0xfu

Definition at line 1566 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_OFFSET   16

Definition at line 1567 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_OFFSET })

Definition at line 1556 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_MASK   0xfu

Definition at line 1554 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_OFFSET   4

Definition at line 1555 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_REG_OFFSET   0x234

Definition at line 1552 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_REG_RESVAL   0x99990u

Definition at line 1553 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_OFFSET })

Definition at line 1564 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_MASK   0xfu

Definition at line 1562 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_OFFSET   12

Definition at line 1563 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_OFFSET })

Definition at line 1560 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_MASK   0xfu

Definition at line 1558 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_OFFSET   8

Definition at line 1559 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_OFFSET })

Definition at line 1588 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_MASK   0xfu

Definition at line 1586 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_OFFSET   16

Definition at line 1587 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_OFFSET })

Definition at line 1576 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_MASK   0xfu

Definition at line 1574 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_OFFSET   4

Definition at line 1575 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_REG_OFFSET   0x238

Definition at line 1572 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_REG_RESVAL   0x99990u

Definition at line 1573 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_OFFSET })

Definition at line 1584 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_MASK   0xfu

Definition at line 1582 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_OFFSET   12

Definition at line 1583 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_FIELD

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_OFFSET })

Definition at line 1580 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_MASK

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_MASK   0xfu

Definition at line 1578 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_OFFSET   8

Definition at line 1579 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_ECC_EN_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_ECC_EN_FIELD_WIDTH   4

Definition at line 1388 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_MULTIREG_COUNT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_MULTIREG_COUNT   24

Definition at line 1389 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_RD_EN_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_RD_EN_FIELD_WIDTH   4

Definition at line 1385 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REG_OFFSET   0x1b4

Definition at line 1261 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REG_RESVAL   0x1u

Definition at line 1262 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_BIT   0

Definition at line 1263 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_VALUE_SUBREGION_ENABLED

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_VALUE_SUBREGION_ENABLED    0x1

Definition at line 1266 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_VALUE_SUBREGION_LOCKED

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_VALUE_SUBREGION_LOCKED    0x0

Definition at line 1264 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REG_OFFSET   0x1dc

Definition at line 1315 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REG_RESVAL   0x1u

Definition at line 1316 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REGION_10_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REGION_10_BIT   0

Definition at line 1317 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REG_OFFSET   0x1e0

Definition at line 1320 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REG_RESVAL   0x1u

Definition at line 1321 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REGION_11_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REGION_11_BIT   0

Definition at line 1322 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REG_OFFSET   0x1e4

Definition at line 1325 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REG_RESVAL   0x1u

Definition at line 1326 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REGION_12_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REGION_12_BIT   0

Definition at line 1327 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REG_OFFSET   0x1e8

Definition at line 1330 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REG_RESVAL   0x1u

Definition at line 1331 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REGION_13_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REGION_13_BIT   0

Definition at line 1332 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REG_OFFSET   0x1ec

Definition at line 1335 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REG_RESVAL   0x1u

Definition at line 1336 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REGION_14_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REGION_14_BIT   0

Definition at line 1337 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REG_OFFSET   0x1f0

Definition at line 1340 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REG_RESVAL   0x1u

Definition at line 1341 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REGION_15_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REGION_15_BIT   0

Definition at line 1342 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REG_OFFSET   0x1f4

Definition at line 1345 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REG_RESVAL   0x1u

Definition at line 1346 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REGION_16_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REGION_16_BIT   0

Definition at line 1347 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REG_OFFSET   0x1f8

Definition at line 1350 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REG_RESVAL   0x1u

Definition at line 1351 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REGION_17_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REGION_17_BIT   0

Definition at line 1352 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REG_OFFSET   0x1fc

Definition at line 1355 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REG_RESVAL   0x1u

Definition at line 1356 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REGION_18_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REGION_18_BIT   0

Definition at line 1357 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REG_OFFSET   0x200

Definition at line 1360 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REG_RESVAL   0x1u

Definition at line 1361 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REGION_19_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REGION_19_BIT   0

Definition at line 1362 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REG_OFFSET   0x1b8

Definition at line 1270 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REG_RESVAL   0x1u

Definition at line 1271 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REGION_1_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REGION_1_BIT   0

Definition at line 1272 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REG_OFFSET   0x204

Definition at line 1365 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REG_RESVAL   0x1u

Definition at line 1366 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REGION_20_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REGION_20_BIT   0

Definition at line 1367 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REG_OFFSET   0x208

Definition at line 1370 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REG_RESVAL   0x1u

Definition at line 1371 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REGION_21_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REGION_21_BIT   0

Definition at line 1372 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REG_OFFSET   0x20c

Definition at line 1375 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REG_RESVAL   0x1u

Definition at line 1376 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REGION_22_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REGION_22_BIT   0

Definition at line 1377 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REG_OFFSET   0x210

Definition at line 1380 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REG_RESVAL   0x1u

Definition at line 1381 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REGION_23_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REGION_23_BIT   0

Definition at line 1382 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REG_OFFSET   0x1bc

Definition at line 1275 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REG_RESVAL   0x1u

Definition at line 1276 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REGION_2_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REGION_2_BIT   0

Definition at line 1277 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REG_OFFSET   0x1c0

Definition at line 1280 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REG_RESVAL   0x1u

Definition at line 1281 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REGION_3_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REGION_3_BIT   0

Definition at line 1282 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REG_OFFSET   0x1c4

Definition at line 1285 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REG_RESVAL   0x1u

Definition at line 1286 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REGION_4_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REGION_4_BIT   0

Definition at line 1287 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REG_OFFSET   0x1c8

Definition at line 1290 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REG_RESVAL   0x1u

Definition at line 1291 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REGION_5_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REGION_5_BIT   0

Definition at line 1292 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REG_OFFSET   0x1cc

Definition at line 1295 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REG_RESVAL   0x1u

Definition at line 1296 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REGION_6_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REGION_6_BIT   0

Definition at line 1297 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REG_OFFSET   0x1d0

Definition at line 1300 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REG_RESVAL   0x1u

Definition at line 1301 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REGION_7_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REGION_7_BIT   0

Definition at line 1302 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REG_OFFSET   0x1d4

Definition at line 1305 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REG_RESVAL   0x1u

Definition at line 1306 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REGION_8_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REGION_8_BIT   0

Definition at line 1307 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REG_OFFSET   0x1d8

Definition at line 1310 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REG_RESVAL   0x1u

Definition at line 1311 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REGION_9_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REGION_9_BIT   0

Definition at line 1312 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_MULTIREG_COUNT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_MULTIREG_COUNT   24

Definition at line 1258 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_REGION_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_REGION_FIELD_WIDTH   1

Definition at line 1257 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_SCRAMBLE_EN_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_SCRAMBLE_EN_FIELD_WIDTH   4

Definition at line 1387 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_WR_EN_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_WR_EN_FIELD_WIDTH   4

Definition at line 1386 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_MULTIREG_COUNT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_MULTIREG_COUNT   24

Definition at line 1038 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REG_OFFSET   0xf4

Definition at line 912 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REG_RESVAL   0x1u

Definition at line 913 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_BIT   0

Definition at line 914 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_VALUE_SUBREGION_ENABLED

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_VALUE_SUBREGION_ENABLED    0x1

Definition at line 917 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_VALUE_SUBREGION_LOCKED

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_VALUE_SUBREGION_LOCKED    0x0

Definition at line 915 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REG_OFFSET   0x11c

Definition at line 966 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REG_RESVAL   0x1u

Definition at line 967 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REGION_10_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REGION_10_BIT   0

Definition at line 968 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REG_OFFSET   0x120

Definition at line 971 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REG_RESVAL   0x1u

Definition at line 972 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REGION_11_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REGION_11_BIT   0

Definition at line 973 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REG_OFFSET   0x124

Definition at line 976 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REG_RESVAL   0x1u

Definition at line 977 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REGION_12_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REGION_12_BIT   0

Definition at line 978 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REG_OFFSET   0x128

Definition at line 981 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REG_RESVAL   0x1u

Definition at line 982 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REGION_13_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REGION_13_BIT   0

Definition at line 983 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REG_OFFSET   0x12c

Definition at line 986 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REG_RESVAL   0x1u

Definition at line 987 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REGION_14_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REGION_14_BIT   0

Definition at line 988 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REG_OFFSET   0x130

Definition at line 991 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REG_RESVAL   0x1u

Definition at line 992 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REGION_15_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REGION_15_BIT   0

Definition at line 993 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REG_OFFSET   0x134

Definition at line 996 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REG_RESVAL   0x1u

Definition at line 997 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REGION_16_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REGION_16_BIT   0

Definition at line 998 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REG_OFFSET   0x138

Definition at line 1001 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REG_RESVAL   0x1u

Definition at line 1002 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REGION_17_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REGION_17_BIT   0

Definition at line 1003 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REG_OFFSET   0x13c

Definition at line 1006 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REG_RESVAL   0x1u

Definition at line 1007 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REGION_18_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REGION_18_BIT   0

Definition at line 1008 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REG_OFFSET   0x140

Definition at line 1011 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REG_RESVAL   0x1u

Definition at line 1012 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REGION_19_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REGION_19_BIT   0

Definition at line 1013 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REG_OFFSET   0xf8

Definition at line 921 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REG_RESVAL   0x1u

Definition at line 922 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REGION_1_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REGION_1_BIT   0

Definition at line 923 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REG_OFFSET   0x144

Definition at line 1016 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REG_RESVAL   0x1u

Definition at line 1017 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REGION_20_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REGION_20_BIT   0

Definition at line 1018 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REG_OFFSET   0x148

Definition at line 1021 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REG_RESVAL   0x1u

Definition at line 1022 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REGION_21_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REGION_21_BIT   0

Definition at line 1023 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REG_OFFSET   0x14c

Definition at line 1026 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REG_RESVAL   0x1u

Definition at line 1027 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REGION_22_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REGION_22_BIT   0

Definition at line 1028 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REG_OFFSET   0x150

Definition at line 1031 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REG_RESVAL   0x1u

Definition at line 1032 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REGION_23_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REGION_23_BIT   0

Definition at line 1033 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REG_OFFSET   0xfc

Definition at line 926 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REG_RESVAL   0x1u

Definition at line 927 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REGION_2_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REGION_2_BIT   0

Definition at line 928 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REG_OFFSET   0x100

Definition at line 931 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REG_RESVAL   0x1u

Definition at line 932 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REGION_3_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REGION_3_BIT   0

Definition at line 933 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REG_OFFSET   0x104

Definition at line 936 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REG_RESVAL   0x1u

Definition at line 937 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REGION_4_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REGION_4_BIT   0

Definition at line 938 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REG_OFFSET   0x108

Definition at line 941 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REG_RESVAL   0x1u

Definition at line 942 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REGION_5_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REGION_5_BIT   0

Definition at line 943 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REG_OFFSET   0x10c

Definition at line 946 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REG_RESVAL   0x1u

Definition at line 947 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REGION_6_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REGION_6_BIT   0

Definition at line 948 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REG_OFFSET   0x110

Definition at line 951 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REG_RESVAL   0x1u

Definition at line 952 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REGION_7_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REGION_7_BIT   0

Definition at line 953 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REG_OFFSET   0x114

Definition at line 956 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REG_RESVAL   0x1u

Definition at line 957 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REGION_8_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REGION_8_BIT   0

Definition at line 958 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REG_OFFSET

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REG_OFFSET   0x118

Definition at line 961 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REG_RESVAL

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REG_RESVAL   0x1u

Definition at line 962 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REGION_9_BIT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REGION_9_BIT   0

Definition at line 963 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_MULTIREG_COUNT

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_MULTIREG_COUNT   24

Definition at line 909 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_REGION_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_REGION_FIELD_WIDTH   1

Definition at line 908 of file rram_ctrl_regs.h.

RRAM_CTRL_EMUL_INFO_SUBREGION_TOP_FIELD_WIDTH

#define RRAM_CTRL_EMUL_INFO_SUBREGION_TOP_FIELD_WIDTH   8

Definition at line 1037 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_ADDR_ERR_ADDR_FIELD

#define RRAM_CTRL_ERR_ADDR_ERR_ADDR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_ERR_ADDR_ERR_ADDR_MASK, .index = RRAM_CTRL_ERR_ADDR_ERR_ADDR_OFFSET })

Definition at line 1947 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_ADDR_ERR_ADDR_MASK

#define RRAM_CTRL_ERR_ADDR_ERR_ADDR_MASK   0x1fffffu

Definition at line 1945 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_ADDR_ERR_ADDR_OFFSET

#define RRAM_CTRL_ERR_ADDR_ERR_ADDR_OFFSET   0

Definition at line 1946 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_ADDR_REG_OFFSET

#define RRAM_CTRL_ERR_ADDR_REG_OFFSET   0x28c

Definition at line 1943 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_ADDR_REG_RESVAL

#define RRAM_CTRL_ERR_ADDR_REG_RESVAL   0x0u

Definition at line 1944 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_CODE_MP_ERR_BIT

#define RRAM_CTRL_ERR_CODE_MP_ERR_BIT   1

Definition at line 1903 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_CODE_OP_ERR_BIT

#define RRAM_CTRL_ERR_CODE_OP_ERR_BIT   0

Definition at line 1902 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_CODE_RD_ERR_BIT

#define RRAM_CTRL_ERR_CODE_RD_ERR_BIT   2

Definition at line 1904 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_CODE_REG_OFFSET

#define RRAM_CTRL_ERR_CODE_REG_OFFSET   0x280

Definition at line 1900 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_CODE_REG_RESVAL

#define RRAM_CTRL_ERR_CODE_REG_RESVAL   0x0u

Definition at line 1901 of file rram_ctrl_regs.h.

RRAM_CTRL_ERR_CODE_WR_ERR_BIT

#define RRAM_CTRL_ERR_CODE_WR_ERR_BIT   3

Definition at line 1905 of file rram_ctrl_regs.h.

RRAM_CTRL_EXEC_REG_OFFSET

#define RRAM_CTRL_EXEC_REG_OFFSET   0x14

Definition at line 120 of file rram_ctrl_regs.h.

RRAM_CTRL_EXEC_REG_RESVAL

#define RRAM_CTRL_EXEC_REG_RESVAL   0x0u

Definition at line 121 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_HOST_GNT_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_HOST_GNT_ERR_BIT   13

Definition at line 1940 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_LCMGR_MP_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_LCMGR_MP_ERR_BIT   1

Definition at line 1928 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_LCMGR_OP_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_LCMGR_OP_ERR_BIT   0

Definition at line 1927 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_LCMGR_RD_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_LCMGR_RD_ERR_BIT   2

Definition at line 1929 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_LCMGR_WR_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_LCMGR_WR_ERR_BIT   3

Definition at line 1930 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_OTP_MP_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_OTP_MP_ERR_BIT   5

Definition at line 1932 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_OTP_OP_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_OTP_OP_ERR_BIT   4

Definition at line 1931 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_OTP_RD_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_OTP_RD_ERR_BIT   6

Definition at line 1933 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_OTP_WR_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_OTP_WR_ERR_BIT   7

Definition at line 1934 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_PHY_RD_CTRL_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_PHY_RD_CTRL_ERR_BIT   11

Definition at line 1938 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_PHY_RD_INTG_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_PHY_RD_INTG_ERR_BIT   10

Definition at line 1937 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_PHY_RELBL_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_PHY_RELBL_ERR_BIT   9

Definition at line 1936 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_REG_OFFSET

#define RRAM_CTRL_FAULT_STATUS_REG_OFFSET   0x288

Definition at line 1925 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_REG_RESVAL

#define RRAM_CTRL_FAULT_STATUS_REG_RESVAL   0x0u

Definition at line 1926 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_SEED_ERR_BIT

#define RRAM_CTRL_FAULT_STATUS_SEED_ERR_BIT   8

Definition at line 1935 of file rram_ctrl_regs.h.

RRAM_CTRL_FAULT_STATUS_SPURIOUS_DONE_BIT

#define RRAM_CTRL_FAULT_STATUS_SPURIOUS_DONE_BIT   12

Definition at line 1939 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_CLR_RD_BIT

#define RRAM_CTRL_FIFO_CLR_RD_BIT   1

Definition at line 2010 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_CLR_REG_OFFSET

#define RRAM_CTRL_FIFO_CLR_REG_OFFSET   0x2ac

Definition at line 2007 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_CLR_REG_RESVAL

#define RRAM_CTRL_FIFO_CLR_REG_RESVAL   0x0u

Definition at line 2008 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_CLR_WR_BIT

#define RRAM_CTRL_FIFO_CLR_WR_BIT   0

Definition at line 2009 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_LVL_RD_FIELD

#define RRAM_CTRL_FIFO_LVL_RD_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_FIFO_LVL_RD_MASK, .index = RRAM_CTRL_FIFO_LVL_RD_OFFSET })

Definition at line 2003 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_LVL_RD_MASK

#define RRAM_CTRL_FIFO_LVL_RD_MASK   0x1fu

Definition at line 2001 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_LVL_RD_OFFSET

#define RRAM_CTRL_FIFO_LVL_RD_OFFSET   8

Definition at line 2002 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_LVL_REG_OFFSET

#define RRAM_CTRL_FIFO_LVL_REG_OFFSET   0x2a8

Definition at line 1995 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_LVL_REG_RESVAL

#define RRAM_CTRL_FIFO_LVL_REG_RESVAL   0xf0fu

Definition at line 1996 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_LVL_WR_FIELD

#define RRAM_CTRL_FIFO_LVL_WR_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_FIFO_LVL_WR_MASK, .index = RRAM_CTRL_FIFO_LVL_WR_OFFSET })

Definition at line 1999 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_LVL_WR_MASK

#define RRAM_CTRL_FIFO_LVL_WR_MASK   0x1fu

Definition at line 1997 of file rram_ctrl_regs.h.

RRAM_CTRL_FIFO_LVL_WR_OFFSET

#define RRAM_CTRL_FIFO_LVL_WR_OFFSET   0

Definition at line 1998 of file rram_ctrl_regs.h.

RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_FIELD

#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK, .index = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET })

Definition at line 1880 of file rram_ctrl_regs.h.

RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK

#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK   0xfu

Definition at line 1878 of file rram_ctrl_regs.h.

RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET

#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET   4

Definition at line 1879 of file rram_ctrl_regs.h.

RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_OFFSET

#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_OFFSET   0x274

Definition at line 1872 of file rram_ctrl_regs.h.

RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_RESVAL

#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_RESVAL   0x99u

Definition at line 1873 of file rram_ctrl_regs.h.

RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_FIELD

#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK, .index = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET })

Definition at line 1876 of file rram_ctrl_regs.h.

RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK

#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK   0xfu

Definition at line 1874 of file rram_ctrl_regs.h.

RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET

#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET   0

Definition at line 1875 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_OFFSET })

Definition at line 682 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_MASK   0xfu

Definition at line 680 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_OFFSET   16

Definition at line 681 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_OFFSET })

Definition at line 666 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_MASK   0xfu

Definition at line 664 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_OFFSET   0

Definition at line 665 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_OFFSET })

Definition at line 670 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_MASK   0xfu

Definition at line 668 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_OFFSET   4

Definition at line 669 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_REG_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_0_REG_OFFSET   0xc4

Definition at line 662 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_REG_RESVAL

#define RRAM_CTRL_INFO_PAGE_CFG_0_REG_RESVAL   0x99999u

Definition at line 663 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET })

Definition at line 678 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_MASK   0xfu

Definition at line 676 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET   12

Definition at line 677 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_OFFSET })

Definition at line 674 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_MASK   0xfu

Definition at line 672 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_OFFSET   8

Definition at line 673 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_OFFSET })

Definition at line 706 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_MASK   0xfu

Definition at line 704 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_OFFSET   16

Definition at line 705 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_OFFSET })

Definition at line 690 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_MASK   0xfu

Definition at line 688 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_OFFSET   0

Definition at line 689 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_OFFSET })

Definition at line 694 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_MASK   0xfu

Definition at line 692 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_OFFSET   4

Definition at line 693 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_REG_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_1_REG_OFFSET   0xc8

Definition at line 686 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_REG_RESVAL

#define RRAM_CTRL_INFO_PAGE_CFG_1_REG_RESVAL   0x99999u

Definition at line 687 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET })

Definition at line 702 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_MASK   0xfu

Definition at line 700 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET   12

Definition at line 701 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_OFFSET })

Definition at line 698 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_MASK   0xfu

Definition at line 696 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_OFFSET   8

Definition at line 697 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_OFFSET })

Definition at line 730 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_MASK   0xfu

Definition at line 728 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_OFFSET   16

Definition at line 729 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_OFFSET })

Definition at line 714 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_MASK   0xfu

Definition at line 712 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_OFFSET   0

Definition at line 713 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_OFFSET })

Definition at line 718 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_MASK   0xfu

Definition at line 716 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_OFFSET   4

Definition at line 717 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_REG_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_2_REG_OFFSET   0xcc

Definition at line 710 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_REG_RESVAL

#define RRAM_CTRL_INFO_PAGE_CFG_2_REG_RESVAL   0x99999u

Definition at line 711 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET })

Definition at line 726 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_MASK   0xfu

Definition at line 724 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET   12

Definition at line 725 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_OFFSET })

Definition at line 722 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_MASK   0xfu

Definition at line 720 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_OFFSET   8

Definition at line 721 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_OFFSET })

Definition at line 754 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_MASK   0xfu

Definition at line 752 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_OFFSET   16

Definition at line 753 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_OFFSET })

Definition at line 738 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_MASK   0xfu

Definition at line 736 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_OFFSET   0

Definition at line 737 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_OFFSET })

Definition at line 742 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_MASK   0xfu

Definition at line 740 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_OFFSET   4

Definition at line 741 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_REG_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_3_REG_OFFSET   0xd0

Definition at line 734 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_REG_RESVAL

#define RRAM_CTRL_INFO_PAGE_CFG_3_REG_RESVAL   0x99999u

Definition at line 735 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET })

Definition at line 750 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_MASK   0xfu

Definition at line 748 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET   12

Definition at line 749 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_OFFSET })

Definition at line 746 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_MASK   0xfu

Definition at line 744 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_OFFSET   8

Definition at line 745 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_OFFSET })

Definition at line 778 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_MASK   0xfu

Definition at line 776 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_OFFSET   16

Definition at line 777 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_OFFSET })

Definition at line 762 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_MASK   0xfu

Definition at line 760 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_OFFSET   0

Definition at line 761 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_OFFSET })

Definition at line 766 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_MASK   0xfu

Definition at line 764 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_OFFSET   4

Definition at line 765 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_REG_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_4_REG_OFFSET   0xd4

Definition at line 758 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_REG_RESVAL

#define RRAM_CTRL_INFO_PAGE_CFG_4_REG_RESVAL   0x99999u

Definition at line 759 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET })

Definition at line 774 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_MASK   0xfu

Definition at line 772 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET   12

Definition at line 773 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_OFFSET })

Definition at line 770 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_MASK   0xfu

Definition at line 768 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_OFFSET   8

Definition at line 769 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_OFFSET })

Definition at line 802 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_MASK   0xfu

Definition at line 800 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_OFFSET   16

Definition at line 801 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_OFFSET })

Definition at line 786 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_MASK   0xfu

Definition at line 784 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_OFFSET   0

Definition at line 785 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_OFFSET })

Definition at line 790 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_MASK   0xfu

Definition at line 788 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_OFFSET   4

Definition at line 789 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_REG_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_5_REG_OFFSET   0xd8

Definition at line 782 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_REG_RESVAL

#define RRAM_CTRL_INFO_PAGE_CFG_5_REG_RESVAL   0x99999u

Definition at line 783 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET })

Definition at line 798 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_MASK   0xfu

Definition at line 796 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET   12

Definition at line 797 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_OFFSET })

Definition at line 794 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_MASK   0xfu

Definition at line 792 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_OFFSET   8

Definition at line 793 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_OFFSET })

Definition at line 826 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_MASK   0xfu

Definition at line 824 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_OFFSET   16

Definition at line 825 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_OFFSET })

Definition at line 810 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_MASK   0xfu

Definition at line 808 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_OFFSET   0

Definition at line 809 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_OFFSET })

Definition at line 814 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_MASK   0xfu

Definition at line 812 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_OFFSET   4

Definition at line 813 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_REG_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_6_REG_OFFSET   0xdc

Definition at line 806 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_REG_RESVAL

#define RRAM_CTRL_INFO_PAGE_CFG_6_REG_RESVAL   0x99999u

Definition at line 807 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET })

Definition at line 822 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_MASK   0xfu

Definition at line 820 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET   12

Definition at line 821 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_OFFSET })

Definition at line 818 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_MASK   0xfu

Definition at line 816 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_OFFSET   8

Definition at line 817 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_OFFSET })

Definition at line 850 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_MASK   0xfu

Definition at line 848 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_OFFSET   16

Definition at line 849 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_OFFSET })

Definition at line 834 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_MASK   0xfu

Definition at line 832 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_OFFSET   0

Definition at line 833 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_OFFSET })

Definition at line 838 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_MASK   0xfu

Definition at line 836 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_OFFSET   4

Definition at line 837 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_REG_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_7_REG_OFFSET   0xe0

Definition at line 830 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_REG_RESVAL

#define RRAM_CTRL_INFO_PAGE_CFG_7_REG_RESVAL   0x99999u

Definition at line 831 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET })

Definition at line 846 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_MASK   0xfu

Definition at line 844 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET   12

Definition at line 845 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_FIELD

#define RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_OFFSET })

Definition at line 842 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_MASK

#define RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_MASK   0xfu

Definition at line 840 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_OFFSET

#define RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_OFFSET   8

Definition at line 841 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_ECC_EN_FIELD_WIDTH

#define RRAM_CTRL_INFO_PAGE_CFG_ECC_EN_FIELD_WIDTH   4

Definition at line 658 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_EN_FIELD_WIDTH

#define RRAM_CTRL_INFO_PAGE_CFG_EN_FIELD_WIDTH   4

Definition at line 654 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_MULTIREG_COUNT

#define RRAM_CTRL_INFO_PAGE_CFG_MULTIREG_COUNT   8

Definition at line 659 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_RD_EN_FIELD_WIDTH

#define RRAM_CTRL_INFO_PAGE_CFG_RD_EN_FIELD_WIDTH   4

Definition at line 655 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH

#define RRAM_CTRL_INFO_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH   4

Definition at line 657 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_PAGE_CFG_WR_EN_FIELD_WIDTH

#define RRAM_CTRL_INFO_PAGE_CFG_WR_EN_FIELD_WIDTH   4

Definition at line 656 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_0_REG_OFFSET

#define RRAM_CTRL_INFO_REGWEN_0_REG_OFFSET   0xa4

Definition at line 612 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_0_REG_RESVAL

#define RRAM_CTRL_INFO_REGWEN_0_REG_RESVAL   0x1u

Definition at line 613 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_0_REGION_0_BIT

#define RRAM_CTRL_INFO_REGWEN_0_REGION_0_BIT   0

Definition at line 614 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_ENABLED

#define RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_ENABLED   0x1

Definition at line 616 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_LOCKED

#define RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_LOCKED   0x0

Definition at line 615 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_1_REG_OFFSET

#define RRAM_CTRL_INFO_REGWEN_1_REG_OFFSET   0xa8

Definition at line 619 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_1_REG_RESVAL

#define RRAM_CTRL_INFO_REGWEN_1_REG_RESVAL   0x1u

Definition at line 620 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_1_REGION_1_BIT

#define RRAM_CTRL_INFO_REGWEN_1_REGION_1_BIT   0

Definition at line 621 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_2_REG_OFFSET

#define RRAM_CTRL_INFO_REGWEN_2_REG_OFFSET   0xac

Definition at line 624 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_2_REG_RESVAL

#define RRAM_CTRL_INFO_REGWEN_2_REG_RESVAL   0x1u

Definition at line 625 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_2_REGION_2_BIT

#define RRAM_CTRL_INFO_REGWEN_2_REGION_2_BIT   0

Definition at line 626 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_3_REG_OFFSET

#define RRAM_CTRL_INFO_REGWEN_3_REG_OFFSET   0xb0

Definition at line 629 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_3_REG_RESVAL

#define RRAM_CTRL_INFO_REGWEN_3_REG_RESVAL   0x1u

Definition at line 630 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_3_REGION_3_BIT

#define RRAM_CTRL_INFO_REGWEN_3_REGION_3_BIT   0

Definition at line 631 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_4_REG_OFFSET

#define RRAM_CTRL_INFO_REGWEN_4_REG_OFFSET   0xb4

Definition at line 634 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_4_REG_RESVAL

#define RRAM_CTRL_INFO_REGWEN_4_REG_RESVAL   0x1u

Definition at line 635 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_4_REGION_4_BIT

#define RRAM_CTRL_INFO_REGWEN_4_REGION_4_BIT   0

Definition at line 636 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_5_REG_OFFSET

#define RRAM_CTRL_INFO_REGWEN_5_REG_OFFSET   0xb8

Definition at line 639 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_5_REG_RESVAL

#define RRAM_CTRL_INFO_REGWEN_5_REG_RESVAL   0x1u

Definition at line 640 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_5_REGION_5_BIT

#define RRAM_CTRL_INFO_REGWEN_5_REGION_5_BIT   0

Definition at line 641 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_6_REG_OFFSET

#define RRAM_CTRL_INFO_REGWEN_6_REG_OFFSET   0xbc

Definition at line 644 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_6_REG_RESVAL

#define RRAM_CTRL_INFO_REGWEN_6_REG_RESVAL   0x1u

Definition at line 645 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_6_REGION_6_BIT

#define RRAM_CTRL_INFO_REGWEN_6_REGION_6_BIT   0

Definition at line 646 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_7_REG_OFFSET

#define RRAM_CTRL_INFO_REGWEN_7_REG_OFFSET   0xc0

Definition at line 649 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_7_REG_RESVAL

#define RRAM_CTRL_INFO_REGWEN_7_REG_RESVAL   0x1u

Definition at line 650 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_7_REGION_7_BIT

#define RRAM_CTRL_INFO_REGWEN_7_REGION_7_BIT   0

Definition at line 651 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_MULTIREG_COUNT

#define RRAM_CTRL_INFO_REGWEN_MULTIREG_COUNT   8

Definition at line 609 of file rram_ctrl_regs.h.

RRAM_CTRL_INFO_REGWEN_REGION_FIELD_WIDTH

#define RRAM_CTRL_INFO_REGWEN_REGION_FIELD_WIDTH   1

Definition at line 608 of file rram_ctrl_regs.h.

RRAM_CTRL_INIT_REG_OFFSET

#define RRAM_CTRL_INIT_REG_OFFSET   0x18

Definition at line 124 of file rram_ctrl_regs.h.

RRAM_CTRL_INIT_REG_RESVAL

#define RRAM_CTRL_INIT_REG_RESVAL   0x0u

Definition at line 125 of file rram_ctrl_regs.h.

RRAM_CTRL_INIT_VAL_BIT

#define RRAM_CTRL_INIT_VAL_BIT   0

Definition at line 126 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_COMMON_CORR1_ERR_BIT

#define RRAM_CTRL_INTR_COMMON_CORR1_ERR_BIT   5

Definition at line 61 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_COMMON_CORR2_ERR_BIT

#define RRAM_CTRL_INTR_COMMON_CORR2_ERR_BIT   6

Definition at line 62 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_COMMON_OP_DONE_BIT

#define RRAM_CTRL_INTR_COMMON_OP_DONE_BIT   4

Definition at line 60 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_COMMON_RD_FULL_BIT

#define RRAM_CTRL_INTR_COMMON_RD_FULL_BIT   2

Definition at line 58 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_COMMON_RD_LVL_BIT

#define RRAM_CTRL_INTR_COMMON_RD_LVL_BIT   3

Definition at line 59 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_COMMON_WR_EMPTY_BIT

#define RRAM_CTRL_INTR_COMMON_WR_EMPTY_BIT   0

Definition at line 56 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_COMMON_WR_LVL_BIT

#define RRAM_CTRL_INTR_COMMON_WR_LVL_BIT   1

Definition at line 57 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_ENABLE_CORR1_ERR_BIT

#define RRAM_CTRL_INTR_ENABLE_CORR1_ERR_BIT   5

Definition at line 83 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_ENABLE_CORR2_ERR_BIT

#define RRAM_CTRL_INTR_ENABLE_CORR2_ERR_BIT   6

Definition at line 84 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_ENABLE_OP_DONE_BIT

#define RRAM_CTRL_INTR_ENABLE_OP_DONE_BIT   4

Definition at line 82 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_ENABLE_RD_FULL_BIT

#define RRAM_CTRL_INTR_ENABLE_RD_FULL_BIT   2

Definition at line 80 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_ENABLE_RD_LVL_BIT

#define RRAM_CTRL_INTR_ENABLE_RD_LVL_BIT   3

Definition at line 81 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_ENABLE_REG_OFFSET

#define RRAM_CTRL_INTR_ENABLE_REG_OFFSET   0x4

Definition at line 76 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_ENABLE_REG_RESVAL

#define RRAM_CTRL_INTR_ENABLE_REG_RESVAL   0x0u

Definition at line 77 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_ENABLE_WR_EMPTY_BIT

#define RRAM_CTRL_INTR_ENABLE_WR_EMPTY_BIT   0

Definition at line 78 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_ENABLE_WR_LVL_BIT

#define RRAM_CTRL_INTR_ENABLE_WR_LVL_BIT   1

Definition at line 79 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_STATE_CORR1_ERR_BIT

#define RRAM_CTRL_INTR_STATE_CORR1_ERR_BIT   5

Definition at line 72 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_STATE_CORR2_ERR_BIT

#define RRAM_CTRL_INTR_STATE_CORR2_ERR_BIT   6

Definition at line 73 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_STATE_OP_DONE_BIT

#define RRAM_CTRL_INTR_STATE_OP_DONE_BIT   4

Definition at line 71 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_STATE_RD_FULL_BIT

#define RRAM_CTRL_INTR_STATE_RD_FULL_BIT   2

Definition at line 69 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_STATE_RD_LVL_BIT

#define RRAM_CTRL_INTR_STATE_RD_LVL_BIT   3

Definition at line 70 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_STATE_REG_OFFSET

#define RRAM_CTRL_INTR_STATE_REG_OFFSET   0x0

Definition at line 65 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_STATE_REG_RESVAL

#define RRAM_CTRL_INTR_STATE_REG_RESVAL   0x3u

Definition at line 66 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_STATE_WR_EMPTY_BIT

#define RRAM_CTRL_INTR_STATE_WR_EMPTY_BIT   0

Definition at line 67 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_STATE_WR_LVL_BIT

#define RRAM_CTRL_INTR_STATE_WR_LVL_BIT   1

Definition at line 68 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_TEST_CORR1_ERR_BIT

#define RRAM_CTRL_INTR_TEST_CORR1_ERR_BIT   5

Definition at line 94 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_TEST_CORR2_ERR_BIT

#define RRAM_CTRL_INTR_TEST_CORR2_ERR_BIT   6

Definition at line 95 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_TEST_OP_DONE_BIT

#define RRAM_CTRL_INTR_TEST_OP_DONE_BIT   4

Definition at line 93 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_TEST_RD_FULL_BIT

#define RRAM_CTRL_INTR_TEST_RD_FULL_BIT   2

Definition at line 91 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_TEST_RD_LVL_BIT

#define RRAM_CTRL_INTR_TEST_RD_LVL_BIT   3

Definition at line 92 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_TEST_REG_OFFSET

#define RRAM_CTRL_INTR_TEST_REG_OFFSET   0x8

Definition at line 87 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_TEST_REG_RESVAL

#define RRAM_CTRL_INTR_TEST_REG_RESVAL   0x0u

Definition at line 88 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_TEST_WR_EMPTY_BIT

#define RRAM_CTRL_INTR_TEST_WR_EMPTY_BIT   0

Definition at line 89 of file rram_ctrl_regs.h.

RRAM_CTRL_INTR_TEST_WR_LVL_BIT

#define RRAM_CTRL_INTR_TEST_WR_LVL_BIT   1

Definition at line 90 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_0_BASE_0_FIELD

#define RRAM_CTRL_MP_REGION_0_BASE_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_0_BASE_0_MASK, .index = RRAM_CTRL_MP_REGION_0_BASE_0_OFFSET })

Definition at line 472 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_0_BASE_0_MASK

#define RRAM_CTRL_MP_REGION_0_BASE_0_MASK   0xfffu

Definition at line 470 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_0_BASE_0_OFFSET

#define RRAM_CTRL_MP_REGION_0_BASE_0_OFFSET   0

Definition at line 471 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_0_REG_OFFSET

#define RRAM_CTRL_MP_REGION_0_REG_OFFSET   0x78

Definition at line 468 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_0_REG_RESVAL

#define RRAM_CTRL_MP_REGION_0_REG_RESVAL   0x0u

Definition at line 469 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_0_SIZE_0_FIELD

#define RRAM_CTRL_MP_REGION_0_SIZE_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_0_SIZE_0_MASK, .index = RRAM_CTRL_MP_REGION_0_SIZE_0_OFFSET })

Definition at line 476 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_0_SIZE_0_MASK

#define RRAM_CTRL_MP_REGION_0_SIZE_0_MASK   0xfffu

Definition at line 474 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_0_SIZE_0_OFFSET

#define RRAM_CTRL_MP_REGION_0_SIZE_0_OFFSET   12

Definition at line 475 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_1_BASE_1_FIELD

#define RRAM_CTRL_MP_REGION_1_BASE_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_1_BASE_1_MASK, .index = RRAM_CTRL_MP_REGION_1_BASE_1_OFFSET })

Definition at line 484 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_1_BASE_1_MASK

#define RRAM_CTRL_MP_REGION_1_BASE_1_MASK   0xfffu

Definition at line 482 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_1_BASE_1_OFFSET

#define RRAM_CTRL_MP_REGION_1_BASE_1_OFFSET   0

Definition at line 483 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_1_REG_OFFSET

#define RRAM_CTRL_MP_REGION_1_REG_OFFSET   0x7c

Definition at line 480 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_1_REG_RESVAL

#define RRAM_CTRL_MP_REGION_1_REG_RESVAL   0x0u

Definition at line 481 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_1_SIZE_1_FIELD

#define RRAM_CTRL_MP_REGION_1_SIZE_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_1_SIZE_1_MASK, .index = RRAM_CTRL_MP_REGION_1_SIZE_1_OFFSET })

Definition at line 488 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_1_SIZE_1_MASK

#define RRAM_CTRL_MP_REGION_1_SIZE_1_MASK   0xfffu

Definition at line 486 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_1_SIZE_1_OFFSET

#define RRAM_CTRL_MP_REGION_1_SIZE_1_OFFSET   12

Definition at line 487 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_2_BASE_2_FIELD

#define RRAM_CTRL_MP_REGION_2_BASE_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_2_BASE_2_MASK, .index = RRAM_CTRL_MP_REGION_2_BASE_2_OFFSET })

Definition at line 496 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_2_BASE_2_MASK

#define RRAM_CTRL_MP_REGION_2_BASE_2_MASK   0xfffu

Definition at line 494 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_2_BASE_2_OFFSET

#define RRAM_CTRL_MP_REGION_2_BASE_2_OFFSET   0

Definition at line 495 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_2_REG_OFFSET

#define RRAM_CTRL_MP_REGION_2_REG_OFFSET   0x80

Definition at line 492 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_2_REG_RESVAL

#define RRAM_CTRL_MP_REGION_2_REG_RESVAL   0x0u

Definition at line 493 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_2_SIZE_2_FIELD

#define RRAM_CTRL_MP_REGION_2_SIZE_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_2_SIZE_2_MASK, .index = RRAM_CTRL_MP_REGION_2_SIZE_2_OFFSET })

Definition at line 500 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_2_SIZE_2_MASK

#define RRAM_CTRL_MP_REGION_2_SIZE_2_MASK   0xfffu

Definition at line 498 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_2_SIZE_2_OFFSET

#define RRAM_CTRL_MP_REGION_2_SIZE_2_OFFSET   12

Definition at line 499 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_3_BASE_3_FIELD

#define RRAM_CTRL_MP_REGION_3_BASE_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_3_BASE_3_MASK, .index = RRAM_CTRL_MP_REGION_3_BASE_3_OFFSET })

Definition at line 508 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_3_BASE_3_MASK

#define RRAM_CTRL_MP_REGION_3_BASE_3_MASK   0xfffu

Definition at line 506 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_3_BASE_3_OFFSET

#define RRAM_CTRL_MP_REGION_3_BASE_3_OFFSET   0

Definition at line 507 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_3_REG_OFFSET

#define RRAM_CTRL_MP_REGION_3_REG_OFFSET   0x84

Definition at line 504 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_3_REG_RESVAL

#define RRAM_CTRL_MP_REGION_3_REG_RESVAL   0x0u

Definition at line 505 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_3_SIZE_3_FIELD

#define RRAM_CTRL_MP_REGION_3_SIZE_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_3_SIZE_3_MASK, .index = RRAM_CTRL_MP_REGION_3_SIZE_3_OFFSET })

Definition at line 512 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_3_SIZE_3_MASK

#define RRAM_CTRL_MP_REGION_3_SIZE_3_MASK   0xfffu

Definition at line 510 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_3_SIZE_3_OFFSET

#define RRAM_CTRL_MP_REGION_3_SIZE_3_OFFSET   12

Definition at line 511 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_4_BASE_4_FIELD

#define RRAM_CTRL_MP_REGION_4_BASE_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_4_BASE_4_MASK, .index = RRAM_CTRL_MP_REGION_4_BASE_4_OFFSET })

Definition at line 520 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_4_BASE_4_MASK

#define RRAM_CTRL_MP_REGION_4_BASE_4_MASK   0xfffu

Definition at line 518 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_4_BASE_4_OFFSET

#define RRAM_CTRL_MP_REGION_4_BASE_4_OFFSET   0

Definition at line 519 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_4_REG_OFFSET

#define RRAM_CTRL_MP_REGION_4_REG_OFFSET   0x88

Definition at line 516 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_4_REG_RESVAL

#define RRAM_CTRL_MP_REGION_4_REG_RESVAL   0x0u

Definition at line 517 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_4_SIZE_4_FIELD

#define RRAM_CTRL_MP_REGION_4_SIZE_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_4_SIZE_4_MASK, .index = RRAM_CTRL_MP_REGION_4_SIZE_4_OFFSET })

Definition at line 524 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_4_SIZE_4_MASK

#define RRAM_CTRL_MP_REGION_4_SIZE_4_MASK   0xfffu

Definition at line 522 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_4_SIZE_4_OFFSET

#define RRAM_CTRL_MP_REGION_4_SIZE_4_OFFSET   12

Definition at line 523 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_5_BASE_5_FIELD

#define RRAM_CTRL_MP_REGION_5_BASE_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_5_BASE_5_MASK, .index = RRAM_CTRL_MP_REGION_5_BASE_5_OFFSET })

Definition at line 532 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_5_BASE_5_MASK

#define RRAM_CTRL_MP_REGION_5_BASE_5_MASK   0xfffu

Definition at line 530 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_5_BASE_5_OFFSET

#define RRAM_CTRL_MP_REGION_5_BASE_5_OFFSET   0

Definition at line 531 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_5_REG_OFFSET

#define RRAM_CTRL_MP_REGION_5_REG_OFFSET   0x8c

Definition at line 528 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_5_REG_RESVAL

#define RRAM_CTRL_MP_REGION_5_REG_RESVAL   0x0u

Definition at line 529 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_5_SIZE_5_FIELD

#define RRAM_CTRL_MP_REGION_5_SIZE_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_5_SIZE_5_MASK, .index = RRAM_CTRL_MP_REGION_5_SIZE_5_OFFSET })

Definition at line 536 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_5_SIZE_5_MASK

#define RRAM_CTRL_MP_REGION_5_SIZE_5_MASK   0xfffu

Definition at line 534 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_5_SIZE_5_OFFSET

#define RRAM_CTRL_MP_REGION_5_SIZE_5_OFFSET   12

Definition at line 535 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_6_BASE_6_FIELD

#define RRAM_CTRL_MP_REGION_6_BASE_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_6_BASE_6_MASK, .index = RRAM_CTRL_MP_REGION_6_BASE_6_OFFSET })

Definition at line 544 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_6_BASE_6_MASK

#define RRAM_CTRL_MP_REGION_6_BASE_6_MASK   0xfffu

Definition at line 542 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_6_BASE_6_OFFSET

#define RRAM_CTRL_MP_REGION_6_BASE_6_OFFSET   0

Definition at line 543 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_6_REG_OFFSET

#define RRAM_CTRL_MP_REGION_6_REG_OFFSET   0x90

Definition at line 540 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_6_REG_RESVAL

#define RRAM_CTRL_MP_REGION_6_REG_RESVAL   0x0u

Definition at line 541 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_6_SIZE_6_FIELD

#define RRAM_CTRL_MP_REGION_6_SIZE_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_6_SIZE_6_MASK, .index = RRAM_CTRL_MP_REGION_6_SIZE_6_OFFSET })

Definition at line 548 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_6_SIZE_6_MASK

#define RRAM_CTRL_MP_REGION_6_SIZE_6_MASK   0xfffu

Definition at line 546 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_6_SIZE_6_OFFSET

#define RRAM_CTRL_MP_REGION_6_SIZE_6_OFFSET   12

Definition at line 547 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_7_BASE_7_FIELD

#define RRAM_CTRL_MP_REGION_7_BASE_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_7_BASE_7_MASK, .index = RRAM_CTRL_MP_REGION_7_BASE_7_OFFSET })

Definition at line 556 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_7_BASE_7_MASK

#define RRAM_CTRL_MP_REGION_7_BASE_7_MASK   0xfffu

Definition at line 554 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_7_BASE_7_OFFSET

#define RRAM_CTRL_MP_REGION_7_BASE_7_OFFSET   0

Definition at line 555 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_7_REG_OFFSET

#define RRAM_CTRL_MP_REGION_7_REG_OFFSET   0x94

Definition at line 552 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_7_REG_RESVAL

#define RRAM_CTRL_MP_REGION_7_REG_RESVAL   0x0u

Definition at line 553 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_7_SIZE_7_FIELD

#define RRAM_CTRL_MP_REGION_7_SIZE_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_7_SIZE_7_MASK, .index = RRAM_CTRL_MP_REGION_7_SIZE_7_OFFSET })

Definition at line 560 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_7_SIZE_7_MASK

#define RRAM_CTRL_MP_REGION_7_SIZE_7_MASK   0xfffu

Definition at line 558 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_7_SIZE_7_OFFSET

#define RRAM_CTRL_MP_REGION_7_SIZE_7_OFFSET   12

Definition at line 559 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_8_BASE_8_FIELD

#define RRAM_CTRL_MP_REGION_8_BASE_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_8_BASE_8_MASK, .index = RRAM_CTRL_MP_REGION_8_BASE_8_OFFSET })

Definition at line 568 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_8_BASE_8_MASK

#define RRAM_CTRL_MP_REGION_8_BASE_8_MASK   0xfffu

Definition at line 566 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_8_BASE_8_OFFSET

#define RRAM_CTRL_MP_REGION_8_BASE_8_OFFSET   0

Definition at line 567 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_8_REG_OFFSET

#define RRAM_CTRL_MP_REGION_8_REG_OFFSET   0x98

Definition at line 564 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_8_REG_RESVAL

#define RRAM_CTRL_MP_REGION_8_REG_RESVAL   0x0u

Definition at line 565 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_8_SIZE_8_FIELD

#define RRAM_CTRL_MP_REGION_8_SIZE_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_8_SIZE_8_MASK, .index = RRAM_CTRL_MP_REGION_8_SIZE_8_OFFSET })

Definition at line 572 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_8_SIZE_8_MASK

#define RRAM_CTRL_MP_REGION_8_SIZE_8_MASK   0xfffu

Definition at line 570 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_8_SIZE_8_OFFSET

#define RRAM_CTRL_MP_REGION_8_SIZE_8_OFFSET   12

Definition at line 571 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_9_BASE_9_FIELD

#define RRAM_CTRL_MP_REGION_9_BASE_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_9_BASE_9_MASK, .index = RRAM_CTRL_MP_REGION_9_BASE_9_OFFSET })

Definition at line 580 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_9_BASE_9_MASK

#define RRAM_CTRL_MP_REGION_9_BASE_9_MASK   0xfffu

Definition at line 578 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_9_BASE_9_OFFSET

#define RRAM_CTRL_MP_REGION_9_BASE_9_OFFSET   0

Definition at line 579 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_9_REG_OFFSET

#define RRAM_CTRL_MP_REGION_9_REG_OFFSET   0x9c

Definition at line 576 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_9_REG_RESVAL

#define RRAM_CTRL_MP_REGION_9_REG_RESVAL   0x0u

Definition at line 577 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_9_SIZE_9_FIELD

#define RRAM_CTRL_MP_REGION_9_SIZE_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_9_SIZE_9_MASK, .index = RRAM_CTRL_MP_REGION_9_SIZE_9_OFFSET })

Definition at line 584 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_9_SIZE_9_MASK

#define RRAM_CTRL_MP_REGION_9_SIZE_9_MASK   0xfffu

Definition at line 582 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_9_SIZE_9_OFFSET

#define RRAM_CTRL_MP_REGION_9_SIZE_9_OFFSET   12

Definition at line 583 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_BASE_FIELD_WIDTH

#define RRAM_CTRL_MP_REGION_BASE_FIELD_WIDTH   12

Definition at line 463 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD

#define RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET })

Definition at line 243 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK

#define RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK   0xfu

Definition at line 241 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET   16

Definition at line 242 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_EN_0_FIELD

#define RRAM_CTRL_MP_REGION_CFG_0_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_EN_0_OFFSET })

Definition at line 227 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_EN_0_MASK

#define RRAM_CTRL_MP_REGION_CFG_0_EN_0_MASK   0xfu

Definition at line 225 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_EN_0_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_0_EN_0_OFFSET   0

Definition at line 226 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD

#define RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET })

Definition at line 231 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK

#define RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK   0xfu

Definition at line 229 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET   4

Definition at line 230 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_0_REG_OFFSET   0x50

Definition at line 223 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_0_REG_RESVAL   0x99999u

Definition at line 224 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD

#define RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET })

Definition at line 239 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK

#define RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK   0xfu

Definition at line 237 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET   12

Definition at line 238 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_FIELD

#define RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_OFFSET })

Definition at line 235 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_MASK

#define RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_MASK   0xfu

Definition at line 233 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_OFFSET   8

Definition at line 234 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_FIELD

#define RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET })

Definition at line 267 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK

#define RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK   0xfu

Definition at line 265 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET   16

Definition at line 266 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_EN_1_FIELD

#define RRAM_CTRL_MP_REGION_CFG_1_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_EN_1_OFFSET })

Definition at line 251 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_EN_1_MASK

#define RRAM_CTRL_MP_REGION_CFG_1_EN_1_MASK   0xfu

Definition at line 249 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_EN_1_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_1_EN_1_OFFSET   0

Definition at line 250 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_FIELD

#define RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET })

Definition at line 255 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK

#define RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK   0xfu

Definition at line 253 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET   4

Definition at line 254 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_1_REG_OFFSET   0x54

Definition at line 247 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_1_REG_RESVAL   0x99999u

Definition at line 248 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_FIELD

#define RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET })

Definition at line 263 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK

#define RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK   0xfu

Definition at line 261 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET   12

Definition at line 262 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_FIELD

#define RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_OFFSET })

Definition at line 259 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_MASK

#define RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_MASK   0xfu

Definition at line 257 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_OFFSET   8

Definition at line 258 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_FIELD

#define RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET })

Definition at line 291 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK

#define RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK   0xfu

Definition at line 289 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET   16

Definition at line 290 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_EN_2_FIELD

#define RRAM_CTRL_MP_REGION_CFG_2_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_EN_2_OFFSET })

Definition at line 275 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_EN_2_MASK

#define RRAM_CTRL_MP_REGION_CFG_2_EN_2_MASK   0xfu

Definition at line 273 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_EN_2_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_2_EN_2_OFFSET   0

Definition at line 274 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_FIELD

#define RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET })

Definition at line 279 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK

#define RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK   0xfu

Definition at line 277 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET   4

Definition at line 278 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_2_REG_OFFSET   0x58

Definition at line 271 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_2_REG_RESVAL   0x99999u

Definition at line 272 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_FIELD

#define RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET })

Definition at line 287 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK

#define RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK   0xfu

Definition at line 285 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET   12

Definition at line 286 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_FIELD

#define RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_OFFSET })

Definition at line 283 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_MASK

#define RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_MASK   0xfu

Definition at line 281 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_OFFSET   8

Definition at line 282 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_FIELD

#define RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET })

Definition at line 315 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK

#define RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK   0xfu

Definition at line 313 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET   16

Definition at line 314 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_EN_3_FIELD

#define RRAM_CTRL_MP_REGION_CFG_3_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_EN_3_OFFSET })

Definition at line 299 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_EN_3_MASK

#define RRAM_CTRL_MP_REGION_CFG_3_EN_3_MASK   0xfu

Definition at line 297 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_EN_3_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_3_EN_3_OFFSET   0

Definition at line 298 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_FIELD

#define RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET })

Definition at line 303 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK

#define RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK   0xfu

Definition at line 301 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET   4

Definition at line 302 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_3_REG_OFFSET   0x5c

Definition at line 295 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_3_REG_RESVAL   0x99999u

Definition at line 296 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_FIELD

#define RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET })

Definition at line 311 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK

#define RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK   0xfu

Definition at line 309 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET   12

Definition at line 310 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_FIELD

#define RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_OFFSET })

Definition at line 307 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_MASK

#define RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_MASK   0xfu

Definition at line 305 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_OFFSET   8

Definition at line 306 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_FIELD

#define RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET })

Definition at line 339 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK

#define RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK   0xfu

Definition at line 337 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET   16

Definition at line 338 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_EN_4_FIELD

#define RRAM_CTRL_MP_REGION_CFG_4_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_EN_4_OFFSET })

Definition at line 323 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_EN_4_MASK

#define RRAM_CTRL_MP_REGION_CFG_4_EN_4_MASK   0xfu

Definition at line 321 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_EN_4_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_4_EN_4_OFFSET   0

Definition at line 322 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_FIELD

#define RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET })

Definition at line 327 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK

#define RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK   0xfu

Definition at line 325 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET   4

Definition at line 326 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_4_REG_OFFSET   0x60

Definition at line 319 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_4_REG_RESVAL   0x99999u

Definition at line 320 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_FIELD

#define RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET })

Definition at line 335 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK

#define RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK   0xfu

Definition at line 333 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET   12

Definition at line 334 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_FIELD

#define RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_OFFSET })

Definition at line 331 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_MASK

#define RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_MASK   0xfu

Definition at line 329 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_OFFSET   8

Definition at line 330 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_FIELD

#define RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET })

Definition at line 363 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK

#define RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK   0xfu

Definition at line 361 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET   16

Definition at line 362 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_EN_5_FIELD

#define RRAM_CTRL_MP_REGION_CFG_5_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_EN_5_OFFSET })

Definition at line 347 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_EN_5_MASK

#define RRAM_CTRL_MP_REGION_CFG_5_EN_5_MASK   0xfu

Definition at line 345 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_EN_5_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_5_EN_5_OFFSET   0

Definition at line 346 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_FIELD

#define RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET })

Definition at line 351 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK

#define RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK   0xfu

Definition at line 349 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET   4

Definition at line 350 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_5_REG_OFFSET   0x64

Definition at line 343 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_5_REG_RESVAL   0x99999u

Definition at line 344 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_FIELD

#define RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET })

Definition at line 359 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK

#define RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK   0xfu

Definition at line 357 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET   12

Definition at line 358 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_FIELD

#define RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_OFFSET })

Definition at line 355 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_MASK

#define RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_MASK   0xfu

Definition at line 353 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_OFFSET   8

Definition at line 354 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_FIELD

#define RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET })

Definition at line 387 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK

#define RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK   0xfu

Definition at line 385 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET   16

Definition at line 386 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_EN_6_FIELD

#define RRAM_CTRL_MP_REGION_CFG_6_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_EN_6_OFFSET })

Definition at line 371 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_EN_6_MASK

#define RRAM_CTRL_MP_REGION_CFG_6_EN_6_MASK   0xfu

Definition at line 369 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_EN_6_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_6_EN_6_OFFSET   0

Definition at line 370 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_FIELD

#define RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET })

Definition at line 375 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK

#define RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK   0xfu

Definition at line 373 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET   4

Definition at line 374 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_6_REG_OFFSET   0x68

Definition at line 367 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_6_REG_RESVAL   0x99999u

Definition at line 368 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_FIELD

#define RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET })

Definition at line 383 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK

#define RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK   0xfu

Definition at line 381 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET   12

Definition at line 382 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_FIELD

#define RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_OFFSET })

Definition at line 379 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_MASK

#define RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_MASK   0xfu

Definition at line 377 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_OFFSET   8

Definition at line 378 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_FIELD

#define RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET })

Definition at line 411 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK

#define RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK   0xfu

Definition at line 409 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET   16

Definition at line 410 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_EN_7_FIELD

#define RRAM_CTRL_MP_REGION_CFG_7_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_EN_7_OFFSET })

Definition at line 395 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_EN_7_MASK

#define RRAM_CTRL_MP_REGION_CFG_7_EN_7_MASK   0xfu

Definition at line 393 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_EN_7_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_7_EN_7_OFFSET   0

Definition at line 394 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_FIELD

#define RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET })

Definition at line 399 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK

#define RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK   0xfu

Definition at line 397 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET   4

Definition at line 398 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_7_REG_OFFSET   0x6c

Definition at line 391 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_7_REG_RESVAL   0x99999u

Definition at line 392 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_FIELD

#define RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET })

Definition at line 407 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK

#define RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK   0xfu

Definition at line 405 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET   12

Definition at line 406 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_FIELD

#define RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_OFFSET })

Definition at line 403 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_MASK

#define RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_MASK   0xfu

Definition at line 401 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_OFFSET   8

Definition at line 402 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_FIELD

#define RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_OFFSET })

Definition at line 435 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_MASK

#define RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_MASK   0xfu

Definition at line 433 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_OFFSET   16

Definition at line 434 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_EN_8_FIELD

#define RRAM_CTRL_MP_REGION_CFG_8_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_EN_8_OFFSET })

Definition at line 419 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_EN_8_MASK

#define RRAM_CTRL_MP_REGION_CFG_8_EN_8_MASK   0xfu

Definition at line 417 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_EN_8_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_8_EN_8_OFFSET   0

Definition at line 418 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_FIELD

#define RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_OFFSET })

Definition at line 423 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_MASK

#define RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_MASK   0xfu

Definition at line 421 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_OFFSET   4

Definition at line 422 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_8_REG_OFFSET   0x70

Definition at line 415 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_8_REG_RESVAL   0x99999u

Definition at line 416 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_FIELD

#define RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_OFFSET })

Definition at line 431 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_MASK

#define RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_MASK   0xfu

Definition at line 429 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_OFFSET   12

Definition at line 430 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_FIELD

#define RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_OFFSET })

Definition at line 427 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_MASK

#define RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_MASK   0xfu

Definition at line 425 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_OFFSET   8

Definition at line 426 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_FIELD

#define RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_OFFSET })

Definition at line 459 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_MASK

#define RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_MASK   0xfu

Definition at line 457 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_OFFSET   16

Definition at line 458 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_EN_9_FIELD

#define RRAM_CTRL_MP_REGION_CFG_9_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_EN_9_OFFSET })

Definition at line 443 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_EN_9_MASK

#define RRAM_CTRL_MP_REGION_CFG_9_EN_9_MASK   0xfu

Definition at line 441 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_EN_9_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_9_EN_9_OFFSET   0

Definition at line 442 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_FIELD

#define RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_OFFSET })

Definition at line 447 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_MASK

#define RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_MASK   0xfu

Definition at line 445 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_OFFSET   4

Definition at line 446 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_REG_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_9_REG_OFFSET   0x74

Definition at line 439 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_REG_RESVAL

#define RRAM_CTRL_MP_REGION_CFG_9_REG_RESVAL   0x99999u

Definition at line 440 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_FIELD

#define RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_OFFSET })

Definition at line 455 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_MASK

#define RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_MASK   0xfu

Definition at line 453 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_OFFSET   12

Definition at line 454 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_FIELD

#define RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_FIELD    ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_OFFSET })

Definition at line 451 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_MASK

#define RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_MASK   0xfu

Definition at line 449 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_OFFSET

#define RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_OFFSET   8

Definition at line 450 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_ECC_EN_FIELD_WIDTH

#define RRAM_CTRL_MP_REGION_CFG_ECC_EN_FIELD_WIDTH   4

Definition at line 219 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_EN_FIELD_WIDTH

#define RRAM_CTRL_MP_REGION_CFG_EN_FIELD_WIDTH   4

Definition at line 215 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_MULTIREG_COUNT

#define RRAM_CTRL_MP_REGION_CFG_MULTIREG_COUNT   10

Definition at line 220 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_RD_EN_FIELD_WIDTH

#define RRAM_CTRL_MP_REGION_CFG_RD_EN_FIELD_WIDTH   4

Definition at line 216 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_SCRAMBLE_EN_FIELD_WIDTH

#define RRAM_CTRL_MP_REGION_CFG_SCRAMBLE_EN_FIELD_WIDTH   4

Definition at line 218 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_CFG_WR_EN_FIELD_WIDTH

#define RRAM_CTRL_MP_REGION_CFG_WR_EN_FIELD_WIDTH   4

Definition at line 217 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_MULTIREG_COUNT

#define RRAM_CTRL_MP_REGION_MULTIREG_COUNT   10

Definition at line 465 of file rram_ctrl_regs.h.

RRAM_CTRL_MP_REGION_SIZE_FIELD_WIDTH

#define RRAM_CTRL_MP_REGION_SIZE_FIELD_WIDTH   12

Definition at line 464 of file rram_ctrl_regs.h.

RRAM_CTRL_OP_STATUS_DONE_BIT

#define RRAM_CTRL_OP_STATUS_DONE_BIT   0

Definition at line 1886 of file rram_ctrl_regs.h.

RRAM_CTRL_OP_STATUS_ERR_BIT

#define RRAM_CTRL_OP_STATUS_ERR_BIT   1

Definition at line 1887 of file rram_ctrl_regs.h.

RRAM_CTRL_OP_STATUS_REG_OFFSET

#define RRAM_CTRL_OP_STATUS_REG_OFFSET   0x278

Definition at line 1884 of file rram_ctrl_regs.h.

RRAM_CTRL_OP_STATUS_REG_RESVAL

#define RRAM_CTRL_OP_STATUS_REG_RESVAL   0x0u

Definition at line 1885 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_BYTES_PER_PAGE

#define RRAM_CTRL_PARAM_BYTES_PER_PAGE   512

Definition at line 47 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_BYTES_PER_WORD

#define RRAM_CTRL_PARAM_BYTES_PER_WORD   16

Definition at line 44 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_EXEC_EN

#define RRAM_CTRL_PARAM_EXEC_EN   2724870391

Definition at line 20 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_NUM_ALERTS

#define RRAM_CTRL_PARAM_NUM_ALERTS   5

Definition at line 50 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_NUM_DATA_PAGES

#define RRAM_CTRL_PARAM_NUM_DATA_PAGES   4096

Definition at line 35 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_NUM_EMUL_INFO_REGIONS

#define RRAM_CTRL_PARAM_NUM_EMUL_INFO_REGIONS   2

Definition at line 29 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_NUM_EMUL_INFO_SUBREGIONS

#define RRAM_CTRL_PARAM_NUM_EMUL_INFO_SUBREGIONS   24

Definition at line 32 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_NUM_INFO_PAGES

#define RRAM_CTRL_PARAM_NUM_INFO_PAGES   8

Definition at line 26 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_NUM_OTP_PAGES

#define RRAM_CTRL_PARAM_NUM_OTP_PAGES   6

Definition at line 38 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_NUM_REGIONS

#define RRAM_CTRL_PARAM_NUM_REGIONS   10

Definition at line 23 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_REG_WIDTH

#define RRAM_CTRL_PARAM_REG_WIDTH   32

Definition at line 53 of file rram_ctrl_regs.h.

RRAM_CTRL_PARAM_WORDS_PER_PAGE

#define RRAM_CTRL_PARAM_WORDS_PER_PAGE   32

Definition at line 41 of file rram_ctrl_regs.h.

RRAM_CTRL_PHY_STATUS_INIT_DONE_BIT

#define RRAM_CTRL_PHY_STATUS_INIT_DONE_BIT   1

Definition at line 1988 of file rram_ctrl_regs.h.

RRAM_CTRL_PHY_STATUS_REG_OFFSET

#define RRAM_CTRL_PHY_STATUS_REG_OFFSET   0x2a0

Definition at line 1985 of file rram_ctrl_regs.h.

RRAM_CTRL_PHY_STATUS_REG_RESVAL

#define RRAM_CTRL_PHY_STATUS_REG_RESVAL   0x0u

Definition at line 1986 of file rram_ctrl_regs.h.

RRAM_CTRL_PHY_STATUS_WR_BUSY_BIT

#define RRAM_CTRL_PHY_STATUS_WR_BUSY_BIT   0

Definition at line 1987 of file rram_ctrl_regs.h.

RRAM_CTRL_RD_FIFO_REG_OFFSET

#define RRAM_CTRL_RD_FIFO_REG_OFFSET   0x2b8

Definition at line 2029 of file rram_ctrl_regs.h.

RRAM_CTRL_RD_FIFO_SIZE_BYTES

#define RRAM_CTRL_RD_FIFO_SIZE_BYTES   4

Definition at line 2031 of file rram_ctrl_regs.h.

RRAM_CTRL_RD_FIFO_SIZE_WORDS

#define RRAM_CTRL_RD_FIFO_SIZE_WORDS   1

Definition at line 2030 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_0_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_0_REG_OFFSET   0x28

Definition at line 163 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_0_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_0_REG_RESVAL   0x1u

Definition at line 164 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT   0

Definition at line 165 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_ENABLED

#define RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_ENABLED   0x1

Definition at line 167 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_LOCKED

#define RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_LOCKED   0x0

Definition at line 166 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_1_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_1_REG_OFFSET   0x2c

Definition at line 170 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_1_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_1_REG_RESVAL   0x1u

Definition at line 171 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_1_REGION_1_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_1_REGION_1_BIT   0

Definition at line 172 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_2_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_2_REG_OFFSET   0x30

Definition at line 175 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_2_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_2_REG_RESVAL   0x1u

Definition at line 176 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_2_REGION_2_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_2_REGION_2_BIT   0

Definition at line 177 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_3_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_3_REG_OFFSET   0x34

Definition at line 180 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_3_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_3_REG_RESVAL   0x1u

Definition at line 181 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_3_REGION_3_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_3_REGION_3_BIT   0

Definition at line 182 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_4_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_4_REG_OFFSET   0x38

Definition at line 185 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_4_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_4_REG_RESVAL   0x1u

Definition at line 186 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_4_REGION_4_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_4_REGION_4_BIT   0

Definition at line 187 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_5_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_5_REG_OFFSET   0x3c

Definition at line 190 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_5_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_5_REG_RESVAL   0x1u

Definition at line 191 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_5_REGION_5_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_5_REGION_5_BIT   0

Definition at line 192 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_6_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_6_REG_OFFSET   0x40

Definition at line 195 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_6_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_6_REG_RESVAL   0x1u

Definition at line 196 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_6_REGION_6_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_6_REGION_6_BIT   0

Definition at line 197 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_7_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_7_REG_OFFSET   0x44

Definition at line 200 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_7_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_7_REG_RESVAL   0x1u

Definition at line 201 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_7_REGION_7_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_7_REGION_7_BIT   0

Definition at line 202 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_8_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_8_REG_OFFSET   0x48

Definition at line 205 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_8_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_8_REG_RESVAL   0x1u

Definition at line 206 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_8_REGION_8_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_8_REGION_8_BIT   0

Definition at line 207 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_9_REG_OFFSET

#define RRAM_CTRL_REGION_CFG_REGWEN_9_REG_OFFSET   0x4c

Definition at line 210 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_9_REG_RESVAL

#define RRAM_CTRL_REGION_CFG_REGWEN_9_REG_RESVAL   0x1u

Definition at line 211 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_9_REGION_9_BIT

#define RRAM_CTRL_REGION_CFG_REGWEN_9_REGION_9_BIT   0

Definition at line 212 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_MULTIREG_COUNT

#define RRAM_CTRL_REGION_CFG_REGWEN_MULTIREG_COUNT   10

Definition at line 160 of file rram_ctrl_regs.h.

RRAM_CTRL_REGION_CFG_REGWEN_REGION_FIELD_WIDTH

#define RRAM_CTRL_REGION_CFG_REGWEN_REGION_FIELD_WIDTH   1

Definition at line 159 of file rram_ctrl_regs.h.

RRAM_CTRL_SCRATCH_REG_OFFSET

#define RRAM_CTRL_SCRATCH_REG_OFFSET   0x2a4

Definition at line 1991 of file rram_ctrl_regs.h.

RRAM_CTRL_SCRATCH_REG_RESVAL

#define RRAM_CTRL_SCRATCH_REG_RESVAL   0x0u

Definition at line 1992 of file rram_ctrl_regs.h.

RRAM_CTRL_STATUS_INIT_DONE_BIT

#define RRAM_CTRL_STATUS_INIT_DONE_BIT   4

Definition at line 1896 of file rram_ctrl_regs.h.

RRAM_CTRL_STATUS_KEYS_VALID_BIT

#define RRAM_CTRL_STATUS_KEYS_VALID_BIT   5

Definition at line 1897 of file rram_ctrl_regs.h.

RRAM_CTRL_STATUS_RD_EMPTY_BIT

#define RRAM_CTRL_STATUS_RD_EMPTY_BIT   1

Definition at line 1893 of file rram_ctrl_regs.h.

RRAM_CTRL_STATUS_RD_FULL_BIT

#define RRAM_CTRL_STATUS_RD_FULL_BIT   0

Definition at line 1892 of file rram_ctrl_regs.h.

RRAM_CTRL_STATUS_REG_OFFSET

#define RRAM_CTRL_STATUS_REG_OFFSET   0x27c

Definition at line 1890 of file rram_ctrl_regs.h.

RRAM_CTRL_STATUS_REG_RESVAL

#define RRAM_CTRL_STATUS_REG_RESVAL   0xau

Definition at line 1891 of file rram_ctrl_regs.h.

RRAM_CTRL_STATUS_WR_EMPTY_BIT

#define RRAM_CTRL_STATUS_WR_EMPTY_BIT   3

Definition at line 1895 of file rram_ctrl_regs.h.

RRAM_CTRL_STATUS_WR_FULL_BIT

#define RRAM_CTRL_STATUS_WR_FULL_BIT   2

Definition at line 1894 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_CTRL_CNT_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_CTRL_CNT_ERR_BIT   11

Definition at line 1921 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_CTRL_FIFO_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_CTRL_FIFO_ERR_BIT   12

Definition at line 1922 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_CTRL_FSM_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_CTRL_FSM_ERR_BIT   10

Definition at line 1920 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT   1

Definition at line 1911 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_LCMGR_INTG_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_LCMGR_INTG_ERR_BIT   2

Definition at line 1912 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_OTP_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_OTP_ERR_BIT   3

Definition at line 1913 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_OTP_INTG_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_OTP_INTG_ERR_BIT   4

Definition at line 1914 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_PHY_ARB_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_PHY_ARB_ERR_BIT   9

Definition at line 1919 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_PHY_CNT_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_PHY_CNT_ERR_BIT   8

Definition at line 1918 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_PHY_FIFO_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_PHY_FIFO_ERR_BIT   6

Definition at line 1916 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_PHY_FSM_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_PHY_FSM_ERR_BIT   7

Definition at line 1917 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_PHY_WR_INTG_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_PHY_WR_INTG_ERR_BIT   5

Definition at line 1915 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT

#define RRAM_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT   0

Definition at line 1910 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_REG_OFFSET

#define RRAM_CTRL_STD_FAULT_STATUS_REG_OFFSET   0x284

Definition at line 1908 of file rram_ctrl_regs.h.

RRAM_CTRL_STD_FAULT_STATUS_REG_RESVAL

#define RRAM_CTRL_STD_FAULT_STATUS_REG_RESVAL   0x0u

Definition at line 1909 of file rram_ctrl_regs.h.

RRAM_CTRL_WR_FIFO_REG_OFFSET

#define RRAM_CTRL_WR_FIFO_REG_OFFSET   0x2b4

Definition at line 2025 of file rram_ctrl_regs.h.

RRAM_CTRL_WR_FIFO_SIZE_BYTES

#define RRAM_CTRL_WR_FIFO_SIZE_BYTES   4

Definition at line 2027 of file rram_ctrl_regs.h.

RRAM_CTRL_WR_FIFO_SIZE_WORDS

#define RRAM_CTRL_WR_FIFO_SIZE_WORDS   1

Definition at line 2026 of file rram_ctrl_regs.h.