rram_ctrl_regs.h

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/**
 * @file
 * @brief Generated register defines for rram_ctrl
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _RRAM_CTRL_REG_DEFS_
#define _RRAM_CTRL_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Constant value that enables RRAM execution
#define RRAM_CTRL_PARAM_EXEC_EN 2724870391
 
// Number of configurable rram regions
#define RRAM_CTRL_PARAM_NUM_REGIONS 8
 
// Number of info pages
#define RRAM_CTRL_PARAM_NUM_INFO_PAGES 8
 
// Number of data pages
#define RRAM_CTRL_PARAM_NUM_DATA_PAGES 4096
 
// Number of words per page
#define RRAM_CTRL_PARAM_WORDS_PER_PAGE 32
 
// Number of bytes per word
#define RRAM_CTRL_PARAM_BYTES_PER_WORD 16
 
// Number of bytes per page
#define RRAM_CTRL_PARAM_BYTES_PER_PAGE 512
 
// Number of alerts
#define RRAM_CTRL_PARAM_NUM_ALERTS 5
 
// Register width
#define RRAM_CTRL_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define RRAM_CTRL_INTR_COMMON_WR_EMPTY_BIT 0
#define RRAM_CTRL_INTR_COMMON_WR_LVL_BIT 1
#define RRAM_CTRL_INTR_COMMON_RD_FULL_BIT 2
#define RRAM_CTRL_INTR_COMMON_RD_LVL_BIT 3
#define RRAM_CTRL_INTR_COMMON_OP_DONE_BIT 4
#define RRAM_CTRL_INTR_COMMON_CORR_ERR_BIT 5
 
// Interrupt State Register
#define RRAM_CTRL_INTR_STATE_REG_OFFSET 0x0
#define RRAM_CTRL_INTR_STATE_REG_RESVAL 0x3u
#define RRAM_CTRL_INTR_STATE_WR_EMPTY_BIT 0
#define RRAM_CTRL_INTR_STATE_WR_LVL_BIT 1
#define RRAM_CTRL_INTR_STATE_RD_FULL_BIT 2
#define RRAM_CTRL_INTR_STATE_RD_LVL_BIT 3
#define RRAM_CTRL_INTR_STATE_OP_DONE_BIT 4
#define RRAM_CTRL_INTR_STATE_CORR_ERR_BIT 5
 
// Interrupt Enable Register
#define RRAM_CTRL_INTR_ENABLE_REG_OFFSET 0x4
#define RRAM_CTRL_INTR_ENABLE_REG_RESVAL 0x0u
#define RRAM_CTRL_INTR_ENABLE_WR_EMPTY_BIT 0
#define RRAM_CTRL_INTR_ENABLE_WR_LVL_BIT 1
#define RRAM_CTRL_INTR_ENABLE_RD_FULL_BIT 2
#define RRAM_CTRL_INTR_ENABLE_RD_LVL_BIT 3
#define RRAM_CTRL_INTR_ENABLE_OP_DONE_BIT 4
#define RRAM_CTRL_INTR_ENABLE_CORR_ERR_BIT 5
 
// Interrupt Test Register
#define RRAM_CTRL_INTR_TEST_REG_OFFSET 0x8
#define RRAM_CTRL_INTR_TEST_REG_RESVAL 0x0u
#define RRAM_CTRL_INTR_TEST_WR_EMPTY_BIT 0
#define RRAM_CTRL_INTR_TEST_WR_LVL_BIT 1
#define RRAM_CTRL_INTR_TEST_RD_FULL_BIT 2
#define RRAM_CTRL_INTR_TEST_RD_LVL_BIT 3
#define RRAM_CTRL_INTR_TEST_OP_DONE_BIT 4
#define RRAM_CTRL_INTR_TEST_CORR_ERR_BIT 5
 
// Alert Test Register
#define RRAM_CTRL_ALERT_TEST_REG_OFFSET 0xc
#define RRAM_CTRL_ALERT_TEST_REG_RESVAL 0x0u
#define RRAM_CTRL_ALERT_TEST_RECOV_ERR_BIT 0
#define RRAM_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT 1
#define RRAM_CTRL_ALERT_TEST_FATAL_ERR_BIT 2
#define RRAM_CTRL_ALERT_TEST_FATAL_MACRO_ERR_BIT 3
#define RRAM_CTRL_ALERT_TEST_RECOV_MACRO_ERR_BIT 4
 
// Disable RRAM functionality
#define RRAM_CTRL_DIS_REG_OFFSET 0x10
#define RRAM_CTRL_DIS_REG_RESVAL 0x99u
#define RRAM_CTRL_DIS_SW_DIS_MASK 0xfu
#define RRAM_CTRL_DIS_SW_DIS_OFFSET 0
#define RRAM_CTRL_DIS_SW_DIS_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DIS_SW_DIS_MASK, .index = RRAM_CTRL_DIS_SW_DIS_OFFSET })
#define RRAM_CTRL_DIS_RELBL_ERR_FATAL_MASK 0xfu
#define RRAM_CTRL_DIS_RELBL_ERR_FATAL_OFFSET 4
#define RRAM_CTRL_DIS_RELBL_ERR_FATAL_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DIS_RELBL_ERR_FATAL_MASK, .index = RRAM_CTRL_DIS_RELBL_ERR_FATAL_OFFSET })
 
// Controls whether RRAM can be used for code execution fetches
#define RRAM_CTRL_EXEC_REG_OFFSET 0x14
#define RRAM_CTRL_EXEC_REG_RESVAL 0x0u
 
// Controller init register
#define RRAM_CTRL_INIT_REG_OFFSET 0x18
#define RRAM_CTRL_INIT_REG_RESVAL 0x0u
#define RRAM_CTRL_INIT_VAL_BIT 0
 
// Controls the configurability of the !!CONTROL register.
#define RRAM_CTRL_CTRL_REGWEN_REG_OFFSET 0x1c
#define RRAM_CTRL_CTRL_REGWEN_REG_RESVAL 0x1u
#define RRAM_CTRL_CTRL_REGWEN_EN_BIT 0
 
// Control register
#define RRAM_CTRL_CONTROL_REG_OFFSET 0x20
#define RRAM_CTRL_CONTROL_REG_RESVAL 0x0u
#define RRAM_CTRL_CONTROL_START_BIT 0
#define RRAM_CTRL_CONTROL_OP_MASK 0x3u
#define RRAM_CTRL_CONTROL_OP_OFFSET 4
#define RRAM_CTRL_CONTROL_OP_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CONTROL_OP_MASK, .index = RRAM_CTRL_CONTROL_OP_OFFSET })
#define RRAM_CTRL_CONTROL_OP_VALUE_READ 0x0
#define RRAM_CTRL_CONTROL_OP_VALUE_WRITE 0x1
#define RRAM_CTRL_CONTROL_OP_VALUE_REWRITE 0x2
#define RRAM_CTRL_CONTROL_PARTITION_BIT 8
#define RRAM_CTRL_CONTROL_NUM_MASK 0x3ffu
#define RRAM_CTRL_CONTROL_NUM_OFFSET 16
#define RRAM_CTRL_CONTROL_NUM_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CONTROL_NUM_MASK, .index = RRAM_CTRL_CONTROL_NUM_OFFSET })
 
// Address for RRAM operation
#define RRAM_CTRL_ADDR_REG_OFFSET 0x24
#define RRAM_CTRL_ADDR_REG_RESVAL 0x0u
#define RRAM_CTRL_ADDR_START_MASK 0x1fffffu
#define RRAM_CTRL_ADDR_START_OFFSET 0
#define RRAM_CTRL_ADDR_START_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_ADDR_START_MASK, .index = RRAM_CTRL_ADDR_START_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define RRAM_CTRL_REGION_CFG_REGWEN_REGION_FIELD_WIDTH 1
#define RRAM_CTRL_REGION_CFG_REGWEN_MULTIREG_COUNT 8
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REG_OFFSET 0x28
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT 0
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_LOCKED 0x0
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_ENABLED 0x1
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_1_REG_OFFSET 0x2c
#define RRAM_CTRL_REGION_CFG_REGWEN_1_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_1_REGION_1_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_2_REG_OFFSET 0x30
#define RRAM_CTRL_REGION_CFG_REGWEN_2_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_2_REGION_2_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_3_REG_OFFSET 0x34
#define RRAM_CTRL_REGION_CFG_REGWEN_3_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_3_REGION_3_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_4_REG_OFFSET 0x38
#define RRAM_CTRL_REGION_CFG_REGWEN_4_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_4_REGION_4_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_5_REG_OFFSET 0x3c
#define RRAM_CTRL_REGION_CFG_REGWEN_5_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_5_REGION_5_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_6_REG_OFFSET 0x40
#define RRAM_CTRL_REGION_CFG_REGWEN_6_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_6_REGION_6_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_7_REG_OFFSET 0x44
#define RRAM_CTRL_REGION_CFG_REGWEN_7_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_7_REGION_7_BIT 0
 
// Memory property configuration for data partition (common parameters)
#define RRAM_CTRL_MP_REGION_CFG_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_RD_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_WR_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_ECC_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_MULTIREG_COUNT 8
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_0_REG_OFFSET 0x48
#define RRAM_CTRL_MP_REGION_CFG_0_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_0_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_EN_0_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_EN_0_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_1_REG_OFFSET 0x4c
#define RRAM_CTRL_MP_REGION_CFG_1_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_1_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_EN_1_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_EN_1_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_2_REG_OFFSET 0x50
#define RRAM_CTRL_MP_REGION_CFG_2_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_2_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_EN_2_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_2_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_EN_2_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_3_REG_OFFSET 0x54
#define RRAM_CTRL_MP_REGION_CFG_3_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_3_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_EN_3_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_3_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_EN_3_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_4_REG_OFFSET 0x58
#define RRAM_CTRL_MP_REGION_CFG_4_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_4_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_EN_4_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_4_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_EN_4_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_5_REG_OFFSET 0x5c
#define RRAM_CTRL_MP_REGION_CFG_5_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_5_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_EN_5_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_5_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_EN_5_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_6_REG_OFFSET 0x60
#define RRAM_CTRL_MP_REGION_CFG_6_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_6_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_EN_6_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_6_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_EN_6_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_7_REG_OFFSET 0x64
#define RRAM_CTRL_MP_REGION_CFG_7_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_7_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_EN_7_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_7_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_EN_7_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET })
 
// Memory base and size configuration for data partition (common parameters)
#define RRAM_CTRL_MP_REGION_BASE_FIELD_WIDTH 12
#define RRAM_CTRL_MP_REGION_SIZE_FIELD_WIDTH 12
#define RRAM_CTRL_MP_REGION_MULTIREG_COUNT 8
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_0_REG_OFFSET 0x68
#define RRAM_CTRL_MP_REGION_0_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_0_BASE_0_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_0_BASE_0_OFFSET 0
#define RRAM_CTRL_MP_REGION_0_BASE_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_0_BASE_0_MASK, .index = RRAM_CTRL_MP_REGION_0_BASE_0_OFFSET })
#define RRAM_CTRL_MP_REGION_0_SIZE_0_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_0_SIZE_0_OFFSET 12
#define RRAM_CTRL_MP_REGION_0_SIZE_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_0_SIZE_0_MASK, .index = RRAM_CTRL_MP_REGION_0_SIZE_0_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_1_REG_OFFSET 0x6c
#define RRAM_CTRL_MP_REGION_1_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_1_BASE_1_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_1_BASE_1_OFFSET 0
#define RRAM_CTRL_MP_REGION_1_BASE_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_1_BASE_1_MASK, .index = RRAM_CTRL_MP_REGION_1_BASE_1_OFFSET })
#define RRAM_CTRL_MP_REGION_1_SIZE_1_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_1_SIZE_1_OFFSET 12
#define RRAM_CTRL_MP_REGION_1_SIZE_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_1_SIZE_1_MASK, .index = RRAM_CTRL_MP_REGION_1_SIZE_1_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_2_REG_OFFSET 0x70
#define RRAM_CTRL_MP_REGION_2_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_2_BASE_2_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_2_BASE_2_OFFSET 0
#define RRAM_CTRL_MP_REGION_2_BASE_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_2_BASE_2_MASK, .index = RRAM_CTRL_MP_REGION_2_BASE_2_OFFSET })
#define RRAM_CTRL_MP_REGION_2_SIZE_2_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_2_SIZE_2_OFFSET 12
#define RRAM_CTRL_MP_REGION_2_SIZE_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_2_SIZE_2_MASK, .index = RRAM_CTRL_MP_REGION_2_SIZE_2_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_3_REG_OFFSET 0x74
#define RRAM_CTRL_MP_REGION_3_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_3_BASE_3_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_3_BASE_3_OFFSET 0
#define RRAM_CTRL_MP_REGION_3_BASE_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_3_BASE_3_MASK, .index = RRAM_CTRL_MP_REGION_3_BASE_3_OFFSET })
#define RRAM_CTRL_MP_REGION_3_SIZE_3_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_3_SIZE_3_OFFSET 12
#define RRAM_CTRL_MP_REGION_3_SIZE_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_3_SIZE_3_MASK, .index = RRAM_CTRL_MP_REGION_3_SIZE_3_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_4_REG_OFFSET 0x78
#define RRAM_CTRL_MP_REGION_4_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_4_BASE_4_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_4_BASE_4_OFFSET 0
#define RRAM_CTRL_MP_REGION_4_BASE_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_4_BASE_4_MASK, .index = RRAM_CTRL_MP_REGION_4_BASE_4_OFFSET })
#define RRAM_CTRL_MP_REGION_4_SIZE_4_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_4_SIZE_4_OFFSET 12
#define RRAM_CTRL_MP_REGION_4_SIZE_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_4_SIZE_4_MASK, .index = RRAM_CTRL_MP_REGION_4_SIZE_4_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_5_REG_OFFSET 0x7c
#define RRAM_CTRL_MP_REGION_5_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_5_BASE_5_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_5_BASE_5_OFFSET 0
#define RRAM_CTRL_MP_REGION_5_BASE_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_5_BASE_5_MASK, .index = RRAM_CTRL_MP_REGION_5_BASE_5_OFFSET })
#define RRAM_CTRL_MP_REGION_5_SIZE_5_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_5_SIZE_5_OFFSET 12
#define RRAM_CTRL_MP_REGION_5_SIZE_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_5_SIZE_5_MASK, .index = RRAM_CTRL_MP_REGION_5_SIZE_5_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_6_REG_OFFSET 0x80
#define RRAM_CTRL_MP_REGION_6_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_6_BASE_6_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_6_BASE_6_OFFSET 0
#define RRAM_CTRL_MP_REGION_6_BASE_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_6_BASE_6_MASK, .index = RRAM_CTRL_MP_REGION_6_BASE_6_OFFSET })
#define RRAM_CTRL_MP_REGION_6_SIZE_6_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_6_SIZE_6_OFFSET 12
#define RRAM_CTRL_MP_REGION_6_SIZE_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_6_SIZE_6_MASK, .index = RRAM_CTRL_MP_REGION_6_SIZE_6_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_7_REG_OFFSET 0x84
#define RRAM_CTRL_MP_REGION_7_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_7_BASE_7_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_7_BASE_7_OFFSET 0
#define RRAM_CTRL_MP_REGION_7_BASE_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_7_BASE_7_MASK, .index = RRAM_CTRL_MP_REGION_7_BASE_7_OFFSET })
#define RRAM_CTRL_MP_REGION_7_SIZE_7_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_7_SIZE_7_OFFSET 12
#define RRAM_CTRL_MP_REGION_7_SIZE_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_7_SIZE_7_MASK, .index = RRAM_CTRL_MP_REGION_7_SIZE_7_OFFSET })
 
// Default region properties
#define RRAM_CTRL_DEFAULT_REGION_REG_OFFSET 0x88
#define RRAM_CTRL_DEFAULT_REGION_REG_RESVAL 0x9999u
#define RRAM_CTRL_DEFAULT_REGION_RD_EN_MASK 0xfu
#define RRAM_CTRL_DEFAULT_REGION_RD_EN_OFFSET 0
#define RRAM_CTRL_DEFAULT_REGION_RD_EN_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_RD_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_RD_EN_OFFSET })
#define RRAM_CTRL_DEFAULT_REGION_WR_EN_MASK 0xfu
#define RRAM_CTRL_DEFAULT_REGION_WR_EN_OFFSET 4
#define RRAM_CTRL_DEFAULT_REGION_WR_EN_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_WR_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_WR_EN_OFFSET })
#define RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK 0xfu
#define RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET 8
#define RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET })
#define RRAM_CTRL_DEFAULT_REGION_ECC_EN_MASK 0xfu
#define RRAM_CTRL_DEFAULT_REGION_ECC_EN_OFFSET 12
#define RRAM_CTRL_DEFAULT_REGION_ECC_EN_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_ECC_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_ECC_EN_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define RRAM_CTRL_INFO_REGWEN_REGION_FIELD_WIDTH 1
#define RRAM_CTRL_INFO_REGWEN_MULTIREG_COUNT 8
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_0_REG_OFFSET 0x8c
#define RRAM_CTRL_INFO_REGWEN_0_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_0_REGION_0_BIT 0
#define RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_LOCKED 0x0
#define RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_ENABLED 0x1
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_1_REG_OFFSET 0x90
#define RRAM_CTRL_INFO_REGWEN_1_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_1_REGION_1_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_2_REG_OFFSET 0x94
#define RRAM_CTRL_INFO_REGWEN_2_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_2_REGION_2_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_3_REG_OFFSET 0x98
#define RRAM_CTRL_INFO_REGWEN_3_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_3_REGION_3_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_4_REG_OFFSET 0x9c
#define RRAM_CTRL_INFO_REGWEN_4_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_4_REGION_4_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_5_REG_OFFSET 0xa0
#define RRAM_CTRL_INFO_REGWEN_5_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_5_REGION_5_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_6_REG_OFFSET 0xa4
#define RRAM_CTRL_INFO_REGWEN_6_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_6_REGION_6_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_7_REG_OFFSET 0xa8
#define RRAM_CTRL_INFO_REGWEN_7_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_7_REGION_7_BIT 0
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_RD_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_WR_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_ECC_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_MULTIREG_COUNT 8
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_0_REG_OFFSET 0xac
#define RRAM_CTRL_INFO_PAGE_CFG_0_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_1_REG_OFFSET 0xb0
#define RRAM_CTRL_INFO_PAGE_CFG_1_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_2_REG_OFFSET 0xb4
#define RRAM_CTRL_INFO_PAGE_CFG_2_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_3_REG_OFFSET 0xb8
#define RRAM_CTRL_INFO_PAGE_CFG_3_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_4_REG_OFFSET 0xbc
#define RRAM_CTRL_INFO_PAGE_CFG_4_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_5_REG_OFFSET 0xc0
#define RRAM_CTRL_INFO_PAGE_CFG_5_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_6_REG_OFFSET 0xc4
#define RRAM_CTRL_INFO_PAGE_CFG_6_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_7_REG_OFFSET 0xc8
#define RRAM_CTRL_INFO_PAGE_CFG_7_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_OFFSET })
 
// HW interface info configuration rule overrides
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_OFFSET 0xcc
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_RESVAL 0x99u
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK 0xfu
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET 0
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK, .index = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET })
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK 0xfu
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET 4
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK, .index = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET })
 
// RRAM Operation Status
#define RRAM_CTRL_OP_STATUS_REG_OFFSET 0xd0
#define RRAM_CTRL_OP_STATUS_REG_RESVAL 0x0u
#define RRAM_CTRL_OP_STATUS_DONE_BIT 0
#define RRAM_CTRL_OP_STATUS_ERR_BIT 1
 
// RRAM Controller Status
#define RRAM_CTRL_STATUS_REG_OFFSET 0xd4
#define RRAM_CTRL_STATUS_REG_RESVAL 0xau
#define RRAM_CTRL_STATUS_RD_FULL_BIT 0
#define RRAM_CTRL_STATUS_RD_EMPTY_BIT 1
#define RRAM_CTRL_STATUS_WR_FULL_BIT 2
#define RRAM_CTRL_STATUS_WR_EMPTY_BIT 3
#define RRAM_CTRL_STATUS_INIT_DONE_BIT 4
#define RRAM_CTRL_STATUS_KEYS_VALID_BIT 5
 
// RRAM error code register.
#define RRAM_CTRL_ERR_CODE_REG_OFFSET 0xd8
#define RRAM_CTRL_ERR_CODE_REG_RESVAL 0x0u
#define RRAM_CTRL_ERR_CODE_OP_ERR_BIT 0
#define RRAM_CTRL_ERR_CODE_MP_ERR_BIT 1
#define RRAM_CTRL_ERR_CODE_RD_ERR_BIT 2
#define RRAM_CTRL_ERR_CODE_WR_ERR_BIT 3
 
// This register tabulates standard fault status of the RRAM.
#define RRAM_CTRL_STD_FAULT_STATUS_REG_OFFSET 0xdc
#define RRAM_CTRL_STD_FAULT_STATUS_REG_RESVAL 0x0u
#define RRAM_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT 0
#define RRAM_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT 1
#define RRAM_CTRL_STD_FAULT_STATUS_LCMGR_INTG_ERR_BIT 2
#define RRAM_CTRL_STD_FAULT_STATUS_OTP_ERR_BIT 3
#define RRAM_CTRL_STD_FAULT_STATUS_OTP_INTG_ERR_BIT 4
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_WR_INTG_ERR_BIT 5
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_FIFO_ERR_BIT 6
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_FSM_ERR_BIT 7
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_CNT_ERR_BIT 8
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_ARB_ERR_BIT 9
#define RRAM_CTRL_STD_FAULT_STATUS_CTRL_FSM_ERR_BIT 10
#define RRAM_CTRL_STD_FAULT_STATUS_CTRL_CNT_ERR_BIT 11
#define RRAM_CTRL_STD_FAULT_STATUS_CTRL_FIFO_ERR_BIT 12
 
// This register tabulates customized fault status of the RRAM.
#define RRAM_CTRL_FAULT_STATUS_REG_OFFSET 0xe0
#define RRAM_CTRL_FAULT_STATUS_REG_RESVAL 0x0u
#define RRAM_CTRL_FAULT_STATUS_LCMGR_OP_ERR_BIT 0
#define RRAM_CTRL_FAULT_STATUS_LCMGR_MP_ERR_BIT 1
#define RRAM_CTRL_FAULT_STATUS_LCMGR_RD_ERR_BIT 2
#define RRAM_CTRL_FAULT_STATUS_LCMGR_WR_ERR_BIT 3
#define RRAM_CTRL_FAULT_STATUS_OTP_OP_ERR_BIT 4
#define RRAM_CTRL_FAULT_STATUS_OTP_MP_ERR_BIT 5
#define RRAM_CTRL_FAULT_STATUS_OTP_RD_ERR_BIT 6
#define RRAM_CTRL_FAULT_STATUS_OTP_WR_ERR_BIT 7
#define RRAM_CTRL_FAULT_STATUS_SEED_ERR_BIT 8
#define RRAM_CTRL_FAULT_STATUS_PHY_RELBL_ERR_BIT 9
#define RRAM_CTRL_FAULT_STATUS_PHY_RD_INTG_ERR_BIT 10
#define RRAM_CTRL_FAULT_STATUS_PHY_RD_CTRL_ERR_BIT 11
#define RRAM_CTRL_FAULT_STATUS_SPURIOUS_DONE_BIT 12
#define RRAM_CTRL_FAULT_STATUS_HOST_GNT_ERR_BIT 13
 
// Synchronous error address
#define RRAM_CTRL_ERR_ADDR_REG_OFFSET 0xe4
#define RRAM_CTRL_ERR_ADDR_REG_RESVAL 0x0u
#define RRAM_CTRL_ERR_ADDR_ERR_ADDR_MASK 0x1fffffu
#define RRAM_CTRL_ERR_ADDR_ERR_ADDR_OFFSET 0
#define RRAM_CTRL_ERR_ADDR_ERR_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_ERR_ADDR_ERR_ADDR_MASK, .index = RRAM_CTRL_ERR_ADDR_ERR_ADDR_OFFSET })
 
// Count of correctable ECC errors
#define RRAM_CTRL_CORR_ERR_CNT_REG_OFFSET 0xe8
#define RRAM_CTRL_CORR_ERR_CNT_REG_RESVAL 0x0u
#define RRAM_CTRL_CORR_ERR_CNT_VAL_MASK 0xffu
#define RRAM_CTRL_CORR_ERR_CNT_VAL_OFFSET 0
#define RRAM_CTRL_CORR_ERR_CNT_VAL_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR_ERR_CNT_VAL_MASK, .index = RRAM_CTRL_CORR_ERR_CNT_VAL_OFFSET })
 
// Last address that was successfully corrected
#define RRAM_CTRL_CORR_ERR_LOC_REG_OFFSET 0xec
#define RRAM_CTRL_CORR_ERR_LOC_REG_RESVAL 0x0u
#define RRAM_CTRL_CORR_ERR_LOC_ADDR_MASK 0x1fffffu
#define RRAM_CTRL_CORR_ERR_LOC_ADDR_OFFSET 0
#define RRAM_CTRL_CORR_ERR_LOC_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR_ERR_LOC_ADDR_MASK, .index = RRAM_CTRL_CORR_ERR_LOC_ADDR_OFFSET })
#define RRAM_CTRL_CORR_ERR_LOC_PART_BIT 24
 
// RRAM Phy Status
#define RRAM_CTRL_PHY_STATUS_REG_OFFSET 0xf0
#define RRAM_CTRL_PHY_STATUS_REG_RESVAL 0x0u
#define RRAM_CTRL_PHY_STATUS_WR_BUSY_BIT 0
#define RRAM_CTRL_PHY_STATUS_INIT_DONE_BIT 1
 
// RRAM Controller Scratch
#define RRAM_CTRL_SCRATCH_REG_OFFSET 0xf4
#define RRAM_CTRL_SCRATCH_REG_RESVAL 0x0u
 
// Programmable depth where FIFOs should generate interrupts
#define RRAM_CTRL_FIFO_LVL_REG_OFFSET 0xf8
#define RRAM_CTRL_FIFO_LVL_REG_RESVAL 0xf0fu
#define RRAM_CTRL_FIFO_LVL_WR_MASK 0x1fu
#define RRAM_CTRL_FIFO_LVL_WR_OFFSET 0
#define RRAM_CTRL_FIFO_LVL_WR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_FIFO_LVL_WR_MASK, .index = RRAM_CTRL_FIFO_LVL_WR_OFFSET })
#define RRAM_CTRL_FIFO_LVL_RD_MASK 0x1fu
#define RRAM_CTRL_FIFO_LVL_RD_OFFSET 8
#define RRAM_CTRL_FIFO_LVL_RD_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_FIFO_LVL_RD_MASK, .index = RRAM_CTRL_FIFO_LVL_RD_OFFSET })
 
// Clears RRAM controller FIFOs
#define RRAM_CTRL_FIFO_CLR_REG_OFFSET 0xfc
#define RRAM_CTRL_FIFO_CLR_REG_RESVAL 0x0u
#define RRAM_CTRL_FIFO_CLR_WR_BIT 0
#define RRAM_CTRL_FIFO_CLR_RD_BIT 1
 
// Current write and read fifo level
#define RRAM_CTRL_CURR_FIFO_LVL_REG_OFFSET 0x100
#define RRAM_CTRL_CURR_FIFO_LVL_REG_RESVAL 0x0u
#define RRAM_CTRL_CURR_FIFO_LVL_WR_MASK 0x1fu
#define RRAM_CTRL_CURR_FIFO_LVL_WR_OFFSET 0
#define RRAM_CTRL_CURR_FIFO_LVL_WR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CURR_FIFO_LVL_WR_MASK, .index = RRAM_CTRL_CURR_FIFO_LVL_WR_OFFSET })
#define RRAM_CTRL_CURR_FIFO_LVL_RD_MASK 0x1fu
#define RRAM_CTRL_CURR_FIFO_LVL_RD_OFFSET 8
#define RRAM_CTRL_CURR_FIFO_LVL_RD_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CURR_FIFO_LVL_RD_MASK, .index = RRAM_CTRL_CURR_FIFO_LVL_RD_OFFSET })
 
// Memory area: RRAM write FIFO.
#define RRAM_CTRL_WR_FIFO_REG_OFFSET 0x104
#define RRAM_CTRL_WR_FIFO_SIZE_WORDS 1
#define RRAM_CTRL_WR_FIFO_SIZE_BYTES 4
// Memory area: RRAM read FIFO.
#define RRAM_CTRL_RD_FIFO_REG_OFFSET 0x108
#define RRAM_CTRL_RD_FIFO_SIZE_WORDS 1
#define RRAM_CTRL_RD_FIFO_SIZE_BYTES 4
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _RRAM_CTRL_REG_DEFS_
// End generated register defines for rram_ctrl