rram_ctrl_regs.h

Go to the documentation of this file.

/**
 * @file
 * @brief Generated register defines for rram_ctrl
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _RRAM_CTRL_REG_DEFS_
#define _RRAM_CTRL_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Constant value that enables RRAM execution
#define RRAM_CTRL_PARAM_EXEC_EN 2724870391
 
// Number of configurable rram regions
#define RRAM_CTRL_PARAM_NUM_REGIONS 10
 
// Number of info pages
#define RRAM_CTRL_PARAM_NUM_INFO_PAGES 8
 
// Number of emulated info page regions (windows) on the data partition
#define RRAM_CTRL_PARAM_NUM_EMUL_INFO_REGIONS 2
 
// Total number of emulated info subregions across all emulated info regions
#define RRAM_CTRL_PARAM_NUM_EMUL_INFO_SUBREGIONS 24
 
// Number of data pages
#define RRAM_CTRL_PARAM_NUM_DATA_PAGES 4096
 
// Number of data pages reserved for OTP
#define RRAM_CTRL_PARAM_NUM_OTP_PAGES 6
 
// Number of words per page
#define RRAM_CTRL_PARAM_WORDS_PER_PAGE 32
 
// Number of bytes per word
#define RRAM_CTRL_PARAM_BYTES_PER_WORD 16
 
// Number of bytes per page
#define RRAM_CTRL_PARAM_BYTES_PER_PAGE 512
 
// Number of alerts
#define RRAM_CTRL_PARAM_NUM_ALERTS 5
 
// Register width
#define RRAM_CTRL_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define RRAM_CTRL_INTR_COMMON_WR_EMPTY_BIT 0
#define RRAM_CTRL_INTR_COMMON_WR_LVL_BIT 1
#define RRAM_CTRL_INTR_COMMON_RD_FULL_BIT 2
#define RRAM_CTRL_INTR_COMMON_RD_LVL_BIT 3
#define RRAM_CTRL_INTR_COMMON_OP_DONE_BIT 4
#define RRAM_CTRL_INTR_COMMON_CORR1_ERR_BIT 5
#define RRAM_CTRL_INTR_COMMON_CORR2_ERR_BIT 6
 
// Interrupt State Register
#define RRAM_CTRL_INTR_STATE_REG_OFFSET 0x0
#define RRAM_CTRL_INTR_STATE_REG_RESVAL 0x3u
#define RRAM_CTRL_INTR_STATE_WR_EMPTY_BIT 0
#define RRAM_CTRL_INTR_STATE_WR_LVL_BIT 1
#define RRAM_CTRL_INTR_STATE_RD_FULL_BIT 2
#define RRAM_CTRL_INTR_STATE_RD_LVL_BIT 3
#define RRAM_CTRL_INTR_STATE_OP_DONE_BIT 4
#define RRAM_CTRL_INTR_STATE_CORR1_ERR_BIT 5
#define RRAM_CTRL_INTR_STATE_CORR2_ERR_BIT 6
 
// Interrupt Enable Register
#define RRAM_CTRL_INTR_ENABLE_REG_OFFSET 0x4
#define RRAM_CTRL_INTR_ENABLE_REG_RESVAL 0x0u
#define RRAM_CTRL_INTR_ENABLE_WR_EMPTY_BIT 0
#define RRAM_CTRL_INTR_ENABLE_WR_LVL_BIT 1
#define RRAM_CTRL_INTR_ENABLE_RD_FULL_BIT 2
#define RRAM_CTRL_INTR_ENABLE_RD_LVL_BIT 3
#define RRAM_CTRL_INTR_ENABLE_OP_DONE_BIT 4
#define RRAM_CTRL_INTR_ENABLE_CORR1_ERR_BIT 5
#define RRAM_CTRL_INTR_ENABLE_CORR2_ERR_BIT 6
 
// Interrupt Test Register
#define RRAM_CTRL_INTR_TEST_REG_OFFSET 0x8
#define RRAM_CTRL_INTR_TEST_REG_RESVAL 0x0u
#define RRAM_CTRL_INTR_TEST_WR_EMPTY_BIT 0
#define RRAM_CTRL_INTR_TEST_WR_LVL_BIT 1
#define RRAM_CTRL_INTR_TEST_RD_FULL_BIT 2
#define RRAM_CTRL_INTR_TEST_RD_LVL_BIT 3
#define RRAM_CTRL_INTR_TEST_OP_DONE_BIT 4
#define RRAM_CTRL_INTR_TEST_CORR1_ERR_BIT 5
#define RRAM_CTRL_INTR_TEST_CORR2_ERR_BIT 6
 
// Alert Test Register
#define RRAM_CTRL_ALERT_TEST_REG_OFFSET 0xc
#define RRAM_CTRL_ALERT_TEST_REG_RESVAL 0x80000000u
#define RRAM_CTRL_ALERT_TEST_RECOV_ERR_BIT 0
#define RRAM_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT 1
#define RRAM_CTRL_ALERT_TEST_FATAL_ERR_BIT 2
#define RRAM_CTRL_ALERT_TEST_FATAL_MACRO_ERR_BIT 3
#define RRAM_CTRL_ALERT_TEST_RECOV_MACRO_ERR_BIT 4
#define RRAM_CTRL_ALERT_TEST_REGWEN_BIT 31
 
// Disable RRAM functionality
#define RRAM_CTRL_DIS_REG_OFFSET 0x10
#define RRAM_CTRL_DIS_REG_RESVAL 0x99u
#define RRAM_CTRL_DIS_SW_DIS_MASK 0xfu
#define RRAM_CTRL_DIS_SW_DIS_OFFSET 0
#define RRAM_CTRL_DIS_SW_DIS_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DIS_SW_DIS_MASK, .index = RRAM_CTRL_DIS_SW_DIS_OFFSET })
#define RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_MASK 0xfu
#define RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_OFFSET 4
#define RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_MASK, .index = RRAM_CTRL_DIS_LOCAL_ESC_RELBL_ERR_OFFSET })
 
// Controls whether RRAM can be used for code execution fetches
#define RRAM_CTRL_EXEC_REG_OFFSET 0x14
#define RRAM_CTRL_EXEC_REG_RESVAL 0x0u
 
// Controller init register
#define RRAM_CTRL_INIT_REG_OFFSET 0x18
#define RRAM_CTRL_INIT_REG_RESVAL 0x0u
#define RRAM_CTRL_INIT_VAL_BIT 0
 
// Controls the configurability of the !!CONTROL register.
#define RRAM_CTRL_CTRL_REGWEN_REG_OFFSET 0x1c
#define RRAM_CTRL_CTRL_REGWEN_REG_RESVAL 0x1u
#define RRAM_CTRL_CTRL_REGWEN_EN_BIT 0
 
// Control register
#define RRAM_CTRL_CONTROL_REG_OFFSET 0x20
#define RRAM_CTRL_CONTROL_REG_RESVAL 0x0u
#define RRAM_CTRL_CONTROL_START_BIT 0
#define RRAM_CTRL_CONTROL_OP_MASK 0x3u
#define RRAM_CTRL_CONTROL_OP_OFFSET 4
#define RRAM_CTRL_CONTROL_OP_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CONTROL_OP_MASK, .index = RRAM_CTRL_CONTROL_OP_OFFSET })
#define RRAM_CTRL_CONTROL_OP_VALUE_READ 0x0
#define RRAM_CTRL_CONTROL_OP_VALUE_WRITE 0x1
#define RRAM_CTRL_CONTROL_OP_VALUE_REWRITE 0x2
#define RRAM_CTRL_CONTROL_PARTITION_BIT 8
#define RRAM_CTRL_CONTROL_NUM_MASK 0x3ffu
#define RRAM_CTRL_CONTROL_NUM_OFFSET 16
#define RRAM_CTRL_CONTROL_NUM_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CONTROL_NUM_MASK, .index = RRAM_CTRL_CONTROL_NUM_OFFSET })
 
// Address for RRAM operation
#define RRAM_CTRL_ADDR_REG_OFFSET 0x24
#define RRAM_CTRL_ADDR_REG_RESVAL 0x0u
#define RRAM_CTRL_ADDR_START_MASK 0x1fffffu
#define RRAM_CTRL_ADDR_START_OFFSET 0
#define RRAM_CTRL_ADDR_START_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_ADDR_START_MASK, .index = RRAM_CTRL_ADDR_START_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define RRAM_CTRL_REGION_CFG_REGWEN_REGION_FIELD_WIDTH 1
#define RRAM_CTRL_REGION_CFG_REGWEN_MULTIREG_COUNT 10
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REG_OFFSET 0x28
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT 0
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_LOCKED 0x0
#define RRAM_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_ENABLED 0x1
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_1_REG_OFFSET 0x2c
#define RRAM_CTRL_REGION_CFG_REGWEN_1_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_1_REGION_1_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_2_REG_OFFSET 0x30
#define RRAM_CTRL_REGION_CFG_REGWEN_2_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_2_REGION_2_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_3_REG_OFFSET 0x34
#define RRAM_CTRL_REGION_CFG_REGWEN_3_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_3_REGION_3_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_4_REG_OFFSET 0x38
#define RRAM_CTRL_REGION_CFG_REGWEN_4_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_4_REGION_4_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_5_REG_OFFSET 0x3c
#define RRAM_CTRL_REGION_CFG_REGWEN_5_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_5_REGION_5_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_6_REG_OFFSET 0x40
#define RRAM_CTRL_REGION_CFG_REGWEN_6_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_6_REGION_6_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_7_REG_OFFSET 0x44
#define RRAM_CTRL_REGION_CFG_REGWEN_7_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_7_REGION_7_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_8_REG_OFFSET 0x48
#define RRAM_CTRL_REGION_CFG_REGWEN_8_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_8_REGION_8_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_REGION_CFG_REGWEN_9_REG_OFFSET 0x4c
#define RRAM_CTRL_REGION_CFG_REGWEN_9_REG_RESVAL 0x1u
#define RRAM_CTRL_REGION_CFG_REGWEN_9_REGION_9_BIT 0
 
// Memory property configuration for data partition (common parameters)
#define RRAM_CTRL_MP_REGION_CFG_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_RD_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_WR_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_ECC_EN_FIELD_WIDTH 4
#define RRAM_CTRL_MP_REGION_CFG_MULTIREG_COUNT 10
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_0_REG_OFFSET 0x50
#define RRAM_CTRL_MP_REGION_CFG_0_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_0_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_EN_0_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_EN_0_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_WR_EN_0_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_1_REG_OFFSET 0x54
#define RRAM_CTRL_MP_REGION_CFG_1_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_1_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_EN_1_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_EN_1_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_WR_EN_1_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_2_REG_OFFSET 0x58
#define RRAM_CTRL_MP_REGION_CFG_2_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_2_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_EN_2_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_2_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_EN_2_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_WR_EN_2_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_3_REG_OFFSET 0x5c
#define RRAM_CTRL_MP_REGION_CFG_3_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_3_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_EN_3_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_3_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_EN_3_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_WR_EN_3_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_4_REG_OFFSET 0x60
#define RRAM_CTRL_MP_REGION_CFG_4_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_4_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_EN_4_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_4_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_EN_4_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_WR_EN_4_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_5_REG_OFFSET 0x64
#define RRAM_CTRL_MP_REGION_CFG_5_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_5_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_EN_5_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_5_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_EN_5_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_WR_EN_5_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_6_REG_OFFSET 0x68
#define RRAM_CTRL_MP_REGION_CFG_6_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_6_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_EN_6_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_6_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_EN_6_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_WR_EN_6_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_7_REG_OFFSET 0x6c
#define RRAM_CTRL_MP_REGION_CFG_7_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_7_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_EN_7_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_7_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_EN_7_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_WR_EN_7_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_8_REG_OFFSET 0x70
#define RRAM_CTRL_MP_REGION_CFG_8_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_8_EN_8_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_8_EN_8_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_8_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_EN_8_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_RD_EN_8_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_WR_EN_8_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_SCRAMBLE_EN_8_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_MASK, .index = RRAM_CTRL_MP_REGION_CFG_8_ECC_EN_8_OFFSET })
 
// Memory property configuration for data partition
#define RRAM_CTRL_MP_REGION_CFG_9_REG_OFFSET 0x74
#define RRAM_CTRL_MP_REGION_CFG_9_REG_RESVAL 0x99999u
#define RRAM_CTRL_MP_REGION_CFG_9_EN_9_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_9_EN_9_OFFSET 0
#define RRAM_CTRL_MP_REGION_CFG_9_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_EN_9_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_OFFSET 4
#define RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_RD_EN_9_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_OFFSET 8
#define RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_WR_EN_9_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_OFFSET 12
#define RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_SCRAMBLE_EN_9_OFFSET })
#define RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_MASK 0xfu
#define RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_OFFSET 16
#define RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_MASK, .index = RRAM_CTRL_MP_REGION_CFG_9_ECC_EN_9_OFFSET })
 
// Memory base and size configuration for data partition (common parameters)
#define RRAM_CTRL_MP_REGION_BASE_FIELD_WIDTH 12
#define RRAM_CTRL_MP_REGION_SIZE_FIELD_WIDTH 12
#define RRAM_CTRL_MP_REGION_MULTIREG_COUNT 10
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_0_REG_OFFSET 0x78
#define RRAM_CTRL_MP_REGION_0_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_0_BASE_0_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_0_BASE_0_OFFSET 0
#define RRAM_CTRL_MP_REGION_0_BASE_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_0_BASE_0_MASK, .index = RRAM_CTRL_MP_REGION_0_BASE_0_OFFSET })
#define RRAM_CTRL_MP_REGION_0_SIZE_0_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_0_SIZE_0_OFFSET 12
#define RRAM_CTRL_MP_REGION_0_SIZE_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_0_SIZE_0_MASK, .index = RRAM_CTRL_MP_REGION_0_SIZE_0_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_1_REG_OFFSET 0x7c
#define RRAM_CTRL_MP_REGION_1_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_1_BASE_1_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_1_BASE_1_OFFSET 0
#define RRAM_CTRL_MP_REGION_1_BASE_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_1_BASE_1_MASK, .index = RRAM_CTRL_MP_REGION_1_BASE_1_OFFSET })
#define RRAM_CTRL_MP_REGION_1_SIZE_1_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_1_SIZE_1_OFFSET 12
#define RRAM_CTRL_MP_REGION_1_SIZE_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_1_SIZE_1_MASK, .index = RRAM_CTRL_MP_REGION_1_SIZE_1_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_2_REG_OFFSET 0x80
#define RRAM_CTRL_MP_REGION_2_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_2_BASE_2_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_2_BASE_2_OFFSET 0
#define RRAM_CTRL_MP_REGION_2_BASE_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_2_BASE_2_MASK, .index = RRAM_CTRL_MP_REGION_2_BASE_2_OFFSET })
#define RRAM_CTRL_MP_REGION_2_SIZE_2_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_2_SIZE_2_OFFSET 12
#define RRAM_CTRL_MP_REGION_2_SIZE_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_2_SIZE_2_MASK, .index = RRAM_CTRL_MP_REGION_2_SIZE_2_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_3_REG_OFFSET 0x84
#define RRAM_CTRL_MP_REGION_3_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_3_BASE_3_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_3_BASE_3_OFFSET 0
#define RRAM_CTRL_MP_REGION_3_BASE_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_3_BASE_3_MASK, .index = RRAM_CTRL_MP_REGION_3_BASE_3_OFFSET })
#define RRAM_CTRL_MP_REGION_3_SIZE_3_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_3_SIZE_3_OFFSET 12
#define RRAM_CTRL_MP_REGION_3_SIZE_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_3_SIZE_3_MASK, .index = RRAM_CTRL_MP_REGION_3_SIZE_3_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_4_REG_OFFSET 0x88
#define RRAM_CTRL_MP_REGION_4_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_4_BASE_4_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_4_BASE_4_OFFSET 0
#define RRAM_CTRL_MP_REGION_4_BASE_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_4_BASE_4_MASK, .index = RRAM_CTRL_MP_REGION_4_BASE_4_OFFSET })
#define RRAM_CTRL_MP_REGION_4_SIZE_4_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_4_SIZE_4_OFFSET 12
#define RRAM_CTRL_MP_REGION_4_SIZE_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_4_SIZE_4_MASK, .index = RRAM_CTRL_MP_REGION_4_SIZE_4_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_5_REG_OFFSET 0x8c
#define RRAM_CTRL_MP_REGION_5_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_5_BASE_5_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_5_BASE_5_OFFSET 0
#define RRAM_CTRL_MP_REGION_5_BASE_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_5_BASE_5_MASK, .index = RRAM_CTRL_MP_REGION_5_BASE_5_OFFSET })
#define RRAM_CTRL_MP_REGION_5_SIZE_5_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_5_SIZE_5_OFFSET 12
#define RRAM_CTRL_MP_REGION_5_SIZE_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_5_SIZE_5_MASK, .index = RRAM_CTRL_MP_REGION_5_SIZE_5_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_6_REG_OFFSET 0x90
#define RRAM_CTRL_MP_REGION_6_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_6_BASE_6_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_6_BASE_6_OFFSET 0
#define RRAM_CTRL_MP_REGION_6_BASE_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_6_BASE_6_MASK, .index = RRAM_CTRL_MP_REGION_6_BASE_6_OFFSET })
#define RRAM_CTRL_MP_REGION_6_SIZE_6_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_6_SIZE_6_OFFSET 12
#define RRAM_CTRL_MP_REGION_6_SIZE_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_6_SIZE_6_MASK, .index = RRAM_CTRL_MP_REGION_6_SIZE_6_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_7_REG_OFFSET 0x94
#define RRAM_CTRL_MP_REGION_7_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_7_BASE_7_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_7_BASE_7_OFFSET 0
#define RRAM_CTRL_MP_REGION_7_BASE_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_7_BASE_7_MASK, .index = RRAM_CTRL_MP_REGION_7_BASE_7_OFFSET })
#define RRAM_CTRL_MP_REGION_7_SIZE_7_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_7_SIZE_7_OFFSET 12
#define RRAM_CTRL_MP_REGION_7_SIZE_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_7_SIZE_7_MASK, .index = RRAM_CTRL_MP_REGION_7_SIZE_7_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_8_REG_OFFSET 0x98
#define RRAM_CTRL_MP_REGION_8_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_8_BASE_8_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_8_BASE_8_OFFSET 0
#define RRAM_CTRL_MP_REGION_8_BASE_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_8_BASE_8_MASK, .index = RRAM_CTRL_MP_REGION_8_BASE_8_OFFSET })
#define RRAM_CTRL_MP_REGION_8_SIZE_8_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_8_SIZE_8_OFFSET 12
#define RRAM_CTRL_MP_REGION_8_SIZE_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_8_SIZE_8_MASK, .index = RRAM_CTRL_MP_REGION_8_SIZE_8_OFFSET })
 
// Memory base and size configuration for data partition
#define RRAM_CTRL_MP_REGION_9_REG_OFFSET 0x9c
#define RRAM_CTRL_MP_REGION_9_REG_RESVAL 0x0u
#define RRAM_CTRL_MP_REGION_9_BASE_9_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_9_BASE_9_OFFSET 0
#define RRAM_CTRL_MP_REGION_9_BASE_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_9_BASE_9_MASK, .index = RRAM_CTRL_MP_REGION_9_BASE_9_OFFSET })
#define RRAM_CTRL_MP_REGION_9_SIZE_9_MASK 0xfffu
#define RRAM_CTRL_MP_REGION_9_SIZE_9_OFFSET 12
#define RRAM_CTRL_MP_REGION_9_SIZE_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_MP_REGION_9_SIZE_9_MASK, .index = RRAM_CTRL_MP_REGION_9_SIZE_9_OFFSET })
 
// Default region properties
#define RRAM_CTRL_DEFAULT_REGION_REG_OFFSET 0xa0
#define RRAM_CTRL_DEFAULT_REGION_REG_RESVAL 0x9999u
#define RRAM_CTRL_DEFAULT_REGION_RD_EN_MASK 0xfu
#define RRAM_CTRL_DEFAULT_REGION_RD_EN_OFFSET 0
#define RRAM_CTRL_DEFAULT_REGION_RD_EN_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_RD_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_RD_EN_OFFSET })
#define RRAM_CTRL_DEFAULT_REGION_WR_EN_MASK 0xfu
#define RRAM_CTRL_DEFAULT_REGION_WR_EN_OFFSET 4
#define RRAM_CTRL_DEFAULT_REGION_WR_EN_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_WR_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_WR_EN_OFFSET })
#define RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK 0xfu
#define RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET 8
#define RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET })
#define RRAM_CTRL_DEFAULT_REGION_ECC_EN_MASK 0xfu
#define RRAM_CTRL_DEFAULT_REGION_ECC_EN_OFFSET 12
#define RRAM_CTRL_DEFAULT_REGION_ECC_EN_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_DEFAULT_REGION_ECC_EN_MASK, .index = RRAM_CTRL_DEFAULT_REGION_ECC_EN_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define RRAM_CTRL_INFO_REGWEN_REGION_FIELD_WIDTH 1
#define RRAM_CTRL_INFO_REGWEN_MULTIREG_COUNT 8
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_0_REG_OFFSET 0xa4
#define RRAM_CTRL_INFO_REGWEN_0_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_0_REGION_0_BIT 0
#define RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_LOCKED 0x0
#define RRAM_CTRL_INFO_REGWEN_0_REGION_0_VALUE_PAGE_ENABLED 0x1
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_1_REG_OFFSET 0xa8
#define RRAM_CTRL_INFO_REGWEN_1_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_1_REGION_1_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_2_REG_OFFSET 0xac
#define RRAM_CTRL_INFO_REGWEN_2_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_2_REGION_2_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_3_REG_OFFSET 0xb0
#define RRAM_CTRL_INFO_REGWEN_3_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_3_REGION_3_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_4_REG_OFFSET 0xb4
#define RRAM_CTRL_INFO_REGWEN_4_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_4_REGION_4_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_5_REG_OFFSET 0xb8
#define RRAM_CTRL_INFO_REGWEN_5_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_5_REGION_5_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_6_REG_OFFSET 0xbc
#define RRAM_CTRL_INFO_REGWEN_6_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_6_REGION_6_BIT 0
 
// Memory region registers configuration enable.
#define RRAM_CTRL_INFO_REGWEN_7_REG_OFFSET 0xc0
#define RRAM_CTRL_INFO_REGWEN_7_REG_RESVAL 0x1u
#define RRAM_CTRL_INFO_REGWEN_7_REGION_7_BIT 0
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_RD_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_WR_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_ECC_EN_FIELD_WIDTH 4
#define RRAM_CTRL_INFO_PAGE_CFG_MULTIREG_COUNT 8
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_0_REG_OFFSET 0xc4
#define RRAM_CTRL_INFO_PAGE_CFG_0_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_EN_0_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_RD_EN_0_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_WR_EN_0_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_0_ECC_EN_0_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_1_REG_OFFSET 0xc8
#define RRAM_CTRL_INFO_PAGE_CFG_1_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_EN_1_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_RD_EN_1_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_WR_EN_1_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_1_ECC_EN_1_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_2_REG_OFFSET 0xcc
#define RRAM_CTRL_INFO_PAGE_CFG_2_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_EN_2_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_RD_EN_2_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_WR_EN_2_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_2_ECC_EN_2_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_3_REG_OFFSET 0xd0
#define RRAM_CTRL_INFO_PAGE_CFG_3_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_EN_3_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_RD_EN_3_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_WR_EN_3_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_3_ECC_EN_3_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_4_REG_OFFSET 0xd4
#define RRAM_CTRL_INFO_PAGE_CFG_4_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_EN_4_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_RD_EN_4_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_WR_EN_4_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_4_ECC_EN_4_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_5_REG_OFFSET 0xd8
#define RRAM_CTRL_INFO_PAGE_CFG_5_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_EN_5_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_RD_EN_5_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_WR_EN_5_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_5_ECC_EN_5_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_6_REG_OFFSET 0xdc
#define RRAM_CTRL_INFO_PAGE_CFG_6_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_EN_6_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_RD_EN_6_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_WR_EN_6_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_6_ECC_EN_6_OFFSET })
 
// Memory property configuration for info partition.
#define RRAM_CTRL_INFO_PAGE_CFG_7_REG_OFFSET 0xe0
#define RRAM_CTRL_INFO_PAGE_CFG_7_REG_RESVAL 0x99999u
#define RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_OFFSET 0
#define RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_EN_7_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_OFFSET 4
#define RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_RD_EN_7_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_OFFSET 8
#define RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_WR_EN_7_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET 12
#define RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_MASK 0xfu
#define RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_OFFSET 16
#define RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_INFO_PAGE_CFG_7_ECC_EN_7_OFFSET })
 
// Emulated info region registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_REGWEN_REGION_FIELD_WIDTH 1
#define RRAM_CTRL_EMUL_INFO_REGWEN_MULTIREG_COUNT 2
 
// Emulated info region registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REG_OFFSET 0xe4
#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_BIT 0
#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_VALUE_REGION_LOCKED 0x0
#define RRAM_CTRL_EMUL_INFO_REGWEN_0_REGION_0_VALUE_REGION_ENABLED 0x1
 
// Emulated info region registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_REGWEN_1_REG_OFFSET 0xe8
#define RRAM_CTRL_EMUL_INFO_REGWEN_1_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_REGWEN_1_REGION_1_BIT 0
 
// Base and size configuration for an emulated info page region (window).
#define RRAM_CTRL_EMUL_INFO_REGION_BASE_FIELD_WIDTH 12
#define RRAM_CTRL_EMUL_INFO_REGION_SIZE_FIELD_WIDTH 12
#define RRAM_CTRL_EMUL_INFO_REGION_EN_FIELD_WIDTH 4
#define RRAM_CTRL_EMUL_INFO_REGION_MULTIREG_COUNT 2
 
// Base and size configuration for an emulated info page region (window).
#define RRAM_CTRL_EMUL_INFO_REGION_0_REG_OFFSET 0xec
#define RRAM_CTRL_EMUL_INFO_REGION_0_REG_RESVAL 0x9000000u
#define RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_MASK 0xfffu
#define RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_0_BASE_0_OFFSET })
#define RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_MASK 0xfffu
#define RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_0_SIZE_0_OFFSET })
#define RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_OFFSET 24
#define RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_0_EN_0_OFFSET })
 
// Base and size configuration for an emulated info page region (window).
#define RRAM_CTRL_EMUL_INFO_REGION_1_REG_OFFSET 0xf0
#define RRAM_CTRL_EMUL_INFO_REGION_1_REG_RESVAL 0x9000000u
#define RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_MASK 0xfffu
#define RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_1_BASE_1_OFFSET })
#define RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_MASK 0xfffu
#define RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_1_SIZE_1_OFFSET })
#define RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_OFFSET 24
#define RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_REGION_1_EN_1_OFFSET })
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_REGION_FIELD_WIDTH 1
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_MULTIREG_COUNT 24
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REG_OFFSET 0xf4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_BIT 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_VALUE_SUBREGION_LOCKED \
  0x0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_0_REGION_0_VALUE_SUBREGION_ENABLED \
  0x1
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REG_OFFSET 0xf8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_1_REGION_1_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REG_OFFSET 0xfc
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_2_REGION_2_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REG_OFFSET 0x100
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_3_REGION_3_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REG_OFFSET 0x104
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_4_REGION_4_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REG_OFFSET 0x108
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_5_REGION_5_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REG_OFFSET 0x10c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_6_REGION_6_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REG_OFFSET 0x110
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_7_REGION_7_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REG_OFFSET 0x114
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_8_REGION_8_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REG_OFFSET 0x118
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_9_REGION_9_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REG_OFFSET 0x11c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_10_REGION_10_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REG_OFFSET 0x120
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_11_REGION_11_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REG_OFFSET 0x124
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_12_REGION_12_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REG_OFFSET 0x128
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_13_REGION_13_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REG_OFFSET 0x12c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_14_REGION_14_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REG_OFFSET 0x130
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_15_REGION_15_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REG_OFFSET 0x134
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_16_REGION_16_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REG_OFFSET 0x138
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_17_REGION_17_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REG_OFFSET 0x13c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_18_REGION_18_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REG_OFFSET 0x140
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_19_REGION_19_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REG_OFFSET 0x144
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_20_REGION_20_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REG_OFFSET 0x148
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_21_REGION_21_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REG_OFFSET 0x14c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_22_REGION_22_BIT 0
 
// Emulated info subregion size registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REG_OFFSET 0x150
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_REGWEN_23_REGION_23_BIT 0
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_TOP_FIELD_WIDTH 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_MULTIREG_COUNT 24
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_REG_OFFSET 0x154
#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_0_TOP_0_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_REG_OFFSET 0x158
#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_1_TOP_1_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_REG_OFFSET 0x15c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_2_TOP_2_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_REG_OFFSET 0x160
#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_3_TOP_3_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_REG_OFFSET 0x164
#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_4_TOP_4_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_REG_OFFSET 0x168
#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_5_TOP_5_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_REG_OFFSET 0x16c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_6_TOP_6_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_REG_OFFSET 0x170
#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_7_TOP_7_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_REG_OFFSET 0x174
#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_8_TOP_8_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_REG_OFFSET 0x178
#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_9_TOP_9_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_REG_OFFSET 0x17c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_10_TOP_10_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_REG_OFFSET 0x180
#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_11_TOP_11_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_REG_OFFSET 0x184
#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_12_TOP_12_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_REG_OFFSET 0x188
#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_13_TOP_13_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_REG_OFFSET 0x18c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_14_TOP_14_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_REG_OFFSET 0x190
#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_15_TOP_15_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_REG_OFFSET 0x194
#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_16_TOP_16_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_REG_OFFSET 0x198
#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_17_TOP_17_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_REG_OFFSET 0x19c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_18_TOP_18_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_REG_OFFSET 0x1a0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_19_TOP_19_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_REG_OFFSET 0x1a4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_20_TOP_20_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_REG_OFFSET 0x1a8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_21_TOP_21_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_REG_OFFSET 0x1ac
#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_22_TOP_22_OFFSET })
 
// Subregions are configured with TOR (top of range) addressing, but relative
// to the window's base.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_REG_OFFSET 0x1b0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_REG_RESVAL 0x0u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_MASK 0xffu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_OFFSET 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_23_TOP_23_OFFSET })
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_REGION_FIELD_WIDTH 1
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_MULTIREG_COUNT 24
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REG_OFFSET 0x1b4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_BIT 0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_VALUE_SUBREGION_LOCKED \
  0x0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_0_REGION_0_VALUE_SUBREGION_ENABLED \
  0x1
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REG_OFFSET 0x1b8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_1_REGION_1_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REG_OFFSET 0x1bc
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_2_REGION_2_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REG_OFFSET 0x1c0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_3_REGION_3_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REG_OFFSET 0x1c4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_4_REGION_4_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REG_OFFSET 0x1c8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_5_REGION_5_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REG_OFFSET 0x1cc
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_6_REGION_6_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REG_OFFSET 0x1d0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_7_REGION_7_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REG_OFFSET 0x1d4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_8_REGION_8_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REG_OFFSET 0x1d8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_9_REGION_9_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REG_OFFSET 0x1dc
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_10_REGION_10_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REG_OFFSET 0x1e0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_11_REGION_11_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REG_OFFSET 0x1e4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_12_REGION_12_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REG_OFFSET 0x1e8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_13_REGION_13_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REG_OFFSET 0x1ec
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_14_REGION_14_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REG_OFFSET 0x1f0
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_15_REGION_15_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REG_OFFSET 0x1f4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_16_REGION_16_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REG_OFFSET 0x1f8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_17_REGION_17_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REG_OFFSET 0x1fc
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_18_REGION_18_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REG_OFFSET 0x200
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_19_REGION_19_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REG_OFFSET 0x204
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_20_REGION_20_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REG_OFFSET 0x208
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_21_REGION_21_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REG_OFFSET 0x20c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_22_REGION_22_BIT 0
 
// Emulated info subregion permission registers configuration enable.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REG_OFFSET 0x210
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REG_RESVAL 0x1u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_REGWEN_23_REGION_23_BIT 0
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_RD_EN_FIELD_WIDTH 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_WR_EN_FIELD_WIDTH 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_ECC_EN_FIELD_WIDTH 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_MULTIREG_COUNT 24
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_REG_OFFSET 0x214
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_RD_EN_0_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_WR_EN_0_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_0_ECC_EN_0_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_REG_OFFSET 0x218
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_RD_EN_1_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_WR_EN_1_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_1_ECC_EN_1_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_REG_OFFSET 0x21c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_RD_EN_2_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_WR_EN_2_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_2_ECC_EN_2_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_REG_OFFSET 0x220
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_RD_EN_3_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_WR_EN_3_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_3_ECC_EN_3_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_REG_OFFSET 0x224
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_RD_EN_4_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_WR_EN_4_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_4_ECC_EN_4_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_REG_OFFSET 0x228
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_RD_EN_5_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_WR_EN_5_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_5_ECC_EN_5_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_REG_OFFSET 0x22c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_RD_EN_6_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_WR_EN_6_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_6_ECC_EN_6_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_REG_OFFSET 0x230
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_RD_EN_7_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_WR_EN_7_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_7_ECC_EN_7_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_REG_OFFSET 0x234
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_RD_EN_8_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_WR_EN_8_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_SCRAMBLE_EN_8_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_8_ECC_EN_8_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_REG_OFFSET 0x238
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_RD_EN_9_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_WR_EN_9_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_SCRAMBLE_EN_9_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_9_ECC_EN_9_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_REG_OFFSET 0x23c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_RD_EN_10_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_WR_EN_10_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_SCRAMBLE_EN_10_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_10_ECC_EN_10_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_REG_OFFSET 0x240
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_RD_EN_11_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_WR_EN_11_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_SCRAMBLE_EN_11_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_11_ECC_EN_11_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_REG_OFFSET 0x244
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_RD_EN_12_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_WR_EN_12_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_SCRAMBLE_EN_12_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_12_ECC_EN_12_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_REG_OFFSET 0x248
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_RD_EN_13_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_WR_EN_13_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_SCRAMBLE_EN_13_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_13_ECC_EN_13_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_REG_OFFSET 0x24c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_RD_EN_14_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_WR_EN_14_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_SCRAMBLE_EN_14_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_14_ECC_EN_14_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_REG_OFFSET 0x250
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_RD_EN_15_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_WR_EN_15_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_SCRAMBLE_EN_15_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_15_ECC_EN_15_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_REG_OFFSET 0x254
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_RD_EN_16_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_WR_EN_16_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_SCRAMBLE_EN_16_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_16_ECC_EN_16_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_REG_OFFSET 0x258
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_RD_EN_17_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_WR_EN_17_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_SCRAMBLE_EN_17_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_17_ECC_EN_17_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_REG_OFFSET 0x25c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_RD_EN_18_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_WR_EN_18_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_SCRAMBLE_EN_18_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_18_ECC_EN_18_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_REG_OFFSET 0x260
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_RD_EN_19_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_WR_EN_19_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_SCRAMBLE_EN_19_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_19_ECC_EN_19_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_REG_OFFSET 0x264
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_RD_EN_20_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_WR_EN_20_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_SCRAMBLE_EN_20_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_20_ECC_EN_20_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_REG_OFFSET 0x268
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_RD_EN_21_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_WR_EN_21_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_SCRAMBLE_EN_21_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_21_ECC_EN_21_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_REG_OFFSET 0x26c
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_RD_EN_22_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_WR_EN_22_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_SCRAMBLE_EN_22_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_22_ECC_EN_22_OFFSET })
 
// Memory property configuration for an emulated info subregion.
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_REG_OFFSET 0x270
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_REG_RESVAL 0x99990u
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_OFFSET 4
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_RD_EN_23_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_OFFSET 8
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_WR_EN_23_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_OFFSET 12
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_SCRAMBLE_EN_23_OFFSET })
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_MASK 0xfu
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_OFFSET 16
#define RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_MASK, .index = RRAM_CTRL_EMUL_INFO_SUBREGION_CFG_23_ECC_EN_23_OFFSET })
 
// HW interface info configuration rule overrides
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_OFFSET 0x274
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_REG_RESVAL 0x99u
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK 0xfu
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET 0
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK, .index = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET })
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK 0xfu
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET 4
#define RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK, .index = RRAM_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET })
 
// RRAM Operation Status
#define RRAM_CTRL_OP_STATUS_REG_OFFSET 0x278
#define RRAM_CTRL_OP_STATUS_REG_RESVAL 0x0u
#define RRAM_CTRL_OP_STATUS_DONE_BIT 0
#define RRAM_CTRL_OP_STATUS_ERR_BIT 1
 
// RRAM Controller Status
#define RRAM_CTRL_STATUS_REG_OFFSET 0x27c
#define RRAM_CTRL_STATUS_REG_RESVAL 0xau
#define RRAM_CTRL_STATUS_RD_FULL_BIT 0
#define RRAM_CTRL_STATUS_RD_EMPTY_BIT 1
#define RRAM_CTRL_STATUS_WR_FULL_BIT 2
#define RRAM_CTRL_STATUS_WR_EMPTY_BIT 3
#define RRAM_CTRL_STATUS_INIT_DONE_BIT 4
#define RRAM_CTRL_STATUS_KEYS_VALID_BIT 5
 
// RRAM error code register.
#define RRAM_CTRL_ERR_CODE_REG_OFFSET 0x280
#define RRAM_CTRL_ERR_CODE_REG_RESVAL 0x0u
#define RRAM_CTRL_ERR_CODE_OP_ERR_BIT 0
#define RRAM_CTRL_ERR_CODE_MP_ERR_BIT 1
#define RRAM_CTRL_ERR_CODE_RD_ERR_BIT 2
#define RRAM_CTRL_ERR_CODE_WR_ERR_BIT 3
 
// This register tabulates standard fault status of the RRAM.
#define RRAM_CTRL_STD_FAULT_STATUS_REG_OFFSET 0x284
#define RRAM_CTRL_STD_FAULT_STATUS_REG_RESVAL 0x0u
#define RRAM_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT 0
#define RRAM_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT 1
#define RRAM_CTRL_STD_FAULT_STATUS_LCMGR_INTG_ERR_BIT 2
#define RRAM_CTRL_STD_FAULT_STATUS_OTP_ERR_BIT 3
#define RRAM_CTRL_STD_FAULT_STATUS_OTP_INTG_ERR_BIT 4
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_WR_INTG_ERR_BIT 5
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_FIFO_ERR_BIT 6
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_FSM_ERR_BIT 7
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_CNT_ERR_BIT 8
#define RRAM_CTRL_STD_FAULT_STATUS_PHY_ARB_ERR_BIT 9
#define RRAM_CTRL_STD_FAULT_STATUS_CTRL_FSM_ERR_BIT 10
#define RRAM_CTRL_STD_FAULT_STATUS_CTRL_CNT_ERR_BIT 11
#define RRAM_CTRL_STD_FAULT_STATUS_CTRL_FIFO_ERR_BIT 12
 
// This register tabulates customized fault status of the RRAM.
#define RRAM_CTRL_FAULT_STATUS_REG_OFFSET 0x288
#define RRAM_CTRL_FAULT_STATUS_REG_RESVAL 0x0u
#define RRAM_CTRL_FAULT_STATUS_LCMGR_OP_ERR_BIT 0
#define RRAM_CTRL_FAULT_STATUS_LCMGR_MP_ERR_BIT 1
#define RRAM_CTRL_FAULT_STATUS_LCMGR_RD_ERR_BIT 2
#define RRAM_CTRL_FAULT_STATUS_LCMGR_WR_ERR_BIT 3
#define RRAM_CTRL_FAULT_STATUS_OTP_OP_ERR_BIT 4
#define RRAM_CTRL_FAULT_STATUS_OTP_MP_ERR_BIT 5
#define RRAM_CTRL_FAULT_STATUS_OTP_RD_ERR_BIT 6
#define RRAM_CTRL_FAULT_STATUS_OTP_WR_ERR_BIT 7
#define RRAM_CTRL_FAULT_STATUS_SEED_ERR_BIT 8
#define RRAM_CTRL_FAULT_STATUS_PHY_RELBL_ERR_BIT 9
#define RRAM_CTRL_FAULT_STATUS_PHY_RD_INTG_ERR_BIT 10
#define RRAM_CTRL_FAULT_STATUS_PHY_RD_CTRL_ERR_BIT 11
#define RRAM_CTRL_FAULT_STATUS_SPURIOUS_DONE_BIT 12
#define RRAM_CTRL_FAULT_STATUS_HOST_GNT_ERR_BIT 13
 
// Synchronous error address
#define RRAM_CTRL_ERR_ADDR_REG_OFFSET 0x28c
#define RRAM_CTRL_ERR_ADDR_REG_RESVAL 0x0u
#define RRAM_CTRL_ERR_ADDR_ERR_ADDR_MASK 0x1fffffu
#define RRAM_CTRL_ERR_ADDR_ERR_ADDR_OFFSET 0
#define RRAM_CTRL_ERR_ADDR_ERR_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_ERR_ADDR_ERR_ADDR_MASK, .index = RRAM_CTRL_ERR_ADDR_ERR_ADDR_OFFSET })
 
// Count of correctable single-bit ECC errors
#define RRAM_CTRL_CORR1_ERR_CNT_REG_OFFSET 0x290
#define RRAM_CTRL_CORR1_ERR_CNT_REG_RESVAL 0x0u
#define RRAM_CTRL_CORR1_ERR_CNT_VAL_MASK 0xffu
#define RRAM_CTRL_CORR1_ERR_CNT_VAL_OFFSET 0
#define RRAM_CTRL_CORR1_ERR_CNT_VAL_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR1_ERR_CNT_VAL_MASK, .index = RRAM_CTRL_CORR1_ERR_CNT_VAL_OFFSET })
 
// Count of correctable double-bit ECC errors
#define RRAM_CTRL_CORR2_ERR_CNT_REG_OFFSET 0x294
#define RRAM_CTRL_CORR2_ERR_CNT_REG_RESVAL 0x0u
#define RRAM_CTRL_CORR2_ERR_CNT_VAL_MASK 0xffu
#define RRAM_CTRL_CORR2_ERR_CNT_VAL_OFFSET 0
#define RRAM_CTRL_CORR2_ERR_CNT_VAL_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR2_ERR_CNT_VAL_MASK, .index = RRAM_CTRL_CORR2_ERR_CNT_VAL_OFFSET })
 
// Last address that was corrected by the ECC decoder with a single-bit error
#define RRAM_CTRL_CORR1_ERR_LOC_REG_OFFSET 0x298
#define RRAM_CTRL_CORR1_ERR_LOC_REG_RESVAL 0x0u
#define RRAM_CTRL_CORR1_ERR_LOC_ADDR_MASK 0x1fffffu
#define RRAM_CTRL_CORR1_ERR_LOC_ADDR_OFFSET 0
#define RRAM_CTRL_CORR1_ERR_LOC_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR1_ERR_LOC_ADDR_MASK, .index = RRAM_CTRL_CORR1_ERR_LOC_ADDR_OFFSET })
#define RRAM_CTRL_CORR1_ERR_LOC_PART_BIT 24
 
// Last address that was corrected by the ECC decoder with a double-bit error
#define RRAM_CTRL_CORR2_ERR_LOC_REG_OFFSET 0x29c
#define RRAM_CTRL_CORR2_ERR_LOC_REG_RESVAL 0x0u
#define RRAM_CTRL_CORR2_ERR_LOC_ADDR_MASK 0x1fffffu
#define RRAM_CTRL_CORR2_ERR_LOC_ADDR_OFFSET 0
#define RRAM_CTRL_CORR2_ERR_LOC_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CORR2_ERR_LOC_ADDR_MASK, .index = RRAM_CTRL_CORR2_ERR_LOC_ADDR_OFFSET })
#define RRAM_CTRL_CORR2_ERR_LOC_PART_BIT 24
 
// RRAM Phy Status
#define RRAM_CTRL_PHY_STATUS_REG_OFFSET 0x2a0
#define RRAM_CTRL_PHY_STATUS_REG_RESVAL 0x0u
#define RRAM_CTRL_PHY_STATUS_WR_BUSY_BIT 0
#define RRAM_CTRL_PHY_STATUS_INIT_DONE_BIT 1
 
// RRAM Controller Scratch
#define RRAM_CTRL_SCRATCH_REG_OFFSET 0x2a4
#define RRAM_CTRL_SCRATCH_REG_RESVAL 0x0u
 
// Programmable depth where FIFOs should generate interrupts
#define RRAM_CTRL_FIFO_LVL_REG_OFFSET 0x2a8
#define RRAM_CTRL_FIFO_LVL_REG_RESVAL 0xf0fu
#define RRAM_CTRL_FIFO_LVL_WR_MASK 0x1fu
#define RRAM_CTRL_FIFO_LVL_WR_OFFSET 0
#define RRAM_CTRL_FIFO_LVL_WR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_FIFO_LVL_WR_MASK, .index = RRAM_CTRL_FIFO_LVL_WR_OFFSET })
#define RRAM_CTRL_FIFO_LVL_RD_MASK 0x1fu
#define RRAM_CTRL_FIFO_LVL_RD_OFFSET 8
#define RRAM_CTRL_FIFO_LVL_RD_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_FIFO_LVL_RD_MASK, .index = RRAM_CTRL_FIFO_LVL_RD_OFFSET })
 
// Clears RRAM controller FIFOs
#define RRAM_CTRL_FIFO_CLR_REG_OFFSET 0x2ac
#define RRAM_CTRL_FIFO_CLR_REG_RESVAL 0x0u
#define RRAM_CTRL_FIFO_CLR_WR_BIT 0
#define RRAM_CTRL_FIFO_CLR_RD_BIT 1
 
// Current write and read fifo level
#define RRAM_CTRL_CURR_FIFO_LVL_REG_OFFSET 0x2b0
#define RRAM_CTRL_CURR_FIFO_LVL_REG_RESVAL 0x0u
#define RRAM_CTRL_CURR_FIFO_LVL_WR_MASK 0x1fu
#define RRAM_CTRL_CURR_FIFO_LVL_WR_OFFSET 0
#define RRAM_CTRL_CURR_FIFO_LVL_WR_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CURR_FIFO_LVL_WR_MASK, .index = RRAM_CTRL_CURR_FIFO_LVL_WR_OFFSET })
#define RRAM_CTRL_CURR_FIFO_LVL_RD_MASK 0x1fu
#define RRAM_CTRL_CURR_FIFO_LVL_RD_OFFSET 8
#define RRAM_CTRL_CURR_FIFO_LVL_RD_FIELD \
  ((bitfield_field32_t) { .mask = RRAM_CTRL_CURR_FIFO_LVL_RD_MASK, .index = RRAM_CTRL_CURR_FIFO_LVL_RD_OFFSET })
 
// Memory area: RRAM write FIFO.
#define RRAM_CTRL_WR_FIFO_REG_OFFSET 0x2b4
#define RRAM_CTRL_WR_FIFO_SIZE_WORDS 1
#define RRAM_CTRL_WR_FIFO_SIZE_BYTES 4
// Memory area: RRAM read FIFO.
#define RRAM_CTRL_RD_FIFO_REG_OFFSET 0x2b8
#define RRAM_CTRL_RD_FIFO_SIZE_WORDS 1
#define RRAM_CTRL_RD_FIFO_SIZE_BYTES 4
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _RRAM_CTRL_REG_DEFS_
// End generated register defines for rram_ctrl