i3c_regs.h File Reference

Generated register defines for i3c. More...

Go to the source code of this file.

Macros
#define	I3C_PARAM_NUM_D_A_T_WORDS   64
#define	I3C_PARAM_NUM_D_C_T_WORDS   128
#define	I3C_PARAM_MAX_TARGETS   4
#define	I3C_PARAM_MAX_GROUPS   8
#define	I3C_PARAM_NUM_ALERTS   1
#define	I3C_PARAM_NUM_ALERTS_PRIMARY   1
#define	I3C_PARAM_NUM_ALERTS_SECONDARY   0
#define	I3C_PARAM_REG_WIDTH   32
#define	I3C_INTR_COMMON_HCI_BIT   0
#define	I3C_INTR_COMMON_TARG_BIT   1
#define	I3C_INTR_STATE_REG_OFFSET   0x0
#define	I3C_INTR_STATE_REG_RESVAL   0x0u
#define	I3C_INTR_STATE_HCI_BIT   0
#define	I3C_INTR_STATE_TARG_BIT   1
#define	I3C_INTR_ENABLE_REG_OFFSET   0x4
#define	I3C_INTR_ENABLE_REG_RESVAL   0x0u
#define	I3C_INTR_ENABLE_HCI_BIT   0
#define	I3C_INTR_ENABLE_TARG_BIT   1
#define	I3C_INTR_TEST_REG_OFFSET   0x8
#define	I3C_INTR_TEST_REG_RESVAL   0x0u
#define	I3C_INTR_TEST_HCI_BIT   0
#define	I3C_INTR_TEST_TARG_BIT   1
#define	I3C_ALERT_TEST_REG_OFFSET   0xc
#define	I3C_ALERT_TEST_REG_RESVAL   0x80000000u
#define	I3C_ALERT_TEST_FATAL_FAULT_BIT   0
#define	I3C_ALERT_TEST_REGWEN_BIT   31
#define	I3C_INFO_REG_OFFSET   0x10
#define	I3C_INFO_REG_RESVAL   0xfffff10u
#define	I3C_INFO_REVISION_MASK   0xfu
#define	I3C_INFO_REVISION_OFFSET   0
#define	I3C_INFO_REVISION_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_REVISION_MASK, .index = I3C_INFO_REVISION_OFFSET })
#define	I3C_INFO_VERSION_MASK   0xfu
#define	I3C_INFO_VERSION_OFFSET   4
#define	I3C_INFO_VERSION_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_VERSION_MASK, .index = I3C_INFO_VERSION_OFFSET })
#define	I3C_INFO_DAT_ENTRY_MAX_MASK   0x1fu
#define	I3C_INFO_DAT_ENTRY_MAX_OFFSET   8
#define	I3C_INFO_DAT_ENTRY_MAX_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_DAT_ENTRY_MAX_MASK, .index = I3C_INFO_DAT_ENTRY_MAX_OFFSET })
#define	I3C_INFO_DCT_ENTRY_MAX_MASK   0x1fu
#define	I3C_INFO_DCT_ENTRY_MAX_OFFSET   13
#define	I3C_INFO_DCT_ENTRY_MAX_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_DCT_ENTRY_MAX_MASK, .index = I3C_INFO_DCT_ENTRY_MAX_OFFSET })
#define	I3C_INFO_BUF_DWORD_MAX_MASK   0x7ffu
#define	I3C_INFO_BUF_DWORD_MAX_OFFSET   18
#define	I3C_INFO_BUF_DWORD_MAX_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_BUF_DWORD_MAX_MASK, .index = I3C_INFO_BUF_DWORD_MAX_OFFSET })
#define	I3C_CTRL_STATUS_REG_OFFSET   0x14
#define	I3C_CTRL_STATUS_REG_RESVAL   0x80000000u
#define	I3C_CTRL_STATUS_PRESENT_BIT   31
#define	I3C_CTRL_ERROR_REG_OFFSET   0x18
#define	I3C_CTRL_ERROR_REG_RESVAL   0x0u
#define	I3C_CTRL_ERROR_CE0_MASK   0xfu
#define	I3C_CTRL_ERROR_CE0_OFFSET   0
#define	I3C_CTRL_ERROR_CE0_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE0_MASK, .index = I3C_CTRL_ERROR_CE0_OFFSET })
#define	I3C_CTRL_ERROR_CE1_MASK   0xfu
#define	I3C_CTRL_ERROR_CE1_OFFSET   4
#define	I3C_CTRL_ERROR_CE1_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE1_MASK, .index = I3C_CTRL_ERROR_CE1_OFFSET })
#define	I3C_CTRL_ERROR_CE2_MASK   0xfu
#define	I3C_CTRL_ERROR_CE2_OFFSET   8
#define	I3C_CTRL_ERROR_CE2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE2_MASK, .index = I3C_CTRL_ERROR_CE2_OFFSET })
#define	I3C_CTRL_ERROR_CE3_MASK   0xfu
#define	I3C_CTRL_ERROR_CE3_OFFSET   12
#define	I3C_CTRL_ERROR_CE3_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE3_MASK, .index = I3C_CTRL_ERROR_CE3_OFFSET })
#define	I3C_TARG_CONTROL_REG_OFFSET   0x1c
#define	I3C_TARG_CONTROL_REG_RESVAL   0x102u
#define	I3C_TARG_CONTROL_EN_BIT   0
#define	I3C_TARG_CONTROL_STBY_CR_SUPPORT_BIT   1
#define	I3C_TARG_CONTROL_CRHDLY1_AS_MASK   0x3u
#define	I3C_TARG_CONTROL_CRHDLY1_AS_OFFSET   2
#define	I3C_TARG_CONTROL_CRHDLY1_AS_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CONTROL_CRHDLY1_AS_MASK, .index = I3C_TARG_CONTROL_CRHDLY1_AS_OFFSET })
#define	I3C_TARG_CONTROL_CRHDLY1_SET_AS_BIT   4
#define	I3C_TARG_CONTROL_EN_HDR_DDR_BIT   8
#define	I3C_TARG_CONTROL_HJ_REQUEST_BIT   30
#define	I3C_TARG_CONTROL_SW_RESET_BIT   31
#define	I3C_TARG_STATUS_REG_OFFSET   0x20
#define	I3C_TARG_STATUS_REG_RESVAL   0x82000000u
#define	I3C_TARG_STATUS_EXT_INFO_MASK   0x7fffu
#define	I3C_TARG_STATUS_EXT_INFO_OFFSET   0
#define	I3C_TARG_STATUS_EXT_INFO_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATUS_EXT_INFO_MASK, .index = I3C_TARG_STATUS_EXT_INFO_OFFSET })
#define	I3C_TARG_STATUS_EXT_PRESENT_BIT   15
#define	I3C_TARG_STATUS_RSTACT_MASK   0xffu
#define	I3C_TARG_STATUS_RSTACT_OFFSET   16
#define	I3C_TARG_STATUS_RSTACT_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATUS_RSTACT_MASK, .index = I3C_TARG_STATUS_RSTACT_OFFSET })
#define	I3C_TARG_STATUS_NUM_TARGETS_MASK   0x7u
#define	I3C_TARG_STATUS_NUM_TARGETS_OFFSET   24
#define	I3C_TARG_STATUS_NUM_TARGETS_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATUS_NUM_TARGETS_MASK, .index = I3C_TARG_STATUS_NUM_TARGETS_OFFSET })
#define	I3C_TARG_STATUS_VTM_BIT   27
#define	I3C_TARG_STATUS_PROTOCOL_ERROR_BIT   28
#define	I3C_TARG_STATUS_CONNECTED_BIT   29
#define	I3C_TARG_STATUS_ACTIVE_BIT   30
#define	I3C_TARG_STATUS_PRESENT_BIT   31
#define	I3C_TARG_SINK_CONTROL_REG_OFFSET   0x24
#define	I3C_TARG_SINK_CONTROL_REG_RESVAL   0x0u
#define	I3C_TARG_SINK_CONTROL_BUFFER_MASK   0x7u
#define	I3C_TARG_SINK_CONTROL_BUFFER_OFFSET   12
#define	I3C_TARG_SINK_CONTROL_BUFFER_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_SINK_CONTROL_BUFFER_MASK, .index = I3C_TARG_SINK_CONTROL_BUFFER_OFFSET })
#define	I3C_TARG_SINK_CONTROL_LENGTH_MASK   0x7ffu
#define	I3C_TARG_SINK_CONTROL_LENGTH_OFFSET   16
#define	I3C_TARG_SINK_CONTROL_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_SINK_CONTROL_LENGTH_MASK, .index = I3C_TARG_SINK_CONTROL_LENGTH_OFFSET })
#define	I3C_TARG_SINK_CONTROL_START_BIT   31
#define	I3C_TARG_SINK_STATUS_REG_OFFSET   0x28
#define	I3C_TARG_SINK_STATUS_REG_RESVAL   0x0u
#define	I3C_TARG_SINK_STATUS_ACTIVE_BIT   0
#define	I3C_TARG_SINK_STATUS_ERROR_BIT   1
#define	I3C_TARG_SINK_STATUS_LENGTH_MASK   0x7ffu
#define	I3C_TARG_SINK_STATUS_LENGTH_OFFSET   16
#define	I3C_TARG_SINK_STATUS_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_SINK_STATUS_LENGTH_MASK, .index = I3C_TARG_SINK_STATUS_LENGTH_OFFSET })
#define	I3C_RESET_DET_CTRL_REG_OFFSET   0x2c
#define	I3C_RESET_DET_CTRL_REG_RESVAL   0x0u
#define	I3C_RESET_DET_CTRL_SLEEP_REQ_BIT   1
#define	I3C_RESET_DET_CTRL_WAKE_ACK_BIT   16
#define	I3C_RESET_DET_CTRL_RST_PERIPH_EN_BIT   20
#define	I3C_RESET_DET_CTRL_RST_TARGET_EN_BIT   21
#define	I3C_RESET_DET_STATUS_REG_OFFSET   0x30
#define	I3C_RESET_DET_STATUS_REG_RESVAL   0x0u
#define	I3C_RESET_DET_STATUS_ACTIVE_BIT   0
#define	I3C_RESET_DET_STATUS_WAKE_UP_BIT   1
#define	I3C_RESET_DET_STATUS_RST_PERIPH_BIT   2
#define	I3C_RESET_DET_STATUS_RST_TARGET_BIT   3
#define	I3C_CTRL_TIME_SP_REG_OFFSET   0x34
#define	I3C_CTRL_TIME_SP_REG_RESVAL   0x3ff03ffu
#define	I3C_CTRL_TIME_SP_TCBP_DIV2_MASK   0x3ffu
#define	I3C_CTRL_TIME_SP_TCBP_DIV2_OFFSET   0
#define	I3C_CTRL_TIME_SP_TCBP_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SP_TCBP_DIV2_MASK, .index = I3C_CTRL_TIME_SP_TCBP_DIV2_OFFSET })
#define	I3C_CTRL_TIME_SP_TCAS_DIV2_MASK   0x3ffu
#define	I3C_CTRL_TIME_SP_TCAS_DIV2_OFFSET   16
#define	I3C_CTRL_TIME_SP_TCAS_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SP_TCAS_DIV2_MASK, .index = I3C_CTRL_TIME_SP_TCAS_DIV2_OFFSET })
#define	I3C_CTRL_TIME_OD_REG_OFFSET   0x38
#define	I3C_CTRL_TIME_OD_REG_RESVAL   0x3ff03ffu
#define	I3C_CTRL_TIME_OD_SCLLO_DIV2_MASK   0x3ffu
#define	I3C_CTRL_TIME_OD_SCLLO_DIV2_OFFSET   0
#define	I3C_CTRL_TIME_OD_SCLLO_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_OD_SCLLO_DIV2_MASK, .index = I3C_CTRL_TIME_OD_SCLLO_DIV2_OFFSET })
#define	I3C_CTRL_TIME_OD_SCLHI_DIV2_MASK   0x3ffu
#define	I3C_CTRL_TIME_OD_SCLHI_DIV2_OFFSET   16
#define	I3C_CTRL_TIME_OD_SCLHI_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_OD_SCLHI_DIV2_MASK, .index = I3C_CTRL_TIME_OD_SCLHI_DIV2_OFFSET })
#define	I3C_CTRL_TIME_PP_REG_OFFSET   0x3c
#define	I3C_CTRL_TIME_PP_REG_RESVAL   0x3ff83ffu
#define	I3C_CTRL_TIME_PP_TCHH_MASK   0x3ffu
#define	I3C_CTRL_TIME_PP_TCHH_OFFSET   0
#define	I3C_CTRL_TIME_PP_TCHH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_PP_TCHH_MASK, .index = I3C_CTRL_TIME_PP_TCHH_OFFSET })
#define	I3C_CTRL_TIME_PP_HCEXT_BIT   15
#define	I3C_CTRL_TIME_PP_TCHS_MASK   0x3ffu
#define	I3C_CTRL_TIME_PP_TCHS_OFFSET   16
#define	I3C_CTRL_TIME_PP_TCHS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_PP_TCHS_MASK, .index = I3C_CTRL_TIME_PP_TCHS_OFFSET })
#define	I3C_CTRL_TIME_SDR0_REG_OFFSET   0x40
#define	I3C_CTRL_TIME_SDR0_REG_RESVAL   0x3ff03ffu
#define	I3C_CTRL_TIME_SDR0_TCLH_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR0_TCLH_OFFSET   0
#define	I3C_CTRL_TIME_SDR0_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR0_TCLH_MASK, .index = I3C_CTRL_TIME_SDR0_TCLH_OFFSET })
#define	I3C_CTRL_TIME_SDR0_TCLS_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR0_TCLS_OFFSET   16
#define	I3C_CTRL_TIME_SDR0_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR0_TCLS_MASK, .index = I3C_CTRL_TIME_SDR0_TCLS_OFFSET })
#define	I3C_CTRL_TIME_SDR1_REG_OFFSET   0x44
#define	I3C_CTRL_TIME_SDR1_REG_RESVAL   0x3ff03ffu
#define	I3C_CTRL_TIME_SDR1_TCLH_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR1_TCLH_OFFSET   0
#define	I3C_CTRL_TIME_SDR1_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR1_TCLH_MASK, .index = I3C_CTRL_TIME_SDR1_TCLH_OFFSET })
#define	I3C_CTRL_TIME_SDR1_TCLS_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR1_TCLS_OFFSET   16
#define	I3C_CTRL_TIME_SDR1_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR1_TCLS_MASK, .index = I3C_CTRL_TIME_SDR1_TCLS_OFFSET })
#define	I3C_CTRL_TIME_SDR2_REG_OFFSET   0x48
#define	I3C_CTRL_TIME_SDR2_REG_RESVAL   0x3ff03ffu
#define	I3C_CTRL_TIME_SDR2_TCLH_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR2_TCLH_OFFSET   0
#define	I3C_CTRL_TIME_SDR2_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR2_TCLH_MASK, .index = I3C_CTRL_TIME_SDR2_TCLH_OFFSET })
#define	I3C_CTRL_TIME_SDR2_TCLS_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR2_TCLS_OFFSET   16
#define	I3C_CTRL_TIME_SDR2_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR2_TCLS_MASK, .index = I3C_CTRL_TIME_SDR2_TCLS_OFFSET })
#define	I3C_CTRL_TIME_SDR3_REG_OFFSET   0x4c
#define	I3C_CTRL_TIME_SDR3_REG_RESVAL   0x3ff03ffu
#define	I3C_CTRL_TIME_SDR3_TCLH_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR3_TCLH_OFFSET   0
#define	I3C_CTRL_TIME_SDR3_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR3_TCLH_MASK, .index = I3C_CTRL_TIME_SDR3_TCLH_OFFSET })
#define	I3C_CTRL_TIME_SDR3_TCLS_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR3_TCLS_OFFSET   16
#define	I3C_CTRL_TIME_SDR3_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR3_TCLS_MASK, .index = I3C_CTRL_TIME_SDR3_TCLS_OFFSET })
#define	I3C_CTRL_TIME_SDR4_REG_OFFSET   0x50
#define	I3C_CTRL_TIME_SDR4_REG_RESVAL   0x3ff03ffu
#define	I3C_CTRL_TIME_SDR4_TCLH_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR4_TCLH_OFFSET   0
#define	I3C_CTRL_TIME_SDR4_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR4_TCLH_MASK, .index = I3C_CTRL_TIME_SDR4_TCLH_OFFSET })
#define	I3C_CTRL_TIME_SDR4_TCLS_MASK   0x3ffu
#define	I3C_CTRL_TIME_SDR4_TCLS_OFFSET   16
#define	I3C_CTRL_TIME_SDR4_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR4_TCLS_MASK, .index = I3C_CTRL_TIME_SDR4_TCLS_OFFSET })
#define	I3C_CTRL_TIME_FMP_REG_OFFSET   0x54
#define	I3C_CTRL_TIME_FMP_REG_RESVAL   0x3ff03ffu
#define	I3C_CTRL_TIME_FMP_SCLLO_DIV2_MASK   0x3ffu
#define	I3C_CTRL_TIME_FMP_SCLLO_DIV2_OFFSET   0
#define	I3C_CTRL_TIME_FMP_SCLLO_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FMP_SCLLO_DIV2_MASK, .index = I3C_CTRL_TIME_FMP_SCLLO_DIV2_OFFSET })
#define	I3C_CTRL_TIME_FMP_SCLHI_DIV2_MASK   0x3ffu
#define	I3C_CTRL_TIME_FMP_SCLHI_DIV2_OFFSET   16
#define	I3C_CTRL_TIME_FMP_SCLHI_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FMP_SCLHI_DIV2_MASK, .index = I3C_CTRL_TIME_FMP_SCLHI_DIV2_OFFSET })
#define	I3C_CTRL_TIME_FM_REG_OFFSET   0x58
#define	I3C_CTRL_TIME_FM_REG_RESVAL   0x3ff03ffu
#define	I3C_CTRL_TIME_FM_SCLLO_DIV2_MASK   0x3ffu
#define	I3C_CTRL_TIME_FM_SCLLO_DIV2_OFFSET   0
#define	I3C_CTRL_TIME_FM_SCLLO_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FM_SCLLO_DIV2_MASK, .index = I3C_CTRL_TIME_FM_SCLLO_DIV2_OFFSET })
#define	I3C_CTRL_TIME_FM_SCLHI_DIV2_MASK   0x3ffu
#define	I3C_CTRL_TIME_FM_SCLHI_DIV2_OFFSET   16
#define	I3C_CTRL_TIME_FM_SCLHI_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FM_SCLHI_DIV2_MASK, .index = I3C_CTRL_TIME_FM_SCLHI_DIV2_OFFSET })
#define	I3C_INTERVAL_TIME0_REG_OFFSET   0x5c
#define	I3C_INTERVAL_TIME0_REG_RESVAL   0x0u
#define	I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_MASK   0xffu
#define	I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_OFFSET   0
#define	I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_MASK, .index = I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_OFFSET })
#define	I3C_INTERVAL_TIME0_READ_STALLED_MASK   0xffu
#define	I3C_INTERVAL_TIME0_READ_STALLED_OFFSET   8
#define	I3C_INTERVAL_TIME0_READ_STALLED_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_READ_STALLED_MASK, .index = I3C_INTERVAL_TIME0_READ_STALLED_OFFSET })
#define	I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_MASK   0xffu
#define	I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_OFFSET   16
#define	I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_MASK, .index = I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_OFFSET })
#define	I3C_INTERVAL_TIME0_DEAD_BUS_MASK   0xffu
#define	I3C_INTERVAL_TIME0_DEAD_BUS_OFFSET   24
#define	I3C_INTERVAL_TIME0_DEAD_BUS_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_DEAD_BUS_MASK, .index = I3C_INTERVAL_TIME0_DEAD_BUS_OFFSET })
#define	I3C_INTERVAL_TIME1_REG_OFFSET   0x60
#define	I3C_INTERVAL_TIME1_REG_RESVAL   0x0u
#define	I3C_INTERVAL_TIME1_COMMAND_RETRY_MASK   0xffu
#define	I3C_INTERVAL_TIME1_COMMAND_RETRY_OFFSET   0
#define	I3C_INTERVAL_TIME1_COMMAND_RETRY_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_COMMAND_RETRY_MASK, .index = I3C_INTERVAL_TIME1_COMMAND_RETRY_OFFSET })
#define	I3C_INTERVAL_TIME1_TARG_BUS_IDLE_MASK   0xffu
#define	I3C_INTERVAL_TIME1_TARG_BUS_IDLE_OFFSET   8
#define	I3C_INTERVAL_TIME1_TARG_BUS_IDLE_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_TARG_BUS_IDLE_MASK, .index = I3C_INTERVAL_TIME1_TARG_BUS_IDLE_OFFSET })
#define	I3C_INTERVAL_TIME1_TE0_RECOV_MASK   0xffu
#define	I3C_INTERVAL_TIME1_TE0_RECOV_OFFSET   16
#define	I3C_INTERVAL_TIME1_TE0_RECOV_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_TE0_RECOV_MASK, .index = I3C_INTERVAL_TIME1_TE0_RECOV_OFFSET })
#define	I3C_INTERVAL_TIME1_TARG_TRX_RST_MASK   0xffu
#define	I3C_INTERVAL_TIME1_TARG_TRX_RST_OFFSET   24
#define	I3C_INTERVAL_TIME1_TARG_TRX_RST_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_TARG_TRX_RST_MASK, .index = I3C_INTERVAL_TIME1_TARG_TRX_RST_OFFSET })
#define	I3C_PHY_CONFIG_REG_OFFSET   0x64
#define	I3C_PHY_CONFIG_REG_RESVAL   0x1100003u
#define	I3C_PHY_CONFIG_SCL_HK_EN_BIT   0
#define	I3C_PHY_CONFIG_SDA_HK_EN_BIT   1
#define	I3C_PHY_CONFIG_CTRL_SDA_BIT   20
#define	I3C_PHY_CONFIG_CTRL_SDA_PU_EN_BIT   21
#define	I3C_PHY_CONFIG_CTRL_SDA_OD_EN_BIT   22
#define	I3C_PHY_CONFIG_CTRL_SDA_PP_EN_BIT   23
#define	I3C_PHY_CONFIG_CTRL_SCL_BIT   24
#define	I3C_PHY_CONFIG_CTRL_SCL_PU_EN_BIT   25
#define	I3C_PHY_CONFIG_CTRL_SCL_PP_EN_BIT   27
#define	I3C_PHY_CONFIG_CTRL_DIRECT_DRIVE_EN_BIT   31
#define	I3C_BLOCKED_ADDR_REG_OFFSET   0x68
#define	I3C_BLOCKED_ADDR_REG_RESVAL   0x7f007fu
#define	I3C_BLOCKED_ADDR_ADDR0_MASK   0x7fu
#define	I3C_BLOCKED_ADDR_ADDR0_OFFSET   0
#define	I3C_BLOCKED_ADDR_ADDR0_FIELD    ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_ADDR0_MASK, .index = I3C_BLOCKED_ADDR_ADDR0_OFFSET })
#define	I3C_BLOCKED_ADDR_MASK0_MASK   0x7fu
#define	I3C_BLOCKED_ADDR_MASK0_OFFSET   8
#define	I3C_BLOCKED_ADDR_MASK0_FIELD    ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_MASK0_MASK, .index = I3C_BLOCKED_ADDR_MASK0_OFFSET })
#define	I3C_BLOCKED_ADDR_ADDR1_MASK   0x7fu
#define	I3C_BLOCKED_ADDR_ADDR1_OFFSET   16
#define	I3C_BLOCKED_ADDR_ADDR1_FIELD    ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_ADDR1_MASK, .index = I3C_BLOCKED_ADDR_ADDR1_OFFSET })
#define	I3C_BLOCKED_ADDR_MASK1_MASK   0x7fu
#define	I3C_BLOCKED_ADDR_MASK1_OFFSET   24
#define	I3C_BLOCKED_ADDR_MASK1_FIELD    ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_MASK1_MASK, .index = I3C_BLOCKED_ADDR_MASK1_OFFSET })
#define	I3C_BUFFER_CTRL_REG_OFFSET   0x6c
#define	I3C_BUFFER_CTRL_REG_RESVAL   0x0u
#define	I3C_BUFFER_CTRL_SW_ADDR_HI_MASK   0x3u
#define	I3C_BUFFER_CTRL_SW_ADDR_HI_OFFSET   28
#define	I3C_BUFFER_CTRL_SW_ADDR_HI_FIELD    ((bitfield_field32_t) { .mask = I3C_BUFFER_CTRL_SW_ADDR_HI_MASK, .index = I3C_BUFFER_CTRL_SW_ADDR_HI_OFFSET })
#define	I3C_BUFFER_CTRL_CLEAR_BIT   31
#define	I3C_BUFFER_STATUS_REG_OFFSET   0x70
#define	I3C_BUFFER_STATUS_REG_RESVAL   0x0u
#define	I3C_BUFFER_STATUS_TTIQ_ERR_BIT   30
#define	I3C_BUFFER_STATUS_HCIQ_ERR_BIT   31
#define	I3C_CTRL_TXBUF_CONFIG_REG_OFFSET   0x74
#define	I3C_CTRL_TXBUF_CONFIG_REG_RESVAL   0x607f0000u
#define	I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_MASK, .index = I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_OFFSET   16
#define	I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_MASK, .index = I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_MASK   0x7u
#define	I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_OFFSET   28
#define	I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_MASK, .index = I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_OFFSET })
#define	I3C_CTRL_TXBUF_STATE_REG_OFFSET   0x78
#define	I3C_CTRL_TXBUF_STATE_REG_RESVAL   0x0u
#define	I3C_CTRL_TXBUF_STATE_WPTR_MASK   0x3ffu
#define	I3C_CTRL_TXBUF_STATE_WPTR_OFFSET   0
#define	I3C_CTRL_TXBUF_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_STATE_WPTR_MASK, .index = I3C_CTRL_TXBUF_STATE_WPTR_OFFSET })
#define	I3C_CTRL_TXBUF_STATE_RPTR_MASK   0x3ffu
#define	I3C_CTRL_TXBUF_STATE_RPTR_OFFSET   16
#define	I3C_CTRL_TXBUF_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_STATE_RPTR_MASK, .index = I3C_CTRL_TXBUF_STATE_RPTR_OFFSET })
#define	I3C_CTRL_TXBUF_STATE_PRE_BIT   30
#define	I3C_CTRL_TXBUF_STATE_FULL_BIT   31
#define	I3C_CTRL_RXBUF_CONFIG_REG_OFFSET   0x7c
#define	I3C_CTRL_RXBUF_CONFIG_REG_RESVAL   0x60ff0080u
#define	I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_MASK, .index = I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_OFFSET   16
#define	I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_MASK, .index = I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_MASK   0x7u
#define	I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_OFFSET   28
#define	I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_MASK, .index = I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_OFFSET })
#define	I3C_CTRL_RXBUF_STATE_REG_OFFSET   0x80
#define	I3C_CTRL_RXBUF_STATE_REG_RESVAL   0x800080u
#define	I3C_CTRL_RXBUF_STATE_WPTR_MASK   0x3ffu
#define	I3C_CTRL_RXBUF_STATE_WPTR_OFFSET   0
#define	I3C_CTRL_RXBUF_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_STATE_WPTR_MASK, .index = I3C_CTRL_RXBUF_STATE_WPTR_OFFSET })
#define	I3C_CTRL_RXBUF_STATE_RPTR_MASK   0x3ffu
#define	I3C_CTRL_RXBUF_STATE_RPTR_OFFSET   16
#define	I3C_CTRL_RXBUF_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_STATE_RPTR_MASK, .index = I3C_CTRL_RXBUF_STATE_RPTR_OFFSET })
#define	I3C_CTRL_RXBUF_STATE_PRE_BIT   30
#define	I3C_CTRL_RXBUF_STATE_FULL_BIT   31
#define	I3C_COMMAND_QUEUE_CONFIG_REG_OFFSET   0x84
#define	I3C_COMMAND_QUEUE_CONFIG_REG_RESVAL   0x1011f100u
#define	I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_MASK, .index = I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_OFFSET   12
#define	I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_MASK, .index = I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_MASK   0xffu
#define	I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_OFFSET   24
#define	I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_MASK, .index = I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_OFFSET })
#define	I3C_COMMAND_QUEUE_STATE_REG_OFFSET   0x88
#define	I3C_COMMAND_QUEUE_STATE_REG_RESVAL   0x1000100u
#define	I3C_COMMAND_QUEUE_STATE_WPTR_MASK   0x3ffu
#define	I3C_COMMAND_QUEUE_STATE_WPTR_OFFSET   0
#define	I3C_COMMAND_QUEUE_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_STATE_WPTR_MASK, .index = I3C_COMMAND_QUEUE_STATE_WPTR_OFFSET })
#define	I3C_COMMAND_QUEUE_STATE_RPTR_MASK   0x3ffu
#define	I3C_COMMAND_QUEUE_STATE_RPTR_OFFSET   16
#define	I3C_COMMAND_QUEUE_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_STATE_RPTR_MASK, .index = I3C_COMMAND_QUEUE_STATE_RPTR_OFFSET })
#define	I3C_COMMAND_QUEUE_STATE_PRE_BIT   30
#define	I3C_COMMAND_QUEUE_STATE_FULL_BIT   31
#define	I3C_RESPONSE_QUEUE_CONFIG_REG_OFFSET   0x8c
#define	I3C_RESPONSE_QUEUE_CONFIG_REG_RESVAL   0x1012f120u
#define	I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_MASK, .index = I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_OFFSET   12
#define	I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_MASK, .index = I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_MASK   0xffu
#define	I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_OFFSET   24
#define	I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_MASK, .index = I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_OFFSET })
#define	I3C_RESPONSE_QUEUE_STATE_REG_OFFSET   0x90
#define	I3C_RESPONSE_QUEUE_STATE_REG_RESVAL   0x1200120u
#define	I3C_RESPONSE_QUEUE_STATE_WPTR_MASK   0x3ffu
#define	I3C_RESPONSE_QUEUE_STATE_WPTR_OFFSET   0
#define	I3C_RESPONSE_QUEUE_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_STATE_WPTR_MASK, .index = I3C_RESPONSE_QUEUE_STATE_WPTR_OFFSET })
#define	I3C_RESPONSE_QUEUE_STATE_RPTR_MASK   0x3ffu
#define	I3C_RESPONSE_QUEUE_STATE_RPTR_OFFSET   16
#define	I3C_RESPONSE_QUEUE_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_STATE_RPTR_MASK, .index = I3C_RESPONSE_QUEUE_STATE_RPTR_OFFSET })
#define	I3C_RESPONSE_QUEUE_STATE_PRE_BIT   30
#define	I3C_RESPONSE_QUEUE_STATE_FULL_BIT   31
#define	I3C_IBI_CONFIG_REG_OFFSET   0x94
#define	I3C_IBI_CONFIG_REG_RESVAL   0x141af130u
#define	I3C_IBI_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_IBI_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_IBI_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_CONFIG_MIN_ADDR_MASK, .index = I3C_IBI_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_IBI_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_IBI_CONFIG_MAX_ADDR_OFFSET   12
#define	I3C_IBI_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_CONFIG_MAX_ADDR_MASK, .index = I3C_IBI_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_IBI_CONFIG_SIZE_VAL_MASK   0xffu
#define	I3C_IBI_CONFIG_SIZE_VAL_OFFSET   24
#define	I3C_IBI_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_CONFIG_SIZE_VAL_MASK, .index = I3C_IBI_CONFIG_SIZE_VAL_OFFSET })
#define	I3C_IBI_STATE_REG_OFFSET   0x98
#define	I3C_IBI_STATE_REG_RESVAL   0x1300130u
#define	I3C_IBI_STATE_WPTR_MASK   0x3ffu
#define	I3C_IBI_STATE_WPTR_OFFSET   0
#define	I3C_IBI_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STATE_WPTR_MASK, .index = I3C_IBI_STATE_WPTR_OFFSET })
#define	I3C_IBI_STATE_RPTR_MASK   0x3ffu
#define	I3C_IBI_STATE_RPTR_OFFSET   16
#define	I3C_IBI_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STATE_RPTR_MASK, .index = I3C_IBI_STATE_RPTR_OFFSET })
#define	I3C_IBI_STATE_PRE_BIT   30
#define	I3C_IBI_STATE_FULL_BIT   31
#define	I3C_IBI_STAT_CONFIG_REG_OFFSET   0x9c
#define	I3C_IBI_STAT_CONFIG_REG_RESVAL   0x1cf1b0u
#define	I3C_IBI_STAT_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_IBI_STAT_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_IBI_STAT_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STAT_CONFIG_MIN_ADDR_MASK, .index = I3C_IBI_STAT_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_IBI_STAT_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_IBI_STAT_CONFIG_MAX_ADDR_OFFSET   12
#define	I3C_IBI_STAT_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STAT_CONFIG_MAX_ADDR_MASK, .index = I3C_IBI_STAT_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_IBI_STAT_STATE_REG_OFFSET   0xa0
#define	I3C_IBI_STAT_STATE_REG_RESVAL   0x1b001b0u
#define	I3C_IBI_STAT_STATE_WPTR_MASK   0x3ffu
#define	I3C_IBI_STAT_STATE_WPTR_OFFSET   0
#define	I3C_IBI_STAT_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STAT_STATE_WPTR_MASK, .index = I3C_IBI_STAT_STATE_WPTR_OFFSET })
#define	I3C_IBI_STAT_STATE_RPTR_MASK   0x3ffu
#define	I3C_IBI_STAT_STATE_RPTR_OFFSET   16
#define	I3C_IBI_STAT_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STAT_STATE_RPTR_MASK, .index = I3C_IBI_STAT_STATE_RPTR_OFFSET })
#define	I3C_IBI_STAT_STATE_PRE_BIT   30
#define	I3C_IBI_STAT_STATE_FULL_BIT   31
#define	I3C_TARG_TXBUF_CONFIG_MIN_ADDR_FIELD_WIDTH   10
#define	I3C_TARG_TXBUF_CONFIG_MAX_ADDR_FIELD_WIDTH   10
#define	I3C_TARG_TXBUF_CONFIG_MULTIREG_COUNT   4
#define	I3C_TARG_TXBUF_CONFIG_0_REG_OFFSET   0xa4
#define	I3C_TARG_TXBUF_CONFIG_0_REG_RESVAL   0x20f01d0u
#define	I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_MASK   0x3ffu
#define	I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_OFFSET   0
#define	I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_MASK, .index = I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_OFFSET })
#define	I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_MASK   0x3ffu
#define	I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_OFFSET   16
#define	I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_MASK, .index = I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_OFFSET })
#define	I3C_TARG_TXBUF_CONFIG_1_REG_OFFSET   0xa8
#define	I3C_TARG_TXBUF_CONFIG_1_REG_RESVAL   0x24f0210u
#define	I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_MASK   0x3ffu
#define	I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_OFFSET   0
#define	I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_MASK, .index = I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_OFFSET })
#define	I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_MASK   0x3ffu
#define	I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_OFFSET   16
#define	I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_MASK, .index = I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_OFFSET })
#define	I3C_TARG_TXBUF_CONFIG_2_REG_OFFSET   0xac
#define	I3C_TARG_TXBUF_CONFIG_2_REG_RESVAL   0x28f0250u
#define	I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_MASK   0x3ffu
#define	I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_OFFSET   0
#define	I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_MASK, .index = I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_OFFSET })
#define	I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_MASK   0x3ffu
#define	I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_OFFSET   16
#define	I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_MASK, .index = I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_OFFSET })
#define	I3C_TARG_TXBUF_CONFIG_3_REG_OFFSET   0xb0
#define	I3C_TARG_TXBUF_CONFIG_3_REG_RESVAL   0x2cf0290u
#define	I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_MASK   0x3ffu
#define	I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_OFFSET   0
#define	I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_MASK, .index = I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_OFFSET })
#define	I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_MASK   0x3ffu
#define	I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_OFFSET   16
#define	I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_MASK, .index = I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_OFFSET })
#define	I3C_TARG_TXBUF_STATE_WPTR_FIELD_WIDTH   10
#define	I3C_TARG_TXBUF_STATE_RPTR_FIELD_WIDTH   10
#define	I3C_TARG_TXBUF_STATE_PRE_FIELD_WIDTH   1
#define	I3C_TARG_TXBUF_STATE_FULL_FIELD_WIDTH   1
#define	I3C_TARG_TXBUF_STATE_MULTIREG_COUNT   4
#define	I3C_TARG_TXBUF_STATE_0_REG_OFFSET   0xb4
#define	I3C_TARG_TXBUF_STATE_0_REG_RESVAL   0x1d001d0u
#define	I3C_TARG_TXBUF_STATE_0_WPTR_0_MASK   0x3ffu
#define	I3C_TARG_TXBUF_STATE_0_WPTR_0_OFFSET   0
#define	I3C_TARG_TXBUF_STATE_0_WPTR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_0_WPTR_0_MASK, .index = I3C_TARG_TXBUF_STATE_0_WPTR_0_OFFSET })
#define	I3C_TARG_TXBUF_STATE_0_RPTR_0_MASK   0x3ffu
#define	I3C_TARG_TXBUF_STATE_0_RPTR_0_OFFSET   16
#define	I3C_TARG_TXBUF_STATE_0_RPTR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_0_RPTR_0_MASK, .index = I3C_TARG_TXBUF_STATE_0_RPTR_0_OFFSET })
#define	I3C_TARG_TXBUF_STATE_0_PRE_0_BIT   30
#define	I3C_TARG_TXBUF_STATE_0_FULL_0_BIT   31
#define	I3C_TARG_TXBUF_STATE_1_REG_OFFSET   0xb8
#define	I3C_TARG_TXBUF_STATE_1_REG_RESVAL   0x2100210u
#define	I3C_TARG_TXBUF_STATE_1_WPTR_1_MASK   0x3ffu
#define	I3C_TARG_TXBUF_STATE_1_WPTR_1_OFFSET   0
#define	I3C_TARG_TXBUF_STATE_1_WPTR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_1_WPTR_1_MASK, .index = I3C_TARG_TXBUF_STATE_1_WPTR_1_OFFSET })
#define	I3C_TARG_TXBUF_STATE_1_RPTR_1_MASK   0x3ffu
#define	I3C_TARG_TXBUF_STATE_1_RPTR_1_OFFSET   16
#define	I3C_TARG_TXBUF_STATE_1_RPTR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_1_RPTR_1_MASK, .index = I3C_TARG_TXBUF_STATE_1_RPTR_1_OFFSET })
#define	I3C_TARG_TXBUF_STATE_1_PRE_1_BIT   30
#define	I3C_TARG_TXBUF_STATE_1_FULL_1_BIT   31
#define	I3C_TARG_TXBUF_STATE_2_REG_OFFSET   0xbc
#define	I3C_TARG_TXBUF_STATE_2_REG_RESVAL   0x2500250u
#define	I3C_TARG_TXBUF_STATE_2_WPTR_2_MASK   0x3ffu
#define	I3C_TARG_TXBUF_STATE_2_WPTR_2_OFFSET   0
#define	I3C_TARG_TXBUF_STATE_2_WPTR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_2_WPTR_2_MASK, .index = I3C_TARG_TXBUF_STATE_2_WPTR_2_OFFSET })
#define	I3C_TARG_TXBUF_STATE_2_RPTR_2_MASK   0x3ffu
#define	I3C_TARG_TXBUF_STATE_2_RPTR_2_OFFSET   16
#define	I3C_TARG_TXBUF_STATE_2_RPTR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_2_RPTR_2_MASK, .index = I3C_TARG_TXBUF_STATE_2_RPTR_2_OFFSET })
#define	I3C_TARG_TXBUF_STATE_2_PRE_2_BIT   30
#define	I3C_TARG_TXBUF_STATE_2_FULL_2_BIT   31
#define	I3C_TARG_TXBUF_STATE_3_REG_OFFSET   0xc0
#define	I3C_TARG_TXBUF_STATE_3_REG_RESVAL   0x2900290u
#define	I3C_TARG_TXBUF_STATE_3_WPTR_3_MASK   0x3ffu
#define	I3C_TARG_TXBUF_STATE_3_WPTR_3_OFFSET   0
#define	I3C_TARG_TXBUF_STATE_3_WPTR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_3_WPTR_3_MASK, .index = I3C_TARG_TXBUF_STATE_3_WPTR_3_OFFSET })
#define	I3C_TARG_TXBUF_STATE_3_RPTR_3_MASK   0x3ffu
#define	I3C_TARG_TXBUF_STATE_3_RPTR_3_OFFSET   16
#define	I3C_TARG_TXBUF_STATE_3_RPTR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_3_RPTR_3_MASK, .index = I3C_TARG_TXBUF_STATE_3_RPTR_3_OFFSET })
#define	I3C_TARG_TXBUF_STATE_3_PRE_3_BIT   30
#define	I3C_TARG_TXBUF_STATE_3_FULL_3_BIT   31
#define	I3C_TARG_RXBUF_CONFIG_REG_OFFSET   0xc4
#define	I3C_TARG_RXBUF_CONFIG_REG_RESVAL   0x36f02d0u
#define	I3C_TARG_RXBUF_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_TARG_RXBUF_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_TARG_RXBUF_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_RXBUF_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_TARG_RXBUF_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_TARG_RXBUF_CONFIG_MAX_ADDR_OFFSET   16
#define	I3C_TARG_RXBUF_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_RXBUF_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_TARG_RXBUF_STATE_REG_OFFSET   0xc8
#define	I3C_TARG_RXBUF_STATE_REG_RESVAL   0x2d002d0u
#define	I3C_TARG_RXBUF_STATE_WPTR_MASK   0x3ffu
#define	I3C_TARG_RXBUF_STATE_WPTR_OFFSET   0
#define	I3C_TARG_RXBUF_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_STATE_WPTR_MASK, .index = I3C_TARG_RXBUF_STATE_WPTR_OFFSET })
#define	I3C_TARG_RXBUF_STATE_RPTR_MASK   0x3ffu
#define	I3C_TARG_RXBUF_STATE_RPTR_OFFSET   16
#define	I3C_TARG_RXBUF_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_STATE_RPTR_MASK, .index = I3C_TARG_RXBUF_STATE_RPTR_OFFSET })
#define	I3C_TARG_RXBUF_STATE_PRE_BIT   30
#define	I3C_TARG_RXBUF_STATE_FULL_BIT   31
#define	I3C_TARG_IBI_CONFIG_REG_OFFSET   0xcc
#define	I3C_TARG_IBI_CONFIG_REG_RESVAL   0x3af0370u
#define	I3C_TARG_IBI_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_TARG_IBI_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_TARG_IBI_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_IBI_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_TARG_IBI_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_TARG_IBI_CONFIG_MAX_ADDR_OFFSET   16
#define	I3C_TARG_IBI_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_IBI_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_TARG_IBI_STATE_REG_OFFSET   0xd0
#define	I3C_TARG_IBI_STATE_REG_RESVAL   0x3700370u
#define	I3C_TARG_IBI_STATE_WPTR_MASK   0x3ffu
#define	I3C_TARG_IBI_STATE_WPTR_OFFSET   0
#define	I3C_TARG_IBI_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_STATE_WPTR_MASK, .index = I3C_TARG_IBI_STATE_WPTR_OFFSET })
#define	I3C_TARG_IBI_STATE_RPTR_MASK   0x3ffu
#define	I3C_TARG_IBI_STATE_RPTR_OFFSET   16
#define	I3C_TARG_IBI_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_STATE_RPTR_MASK, .index = I3C_TARG_IBI_STATE_RPTR_OFFSET })
#define	I3C_TARG_IBI_STATE_PRE_BIT   30
#define	I3C_TARG_IBI_STATE_FULL_BIT   31
#define	I3C_TARG_TXDESC_CONFIG_MIN_ADDR_FIELD_WIDTH   10
#define	I3C_TARG_TXDESC_CONFIG_MAX_ADDR_FIELD_WIDTH   10
#define	I3C_TARG_TXDESC_CONFIG_MULTIREG_COUNT   4
#define	I3C_TARG_TXDESC_CONFIG_0_REG_OFFSET   0xd4
#define	I3C_TARG_TXDESC_CONFIG_0_REG_RESVAL   0x3b703b0u
#define	I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_MASK   0x3ffu
#define	I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_OFFSET   0
#define	I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_MASK, .index = I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_OFFSET })
#define	I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_MASK   0x3ffu
#define	I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_OFFSET   16
#define	I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_MASK, .index = I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_OFFSET })
#define	I3C_TARG_TXDESC_CONFIG_1_REG_OFFSET   0xd8
#define	I3C_TARG_TXDESC_CONFIG_1_REG_RESVAL   0x3bf03b8u
#define	I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_MASK   0x3ffu
#define	I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_OFFSET   0
#define	I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_MASK, .index = I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_OFFSET })
#define	I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_MASK   0x3ffu
#define	I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_OFFSET   16
#define	I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_MASK, .index = I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_OFFSET })
#define	I3C_TARG_TXDESC_CONFIG_2_REG_OFFSET   0xdc
#define	I3C_TARG_TXDESC_CONFIG_2_REG_RESVAL   0x3c703c0u
#define	I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_MASK   0x3ffu
#define	I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_OFFSET   0
#define	I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_MASK, .index = I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_OFFSET })
#define	I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_MASK   0x3ffu
#define	I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_OFFSET   16
#define	I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_MASK, .index = I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_OFFSET })
#define	I3C_TARG_TXDESC_CONFIG_3_REG_OFFSET   0xe0
#define	I3C_TARG_TXDESC_CONFIG_3_REG_RESVAL   0x3cf03c8u
#define	I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_MASK   0x3ffu
#define	I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_OFFSET   0
#define	I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_MASK, .index = I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_OFFSET })
#define	I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_MASK   0x3ffu
#define	I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_OFFSET   16
#define	I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_MASK, .index = I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_OFFSET })
#define	I3C_TARG_TXDESC_STATE_WPTR_FIELD_WIDTH   10
#define	I3C_TARG_TXDESC_STATE_RPTR_FIELD_WIDTH   10
#define	I3C_TARG_TXDESC_STATE_PRE_FIELD_WIDTH   1
#define	I3C_TARG_TXDESC_STATE_FULL_FIELD_WIDTH   1
#define	I3C_TARG_TXDESC_STATE_MULTIREG_COUNT   4
#define	I3C_TARG_TXDESC_STATE_0_REG_OFFSET   0xe4
#define	I3C_TARG_TXDESC_STATE_0_REG_RESVAL   0x3b003b0u
#define	I3C_TARG_TXDESC_STATE_0_WPTR_0_MASK   0x3ffu
#define	I3C_TARG_TXDESC_STATE_0_WPTR_0_OFFSET   0
#define	I3C_TARG_TXDESC_STATE_0_WPTR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_0_WPTR_0_MASK, .index = I3C_TARG_TXDESC_STATE_0_WPTR_0_OFFSET })
#define	I3C_TARG_TXDESC_STATE_0_RPTR_0_MASK   0x3ffu
#define	I3C_TARG_TXDESC_STATE_0_RPTR_0_OFFSET   16
#define	I3C_TARG_TXDESC_STATE_0_RPTR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_0_RPTR_0_MASK, .index = I3C_TARG_TXDESC_STATE_0_RPTR_0_OFFSET })
#define	I3C_TARG_TXDESC_STATE_0_PRE_0_BIT   30
#define	I3C_TARG_TXDESC_STATE_0_FULL_0_BIT   31
#define	I3C_TARG_TXDESC_STATE_1_REG_OFFSET   0xe8
#define	I3C_TARG_TXDESC_STATE_1_REG_RESVAL   0x3b803b8u
#define	I3C_TARG_TXDESC_STATE_1_WPTR_1_MASK   0x3ffu
#define	I3C_TARG_TXDESC_STATE_1_WPTR_1_OFFSET   0
#define	I3C_TARG_TXDESC_STATE_1_WPTR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_1_WPTR_1_MASK, .index = I3C_TARG_TXDESC_STATE_1_WPTR_1_OFFSET })
#define	I3C_TARG_TXDESC_STATE_1_RPTR_1_MASK   0x3ffu
#define	I3C_TARG_TXDESC_STATE_1_RPTR_1_OFFSET   16
#define	I3C_TARG_TXDESC_STATE_1_RPTR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_1_RPTR_1_MASK, .index = I3C_TARG_TXDESC_STATE_1_RPTR_1_OFFSET })
#define	I3C_TARG_TXDESC_STATE_1_PRE_1_BIT   30
#define	I3C_TARG_TXDESC_STATE_1_FULL_1_BIT   31
#define	I3C_TARG_TXDESC_STATE_2_REG_OFFSET   0xec
#define	I3C_TARG_TXDESC_STATE_2_REG_RESVAL   0x3c003c0u
#define	I3C_TARG_TXDESC_STATE_2_WPTR_2_MASK   0x3ffu
#define	I3C_TARG_TXDESC_STATE_2_WPTR_2_OFFSET   0
#define	I3C_TARG_TXDESC_STATE_2_WPTR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_2_WPTR_2_MASK, .index = I3C_TARG_TXDESC_STATE_2_WPTR_2_OFFSET })
#define	I3C_TARG_TXDESC_STATE_2_RPTR_2_MASK   0x3ffu
#define	I3C_TARG_TXDESC_STATE_2_RPTR_2_OFFSET   16
#define	I3C_TARG_TXDESC_STATE_2_RPTR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_2_RPTR_2_MASK, .index = I3C_TARG_TXDESC_STATE_2_RPTR_2_OFFSET })
#define	I3C_TARG_TXDESC_STATE_2_PRE_2_BIT   30
#define	I3C_TARG_TXDESC_STATE_2_FULL_2_BIT   31
#define	I3C_TARG_TXDESC_STATE_3_REG_OFFSET   0xf0
#define	I3C_TARG_TXDESC_STATE_3_REG_RESVAL   0x3c803c8u
#define	I3C_TARG_TXDESC_STATE_3_WPTR_3_MASK   0x3ffu
#define	I3C_TARG_TXDESC_STATE_3_WPTR_3_OFFSET   0
#define	I3C_TARG_TXDESC_STATE_3_WPTR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_3_WPTR_3_MASK, .index = I3C_TARG_TXDESC_STATE_3_WPTR_3_OFFSET })
#define	I3C_TARG_TXDESC_STATE_3_RPTR_3_MASK   0x3ffu
#define	I3C_TARG_TXDESC_STATE_3_RPTR_3_OFFSET   16
#define	I3C_TARG_TXDESC_STATE_3_RPTR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_3_RPTR_3_MASK, .index = I3C_TARG_TXDESC_STATE_3_RPTR_3_OFFSET })
#define	I3C_TARG_TXDESC_STATE_3_PRE_3_BIT   30
#define	I3C_TARG_TXDESC_STATE_3_FULL_3_BIT   31
#define	I3C_TARG_RXDESC_CONFIG_REG_OFFSET   0xf4
#define	I3C_TARG_RXDESC_CONFIG_REG_RESVAL   0x3df03d0u
#define	I3C_TARG_RXDESC_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_TARG_RXDESC_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_TARG_RXDESC_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_RXDESC_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_TARG_RXDESC_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_TARG_RXDESC_CONFIG_MAX_ADDR_OFFSET   16
#define	I3C_TARG_RXDESC_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_RXDESC_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_TARG_RXDESC_STATE_REG_OFFSET   0xf8
#define	I3C_TARG_RXDESC_STATE_REG_RESVAL   0x3d003d0u
#define	I3C_TARG_RXDESC_STATE_WPTR_MASK   0x3ffu
#define	I3C_TARG_RXDESC_STATE_WPTR_OFFSET   0
#define	I3C_TARG_RXDESC_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_STATE_WPTR_MASK, .index = I3C_TARG_RXDESC_STATE_WPTR_OFFSET })
#define	I3C_TARG_RXDESC_STATE_RPTR_MASK   0x3ffu
#define	I3C_TARG_RXDESC_STATE_RPTR_OFFSET   16
#define	I3C_TARG_RXDESC_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_STATE_RPTR_MASK, .index = I3C_TARG_RXDESC_STATE_RPTR_OFFSET })
#define	I3C_TARG_RXDESC_STATE_PRE_BIT   30
#define	I3C_TARG_RXDESC_STATE_FULL_BIT   31
#define	I3C_TARG_IBIDESC_CONFIG_REG_OFFSET   0xfc
#define	I3C_TARG_IBIDESC_CONFIG_REG_RESVAL   0x3ef03e0u
#define	I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_OFFSET   16
#define	I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_TARG_IBIDESC_STATE_REG_OFFSET   0x100
#define	I3C_TARG_IBIDESC_STATE_REG_RESVAL   0x3e003e0u
#define	I3C_TARG_IBIDESC_STATE_WPTR_MASK   0x3ffu
#define	I3C_TARG_IBIDESC_STATE_WPTR_OFFSET   0
#define	I3C_TARG_IBIDESC_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_STATE_WPTR_MASK, .index = I3C_TARG_IBIDESC_STATE_WPTR_OFFSET })
#define	I3C_TARG_IBIDESC_STATE_RPTR_MASK   0x3ffu
#define	I3C_TARG_IBIDESC_STATE_RPTR_OFFSET   16
#define	I3C_TARG_IBIDESC_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_STATE_RPTR_MASK, .index = I3C_TARG_IBIDESC_STATE_RPTR_OFFSET })
#define	I3C_TARG_IBIDESC_STATE_PRE_BIT   30
#define	I3C_TARG_IBIDESC_STATE_FULL_BIT   31
#define	I3C_TARG_ASYNC_CONFIG_REG_OFFSET   0x104
#define	I3C_TARG_ASYNC_CONFIG_REG_RESVAL   0x3ff03f0u
#define	I3C_TARG_ASYNC_CONFIG_MIN_ADDR_MASK   0x3ffu
#define	I3C_TARG_ASYNC_CONFIG_MIN_ADDR_OFFSET   0
#define	I3C_TARG_ASYNC_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_ASYNC_CONFIG_MIN_ADDR_OFFSET })
#define	I3C_TARG_ASYNC_CONFIG_MAX_ADDR_MASK   0x3ffu
#define	I3C_TARG_ASYNC_CONFIG_MAX_ADDR_OFFSET   16
#define	I3C_TARG_ASYNC_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_ASYNC_CONFIG_MAX_ADDR_OFFSET })
#define	I3C_TARG_ASYNC_STATE_REG_OFFSET   0x108
#define	I3C_TARG_ASYNC_STATE_REG_RESVAL   0x3f003f0u
#define	I3C_TARG_ASYNC_STATE_WPTR_MASK   0x3ffu
#define	I3C_TARG_ASYNC_STATE_WPTR_OFFSET   0
#define	I3C_TARG_ASYNC_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_STATE_WPTR_MASK, .index = I3C_TARG_ASYNC_STATE_WPTR_OFFSET })
#define	I3C_TARG_ASYNC_STATE_RPTR_MASK   0x3ffu
#define	I3C_TARG_ASYNC_STATE_RPTR_OFFSET   16
#define	I3C_TARG_ASYNC_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_STATE_RPTR_MASK, .index = I3C_TARG_ASYNC_STATE_RPTR_OFFSET })
#define	I3C_TARG_ASYNC_STATE_PRE_BIT   30
#define	I3C_TARG_ASYNC_STATE_FULL_BIT   31
#define	I3C_HCI_VERSION_REG_OFFSET   0x180
#define	I3C_HCI_VERSION_REG_RESVAL   0x120u
#define	I3C_HC_CONTROL_REG_OFFSET   0x184
#define	I3C_HC_CONTROL_REG_RESVAL   0x48u
#define	I3C_HC_CONTROL_IBA_INCLUDE_BIT   0
#define	I3C_HC_CONTROL_AUTOCMD_DATA_RPT_BIT   3
#define	I3C_HC_CONTROL_DATA_BYTE_ORDER_MODE_BIT   4
#define	I3C_HC_CONTROL_MODE_SELECTOR_BIT   6
#define	I3C_HC_CONTROL_I2C_DEV_PRESENT_BIT   7
#define	I3C_HC_CONTROL_HOT_JOIN_CTRL_BIT   8
#define	I3C_HC_CONTROL_HALT_ON_CMD_SEQ_TIMEOUT_BIT   12
#define	I3C_HC_CONTROL_ABORT_BIT   29
#define	I3C_HC_CONTROL_RESUME_BIT   30
#define	I3C_HC_CONTROL_BUS_ENABLE_BIT   31
#define	I3C_CONTROLLER_DEVICE_ADDR_REG_OFFSET   0x188
#define	I3C_CONTROLLER_DEVICE_ADDR_REG_RESVAL   0x0u
#define	I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_MASK   0x7fu
#define	I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET   16
#define	I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_MASK, .index = I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET })
#define	I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_VALID_BIT   31
#define	I3C_HC_CAPABILITIES_REG_OFFSET   0x18c
#define	I3C_HC_CAPABILITIES_REG_RESVAL   0x448u
#define	I3C_HC_CAPABILITIES_COMBO_COMMAND_BIT   2
#define	I3C_HC_CAPABILITIES_AUTO_COMMAND_BIT   3
#define	I3C_HC_CAPABILITIES_STANDBY_CR_CAP_BIT   5
#define	I3C_HC_CAPABILITIES_HDR_DDR_EN_BIT   6
#define	I3C_HC_CAPABILITIES_HDR_TS_EN_BIT   7
#define	I3C_HC_CAPABILITIES_CMD_CCC_DEFBYTE_BIT   10
#define	I3C_HC_CAPABILITIES_IBI_DATA_ABORT_EN_BIT   11
#define	I3C_HC_CAPABILITIES_IBI_CREDIT_COUNT_EN_BIT   12
#define	I3C_HC_CAPABILITIES_SCHEDULED_COMMANDS_EN_BIT   13
#define	I3C_HC_CAPABILITIES_CMD_SIZE_MASK   0x3u
#define	I3C_HC_CAPABILITIES_CMD_SIZE_OFFSET   20
#define	I3C_HC_CAPABILITIES_CMD_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_HC_CAPABILITIES_CMD_SIZE_MASK, .index = I3C_HC_CAPABILITIES_CMD_SIZE_OFFSET })
#define	I3C_HC_CAPABILITIES_SG_CAPABILITY_CR_EN_BIT   28
#define	I3C_HC_CAPABILITIES_SG_CAPABILITY_IBI_EN_BIT   29
#define	I3C_HC_CAPABILITIES_SG_CAPABILITY_DC_EN_BIT   30
#define	I3C_RESET_CONTROL_REG_OFFSET   0x190
#define	I3C_RESET_CONTROL_REG_RESVAL   0x0u
#define	I3C_RESET_CONTROL_SOFT_RST_BIT   0
#define	I3C_RESET_CONTROL_CMD_QUEUE_RST_BIT   1
#define	I3C_RESET_CONTROL_RESP_QUEUE_RST_BIT   2
#define	I3C_RESET_CONTROL_TX_FIFO_RST_BIT   3
#define	I3C_RESET_CONTROL_RX_FIFO_RST_BIT   4
#define	I3C_RESET_CONTROL_IBI_QUEUE_RST_BIT   5
#define	I3C_PRESENT_STATE_REG_OFFSET   0x194
#define	I3C_PRESENT_STATE_REG_RESVAL   0x0u
#define	I3C_PRESENT_STATE_AC_CURRENT_OWN_BIT   2
#define	I3C_INTR_STATUS_REG_OFFSET   0x1a0
#define	I3C_INTR_STATUS_REG_RESVAL   0x0u
#define	I3C_INTR_STATUS_HC_INTERNAL_ERR_STAT_BIT   10
#define	I3C_INTR_STATUS_HC_SEQ_CANCEL_STAT_BIT   11
#define	I3C_INTR_STATUS_HC_WARN_CMD_SEQ_STALL_STAT_BIT   12
#define	I3C_INTR_STATUS_HC_ERR_CMD_SEQ_TIMEOUT_STAT_BIT   13
#define	I3C_INTR_STATUS_SCHED_CMD_MISSED_TICK_STAT_BIT   14
#define	I3C_INTR_STATUS_ENABLE_REG_OFFSET   0x1a4
#define	I3C_INTR_STATUS_ENABLE_REG_RESVAL   0x0u
#define	I3C_INTR_STATUS_ENABLE_HC_INTERNAL_ERR_STAT_EN_BIT   10
#define	I3C_INTR_STATUS_ENABLE_HC_SEQ_CANCEL_STAT_EN_BIT   11
#define	I3C_INTR_STATUS_ENABLE_HC_WARN_CMD_SEQ_STALL_STAT_EN_BIT   12
#define	I3C_INTR_STATUS_ENABLE_HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN_BIT   13
#define	I3C_INTR_STATUS_ENABLE_SCHED_CMD_MISSED_TICK_STAT_EN_BIT   14
#define	I3C_INTR_SIGNAL_ENABLE_REG_OFFSET   0x1a8
#define	I3C_INTR_SIGNAL_ENABLE_REG_RESVAL   0x0u
#define	I3C_INTR_SIGNAL_ENABLE_HC_INTERNAL_ERR_SIGNAL_EN_BIT   10
#define	I3C_INTR_SIGNAL_ENABLE_HC_SEQ_CANCEL_SIGNAL_EN_BIT   11
#define	I3C_INTR_SIGNAL_ENABLE_HC_WARN_CMD_SEQ_STALL_SIGNAL_EN_BIT   12
#define	I3C_INTR_SIGNAL_ENABLE_HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN_BIT   13
#define	I3C_INTR_SIGNAL_ENABLE_SCHED_CMD_MISSED_TICK_SIGNAL_EN_BIT   14
#define	I3C_INTR_FORCE_REG_OFFSET   0x1ac
#define	I3C_INTR_FORCE_REG_RESVAL   0x0u
#define	I3C_INTR_FORCE_HC_INTERNAL_ERR_FORCE_BIT   10
#define	I3C_INTR_FORCE_HC_SEQ_CANCEL_FORCE_BIT   11
#define	I3C_INTR_FORCE_HC_WARN_CMD_SEQ_STALL_FORCE_BIT   12
#define	I3C_INTR_FORCE_HC_ERR_CMD_SEQ_TIMEOUT_FORCE_BIT   13
#define	I3C_INTR_FORCE_SCHED_CMD_MISSED_TICK_FORCE_BIT   14
#define	I3C_DAT_SECTION_OFFSET_REG_OFFSET   0x1b0
#define	I3C_DAT_SECTION_OFFSET_REG_RESVAL   0x20880u
#define	I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_MASK   0xfffu
#define	I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_OFFSET   0
#define	I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_MASK, .index = I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_OFFSET })
#define	I3C_DAT_SECTION_OFFSET_TABLE_SIZE_MASK   0x7fu
#define	I3C_DAT_SECTION_OFFSET_TABLE_SIZE_OFFSET   12
#define	I3C_DAT_SECTION_OFFSET_TABLE_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DAT_SECTION_OFFSET_TABLE_SIZE_MASK, .index = I3C_DAT_SECTION_OFFSET_TABLE_SIZE_OFFSET })
#define	I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_MASK   0xfu
#define	I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_OFFSET   28
#define	I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_MASK, .index = I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_OFFSET })
#define	I3C_DCT_SECTION_OFFSET_REG_OFFSET   0x1b4
#define	I3C_DCT_SECTION_OFFSET_REG_RESVAL   0x20a80u
#define	I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_MASK   0xfffu
#define	I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_OFFSET   0
#define	I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_MASK, .index = I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_OFFSET })
#define	I3C_DCT_SECTION_OFFSET_TABLE_SIZE_MASK   0x7fu
#define	I3C_DCT_SECTION_OFFSET_TABLE_SIZE_OFFSET   12
#define	I3C_DCT_SECTION_OFFSET_TABLE_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_TABLE_SIZE_MASK, .index = I3C_DCT_SECTION_OFFSET_TABLE_SIZE_OFFSET })
#define	I3C_DCT_SECTION_OFFSET_TABLE_INDEX_MASK   0x1fu
#define	I3C_DCT_SECTION_OFFSET_TABLE_INDEX_OFFSET   19
#define	I3C_DCT_SECTION_OFFSET_TABLE_INDEX_FIELD    ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_TABLE_INDEX_MASK, .index = I3C_DCT_SECTION_OFFSET_TABLE_INDEX_OFFSET })
#define	I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_MASK   0xfu
#define	I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_OFFSET   28
#define	I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_MASK, .index = I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_OFFSET })
#define	I3C_RING_HEADERS_SECTION_OFFSET_REG_OFFSET   0x1b8
#define	I3C_RING_HEADERS_SECTION_OFFSET_REG_RESVAL   0x0u
#define	I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_MASK   0xffffu
#define	I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_OFFSET   0
#define	I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_MASK, .index = I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_OFFSET })
#define	I3C_PIO_SECTION_OFFSET_REG_OFFSET   0x1bc
#define	I3C_PIO_SECTION_OFFSET_REG_RESVAL   0x80u
#define	I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_MASK   0xffffu
#define	I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_OFFSET   0
#define	I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_MASK, .index = I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_OFFSET })
#define	I3C_EXT_CAPS_SECTION_OFFSET_REG_OFFSET   0x1c0
#define	I3C_EXT_CAPS_SECTION_OFFSET_REG_RESVAL   0x120u
#define	I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_MASK   0xffffu
#define	I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_OFFSET   0
#define	I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_MASK, .index = I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_OFFSET })
#define	I3C_INT_CTRL_CMDS_EN_REG_OFFSET   0x1cc
#define	I3C_INT_CTRL_CMDS_EN_REG_RESVAL   0x20f5u
#define	I3C_INT_CTRL_CMDS_EN_ICC_SUPPORT_BIT   0
#define	I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_MASK   0x7fffu
#define	I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_OFFSET   1
#define	I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_FIELD    ((bitfield_field32_t) { .mask = I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_MASK, .index = I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_OFFSET })
#define	I3C_IBI_NOTIFY_CTRL_REG_OFFSET   0x1d8
#define	I3C_IBI_NOTIFY_CTRL_REG_RESVAL   0x0u
#define	I3C_IBI_NOTIFY_CTRL_NOTIFY_HJ_REJECTED_BIT   0
#define	I3C_IBI_NOTIFY_CTRL_NOTIFY_CRR_REJECTED_BIT   1
#define	I3C_IBI_NOTIFY_CTRL_NOTIFY_IBI_REJECTED_BIT   3
#define	I3C_IBI_DATA_ABORT_CTRL_REG_OFFSET   0x1dc
#define	I3C_IBI_DATA_ABORT_CTRL_REG_RESVAL   0x0u
#define	I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_MASK   0xffu
#define	I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_OFFSET   8
#define	I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_MASK, .index = I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_OFFSET })
#define	I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_MASK   0x3u
#define	I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_OFFSET   16
#define	I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_MASK, .index = I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_OFFSET })
#define	I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_MASK   0x7u
#define	I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_OFFSET   18
#define	I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_MASK, .index = I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_OFFSET })
#define	I3C_IBI_DATA_ABORT_CTRL_IBI_DATA_ABORT_MON_BIT   31
#define	I3C_DEV_CTX_BASE_LO_REG_OFFSET   0x1e0
#define	I3C_DEV_CTX_BASE_LO_REG_RESVAL   0x0u
#define	I3C_DEV_CTX_BASE_HI_REG_OFFSET   0x1e4
#define	I3C_DEV_CTX_BASE_HI_REG_RESVAL   0x0u
#define	I3C_DEV_CTX_SG_REG_OFFSET   0x1e8
#define	I3C_DEV_CTX_SG_REG_RESVAL   0x0u
#define	I3C_DEV_CTX_SG_LIST_SIZE_MASK   0xffffu
#define	I3C_DEV_CTX_SG_LIST_SIZE_OFFSET   0
#define	I3C_DEV_CTX_SG_LIST_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DEV_CTX_SG_LIST_SIZE_MASK, .index = I3C_DEV_CTX_SG_LIST_SIZE_OFFSET })
#define	I3C_DEV_CTX_SG_BLP_BIT   31
#define	I3C_HCI_PORTS_REG_OFFSET   0x200
#define	I3C_HCI_PORTS_SIZE_WORDS   4
#define	I3C_HCI_PORTS_SIZE_BYTES   16
#define	I3C_QUEUE_THLD_CTRL_REG_OFFSET   0x210
#define	I3C_QUEUE_THLD_CTRL_REG_RESVAL   0x1010101u
#define	I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_MASK   0xffu
#define	I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_OFFSET   0
#define	I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_MASK, .index = I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_OFFSET })
#define	I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_MASK   0xffu
#define	I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_OFFSET   8
#define	I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_MASK, .index = I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_OFFSET })
#define	I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_MASK   0xffu
#define	I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_OFFSET   16
#define	I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_MASK, .index = I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_OFFSET })
#define	I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK   0xffu
#define	I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET   24
#define	I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK, .index = I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET })
#define	I3C_DATA_BUFFER_THLD_CTRL_REG_OFFSET   0x214
#define	I3C_DATA_BUFFER_THLD_CTRL_REG_RESVAL   0x1010101u
#define	I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_MASK   0x7u
#define	I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_OFFSET   0
#define	I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_OFFSET })
#define	I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_MASK   0x7u
#define	I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_OFFSET   8
#define	I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_OFFSET })
#define	I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_MASK   0x7u
#define	I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_OFFSET   16
#define	I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_OFFSET })
#define	I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_MASK   0x7u
#define	I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_OFFSET   24
#define	I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_OFFSET })
#define	I3C_QUEUE_SIZE_REG_OFFSET   0x218
#define	I3C_QUEUE_SIZE_REG_RESVAL   0x6061410u
#define	I3C_QUEUE_SIZE_CR_QUEUE_SIZE_MASK   0xffu
#define	I3C_QUEUE_SIZE_CR_QUEUE_SIZE_OFFSET   0
#define	I3C_QUEUE_SIZE_CR_QUEUE_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_CR_QUEUE_SIZE_MASK, .index = I3C_QUEUE_SIZE_CR_QUEUE_SIZE_OFFSET })
#define	I3C_QUEUE_SIZE_IBI_STATUS_SIZE_MASK   0xffu
#define	I3C_QUEUE_SIZE_IBI_STATUS_SIZE_OFFSET   8
#define	I3C_QUEUE_SIZE_IBI_STATUS_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_IBI_STATUS_SIZE_MASK, .index = I3C_QUEUE_SIZE_IBI_STATUS_SIZE_OFFSET })
#define	I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_MASK   0xffu
#define	I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_OFFSET   16
#define	I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_MASK, .index = I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_OFFSET })
#define	I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_MASK   0xffu
#define	I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_OFFSET   24
#define	I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_MASK, .index = I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_OFFSET })
#define	I3C_ALT_QUEUE_SIZE_REG_OFFSET   0x21c
#define	I3C_ALT_QUEUE_SIZE_REG_RESVAL   0x11000010u
#define	I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_MASK   0xffu
#define	I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_OFFSET   0
#define	I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_MASK, .index = I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_OFFSET })
#define	I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_EN_BIT   24
#define	I3C_ALT_QUEUE_SIZE_EXT_IBI_QUEUE_EN_BIT   28
#define	I3C_PIO_INTR_STATUS_REG_OFFSET   0x220
#define	I3C_PIO_INTR_STATUS_REG_RESVAL   0x0u
#define	I3C_PIO_INTR_STATUS_TX_THLD_STAT_BIT   0
#define	I3C_PIO_INTR_STATUS_RX_THLD_STAT_BIT   1
#define	I3C_PIO_INTR_STATUS_IBI_STATUS_THLD_STAT_BIT   2
#define	I3C_PIO_INTR_STATUS_CMD_QUEUE_READY_STAT_BIT   3
#define	I3C_PIO_INTR_STATUS_RESP_READY_STAT_BIT   4
#define	I3C_PIO_INTR_STATUS_TRANSFER_ABORT_STAT_BIT   5
#define	I3C_PIO_INTR_STATUS_TRANSFER_ERR_STAT_BIT   9
#define	I3C_PIO_INTR_STATUS_ENABLE_REG_OFFSET   0x224
#define	I3C_PIO_INTR_STATUS_ENABLE_REG_RESVAL   0x0u
#define	I3C_PIO_INTR_STATUS_ENABLE_TX_THLD_STAT_EN_BIT   0
#define	I3C_PIO_INTR_STATUS_ENABLE_RX_THLD_STAT_EN_BIT   1
#define	I3C_PIO_INTR_STATUS_ENABLE_IBI_STATUS_THLD_STAT_EN_BIT   2
#define	I3C_PIO_INTR_STATUS_ENABLE_CMD_QUEUE_READY_STAT_EN_BIT   3
#define	I3C_PIO_INTR_STATUS_ENABLE_RESP_READY_STAT_EN_BIT   4
#define	I3C_PIO_INTR_STATUS_ENABLE_TRANSFER_ABORT_STAT_EN_BIT   5
#define	I3C_PIO_INTR_STATUS_ENABLE_TRANSFER_ERR_STAT_EN_BIT   9
#define	I3C_PIO_INTR_SIGNAL_ENABLE_REG_OFFSET   0x228
#define	I3C_PIO_INTR_SIGNAL_ENABLE_REG_RESVAL   0x0u
#define	I3C_PIO_INTR_SIGNAL_ENABLE_TX_THLD_SIGNAL_EN_BIT   0
#define	I3C_PIO_INTR_SIGNAL_ENABLE_RX_THLD_SIGNAL_EN_BIT   1
#define	I3C_PIO_INTR_SIGNAL_ENABLE_IBI_STATUS_THLD_SIGNAL_EN_BIT   2
#define	I3C_PIO_INTR_SIGNAL_ENABLE_CMD_QUEUE_READY_SIGNAL_EN_BIT   3
#define	I3C_PIO_INTR_SIGNAL_ENABLE_RESP_READY_SIGNAL_EN_BIT   4
#define	I3C_PIO_INTR_SIGNAL_ENABLE_TRANSFER_ABORT_SIGNAL_EN_BIT   5
#define	I3C_PIO_INTR_SIGNAL_ENABLE_TRANSFER_ERR_SIGNAL_EN_BIT   9
#define	I3C_PIO_INTR_FORCE_REG_OFFSET   0x22c
#define	I3C_PIO_INTR_FORCE_REG_RESVAL   0x0u
#define	I3C_PIO_INTR_FORCE_TX_THLD_FORCE_BIT   0
#define	I3C_PIO_INTR_FORCE_RX_THLD_FORCE_BIT   1
#define	I3C_PIO_INTR_FORCE_IBI_THLD_FORCE_BIT   2
#define	I3C_PIO_INTR_FORCE_CMD_QUEUE_READY_FORCE_BIT   3
#define	I3C_PIO_INTR_FORCE_RESP_READY_FORCE_BIT   4
#define	I3C_PIO_INTR_FORCE_TRANSFER_ABORT_FORCE_BIT   5
#define	I3C_PIO_INTR_FORCE_TRANSFER_ERR_FORCE_BIT   9
#define	I3C_PIO_CONTROL_REG_OFFSET   0x230
#define	I3C_PIO_CONTROL_REG_RESVAL   0x1u
#define	I3C_PIO_CONTROL_ENABLE_BIT   0
#define	I3C_PIO_CONTROL_RS_BIT   1
#define	I3C_PIO_CONTROL_ABORT_BIT   2
#define	I3C_ID_EXTCAP_HEADER_REG_OFFSET   0x2a0
#define	I3C_ID_EXTCAP_HEADER_REG_RESVAL   0x401u
#define	I3C_ID_EXTCAP_HEADER_CAP_ID_MASK   0xffu
#define	I3C_ID_EXTCAP_HEADER_CAP_ID_OFFSET   0
#define	I3C_ID_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_ID_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_ID_EXTCAP_HEADER_CAP_ID_OFFSET })
#define	I3C_ID_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu
#define	I3C_ID_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8
#define	I3C_ID_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_ID_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_ID_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
#define	I3C_COMP_MANUFACTURER_REG_OFFSET   0x2a4
#define	I3C_COMP_MANUFACTURER_REG_RESVAL   0x0u
#define	I3C_COMP_VERSION_REG_OFFSET   0x2a8
#define	I3C_COMP_VERSION_REG_RESVAL   0x0u
#define	I3C_COMP_TYPE_REG_OFFSET   0x2ac
#define	I3C_COMP_TYPE_REG_RESVAL   0x0u
#define	I3C_CTRL_CFG_EXTCAP_HEADER_REG_OFFSET   0x2b0
#define	I3C_CTRL_CFG_EXTCAP_HEADER_REG_RESVAL   0x202u
#define	I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_MASK   0xffu
#define	I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_OFFSET   0
#define	I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_OFFSET })
#define	I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu
#define	I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8
#define	I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
#define	I3C_CONTROLLER_CONFIG_REG_OFFSET   0x2b4
#define	I3C_CONTROLLER_CONFIG_REG_RESVAL   0x10u
#define	I3C_CONTROLLER_CONFIG_OPERATION_MODE_MASK   0x3u
#define	I3C_CONTROLLER_CONFIG_OPERATION_MODE_OFFSET   4
#define	I3C_CONTROLLER_CONFIG_OPERATION_MODE_FIELD    ((bitfield_field32_t) { .mask = I3C_CONTROLLER_CONFIG_OPERATION_MODE_MASK, .index = I3C_CONTROLLER_CONFIG_OPERATION_MODE_OFFSET })
#define	I3C_DBR_EXTCAP_HEADER_REG_OFFSET   0x2b8
#define	I3C_DBR_EXTCAP_HEADER_REG_RESVAL   0x20bu
#define	I3C_DBR_EXTCAP_HEADER_CAP_ID_MASK   0xffu
#define	I3C_DBR_EXTCAP_HEADER_CAP_ID_OFFSET   0
#define	I3C_DBR_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_DBR_EXTCAP_HEADER_CAP_ID_OFFSET })
#define	I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu
#define	I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8
#define	I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
#define	I3C_DBR_ENGAGE_REG_OFFSET   0x2bc
#define	I3C_DBR_ENGAGE_REG_RESVAL   0x0u
#define	I3C_DBR_ENGAGE_DBR_VERIF_KEY_MASK   0xfu
#define	I3C_DBR_ENGAGE_DBR_VERIF_KEY_OFFSET   0
#define	I3C_DBR_ENGAGE_DBR_VERIF_KEY_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_VERIF_KEY_MASK, .index = I3C_DBR_ENGAGE_DBR_VERIF_KEY_OFFSET })
#define	I3C_DBR_ENGAGE_DBR_MODE_MASK   0x7u
#define	I3C_DBR_ENGAGE_DBR_MODE_OFFSET   4
#define	I3C_DBR_ENGAGE_DBR_MODE_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_MODE_MASK, .index = I3C_DBR_ENGAGE_DBR_MODE_OFFSET })
#define	I3C_DBR_ENGAGE_DBR_ASX_TIMING_MASK   0x3u
#define	I3C_DBR_ENGAGE_DBR_ASX_TIMING_OFFSET   8
#define	I3C_DBR_ENGAGE_DBR_ASX_TIMING_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_ASX_TIMING_MASK, .index = I3C_DBR_ENGAGE_DBR_ASX_TIMING_OFFSET })
#define	I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_MASK   0x7fu
#define	I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_OFFSET   16
#define	I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_MASK, .index = I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_OFFSET })
#define	I3C_DEBUG_EXTCAP_HEADER_REG_OFFSET   0x2c0
#define	I3C_DEBUG_EXTCAP_HEADER_REG_RESVAL   0x60cu
#define	I3C_DEBUG_EXTCAP_HEADER_CAP_ID_MASK   0xffu
#define	I3C_DEBUG_EXTCAP_HEADER_CAP_ID_OFFSET   0
#define	I3C_DEBUG_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_DEBUG_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_DEBUG_EXTCAP_HEADER_CAP_ID_OFFSET })
#define	I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu
#define	I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8
#define	I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
#define	I3C_QUEUE_STATUS_LEVEL_REG_OFFSET   0x2c4
#define	I3C_QUEUE_STATUS_LEVEL_REG_RESVAL   0x10u
#define	I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_MASK   0xffu
#define	I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_OFFSET   0
#define	I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_MASK, .index = I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_OFFSET })
#define	I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_MASK   0xffu
#define	I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_OFFSET   8
#define	I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_MASK, .index = I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_OFFSET })
#define	I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_MASK   0xffu
#define	I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_OFFSET   16
#define	I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_MASK, .index = I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_OFFSET })
#define	I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_MASK   0x1fu
#define	I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_OFFSET   24
#define	I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_MASK, .index = I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_OFFSET })
#define	I3C_DATA_BUFFER_STATUS_LEVEL_REG_OFFSET   0x2c8
#define	I3C_DATA_BUFFER_STATUS_LEVEL_REG_RESVAL   0x80u
#define	I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_MASK   0xffu
#define	I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_OFFSET   0
#define	I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_MASK, .index = I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_OFFSET })
#define	I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_MASK   0xffu
#define	I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_OFFSET   8
#define	I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_MASK, .index = I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_OFFSET })
#define	I3C_PRESENT_STATE_DEBUG_REG_OFFSET   0x2cc
#define	I3C_PRESENT_STATE_DEBUG_REG_RESVAL   0x3u
#define	I3C_PRESENT_STATE_DEBUG_SCL_LINE_SIGNAL_LEVEL_BIT   0
#define	I3C_PRESENT_STATE_DEBUG_SDA_LINE_SIGNAL_LEVEL_BIT   1
#define	I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_MASK   0x3fu
#define	I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_OFFSET   8
#define	I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_FIELD    ((bitfield_field32_t) { .mask = I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_MASK, .index = I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_OFFSET })
#define	I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_MASK   0x3fu
#define	I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_OFFSET   16
#define	I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_FIELD    ((bitfield_field32_t) { .mask = I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_MASK, .index = I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_OFFSET })
#define	I3C_PRESENT_STATE_DEBUG_CMD_TID_MASK   0xfu
#define	I3C_PRESENT_STATE_DEBUG_CMD_TID_OFFSET   24
#define	I3C_PRESENT_STATE_DEBUG_CMD_TID_FIELD    ((bitfield_field32_t) { .mask = I3C_PRESENT_STATE_DEBUG_CMD_TID_MASK, .index = I3C_PRESENT_STATE_DEBUG_CMD_TID_OFFSET })
#define	I3C_MX_ERROR_COUNTERS_REG_OFFSET   0x2d0
#define	I3C_MX_ERROR_COUNTERS_REG_RESVAL   0x0u
#define	I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_MASK   0xffu
#define	I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_OFFSET   0
#define	I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_FIELD    ((bitfield_field32_t) { .mask = I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_MASK, .index = I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_OFFSET })
#define	I3C_SCHED_CMDS_DEBUG_REG_OFFSET   0x2d4
#define	I3C_SCHED_CMDS_DEBUG_REG_RESVAL   0x0u
#define	I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_MASK   0xfu
#define	I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_OFFSET   0
#define	I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_FIELD    ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_MASK, .index = I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_OFFSET })
#define	I3C_SCHED_CMDS_DEBUG_INST_ID_MASK   0x7u
#define	I3C_SCHED_CMDS_DEBUG_INST_ID_OFFSET   4
#define	I3C_SCHED_CMDS_DEBUG_INST_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_INST_ID_MASK, .index = I3C_SCHED_CMDS_DEBUG_INST_ID_OFFSET })
#define	I3C_SCHED_CMDS_DEBUG_ERR_TYPE_BIT   7
#define	I3C_SCHED_CMDS_DEBUG_ENTITY_ID_MASK   0xffu
#define	I3C_SCHED_CMDS_DEBUG_ENTITY_ID_OFFSET   8
#define	I3C_SCHED_CMDS_DEBUG_ENTITY_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_ENTITY_ID_MASK, .index = I3C_SCHED_CMDS_DEBUG_ENTITY_ID_OFFSET })
#define	I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_MASK   0x1fu
#define	I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_OFFSET   16
#define	I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_FIELD    ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_MASK, .index = I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_OFFSET })
#define	I3C_SCHED_CMDS_DEBUG_ERR_OCCURRED_BIT   21
#define	I3C_STBY_CR_EXTCAP_HEADER_REG_OFFSET   0x2d8
#define	I3C_STBY_CR_EXTCAP_HEADER_REG_RESVAL   0xe12u
#define	I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_MASK   0xffu
#define	I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_OFFSET   0
#define	I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_OFFSET })
#define	I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu
#define	I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8
#define	I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
#define	I3C_STBY_CR_CONTROL_REG_OFFSET   0x2dc
#define	I3C_STBY_CR_CONTROL_REG_RESVAL   0x100cu
#define	I3C_STBY_CR_CONTROL_PENDING_RX_NACK_BIT   0
#define	I3C_STBY_CR_CONTROL_HANDOFF_DELAY_NACK_BIT   1
#define	I3C_STBY_CR_CONTROL_ACR_FSM_OP_SELECT_BIT   2
#define	I3C_STBY_CR_CONTROL_PRIME_ACCEPT_GETACCCR_BIT   3
#define	I3C_STBY_CR_CONTROL_HANDOFF_DEEP_SLEEP_BIT   4
#define	I3C_STBY_CR_CONTROL_CR_REQUEST_SEND_BIT   5
#define	I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_MASK   0x7u
#define	I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_OFFSET   8
#define	I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_MASK, .index = I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_OFFSET })
#define	I3C_STBY_CR_CONTROL_TARGET_XACT_ENABLE_BIT   12
#define	I3C_STBY_CR_CONTROL_DAA_SETAASA_ENABLE_BIT   13
#define	I3C_STBY_CR_CONTROL_DAA_SETDASA_ENABLE_BIT   14
#define	I3C_STBY_CR_CONTROL_DAA_ENTDAA_ENABLE_BIT   15
#define	I3C_STBY_CR_CONTROL_RSTACT_DEFBYTE_02_BIT   20
#define	I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_MASK   0x3u
#define	I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_OFFSET   30
#define	I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_MASK, .index = I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_OFFSET })
#define	I3C_STBY_CR_DEVICE_ADDR_REG_OFFSET   0x2e0
#define	I3C_STBY_CR_DEVICE_ADDR_REG_RESVAL   0x0u
#define	I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_MASK   0x7fu
#define	I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_OFFSET   0
#define	I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_MASK, .index = I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_OFFSET })
#define	I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_VALID_BIT   15
#define	I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_MASK   0x7fu
#define	I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET   16
#define	I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_MASK, .index = I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET })
#define	I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_VALID_BIT   31
#define	I3C_STBY_CR_CAPABILITIES_REG_OFFSET   0x2e4
#define	I3C_STBY_CR_CAPABILITIES_REG_RESVAL   0xf020u
#define	I3C_STBY_CR_CAPABILITIES_SIMPLE_CRR_SUPPORT_BIT   5
#define	I3C_STBY_CR_CAPABILITIES_TARGET_XACT_SUPPORT_BIT   12
#define	I3C_STBY_CR_CAPABILITIES_DAA_SETAASA_SUPPORT_BIT   13
#define	I3C_STBY_CR_CAPABILITIES_DAA_SETDASA_SUPPORT_BIT   14
#define	I3C_STBY_CR_CAPABILITIES_DAA_ENTDAA_SUPPORT_BIT   15
#define	I3C_STBY_CR_STATUS_REG_OFFSET   0x2ec
#define	I3C_STBY_CR_STATUS_REG_RESVAL   0x0u
#define	I3C_STBY_CR_STATUS_AC_CURRENT_OWN_BIT   2
#define	I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_MASK   0x7u
#define	I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_OFFSET   5
#define	I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_MASK, .index = I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_OFFSET })
#define	I3C_STBY_CR_STATUS_HJ_REQ_STATUS_BIT   8
#define	I3C_STBY_CR_DEVICE_CHAR_REG_OFFSET   0x2f0
#define	I3C_STBY_CR_DEVICE_CHAR_REG_RESVAL   0x60000000u
#define	I3C_STBY_CR_DEVICE_CHAR_PID_HI_MASK   0x7fffu
#define	I3C_STBY_CR_DEVICE_CHAR_PID_HI_OFFSET   1
#define	I3C_STBY_CR_DEVICE_CHAR_PID_HI_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_PID_HI_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_PID_HI_OFFSET })
#define	I3C_STBY_CR_DEVICE_CHAR_DCR_MASK   0xffu
#define	I3C_STBY_CR_DEVICE_CHAR_DCR_OFFSET   16
#define	I3C_STBY_CR_DEVICE_CHAR_DCR_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_DCR_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_DCR_OFFSET })
#define	I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_MASK   0x1fu
#define	I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_OFFSET   24
#define	I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_OFFSET })
#define	I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_MASK   0x7u
#define	I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_OFFSET   29
#define	I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_OFFSET })
#define	I3C_STBY_CR_DEVICE_PID_LO_REG_OFFSET   0x2f4
#define	I3C_STBY_CR_DEVICE_PID_LO_REG_RESVAL   0x0u
#define	I3C_STBY_CR_INTR_STATUS_REG_OFFSET   0x2f8
#define	I3C_STBY_CR_INTR_STATUS_REG_RESVAL   0x0u
#define	I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_OK_REMAIN_STAT_BIT   0
#define	I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_OK_PRIMED_STAT_BIT   1
#define	I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_ERR_FAIL_STAT_BIT   2
#define	I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_ERR_M3_STAT_BIT   3
#define	I3C_STBY_CR_INTR_STATUS_CRR_RESPONSE_STAT_BIT   10
#define	I3C_STBY_CR_INTR_STATUS_STBY_CR_DYN_ADDR_STAT_BIT   11
#define	I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_NACKED_STAT_BIT   12
#define	I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_OK_STAT_BIT   13
#define	I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_ERR_STAT_BIT   14
#define	I3C_STBY_CR_INTR_STATUS_STBY_CR_OP_RSTACT_STAT_BIT   16
#define	I3C_STBY_CR_INTR_STATUS_CCC_PARAM_MODIFIED_STAT_BIT   17
#define	I3C_STBY_CR_INTR_STATUS_CCC_UNHANDLED_NACK_STAT_BIT   18
#define	I3C_STBY_CR_INTR_STATUS_CCC_FATAL_RSTDAA_ERR_STAT_BIT   19
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_REG_OFFSET   0x300
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_REG_RESVAL   0xc0000u
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_OK_REMAIN_SIGNAL_EN_BIT   0
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_OK_PRIMED_SIGNAL_EN_BIT   1
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_ERR_FAIL_SIGNAL_EN_BIT   2
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_ERR_M3_SIGNAL_EN_BIT   3
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_CRR_RESPONSE_SIGNAL_EN_BIT   10
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_DYN_ADDR_SIGNAL_EN_BIT   11
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_NACKED_SIGNAL_EN_BIT   12
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_OK_SIGNAL_EN_BIT   13
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_ERR_SIGNAL_EN_BIT   14
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_OP_RSTACT_SIGNAL_EN_BIT   16
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_PARAM_MODIFIED_SIGNAL_EN_BIT   17
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_UNHANDLED_NACK_SIGNAL_EN_BIT   18
#define	I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_FATAL_RSTDAA_ERR_SIGNAL_EN_BIT   19
#define	I3C_STBY_CR_INTR_FORCE_REG_OFFSET   0x304
#define	I3C_STBY_CR_INTR_FORCE_REG_RESVAL   0x0u
#define	I3C_STBY_CR_INTR_FORCE_CRR_RESPONSE_FORCE_BIT   10
#define	I3C_STBY_CR_INTR_FORCE_STBY_CR_DYN_ADDR_FORCE_BIT   11
#define	I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_NACKED_FORCE_BIT   12
#define	I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_OK_FORCE_BIT   13
#define	I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_ERR_FORCE_BIT   14
#define	I3C_STBY_CR_INTR_FORCE_STBY_CR_OP_RSTACT_FORCE_BIT   16
#define	I3C_STBY_CR_INTR_FORCE_CCC_PARAM_MODIFIED_FORCE_BIT   17
#define	I3C_STBY_CR_INTR_FORCE_CCC_UNHANDLED_NACK_FORCE_BIT   18
#define	I3C_STBY_CR_INTR_FORCE_CCC_FATAL_RSTDAA_ERR_FORCE_BIT   19
#define	I3C_STBY_CR_CCC_CONFIG_GETCAPS_REG_OFFSET   0x308
#define	I3C_STBY_CR_CCC_CONFIG_GETCAPS_REG_RESVAL   0x0u
#define	I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_MASK   0x7u
#define	I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_OFFSET   0
#define	I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_MASK, .index = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_OFFSET })
#define	I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_MASK   0xfu
#define	I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_OFFSET   8
#define	I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_MASK, .index = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_OFFSET })
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_REG_OFFSET   0x30c
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_REG_RESVAL   0x80000000u
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_MASK   0xffu
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_OFFSET   0
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_MASK, .index = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_OFFSET })
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_MASK   0xffu
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_OFFSET   8
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_MASK, .index = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_OFFSET })
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_MASK   0xffu
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_OFFSET   16
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_MASK, .index = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_OFFSET })
#define	I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_DYNAMIC_ADDR_BIT   31
#define	I3C_TTI_EXTCAP_HEADER_REG_OFFSET   0x310
#define	I3C_TTI_EXTCAP_HEADER_REG_RESVAL   0x59c8u
#define	I3C_TTI_EXTCAP_HEADER_CAP_ID_MASK   0xffu
#define	I3C_TTI_EXTCAP_HEADER_CAP_ID_OFFSET   0
#define	I3C_TTI_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_TTI_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_TTI_EXTCAP_HEADER_CAP_ID_OFFSET })
#define	I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu
#define	I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8
#define	I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
#define	I3C_TARG_INTR_STATUS_REG_OFFSET   0x314
#define	I3C_TARG_INTR_STATUS_REG_RESVAL   0x0u
#define	I3C_TARG_INTR_STATUS_RX_DESC_READY_STAT_BIT   0
#define	I3C_TARG_INTR_STATUS_IBI_STATUS_THLD_STAT_BIT   1
#define	I3C_TARG_INTR_STATUS_ASYNC_EVT_READY_STAT_BIT   2
#define	I3C_TARG_INTR_STATUS_TRANSFER_ABORT_STAT_BIT   3
#define	I3C_TARG_INTR_STATUS_TRANSFER_ERR_STAT_BIT   4
#define	I3C_TARG_INTR_STATUS_RX_BUFFER_OVF_STAT_BIT   5
#define	I3C_TARG_INTR_STATUS_ASYNC_EVT_OVF_STAT_BIT   6
#define	I3C_TARG_INTR_STATUS_TX0_THLD_STAT_BIT   8
#define	I3C_TARG_INTR_STATUS_TX1_THLD_STAT_BIT   9
#define	I3C_TARG_INTR_STATUS_TX2_THLD_STAT_BIT   10
#define	I3C_TARG_INTR_STATUS_TX3_THLD_STAT_BIT   11
#define	I3C_TARG_INTR_STATUS_TX0_DESC_READY_STAT_BIT   16
#define	I3C_TARG_INTR_STATUS_TX1_DESC_READY_STAT_BIT   17
#define	I3C_TARG_INTR_STATUS_TX2_DESC_READY_STAT_BIT   18
#define	I3C_TARG_INTR_STATUS_TX3_DESC_READY_STAT_BIT   19
#define	I3C_TARG_INTR_STATUS_TE_STAT_BIT   31
#define	I3C_TARG_INTR_STATUS_ENABLE_REG_OFFSET   0x318
#define	I3C_TARG_INTR_STATUS_ENABLE_REG_RESVAL   0x0u
#define	I3C_TARG_INTR_STATUS_ENABLE_RX_DESC_READY_STAT_EN_BIT   0
#define	I3C_TARG_INTR_STATUS_ENABLE_IBI_STATUS_THLD_STAT_EN_BIT   1
#define	I3C_TARG_INTR_STATUS_ENABLE_ASYNC_EVT_READY_STAT_EN_BIT   2
#define	I3C_TARG_INTR_STATUS_ENABLE_TRANSFER_ABORT_STAT_EN_BIT   3
#define	I3C_TARG_INTR_STATUS_ENABLE_TRANSFER_ERR_STAT_EN_BIT   4
#define	I3C_TARG_INTR_STATUS_ENABLE_RX_BUFFER_OVF_STAT_EN_BIT   5
#define	I3C_TARG_INTR_STATUS_ENABLE_ASYNC_EVT_OVF_STAT_EN_BIT   6
#define	I3C_TARG_INTR_STATUS_ENABLE_TX0_THLD_STAT_EN_BIT   8
#define	I3C_TARG_INTR_STATUS_ENABLE_TX1_THLD_STAT_EN_BIT   9
#define	I3C_TARG_INTR_STATUS_ENABLE_TX2_THLD_STAT_EN_BIT   10
#define	I3C_TARG_INTR_STATUS_ENABLE_TX3_THLD_STAT_EN_BIT   11
#define	I3C_TARG_INTR_STATUS_ENABLE_TX0_DESC_READY_STAT_EN_BIT   16
#define	I3C_TARG_INTR_STATUS_ENABLE_TX1_DESC_READY_STAT_EN_BIT   17
#define	I3C_TARG_INTR_STATUS_ENABLE_TX2_DESC_READY_STAT_EN_BIT   18
#define	I3C_TARG_INTR_STATUS_ENABLE_TX3_DESC_READY_STAT_EN_BIT   19
#define	I3C_TARG_INTR_STATUS_ENABLE_TE_STAT_EN_BIT   31
#define	I3C_TARG_INTR_SIGNAL_ENABLE_REG_OFFSET   0x31c
#define	I3C_TARG_INTR_SIGNAL_ENABLE_REG_RESVAL   0x0u
#define	I3C_TARG_INTR_SIGNAL_ENABLE_RX_DESC_READY_SIGNAL_EN_BIT   0
#define	I3C_TARG_INTR_SIGNAL_ENABLE_IBI_STATUS_THLD_SIGNAL_EN_BIT   1
#define	I3C_TARG_INTR_SIGNAL_ENABLE_ASYNC_EVT_READY_SIGNAL_EN_BIT   2
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TRANSFER_ABORT_SIGNAL_EN_BIT   3
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TRANSFER_ERR_SIGNAL_EN_BIT   4
#define	I3C_TARG_INTR_SIGNAL_ENABLE_RX_BUFFER_OVF_SIGNAL_EN_BIT   5
#define	I3C_TARG_INTR_SIGNAL_ENABLE_ASYNC_EVT_OVF_SIGNAL_EN_BIT   6
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TX0_THLD_SIGNAL_EN_BIT   8
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TX1_THLD_SIGNAL_EN_BIT   9
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TX2_THLD_SIGNAL_EN_BIT   10
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TX3_THLD_SIGNAL_EN_BIT   11
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TX0_DESC_READY_SIGNAL_EN_BIT   16
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TX1_DESC_READY_SIGNAL_EN_BIT   17
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TX2_DESC_READY_SIGNAL_EN_BIT   18
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TX3_DESC_READY_SIGNAL_EN_BIT   19
#define	I3C_TARG_INTR_SIGNAL_ENABLE_TE_SIGNAL_EN_BIT   31
#define	I3C_TARG_INTR_FORCE_REG_OFFSET   0x320
#define	I3C_TARG_INTR_FORCE_REG_RESVAL   0x0u
#define	I3C_TARG_INTR_FORCE_RX_DESC_READY_FORCE_BIT   0
#define	I3C_TARG_INTR_FORCE_IBI_THLD_FORCE_BIT   1
#define	I3C_TARG_INTR_FORCE_ASYNC_EVT_READY_FORCE_BIT   2
#define	I3C_TARG_INTR_FORCE_TRANSFER_ABORT_FORCE_BIT   3
#define	I3C_TARG_INTR_FORCE_TRANSFER_ERR_FORCE_BIT   4
#define	I3C_TARG_INTR_FORCE_RX_BUFFER_OVF_FORCE_BIT   5
#define	I3C_TARG_INTR_FORCE_ASYNC_EVT_OVF_FORCE_BIT   6
#define	I3C_TARG_INTR_FORCE_TX0_THLD_FORCE_BIT   8
#define	I3C_TARG_INTR_FORCE_TX1_THLD_FORCE_BIT   9
#define	I3C_TARG_INTR_FORCE_TX2_THLD_FORCE_BIT   10
#define	I3C_TARG_INTR_FORCE_TX3_THLD_FORCE_BIT   11
#define	I3C_TARG_INTR_FORCE_TX0_DESC_READY_FORCE_BIT   16
#define	I3C_TARG_INTR_FORCE_TX1_DESC_READY_FORCE_BIT   17
#define	I3C_TARG_INTR_FORCE_TX2_DESC_READY_FORCE_BIT   18
#define	I3C_TARG_INTR_FORCE_TX3_DESC_READY_FORCE_BIT   19
#define	I3C_TARG_INTR_FORCE_TE_FORCE_BIT   31
#define	I3C_TARG_PIO_CONTROL_REG_OFFSET   0x324
#define	I3C_TARG_PIO_CONTROL_REG_RESVAL   0x0u
#define	I3C_TARG_PIO_CONTROL_IBI_SUSPENDED_BIT   0
#define	I3C_TARG_PIO_CONTROL_IBI_ABORT_BIT   1
#define	I3C_TARG_PIO_CONTROL_SUSPENDED_MASK   0xfu
#define	I3C_TARG_PIO_CONTROL_SUSPENDED_OFFSET   16
#define	I3C_TARG_PIO_CONTROL_SUSPENDED_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_PIO_CONTROL_SUSPENDED_MASK, .index = I3C_TARG_PIO_CONTROL_SUSPENDED_OFFSET })
#define	I3C_TARG_PIO_CONTROL_ABORT_MASK   0xfu
#define	I3C_TARG_PIO_CONTROL_ABORT_OFFSET   24
#define	I3C_TARG_PIO_CONTROL_ABORT_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_PIO_CONTROL_ABORT_MASK, .index = I3C_TARG_PIO_CONTROL_ABORT_OFFSET })
#define	I3C_TARG_ASYNC_EVT_CONTROL_REG_OFFSET   0x328
#define	I3C_TARG_ASYNC_EVT_CONTROL_REG_RESVAL   0x0u
#define	I3C_TARG_ASYNC_EVT_CONTROL_BCST_CCC_BIT   0
#define	I3C_TARG_ASYNC_EVT_CONTROL_DIR_SET_CCC_BIT   1
#define	I3C_TARG_ASYNC_EVT_CONTROL_DIR_GET_CCC_BIT   2
#define	I3C_TARG_ASYNC_EVT_CONTROL_TX_NOTIFY_BIT   3
#define	I3C_TARG_ASYNC_EVT_CONTROL_IBI_NOTIFY_BIT   4
#define	I3C_TARG_ASYNC_EVT_CONTROL_TX_SUSPEND_BIT   5
#define	I3C_TARG_ASYNC_EVT_CONTROL_IBI_SUSPEND_BIT   6
#define	I3C_TARG_ASYNC_EVT_CONTROL_BUS_EVENTS_BIT   7
#define	I3C_TARG_ASYNC_EVT_CONTROL_QUEUE_RESET_BIT   31
#define	I3C_TARG_ERROR_REG_OFFSET   0x32c
#define	I3C_TARG_ERROR_REG_RESVAL   0x0u
#define	I3C_TARG_ERROR_TE0_MASK   0xfu
#define	I3C_TARG_ERROR_TE0_OFFSET   0
#define	I3C_TARG_ERROR_TE0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE0_MASK, .index = I3C_TARG_ERROR_TE0_OFFSET })
#define	I3C_TARG_ERROR_TE1_MASK   0xfu
#define	I3C_TARG_ERROR_TE1_OFFSET   4
#define	I3C_TARG_ERROR_TE1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE1_MASK, .index = I3C_TARG_ERROR_TE1_OFFSET })
#define	I3C_TARG_ERROR_TE2_MASK   0xfu
#define	I3C_TARG_ERROR_TE2_OFFSET   8
#define	I3C_TARG_ERROR_TE2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE2_MASK, .index = I3C_TARG_ERROR_TE2_OFFSET })
#define	I3C_TARG_ERROR_TE3_MASK   0xfu
#define	I3C_TARG_ERROR_TE3_OFFSET   12
#define	I3C_TARG_ERROR_TE3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE3_MASK, .index = I3C_TARG_ERROR_TE3_OFFSET })
#define	I3C_TARG_ERROR_TE4_MASK   0xfu
#define	I3C_TARG_ERROR_TE4_OFFSET   16
#define	I3C_TARG_ERROR_TE4_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE4_MASK, .index = I3C_TARG_ERROR_TE4_OFFSET })
#define	I3C_TARG_ERROR_TE5_MASK   0xfu
#define	I3C_TARG_ERROR_TE5_OFFSET   20
#define	I3C_TARG_ERROR_TE5_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE5_MASK, .index = I3C_TARG_ERROR_TE5_OFFSET })
#define	I3C_TARG_ERROR_TE6_MASK   0xfu
#define	I3C_TARG_ERROR_TE6_OFFSET   24
#define	I3C_TARG_ERROR_TE6_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE6_MASK, .index = I3C_TARG_ERROR_TE6_OFFSET })
#define	I3C_TARG_ERROR_DBR_MASK   0xfu
#define	I3C_TARG_ERROR_DBR_OFFSET   28
#define	I3C_TARG_ERROR_DBR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_DBR_MASK, .index = I3C_TARG_ERROR_DBR_OFFSET })
#define	I3C_TARG_QUEUE_THLD_CTRL_REG_OFFSET   0x330
#define	I3C_TARG_QUEUE_THLD_CTRL_REG_RESVAL   0x1000100u
#define	I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_MASK   0xffu
#define	I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_OFFSET   8
#define	I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_MASK, .index = I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_OFFSET })
#define	I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK   0xffu
#define	I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET   24
#define	I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK, .index = I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET })
#define	I3C_TARG_QUEUE_STATUS_LEVEL_REG_OFFSET   0x334
#define	I3C_TARG_QUEUE_STATUS_LEVEL_REG_RESVAL   0x0u
#define	I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_MASK   0xffu
#define	I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_OFFSET   0
#define	I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_MASK, .index = I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_OFFSET })
#define	I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_MASK   0xfffu
#define	I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_OFFSET   16
#define	I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_MASK, .index = I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_OFFSET })
#define	I3C_TARG_BUF_THLD_CTRL_REG_OFFSET   0x338
#define	I3C_TARG_BUF_THLD_CTRL_REG_RESVAL   0x10000001u
#define	I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_MASK   0xfffu
#define	I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_OFFSET   0
#define	I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_MASK, .index = I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_OFFSET })
#define	I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_MASK   0x7u
#define	I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_OFFSET   28
#define	I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_MASK, .index = I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_OFFSET })
#define	I3C_TARG_BUF_STATUS_LEVEL_REG_OFFSET   0x33c
#define	I3C_TARG_BUF_STATUS_LEVEL_REG_RESVAL   0x400000u
#define	I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_MASK   0xfffu
#define	I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_OFFSET   0
#define	I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_MASK, .index = I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_OFFSET })
#define	I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_MASK   0xfffu
#define	I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_OFFSET   16
#define	I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_MASK, .index = I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_OFFSET })
#define	I3C_TARG_RW_LEN_MRL_FIELD_WIDTH   16
#define	I3C_TARG_RW_LEN_MWL_FIELD_WIDTH   16
#define	I3C_TARG_RW_LEN_MULTIREG_COUNT   4
#define	I3C_TARG_RW_LEN_0_REG_OFFSET   0x340
#define	I3C_TARG_RW_LEN_0_REG_RESVAL   0xffffffffu
#define	I3C_TARG_RW_LEN_0_MRL_0_MASK   0xffffu
#define	I3C_TARG_RW_LEN_0_MRL_0_OFFSET   0
#define	I3C_TARG_RW_LEN_0_MRL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_0_MRL_0_MASK, .index = I3C_TARG_RW_LEN_0_MRL_0_OFFSET })
#define	I3C_TARG_RW_LEN_0_MWL_0_MASK   0xffffu
#define	I3C_TARG_RW_LEN_0_MWL_0_OFFSET   16
#define	I3C_TARG_RW_LEN_0_MWL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_0_MWL_0_MASK, .index = I3C_TARG_RW_LEN_0_MWL_0_OFFSET })
#define	I3C_TARG_RW_LEN_1_REG_OFFSET   0x344
#define	I3C_TARG_RW_LEN_1_REG_RESVAL   0xffffffffu
#define	I3C_TARG_RW_LEN_1_MRL_1_MASK   0xffffu
#define	I3C_TARG_RW_LEN_1_MRL_1_OFFSET   0
#define	I3C_TARG_RW_LEN_1_MRL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_1_MRL_1_MASK, .index = I3C_TARG_RW_LEN_1_MRL_1_OFFSET })
#define	I3C_TARG_RW_LEN_1_MWL_1_MASK   0xffffu
#define	I3C_TARG_RW_LEN_1_MWL_1_OFFSET   16
#define	I3C_TARG_RW_LEN_1_MWL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_1_MWL_1_MASK, .index = I3C_TARG_RW_LEN_1_MWL_1_OFFSET })
#define	I3C_TARG_RW_LEN_2_REG_OFFSET   0x348
#define	I3C_TARG_RW_LEN_2_REG_RESVAL   0xffffffffu
#define	I3C_TARG_RW_LEN_2_MRL_2_MASK   0xffffu
#define	I3C_TARG_RW_LEN_2_MRL_2_OFFSET   0
#define	I3C_TARG_RW_LEN_2_MRL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_2_MRL_2_MASK, .index = I3C_TARG_RW_LEN_2_MRL_2_OFFSET })
#define	I3C_TARG_RW_LEN_2_MWL_2_MASK   0xffffu
#define	I3C_TARG_RW_LEN_2_MWL_2_OFFSET   16
#define	I3C_TARG_RW_LEN_2_MWL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_2_MWL_2_MASK, .index = I3C_TARG_RW_LEN_2_MWL_2_OFFSET })
#define	I3C_TARG_RW_LEN_3_REG_OFFSET   0x34c
#define	I3C_TARG_RW_LEN_3_REG_RESVAL   0xffffffffu
#define	I3C_TARG_RW_LEN_3_MRL_3_MASK   0xffffu
#define	I3C_TARG_RW_LEN_3_MRL_3_OFFSET   0
#define	I3C_TARG_RW_LEN_3_MRL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_3_MRL_3_MASK, .index = I3C_TARG_RW_LEN_3_MRL_3_OFFSET })
#define	I3C_TARG_RW_LEN_3_MWL_3_MASK   0xffffu
#define	I3C_TARG_RW_LEN_3_MWL_3_OFFSET   16
#define	I3C_TARG_RW_LEN_3_MWL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_3_MWL_3_MASK, .index = I3C_TARG_RW_LEN_3_MWL_3_OFFSET })
#define	I3C_TARG_IBI_LEN_IBI_LEN_FIELD_WIDTH   8
#define	I3C_TARG_IBI_LEN_MULTIREG_COUNT   1
#define	I3C_TARG_IBI_LEN_REG_OFFSET   0x350
#define	I3C_TARG_IBI_LEN_REG_RESVAL   0xffffffffu
#define	I3C_TARG_IBI_LEN_IBI_LEN_0_MASK   0xffu
#define	I3C_TARG_IBI_LEN_IBI_LEN_0_OFFSET   0
#define	I3C_TARG_IBI_LEN_IBI_LEN_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_0_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_0_OFFSET })
#define	I3C_TARG_IBI_LEN_IBI_LEN_1_MASK   0xffu
#define	I3C_TARG_IBI_LEN_IBI_LEN_1_OFFSET   8
#define	I3C_TARG_IBI_LEN_IBI_LEN_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_1_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_1_OFFSET })
#define	I3C_TARG_IBI_LEN_IBI_LEN_2_MASK   0xffu
#define	I3C_TARG_IBI_LEN_IBI_LEN_2_OFFSET   16
#define	I3C_TARG_IBI_LEN_IBI_LEN_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_2_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_2_OFFSET })
#define	I3C_TARG_IBI_LEN_IBI_LEN_3_MASK   0xffu
#define	I3C_TARG_IBI_LEN_IBI_LEN_3_OFFSET   24
#define	I3C_TARG_IBI_LEN_IBI_LEN_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_3_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_3_OFFSET })
#define	I3C_TARG_EVENT_ENABLE_ENINT_FIELD_WIDTH   1
#define	I3C_TARG_EVENT_ENABLE_ENCR_FIELD_WIDTH   1
#define	I3C_TARG_EVENT_ENABLE_ENHJ_FIELD_WIDTH   1
#define	I3C_TARG_EVENT_ENABLE_MULTIREG_COUNT   4
#define	I3C_TARG_EVENT_ENABLE_0_REG_OFFSET   0x354
#define	I3C_TARG_EVENT_ENABLE_0_REG_RESVAL   0x7u
#define	I3C_TARG_EVENT_ENABLE_0_ENINT_0_BIT   0
#define	I3C_TARG_EVENT_ENABLE_0_ENCR_0_BIT   1
#define	I3C_TARG_EVENT_ENABLE_0_ENHJ_0_BIT   2
#define	I3C_TARG_EVENT_ENABLE_1_REG_OFFSET   0x358
#define	I3C_TARG_EVENT_ENABLE_1_REG_RESVAL   0x7u
#define	I3C_TARG_EVENT_ENABLE_1_ENINT_1_BIT   0
#define	I3C_TARG_EVENT_ENABLE_1_ENCR_1_BIT   1
#define	I3C_TARG_EVENT_ENABLE_1_ENHJ_1_BIT   2
#define	I3C_TARG_EVENT_ENABLE_2_REG_OFFSET   0x35c
#define	I3C_TARG_EVENT_ENABLE_2_REG_RESVAL   0x7u
#define	I3C_TARG_EVENT_ENABLE_2_ENINT_2_BIT   0
#define	I3C_TARG_EVENT_ENABLE_2_ENCR_2_BIT   1
#define	I3C_TARG_EVENT_ENABLE_2_ENHJ_2_BIT   2
#define	I3C_TARG_EVENT_ENABLE_3_REG_OFFSET   0x360
#define	I3C_TARG_EVENT_ENABLE_3_REG_RESVAL   0x7u
#define	I3C_TARG_EVENT_ENABLE_3_ENINT_3_BIT   0
#define	I3C_TARG_EVENT_ENABLE_3_ENCR_3_BIT   1
#define	I3C_TARG_EVENT_ENABLE_3_ENHJ_3_BIT   2
#define	I3C_TARG_STATE_DEBUG_REG_OFFSET   0x364
#define	I3C_TARG_STATE_DEBUG_REG_RESVAL   0x3u
#define	I3C_TARG_STATE_DEBUG_SCL_LINE_SIGNAL_LEVEL_BIT   0
#define	I3C_TARG_STATE_DEBUG_SDA_LINE_SIGNAL_LEVEL_BIT   1
#define	I3C_TARG_STATE_DEBUG_BUS_AVAIL_BIT   8
#define	I3C_TARG_STATE_DEBUG_BUS_IDLE_BIT   9
#define	I3C_TARG_STATE_DEBUG_BUS_MODE_MASK   0xfu
#define	I3C_TARG_STATE_DEBUG_BUS_MODE_OFFSET   12
#define	I3C_TARG_STATE_DEBUG_BUS_MODE_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATE_DEBUG_BUS_MODE_MASK, .index = I3C_TARG_STATE_DEBUG_BUS_MODE_OFFSET })
#define	I3C_TARG_STATE_DEBUG_FSM_STATE_MASK   0xffu
#define	I3C_TARG_STATE_DEBUG_FSM_STATE_OFFSET   16
#define	I3C_TARG_STATE_DEBUG_FSM_STATE_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATE_DEBUG_FSM_STATE_MASK, .index = I3C_TARG_STATE_DEBUG_FSM_STATE_OFFSET })
#define	I3C_TARG_STATE_DEBUG_TRX_STATE_MASK   0xffu
#define	I3C_TARG_STATE_DEBUG_TRX_STATE_OFFSET   24
#define	I3C_TARG_STATE_DEBUG_TRX_STATE_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATE_DEBUG_TRX_STATE_MASK, .index = I3C_TARG_STATE_DEBUG_TRX_STATE_OFFSET })
#define	I3C_TARG_ENABLE_ENABLE_FIELD_WIDTH   1
#define	I3C_TARG_ENABLE_MULTIREG_COUNT   1
#define	I3C_TARG_ENABLE_REG_OFFSET   0x368
#define	I3C_TARG_ENABLE_REG_RESVAL   0x0u
#define	I3C_TARG_ENABLE_ENABLE_0_BIT   0
#define	I3C_TARG_ENABLE_ENABLE_1_BIT   1
#define	I3C_TARG_ENABLE_ENABLE_2_BIT   2
#define	I3C_TARG_ENABLE_ENABLE_3_BIT   3
#define	I3C_TARG_GROUP_GROUP_ADDR_FIELD_WIDTH   7
#define	I3C_TARG_GROUP_TARGETS_FIELD_WIDTH   4
#define	I3C_TARG_GROUP_MULTIREG_COUNT   8
#define	I3C_TARG_GROUP_0_REG_OFFSET   0x36c
#define	I3C_TARG_GROUP_0_REG_RESVAL   0x0u
#define	I3C_TARG_GROUP_0_GROUP_ADDR_0_MASK   0x7fu
#define	I3C_TARG_GROUP_0_GROUP_ADDR_0_OFFSET   0
#define	I3C_TARG_GROUP_0_GROUP_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_0_GROUP_ADDR_0_MASK, .index = I3C_TARG_GROUP_0_GROUP_ADDR_0_OFFSET })
#define	I3C_TARG_GROUP_0_TARGETS_0_MASK   0xfu
#define	I3C_TARG_GROUP_0_TARGETS_0_OFFSET   8
#define	I3C_TARG_GROUP_0_TARGETS_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_0_TARGETS_0_MASK, .index = I3C_TARG_GROUP_0_TARGETS_0_OFFSET })
#define	I3C_TARG_GROUP_1_REG_OFFSET   0x370
#define	I3C_TARG_GROUP_1_REG_RESVAL   0x0u
#define	I3C_TARG_GROUP_1_GROUP_ADDR_1_MASK   0x7fu
#define	I3C_TARG_GROUP_1_GROUP_ADDR_1_OFFSET   0
#define	I3C_TARG_GROUP_1_GROUP_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_1_GROUP_ADDR_1_MASK, .index = I3C_TARG_GROUP_1_GROUP_ADDR_1_OFFSET })
#define	I3C_TARG_GROUP_1_TARGETS_1_MASK   0xfu
#define	I3C_TARG_GROUP_1_TARGETS_1_OFFSET   8
#define	I3C_TARG_GROUP_1_TARGETS_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_1_TARGETS_1_MASK, .index = I3C_TARG_GROUP_1_TARGETS_1_OFFSET })
#define	I3C_TARG_GROUP_2_REG_OFFSET   0x374
#define	I3C_TARG_GROUP_2_REG_RESVAL   0x0u
#define	I3C_TARG_GROUP_2_GROUP_ADDR_2_MASK   0x7fu
#define	I3C_TARG_GROUP_2_GROUP_ADDR_2_OFFSET   0
#define	I3C_TARG_GROUP_2_GROUP_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_2_GROUP_ADDR_2_MASK, .index = I3C_TARG_GROUP_2_GROUP_ADDR_2_OFFSET })
#define	I3C_TARG_GROUP_2_TARGETS_2_MASK   0xfu
#define	I3C_TARG_GROUP_2_TARGETS_2_OFFSET   8
#define	I3C_TARG_GROUP_2_TARGETS_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_2_TARGETS_2_MASK, .index = I3C_TARG_GROUP_2_TARGETS_2_OFFSET })
#define	I3C_TARG_GROUP_3_REG_OFFSET   0x378
#define	I3C_TARG_GROUP_3_REG_RESVAL   0x0u
#define	I3C_TARG_GROUP_3_GROUP_ADDR_3_MASK   0x7fu
#define	I3C_TARG_GROUP_3_GROUP_ADDR_3_OFFSET   0
#define	I3C_TARG_GROUP_3_GROUP_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_3_GROUP_ADDR_3_MASK, .index = I3C_TARG_GROUP_3_GROUP_ADDR_3_OFFSET })
#define	I3C_TARG_GROUP_3_TARGETS_3_MASK   0xfu
#define	I3C_TARG_GROUP_3_TARGETS_3_OFFSET   8
#define	I3C_TARG_GROUP_3_TARGETS_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_3_TARGETS_3_MASK, .index = I3C_TARG_GROUP_3_TARGETS_3_OFFSET })
#define	I3C_TARG_GROUP_4_REG_OFFSET   0x37c
#define	I3C_TARG_GROUP_4_REG_RESVAL   0x0u
#define	I3C_TARG_GROUP_4_GROUP_ADDR_4_MASK   0x7fu
#define	I3C_TARG_GROUP_4_GROUP_ADDR_4_OFFSET   0
#define	I3C_TARG_GROUP_4_GROUP_ADDR_4_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_4_GROUP_ADDR_4_MASK, .index = I3C_TARG_GROUP_4_GROUP_ADDR_4_OFFSET })
#define	I3C_TARG_GROUP_4_TARGETS_4_MASK   0xfu
#define	I3C_TARG_GROUP_4_TARGETS_4_OFFSET   8
#define	I3C_TARG_GROUP_4_TARGETS_4_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_4_TARGETS_4_MASK, .index = I3C_TARG_GROUP_4_TARGETS_4_OFFSET })
#define	I3C_TARG_GROUP_5_REG_OFFSET   0x380
#define	I3C_TARG_GROUP_5_REG_RESVAL   0x0u
#define	I3C_TARG_GROUP_5_GROUP_ADDR_5_MASK   0x7fu
#define	I3C_TARG_GROUP_5_GROUP_ADDR_5_OFFSET   0
#define	I3C_TARG_GROUP_5_GROUP_ADDR_5_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_5_GROUP_ADDR_5_MASK, .index = I3C_TARG_GROUP_5_GROUP_ADDR_5_OFFSET })
#define	I3C_TARG_GROUP_5_TARGETS_5_MASK   0xfu
#define	I3C_TARG_GROUP_5_TARGETS_5_OFFSET   8
#define	I3C_TARG_GROUP_5_TARGETS_5_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_5_TARGETS_5_MASK, .index = I3C_TARG_GROUP_5_TARGETS_5_OFFSET })
#define	I3C_TARG_GROUP_6_REG_OFFSET   0x384
#define	I3C_TARG_GROUP_6_REG_RESVAL   0x0u
#define	I3C_TARG_GROUP_6_GROUP_ADDR_6_MASK   0x7fu
#define	I3C_TARG_GROUP_6_GROUP_ADDR_6_OFFSET   0
#define	I3C_TARG_GROUP_6_GROUP_ADDR_6_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_6_GROUP_ADDR_6_MASK, .index = I3C_TARG_GROUP_6_GROUP_ADDR_6_OFFSET })
#define	I3C_TARG_GROUP_6_TARGETS_6_MASK   0xfu
#define	I3C_TARG_GROUP_6_TARGETS_6_OFFSET   8
#define	I3C_TARG_GROUP_6_TARGETS_6_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_6_TARGETS_6_MASK, .index = I3C_TARG_GROUP_6_TARGETS_6_OFFSET })
#define	I3C_TARG_GROUP_7_REG_OFFSET   0x388
#define	I3C_TARG_GROUP_7_REG_RESVAL   0x0u
#define	I3C_TARG_GROUP_7_GROUP_ADDR_7_MASK   0x7fu
#define	I3C_TARG_GROUP_7_GROUP_ADDR_7_OFFSET   0
#define	I3C_TARG_GROUP_7_GROUP_ADDR_7_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_7_GROUP_ADDR_7_MASK, .index = I3C_TARG_GROUP_7_GROUP_ADDR_7_OFFSET })
#define	I3C_TARG_GROUP_7_TARGETS_7_MASK   0xfu
#define	I3C_TARG_GROUP_7_TARGETS_7_OFFSET   8
#define	I3C_TARG_GROUP_7_TARGETS_7_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_7_TARGETS_7_MASK, .index = I3C_TARG_GROUP_7_TARGETS_7_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_TX_BUF_FREE_THLD_FIELD_WIDTH   12
#define	I3C_TARG_TX_THLD_CTRL_TX_DESC_EMPTY_THLD_FIELD_WIDTH   8
#define	I3C_TARG_TX_THLD_CTRL_TX_START_THLD_FIELD_WIDTH   4
#define	I3C_TARG_TX_THLD_CTRL_MULTIREG_COUNT   4
#define	I3C_TARG_TX_THLD_CTRL_0_REG_OFFSET   0x38c
#define	I3C_TARG_TX_THLD_CTRL_0_REG_RESVAL   0x10010001u
#define	I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_MASK   0xfffu
#define	I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_OFFSET   0
#define	I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_MASK, .index = I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_MASK   0xffu
#define	I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_OFFSET   16
#define	I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_MASK, .index = I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_MASK   0xfu
#define	I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_OFFSET   28
#define	I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_MASK, .index = I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_1_REG_OFFSET   0x390
#define	I3C_TARG_TX_THLD_CTRL_1_REG_RESVAL   0x10010001u
#define	I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_MASK   0xfffu
#define	I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_OFFSET   0
#define	I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_MASK, .index = I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_MASK   0xffu
#define	I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_OFFSET   16
#define	I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_MASK, .index = I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_MASK   0xfu
#define	I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_OFFSET   28
#define	I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_MASK, .index = I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_2_REG_OFFSET   0x394
#define	I3C_TARG_TX_THLD_CTRL_2_REG_RESVAL   0x10010001u
#define	I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_MASK   0xfffu
#define	I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_OFFSET   0
#define	I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_MASK, .index = I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_MASK   0xffu
#define	I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_OFFSET   16
#define	I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_MASK, .index = I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_MASK   0xfu
#define	I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_OFFSET   28
#define	I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_MASK, .index = I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_3_REG_OFFSET   0x398
#define	I3C_TARG_TX_THLD_CTRL_3_REG_RESVAL   0x10010001u
#define	I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_MASK   0xfffu
#define	I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_OFFSET   0
#define	I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_MASK, .index = I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_MASK   0xffu
#define	I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_OFFSET   16
#define	I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_MASK, .index = I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_OFFSET })
#define	I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_MASK   0xfu
#define	I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_OFFSET   28
#define	I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_MASK, .index = I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_OFFSET })
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_TX_BUF_FREE_LVL_FIELD_WIDTH   12
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_TX_DESC_FREE_LVL_FIELD_WIDTH   8
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_MULTIREG_COUNT   4
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_REG_OFFSET   0x39c
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_REG_RESVAL   0x80040u
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_MASK   0xfffu
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_OFFSET   0
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_OFFSET })
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_MASK   0xffu
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_OFFSET   16
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_OFFSET })
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_REG_OFFSET   0x3a0
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_REG_RESVAL   0x80040u
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_MASK   0xfffu
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_OFFSET   0
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_OFFSET })
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_MASK   0xffu
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_OFFSET   16
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_OFFSET })
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_REG_OFFSET   0x3a4
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_REG_RESVAL   0x80040u
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_MASK   0xfffu
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_OFFSET   0
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_OFFSET })
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_MASK   0xffu
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_OFFSET   16
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_OFFSET })
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_REG_OFFSET   0x3a8
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_REG_RESVAL   0x80040u
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_MASK   0xfffu
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_OFFSET   0
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_OFFSET })
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_MASK   0xffu
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_OFFSET   16
#define	I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_OFFSET })
#define	I3C_TARG_ADDR_STATIC_ADDR_FIELD_WIDTH   7
#define	I3C_TARG_ADDR_STATIC_ADDR_VALID_FIELD_WIDTH   1
#define	I3C_TARG_ADDR_DYNAMIC_ADDR_FIELD_WIDTH   7
#define	I3C_TARG_ADDR_DYNAMIC_ADDR_VALID_FIELD_WIDTH   1
#define	I3C_TARG_ADDR_MULTIREG_COUNT   4
#define	I3C_TARG_ADDR_0_REG_OFFSET   0x3ac
#define	I3C_TARG_ADDR_0_REG_RESVAL   0x0u
#define	I3C_TARG_ADDR_0_STATIC_ADDR_0_MASK   0x7fu
#define	I3C_TARG_ADDR_0_STATIC_ADDR_0_OFFSET   0
#define	I3C_TARG_ADDR_0_STATIC_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_0_STATIC_ADDR_0_MASK, .index = I3C_TARG_ADDR_0_STATIC_ADDR_0_OFFSET })
#define	I3C_TARG_ADDR_0_STATIC_ADDR_VALID_0_BIT   15
#define	I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_MASK   0x7fu
#define	I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_OFFSET   16
#define	I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_MASK, .index = I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_OFFSET })
#define	I3C_TARG_ADDR_0_DYNAMIC_ADDR_VALID_0_BIT   31
#define	I3C_TARG_ADDR_1_REG_OFFSET   0x3b0
#define	I3C_TARG_ADDR_1_REG_RESVAL   0x0u
#define	I3C_TARG_ADDR_1_STATIC_ADDR_1_MASK   0x7fu
#define	I3C_TARG_ADDR_1_STATIC_ADDR_1_OFFSET   0
#define	I3C_TARG_ADDR_1_STATIC_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_1_STATIC_ADDR_1_MASK, .index = I3C_TARG_ADDR_1_STATIC_ADDR_1_OFFSET })
#define	I3C_TARG_ADDR_1_STATIC_ADDR_VALID_1_BIT   15
#define	I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_MASK   0x7fu
#define	I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_OFFSET   16
#define	I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_MASK, .index = I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_OFFSET })
#define	I3C_TARG_ADDR_1_DYNAMIC_ADDR_VALID_1_BIT   31
#define	I3C_TARG_ADDR_2_REG_OFFSET   0x3b4
#define	I3C_TARG_ADDR_2_REG_RESVAL   0x0u
#define	I3C_TARG_ADDR_2_STATIC_ADDR_2_MASK   0x7fu
#define	I3C_TARG_ADDR_2_STATIC_ADDR_2_OFFSET   0
#define	I3C_TARG_ADDR_2_STATIC_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_2_STATIC_ADDR_2_MASK, .index = I3C_TARG_ADDR_2_STATIC_ADDR_2_OFFSET })
#define	I3C_TARG_ADDR_2_STATIC_ADDR_VALID_2_BIT   15
#define	I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_MASK   0x7fu
#define	I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_OFFSET   16
#define	I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_MASK, .index = I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_OFFSET })
#define	I3C_TARG_ADDR_2_DYNAMIC_ADDR_VALID_2_BIT   31
#define	I3C_TARG_ADDR_3_REG_OFFSET   0x3b8
#define	I3C_TARG_ADDR_3_REG_RESVAL   0x0u
#define	I3C_TARG_ADDR_3_STATIC_ADDR_3_MASK   0x7fu
#define	I3C_TARG_ADDR_3_STATIC_ADDR_3_OFFSET   0
#define	I3C_TARG_ADDR_3_STATIC_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_3_STATIC_ADDR_3_MASK, .index = I3C_TARG_ADDR_3_STATIC_ADDR_3_OFFSET })
#define	I3C_TARG_ADDR_3_STATIC_ADDR_VALID_3_BIT   15
#define	I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_MASK   0x7fu
#define	I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_OFFSET   16
#define	I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_MASK, .index = I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_OFFSET })
#define	I3C_TARG_ADDR_3_DYNAMIC_ADDR_VALID_3_BIT   31
#define	I3C_TARG_CHAR_PID_HI_FIELD_WIDTH   16
#define	I3C_TARG_CHAR_DCR_FIELD_WIDTH   8
#define	I3C_TARG_CHAR_BCR_FIELD_WIDTH   8
#define	I3C_TARG_CHAR_MULTIREG_COUNT   4
#define	I3C_TARG_CHAR_0_REG_OFFSET   0x3bc
#define	I3C_TARG_CHAR_0_REG_RESVAL   0x3e000000u
#define	I3C_TARG_CHAR_0_PID_HI_0_MASK   0xffffu
#define	I3C_TARG_CHAR_0_PID_HI_0_OFFSET   0
#define	I3C_TARG_CHAR_0_PID_HI_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_0_PID_HI_0_MASK, .index = I3C_TARG_CHAR_0_PID_HI_0_OFFSET })
#define	I3C_TARG_CHAR_0_DCR_0_MASK   0xffu
#define	I3C_TARG_CHAR_0_DCR_0_OFFSET   16
#define	I3C_TARG_CHAR_0_DCR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_0_DCR_0_MASK, .index = I3C_TARG_CHAR_0_DCR_0_OFFSET })
#define	I3C_TARG_CHAR_0_BCR_0_MASK   0xffu
#define	I3C_TARG_CHAR_0_BCR_0_OFFSET   24
#define	I3C_TARG_CHAR_0_BCR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_0_BCR_0_MASK, .index = I3C_TARG_CHAR_0_BCR_0_OFFSET })
#define	I3C_TARG_CHAR_1_REG_OFFSET   0x3c0
#define	I3C_TARG_CHAR_1_REG_RESVAL   0x3e000000u
#define	I3C_TARG_CHAR_1_PID_HI_1_MASK   0xffffu
#define	I3C_TARG_CHAR_1_PID_HI_1_OFFSET   0
#define	I3C_TARG_CHAR_1_PID_HI_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_1_PID_HI_1_MASK, .index = I3C_TARG_CHAR_1_PID_HI_1_OFFSET })
#define	I3C_TARG_CHAR_1_DCR_1_MASK   0xffu
#define	I3C_TARG_CHAR_1_DCR_1_OFFSET   16
#define	I3C_TARG_CHAR_1_DCR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_1_DCR_1_MASK, .index = I3C_TARG_CHAR_1_DCR_1_OFFSET })
#define	I3C_TARG_CHAR_1_BCR_1_MASK   0xffu
#define	I3C_TARG_CHAR_1_BCR_1_OFFSET   24
#define	I3C_TARG_CHAR_1_BCR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_1_BCR_1_MASK, .index = I3C_TARG_CHAR_1_BCR_1_OFFSET })
#define	I3C_TARG_CHAR_2_REG_OFFSET   0x3c4
#define	I3C_TARG_CHAR_2_REG_RESVAL   0x3e000000u
#define	I3C_TARG_CHAR_2_PID_HI_2_MASK   0xffffu
#define	I3C_TARG_CHAR_2_PID_HI_2_OFFSET   0
#define	I3C_TARG_CHAR_2_PID_HI_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_2_PID_HI_2_MASK, .index = I3C_TARG_CHAR_2_PID_HI_2_OFFSET })
#define	I3C_TARG_CHAR_2_DCR_2_MASK   0xffu
#define	I3C_TARG_CHAR_2_DCR_2_OFFSET   16
#define	I3C_TARG_CHAR_2_DCR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_2_DCR_2_MASK, .index = I3C_TARG_CHAR_2_DCR_2_OFFSET })
#define	I3C_TARG_CHAR_2_BCR_2_MASK   0xffu
#define	I3C_TARG_CHAR_2_BCR_2_OFFSET   24
#define	I3C_TARG_CHAR_2_BCR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_2_BCR_2_MASK, .index = I3C_TARG_CHAR_2_BCR_2_OFFSET })
#define	I3C_TARG_CHAR_3_REG_OFFSET   0x3c8
#define	I3C_TARG_CHAR_3_REG_RESVAL   0x3e000000u
#define	I3C_TARG_CHAR_3_PID_HI_3_MASK   0xffffu
#define	I3C_TARG_CHAR_3_PID_HI_3_OFFSET   0
#define	I3C_TARG_CHAR_3_PID_HI_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_3_PID_HI_3_MASK, .index = I3C_TARG_CHAR_3_PID_HI_3_OFFSET })
#define	I3C_TARG_CHAR_3_DCR_3_MASK   0xffu
#define	I3C_TARG_CHAR_3_DCR_3_OFFSET   16
#define	I3C_TARG_CHAR_3_DCR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_3_DCR_3_MASK, .index = I3C_TARG_CHAR_3_DCR_3_OFFSET })
#define	I3C_TARG_CHAR_3_BCR_3_MASK   0xffu
#define	I3C_TARG_CHAR_3_BCR_3_OFFSET   24
#define	I3C_TARG_CHAR_3_BCR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_3_BCR_3_MASK, .index = I3C_TARG_CHAR_3_BCR_3_OFFSET })
#define	I3C_TARG_PID_LO_PID_LO_FIELD_WIDTH   32
#define	I3C_TARG_PID_LO_MULTIREG_COUNT   4
#define	I3C_TARG_PID_LO_0_REG_OFFSET   0x3cc
#define	I3C_TARG_PID_LO_0_REG_RESVAL   0x0u
#define	I3C_TARG_PID_LO_1_REG_OFFSET   0x3d0
#define	I3C_TARG_PID_LO_1_REG_RESVAL   0x0u
#define	I3C_TARG_PID_LO_2_REG_OFFSET   0x3d4
#define	I3C_TARG_PID_LO_2_REG_RESVAL   0x0u
#define	I3C_TARG_PID_LO_3_REG_OFFSET   0x3d8
#define	I3C_TARG_PID_LO_3_REG_RESVAL   0x0u
#define	I3C_TARG_CAPS_VTCAP1_TYPE_FIELD_WIDTH   3
#define	I3C_TARG_CAPS_VTCAP1_SIDE_FX_FIELD_WIDTH   1
#define	I3C_TARG_CAPS_VTCAP1_SHARED_DET_FIELD_WIDTH   1
#define	I3C_TARG_CAPS_VTCAP2_IRQ_FIELD_WIDTH   2
#define	I3C_TARG_CAPS_VTCAP2_ADDR_REMAP_FIELD_WIDTH   1
#define	I3C_TARG_CAPS_VTCAP2_BUS_CTX_FIELD_WIDTH   2
#define	I3C_TARG_CAPS_MULTIREG_COUNT   4
#define	I3C_TARG_CAPS_0_REG_OFFSET   0x3dc
#define	I3C_TARG_CAPS_0_REG_RESVAL   0x0u
#define	I3C_TARG_CAPS_0_VTCAP1_TYPE_0_MASK   0x7u
#define	I3C_TARG_CAPS_0_VTCAP1_TYPE_0_OFFSET   0
#define	I3C_TARG_CAPS_0_VTCAP1_TYPE_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_0_VTCAP1_TYPE_0_MASK, .index = I3C_TARG_CAPS_0_VTCAP1_TYPE_0_OFFSET })
#define	I3C_TARG_CAPS_0_VTCAP1_SIDE_FX_0_BIT   4
#define	I3C_TARG_CAPS_0_VTCAP1_SHARED_DET_0_BIT   5
#define	I3C_TARG_CAPS_0_VTCAP2_IRQ_0_MASK   0x3u
#define	I3C_TARG_CAPS_0_VTCAP2_IRQ_0_OFFSET   8
#define	I3C_TARG_CAPS_0_VTCAP2_IRQ_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_0_VTCAP2_IRQ_0_MASK, .index = I3C_TARG_CAPS_0_VTCAP2_IRQ_0_OFFSET })
#define	I3C_TARG_CAPS_0_VTCAP2_ADDR_REMAP_0_BIT   10
#define	I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_MASK   0x3u
#define	I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_OFFSET   11
#define	I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_MASK, .index = I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_OFFSET })
#define	I3C_TARG_CAPS_1_REG_OFFSET   0x3e0
#define	I3C_TARG_CAPS_1_REG_RESVAL   0x0u
#define	I3C_TARG_CAPS_1_VTCAP1_TYPE_1_MASK   0x7u
#define	I3C_TARG_CAPS_1_VTCAP1_TYPE_1_OFFSET   0
#define	I3C_TARG_CAPS_1_VTCAP1_TYPE_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_1_VTCAP1_TYPE_1_MASK, .index = I3C_TARG_CAPS_1_VTCAP1_TYPE_1_OFFSET })
#define	I3C_TARG_CAPS_1_VTCAP1_SIDE_FX_1_BIT   4
#define	I3C_TARG_CAPS_1_VTCAP1_SHARED_DET_1_BIT   5
#define	I3C_TARG_CAPS_1_VTCAP2_IRQ_1_MASK   0x3u
#define	I3C_TARG_CAPS_1_VTCAP2_IRQ_1_OFFSET   8
#define	I3C_TARG_CAPS_1_VTCAP2_IRQ_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_1_VTCAP2_IRQ_1_MASK, .index = I3C_TARG_CAPS_1_VTCAP2_IRQ_1_OFFSET })
#define	I3C_TARG_CAPS_1_VTCAP2_ADDR_REMAP_1_BIT   10
#define	I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_MASK   0x3u
#define	I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_OFFSET   11
#define	I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_MASK, .index = I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_OFFSET })
#define	I3C_TARG_CAPS_2_REG_OFFSET   0x3e4
#define	I3C_TARG_CAPS_2_REG_RESVAL   0x0u
#define	I3C_TARG_CAPS_2_VTCAP1_TYPE_2_MASK   0x7u
#define	I3C_TARG_CAPS_2_VTCAP1_TYPE_2_OFFSET   0
#define	I3C_TARG_CAPS_2_VTCAP1_TYPE_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_2_VTCAP1_TYPE_2_MASK, .index = I3C_TARG_CAPS_2_VTCAP1_TYPE_2_OFFSET })
#define	I3C_TARG_CAPS_2_VTCAP1_SIDE_FX_2_BIT   4
#define	I3C_TARG_CAPS_2_VTCAP1_SHARED_DET_2_BIT   5
#define	I3C_TARG_CAPS_2_VTCAP2_IRQ_2_MASK   0x3u
#define	I3C_TARG_CAPS_2_VTCAP2_IRQ_2_OFFSET   8
#define	I3C_TARG_CAPS_2_VTCAP2_IRQ_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_2_VTCAP2_IRQ_2_MASK, .index = I3C_TARG_CAPS_2_VTCAP2_IRQ_2_OFFSET })
#define	I3C_TARG_CAPS_2_VTCAP2_ADDR_REMAP_2_BIT   10
#define	I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_MASK   0x3u
#define	I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_OFFSET   11
#define	I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_MASK, .index = I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_OFFSET })
#define	I3C_TARG_CAPS_3_REG_OFFSET   0x3e8
#define	I3C_TARG_CAPS_3_REG_RESVAL   0x0u
#define	I3C_TARG_CAPS_3_VTCAP1_TYPE_3_MASK   0x7u
#define	I3C_TARG_CAPS_3_VTCAP1_TYPE_3_OFFSET   0
#define	I3C_TARG_CAPS_3_VTCAP1_TYPE_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_3_VTCAP1_TYPE_3_MASK, .index = I3C_TARG_CAPS_3_VTCAP1_TYPE_3_OFFSET })
#define	I3C_TARG_CAPS_3_VTCAP1_SIDE_FX_3_BIT   4
#define	I3C_TARG_CAPS_3_VTCAP1_SHARED_DET_3_BIT   5
#define	I3C_TARG_CAPS_3_VTCAP2_IRQ_3_MASK   0x3u
#define	I3C_TARG_CAPS_3_VTCAP2_IRQ_3_OFFSET   8
#define	I3C_TARG_CAPS_3_VTCAP2_IRQ_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_3_VTCAP2_IRQ_3_MASK, .index = I3C_TARG_CAPS_3_VTCAP2_IRQ_3_OFFSET })
#define	I3C_TARG_CAPS_3_VTCAP2_ADDR_REMAP_3_BIT   10
#define	I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_MASK   0x3u
#define	I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_OFFSET   11
#define	I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_MASK, .index = I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_OFFSET })
#define	I3C_TARG_INFO_AS_FIELD_WIDTH   2
#define	I3C_TARG_INFO_ENDXFER_WR_NACK_FIELD_WIDTH   1
#define	I3C_TARG_INFO_ENDXFER_WR_EARLY_TERM_FIELD_WIDTH   1
#define	I3C_TARG_INFO_ENDXFER_CRC_EARLY_FIELD_WIDTH   1
#define	I3C_TARG_INFO_ENDXFER_CAND_WR_NACK_FIELD_WIDTH   1
#define	I3C_TARG_INFO_ENDXFER_CAND_WR_EARLY_TERM_FIELD_WIDTH   1
#define	I3C_TARG_INFO_ENDXFER_CAND_CRC_EARLY_FIELD_WIDTH   1
#define	I3C_TARG_INFO_MULTIREG_COUNT   4
#define	I3C_TARG_INFO_0_REG_OFFSET   0x3ec
#define	I3C_TARG_INFO_0_REG_RESVAL   0x2020u
#define	I3C_TARG_INFO_0_AS_0_MASK   0x3u
#define	I3C_TARG_INFO_0_AS_0_OFFSET   0
#define	I3C_TARG_INFO_0_AS_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_INFO_0_AS_0_MASK, .index = I3C_TARG_INFO_0_AS_0_OFFSET })
#define	I3C_TARG_INFO_0_ENDXFER_WR_NACK_0_BIT   3
#define	I3C_TARG_INFO_0_ENDXFER_WR_EARLY_TERM_0_BIT   4
#define	I3C_TARG_INFO_0_ENDXFER_CRC_EARLY_0_BIT   5
#define	I3C_TARG_INFO_0_ENDXFER_CAND_WR_NACK_0_BIT   11
#define	I3C_TARG_INFO_0_ENDXFER_CAND_WR_EARLY_TERM_0_BIT   12
#define	I3C_TARG_INFO_0_ENDXFER_CAND_CRC_EARLY_0_BIT   13
#define	I3C_TARG_INFO_1_REG_OFFSET   0x3f0
#define	I3C_TARG_INFO_1_REG_RESVAL   0x2020u
#define	I3C_TARG_INFO_1_AS_1_MASK   0x3u
#define	I3C_TARG_INFO_1_AS_1_OFFSET   0
#define	I3C_TARG_INFO_1_AS_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_INFO_1_AS_1_MASK, .index = I3C_TARG_INFO_1_AS_1_OFFSET })
#define	I3C_TARG_INFO_1_ENDXFER_WR_NACK_1_BIT   3
#define	I3C_TARG_INFO_1_ENDXFER_WR_EARLY_TERM_1_BIT   4
#define	I3C_TARG_INFO_1_ENDXFER_CRC_EARLY_1_BIT   5
#define	I3C_TARG_INFO_1_ENDXFER_CAND_WR_NACK_1_BIT   11
#define	I3C_TARG_INFO_1_ENDXFER_CAND_WR_EARLY_TERM_1_BIT   12
#define	I3C_TARG_INFO_1_ENDXFER_CAND_CRC_EARLY_1_BIT   13
#define	I3C_TARG_INFO_2_REG_OFFSET   0x3f4
#define	I3C_TARG_INFO_2_REG_RESVAL   0x2020u
#define	I3C_TARG_INFO_2_AS_2_MASK   0x3u
#define	I3C_TARG_INFO_2_AS_2_OFFSET   0
#define	I3C_TARG_INFO_2_AS_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_INFO_2_AS_2_MASK, .index = I3C_TARG_INFO_2_AS_2_OFFSET })
#define	I3C_TARG_INFO_2_ENDXFER_WR_NACK_2_BIT   3
#define	I3C_TARG_INFO_2_ENDXFER_WR_EARLY_TERM_2_BIT   4
#define	I3C_TARG_INFO_2_ENDXFER_CRC_EARLY_2_BIT   5
#define	I3C_TARG_INFO_2_ENDXFER_CAND_WR_NACK_2_BIT   11
#define	I3C_TARG_INFO_2_ENDXFER_CAND_WR_EARLY_TERM_2_BIT   12
#define	I3C_TARG_INFO_2_ENDXFER_CAND_CRC_EARLY_2_BIT   13
#define	I3C_TARG_INFO_3_REG_OFFSET   0x3f8
#define	I3C_TARG_INFO_3_REG_RESVAL   0x2020u
#define	I3C_TARG_INFO_3_AS_3_MASK   0x3u
#define	I3C_TARG_INFO_3_AS_3_OFFSET   0
#define	I3C_TARG_INFO_3_AS_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_INFO_3_AS_3_MASK, .index = I3C_TARG_INFO_3_AS_3_OFFSET })
#define	I3C_TARG_INFO_3_ENDXFER_WR_NACK_3_BIT   3
#define	I3C_TARG_INFO_3_ENDXFER_WR_EARLY_TERM_3_BIT   4
#define	I3C_TARG_INFO_3_ENDXFER_CRC_EARLY_3_BIT   5
#define	I3C_TARG_INFO_3_ENDXFER_CAND_WR_NACK_3_BIT   11
#define	I3C_TARG_INFO_3_ENDXFER_CAND_WR_EARLY_TERM_3_BIT   12
#define	I3C_TARG_INFO_3_ENDXFER_CAND_CRC_EARLY_3_BIT   13
#define	I3C_TARG_MAX_RDWR_MAXRD_FIELD_WIDTH   7
#define	I3C_TARG_MAX_RDWR_MAXWR_FIELD_WIDTH   8
#define	I3C_TARG_MAX_RDWR_RDTURN_VAL_FIELD_WIDTH   12
#define	I3C_TARG_MAX_RDWR_RDTURN_SCALE_FIELD_WIDTH   4
#define	I3C_TARG_MAX_RDWR_MULTIREG_COUNT   4
#define	I3C_TARG_MAX_RDWR_0_REG_OFFSET   0x3fc
#define	I3C_TARG_MAX_RDWR_0_REG_RESVAL   0x10000u
#define	I3C_TARG_MAX_RDWR_0_MAXRD_0_MASK   0x7fu
#define	I3C_TARG_MAX_RDWR_0_MAXRD_0_OFFSET   0
#define	I3C_TARG_MAX_RDWR_0_MAXRD_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_MAXRD_0_MASK, .index = I3C_TARG_MAX_RDWR_0_MAXRD_0_OFFSET })
#define	I3C_TARG_MAX_RDWR_0_MAXWR_0_MASK   0xffu
#define	I3C_TARG_MAX_RDWR_0_MAXWR_0_OFFSET   8
#define	I3C_TARG_MAX_RDWR_0_MAXWR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_MAXWR_0_MASK, .index = I3C_TARG_MAX_RDWR_0_MAXWR_0_OFFSET })
#define	I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_MASK   0xfffu
#define	I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_OFFSET   16
#define	I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_MASK, .index = I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_OFFSET })
#define	I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_MASK   0xfu
#define	I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_OFFSET   28
#define	I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_MASK, .index = I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_OFFSET })
#define	I3C_TARG_MAX_RDWR_1_REG_OFFSET   0x400
#define	I3C_TARG_MAX_RDWR_1_REG_RESVAL   0x10000u
#define	I3C_TARG_MAX_RDWR_1_MAXRD_1_MASK   0x7fu
#define	I3C_TARG_MAX_RDWR_1_MAXRD_1_OFFSET   0
#define	I3C_TARG_MAX_RDWR_1_MAXRD_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_MAXRD_1_MASK, .index = I3C_TARG_MAX_RDWR_1_MAXRD_1_OFFSET })
#define	I3C_TARG_MAX_RDWR_1_MAXWR_1_MASK   0xffu
#define	I3C_TARG_MAX_RDWR_1_MAXWR_1_OFFSET   8
#define	I3C_TARG_MAX_RDWR_1_MAXWR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_MAXWR_1_MASK, .index = I3C_TARG_MAX_RDWR_1_MAXWR_1_OFFSET })
#define	I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_MASK   0xfffu
#define	I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_OFFSET   16
#define	I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_MASK, .index = I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_OFFSET })
#define	I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_MASK   0xfu
#define	I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_OFFSET   28
#define	I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_MASK, .index = I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_OFFSET })
#define	I3C_TARG_MAX_RDWR_2_REG_OFFSET   0x404
#define	I3C_TARG_MAX_RDWR_2_REG_RESVAL   0x10000u
#define	I3C_TARG_MAX_RDWR_2_MAXRD_2_MASK   0x7fu
#define	I3C_TARG_MAX_RDWR_2_MAXRD_2_OFFSET   0
#define	I3C_TARG_MAX_RDWR_2_MAXRD_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_MAXRD_2_MASK, .index = I3C_TARG_MAX_RDWR_2_MAXRD_2_OFFSET })
#define	I3C_TARG_MAX_RDWR_2_MAXWR_2_MASK   0xffu
#define	I3C_TARG_MAX_RDWR_2_MAXWR_2_OFFSET   8
#define	I3C_TARG_MAX_RDWR_2_MAXWR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_MAXWR_2_MASK, .index = I3C_TARG_MAX_RDWR_2_MAXWR_2_OFFSET })
#define	I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_MASK   0xfffu
#define	I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_OFFSET   16
#define	I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_MASK, .index = I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_OFFSET })
#define	I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_MASK   0xfu
#define	I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_OFFSET   28
#define	I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_MASK, .index = I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_OFFSET })
#define	I3C_TARG_MAX_RDWR_3_REG_OFFSET   0x408
#define	I3C_TARG_MAX_RDWR_3_REG_RESVAL   0x10000u
#define	I3C_TARG_MAX_RDWR_3_MAXRD_3_MASK   0x7fu
#define	I3C_TARG_MAX_RDWR_3_MAXRD_3_OFFSET   0
#define	I3C_TARG_MAX_RDWR_3_MAXRD_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_MAXRD_3_MASK, .index = I3C_TARG_MAX_RDWR_3_MAXRD_3_OFFSET })
#define	I3C_TARG_MAX_RDWR_3_MAXWR_3_MASK   0xffu
#define	I3C_TARG_MAX_RDWR_3_MAXWR_3_OFFSET   8
#define	I3C_TARG_MAX_RDWR_3_MAXWR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_MAXWR_3_MASK, .index = I3C_TARG_MAX_RDWR_3_MAXWR_3_OFFSET })
#define	I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_MASK   0xfffu
#define	I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_OFFSET   16
#define	I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_MASK, .index = I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_OFFSET })
#define	I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_MASK   0xfu
#define	I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_OFFSET   28
#define	I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_MASK, .index = I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_OFFSET })
#define	I3C_TTI_PORTS_REG_OFFSET   0x440
#define	I3C_TTI_PORTS_SIZE_WORDS   13
#define	I3C_TTI_PORTS_SIZE_BYTES   52
#define	I3C_TARGEXT_EXTCAP_HEADER_REG_OFFSET   0x474
#define	I3C_TARGEXT_EXTCAP_HEADER_REG_RESVAL   0x1c0u
#define	I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_MASK   0xffu
#define	I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_OFFSET   0
#define	I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_OFFSET })
#define	I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu
#define	I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8
#define	I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
#define	I3C_TERM_EXTCAP_HEADER_REG_OFFSET   0x478
#define	I3C_TERM_EXTCAP_HEADER_REG_RESVAL   0x100u
#define	I3C_TERM_EXTCAP_HEADER_CAP_ID_MASK   0xffu
#define	I3C_TERM_EXTCAP_HEADER_CAP_ID_OFFSET   0
#define	I3C_TERM_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_TERM_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_TERM_EXTCAP_HEADER_CAP_ID_OFFSET })
#define	I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu
#define	I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8
#define	I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
#define	I3C_DAT_REG_OFFSET   0xa00
#define	I3C_DAT_SIZE_WORDS   64
#define	I3C_DAT_SIZE_BYTES   256
#define	I3C_DCT_REG_OFFSET   0xc00
#define	I3C_DCT_SIZE_WORDS   128
#define	I3C_DCT_SIZE_BYTES   512
#define	I3C_BUFFER_REG_OFFSET   0x1000
#define	I3C_BUFFER_SIZE_WORDS   1024
#define	I3C_BUFFER_SIZE_BYTES   4096

Detailed Description

Generated register defines for i3c.

Definition in file i3c_regs.h.

Macro Definition Documentation

I3C_ALERT_TEST_FATAL_FAULT_BIT

#define I3C_ALERT_TEST_FATAL_FAULT_BIT   0

Definition at line 68 of file i3c_regs.h.

I3C_ALERT_TEST_REG_OFFSET

#define I3C_ALERT_TEST_REG_OFFSET   0xc

Definition at line 66 of file i3c_regs.h.

I3C_ALERT_TEST_REG_RESVAL

#define I3C_ALERT_TEST_REG_RESVAL   0x80000000u

Definition at line 67 of file i3c_regs.h.

I3C_ALERT_TEST_REGWEN_BIT

#define I3C_ALERT_TEST_REGWEN_BIT   31

Definition at line 69 of file i3c_regs.h.

I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_EN_BIT

#define I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_EN_BIT   24

Definition at line 1222 of file i3c_regs.h.

I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_FIELD

#define I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_MASK, .index = I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_OFFSET })

Definition at line 1220 of file i3c_regs.h.

I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_MASK

#define I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_MASK   0xffu

Definition at line 1218 of file i3c_regs.h.

I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_OFFSET

#define I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_OFFSET   0

Definition at line 1219 of file i3c_regs.h.

I3C_ALT_QUEUE_SIZE_EXT_IBI_QUEUE_EN_BIT

#define I3C_ALT_QUEUE_SIZE_EXT_IBI_QUEUE_EN_BIT   28

Definition at line 1223 of file i3c_regs.h.

I3C_ALT_QUEUE_SIZE_REG_OFFSET

#define I3C_ALT_QUEUE_SIZE_REG_OFFSET   0x21c

Definition at line 1216 of file i3c_regs.h.

I3C_ALT_QUEUE_SIZE_REG_RESVAL

#define I3C_ALT_QUEUE_SIZE_REG_RESVAL   0x11000010u

Definition at line 1217 of file i3c_regs.h.

I3C_BLOCKED_ADDR_ADDR0_FIELD

#define I3C_BLOCKED_ADDR_ADDR0_FIELD    ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_ADDR0_MASK, .index = I3C_BLOCKED_ADDR_ADDR0_OFFSET })

Definition at line 375 of file i3c_regs.h.

I3C_BLOCKED_ADDR_ADDR0_MASK

#define I3C_BLOCKED_ADDR_ADDR0_MASK   0x7fu

Definition at line 373 of file i3c_regs.h.

I3C_BLOCKED_ADDR_ADDR0_OFFSET

#define I3C_BLOCKED_ADDR_ADDR0_OFFSET   0

Definition at line 374 of file i3c_regs.h.

I3C_BLOCKED_ADDR_ADDR1_FIELD

#define I3C_BLOCKED_ADDR_ADDR1_FIELD    ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_ADDR1_MASK, .index = I3C_BLOCKED_ADDR_ADDR1_OFFSET })

Definition at line 383 of file i3c_regs.h.

I3C_BLOCKED_ADDR_ADDR1_MASK

#define I3C_BLOCKED_ADDR_ADDR1_MASK   0x7fu

Definition at line 381 of file i3c_regs.h.

I3C_BLOCKED_ADDR_ADDR1_OFFSET

#define I3C_BLOCKED_ADDR_ADDR1_OFFSET   16

Definition at line 382 of file i3c_regs.h.

I3C_BLOCKED_ADDR_MASK0_FIELD

#define I3C_BLOCKED_ADDR_MASK0_FIELD    ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_MASK0_MASK, .index = I3C_BLOCKED_ADDR_MASK0_OFFSET })

Definition at line 379 of file i3c_regs.h.

I3C_BLOCKED_ADDR_MASK0_MASK

#define I3C_BLOCKED_ADDR_MASK0_MASK   0x7fu

Definition at line 377 of file i3c_regs.h.

I3C_BLOCKED_ADDR_MASK0_OFFSET

#define I3C_BLOCKED_ADDR_MASK0_OFFSET   8

Definition at line 378 of file i3c_regs.h.

I3C_BLOCKED_ADDR_MASK1_FIELD

#define I3C_BLOCKED_ADDR_MASK1_FIELD    ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_MASK1_MASK, .index = I3C_BLOCKED_ADDR_MASK1_OFFSET })

Definition at line 387 of file i3c_regs.h.

I3C_BLOCKED_ADDR_MASK1_MASK

#define I3C_BLOCKED_ADDR_MASK1_MASK   0x7fu

Definition at line 385 of file i3c_regs.h.

I3C_BLOCKED_ADDR_MASK1_OFFSET

#define I3C_BLOCKED_ADDR_MASK1_OFFSET   24

Definition at line 386 of file i3c_regs.h.

I3C_BLOCKED_ADDR_REG_OFFSET

#define I3C_BLOCKED_ADDR_REG_OFFSET   0x68

Definition at line 371 of file i3c_regs.h.

I3C_BLOCKED_ADDR_REG_RESVAL

#define I3C_BLOCKED_ADDR_REG_RESVAL   0x7f007fu

Definition at line 372 of file i3c_regs.h.

I3C_BUFFER_CTRL_CLEAR_BIT

#define I3C_BUFFER_CTRL_CLEAR_BIT   31

Definition at line 397 of file i3c_regs.h.

I3C_BUFFER_CTRL_REG_OFFSET

#define I3C_BUFFER_CTRL_REG_OFFSET   0x6c

Definition at line 391 of file i3c_regs.h.

I3C_BUFFER_CTRL_REG_RESVAL

#define I3C_BUFFER_CTRL_REG_RESVAL   0x0u

Definition at line 392 of file i3c_regs.h.

I3C_BUFFER_CTRL_SW_ADDR_HI_FIELD

#define I3C_BUFFER_CTRL_SW_ADDR_HI_FIELD    ((bitfield_field32_t) { .mask = I3C_BUFFER_CTRL_SW_ADDR_HI_MASK, .index = I3C_BUFFER_CTRL_SW_ADDR_HI_OFFSET })

Definition at line 395 of file i3c_regs.h.

I3C_BUFFER_CTRL_SW_ADDR_HI_MASK

#define I3C_BUFFER_CTRL_SW_ADDR_HI_MASK   0x3u

Definition at line 393 of file i3c_regs.h.

I3C_BUFFER_CTRL_SW_ADDR_HI_OFFSET

#define I3C_BUFFER_CTRL_SW_ADDR_HI_OFFSET   28

Definition at line 394 of file i3c_regs.h.

I3C_BUFFER_REG_OFFSET

#define I3C_BUFFER_REG_OFFSET   0x1000

Definition at line 2612 of file i3c_regs.h.

I3C_BUFFER_SIZE_BYTES

#define I3C_BUFFER_SIZE_BYTES   4096

Definition at line 2614 of file i3c_regs.h.

I3C_BUFFER_SIZE_WORDS

#define I3C_BUFFER_SIZE_WORDS   1024

Definition at line 2613 of file i3c_regs.h.

I3C_BUFFER_STATUS_HCIQ_ERR_BIT

#define I3C_BUFFER_STATUS_HCIQ_ERR_BIT   31

Definition at line 403 of file i3c_regs.h.

I3C_BUFFER_STATUS_REG_OFFSET

#define I3C_BUFFER_STATUS_REG_OFFSET   0x70

Definition at line 400 of file i3c_regs.h.

I3C_BUFFER_STATUS_REG_RESVAL

#define I3C_BUFFER_STATUS_REG_RESVAL   0x0u

Definition at line 401 of file i3c_regs.h.

I3C_BUFFER_STATUS_TTIQ_ERR_BIT

#define I3C_BUFFER_STATUS_TTIQ_ERR_BIT   30

Definition at line 402 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_FIELD

#define I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_MASK, .index = I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_OFFSET })

Definition at line 474 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_MASK

#define I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 472 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_OFFSET

#define I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_OFFSET   12

Definition at line 473 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_FIELD

#define I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_MASK, .index = I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_OFFSET })

Definition at line 470 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_MASK

#define I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 468 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_OFFSET

#define I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 469 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_REG_OFFSET

#define I3C_COMMAND_QUEUE_CONFIG_REG_OFFSET   0x84

Definition at line 466 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_REG_RESVAL

#define I3C_COMMAND_QUEUE_CONFIG_REG_RESVAL   0x1011f100u

Definition at line 467 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_FIELD

#define I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_MASK, .index = I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_OFFSET })

Definition at line 478 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_MASK

#define I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_MASK   0xffu

Definition at line 476 of file i3c_regs.h.

I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_OFFSET

#define I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_OFFSET   24

Definition at line 477 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_FULL_BIT

#define I3C_COMMAND_QUEUE_STATE_FULL_BIT   31

Definition at line 493 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_PRE_BIT

#define I3C_COMMAND_QUEUE_STATE_PRE_BIT   30

Definition at line 492 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_REG_OFFSET

#define I3C_COMMAND_QUEUE_STATE_REG_OFFSET   0x88

Definition at line 482 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_REG_RESVAL

#define I3C_COMMAND_QUEUE_STATE_REG_RESVAL   0x1000100u

Definition at line 483 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_RPTR_FIELD

#define I3C_COMMAND_QUEUE_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_STATE_RPTR_MASK, .index = I3C_COMMAND_QUEUE_STATE_RPTR_OFFSET })

Definition at line 490 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_RPTR_MASK

#define I3C_COMMAND_QUEUE_STATE_RPTR_MASK   0x3ffu

Definition at line 488 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_RPTR_OFFSET

#define I3C_COMMAND_QUEUE_STATE_RPTR_OFFSET   16

Definition at line 489 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_WPTR_FIELD

#define I3C_COMMAND_QUEUE_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_STATE_WPTR_MASK, .index = I3C_COMMAND_QUEUE_STATE_WPTR_OFFSET })

Definition at line 486 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_WPTR_MASK

#define I3C_COMMAND_QUEUE_STATE_WPTR_MASK   0x3ffu

Definition at line 484 of file i3c_regs.h.

I3C_COMMAND_QUEUE_STATE_WPTR_OFFSET

#define I3C_COMMAND_QUEUE_STATE_WPTR_OFFSET   0

Definition at line 485 of file i3c_regs.h.

I3C_COMP_MANUFACTURER_REG_OFFSET

#define I3C_COMP_MANUFACTURER_REG_OFFSET   0x2a4

Definition at line 1289 of file i3c_regs.h.

I3C_COMP_MANUFACTURER_REG_RESVAL

#define I3C_COMP_MANUFACTURER_REG_RESVAL   0x0u

Definition at line 1290 of file i3c_regs.h.

I3C_COMP_TYPE_REG_OFFSET

#define I3C_COMP_TYPE_REG_OFFSET   0x2ac

Definition at line 1297 of file i3c_regs.h.

I3C_COMP_TYPE_REG_RESVAL

#define I3C_COMP_TYPE_REG_RESVAL   0x0u

Definition at line 1298 of file i3c_regs.h.

I3C_COMP_VERSION_REG_OFFSET

#define I3C_COMP_VERSION_REG_OFFSET   0x2a8

Definition at line 1293 of file i3c_regs.h.

I3C_COMP_VERSION_REG_RESVAL

#define I3C_COMP_VERSION_REG_RESVAL   0x0u

Definition at line 1294 of file i3c_regs.h.

I3C_CONTROLLER_CONFIG_OPERATION_MODE_FIELD

#define I3C_CONTROLLER_CONFIG_OPERATION_MODE_FIELD    ((bitfield_field32_t) { .mask = I3C_CONTROLLER_CONFIG_OPERATION_MODE_MASK, .index = I3C_CONTROLLER_CONFIG_OPERATION_MODE_OFFSET })

Definition at line 1317 of file i3c_regs.h.

I3C_CONTROLLER_CONFIG_OPERATION_MODE_MASK

#define I3C_CONTROLLER_CONFIG_OPERATION_MODE_MASK   0x3u

Definition at line 1315 of file i3c_regs.h.

I3C_CONTROLLER_CONFIG_OPERATION_MODE_OFFSET

#define I3C_CONTROLLER_CONFIG_OPERATION_MODE_OFFSET   4

Definition at line 1316 of file i3c_regs.h.

I3C_CONTROLLER_CONFIG_REG_OFFSET

#define I3C_CONTROLLER_CONFIG_REG_OFFSET   0x2b4

Definition at line 1313 of file i3c_regs.h.

I3C_CONTROLLER_CONFIG_REG_RESVAL

#define I3C_CONTROLLER_CONFIG_REG_RESVAL   0x10u

Definition at line 1314 of file i3c_regs.h.

I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_FIELD

#define I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_MASK, .index = I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET })

Definition at line 966 of file i3c_regs.h.

I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_MASK

#define I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_MASK   0x7fu

Definition at line 964 of file i3c_regs.h.

I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET

#define I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET   16

Definition at line 965 of file i3c_regs.h.

I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_VALID_BIT

#define I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_VALID_BIT   31

Definition at line 968 of file i3c_regs.h.

I3C_CONTROLLER_DEVICE_ADDR_REG_OFFSET

#define I3C_CONTROLLER_DEVICE_ADDR_REG_OFFSET   0x188

Definition at line 962 of file i3c_regs.h.

I3C_CONTROLLER_DEVICE_ADDR_REG_RESVAL

#define I3C_CONTROLLER_DEVICE_ADDR_REG_RESVAL   0x0u

Definition at line 963 of file i3c_regs.h.

I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_FIELD

#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_OFFSET })

Definition at line 1305 of file i3c_regs.h.

I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_MASK

#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_MASK   0xffu

Definition at line 1303 of file i3c_regs.h.

I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_OFFSET

#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_OFFSET   0

Definition at line 1304 of file i3c_regs.h.

I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_FIELD

#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_OFFSET })

Definition at line 1309 of file i3c_regs.h.

I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_MASK

#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu

Definition at line 1307 of file i3c_regs.h.

I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_OFFSET

#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8

Definition at line 1308 of file i3c_regs.h.

I3C_CTRL_CFG_EXTCAP_HEADER_REG_OFFSET

#define I3C_CTRL_CFG_EXTCAP_HEADER_REG_OFFSET   0x2b0

Definition at line 1301 of file i3c_regs.h.

I3C_CTRL_CFG_EXTCAP_HEADER_REG_RESVAL

#define I3C_CTRL_CFG_EXTCAP_HEADER_REG_RESVAL   0x202u

Definition at line 1302 of file i3c_regs.h.

I3C_CTRL_ERROR_CE0_FIELD

#define I3C_CTRL_ERROR_CE0_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE0_MASK, .index = I3C_CTRL_ERROR_CE0_OFFSET })

Definition at line 105 of file i3c_regs.h.

I3C_CTRL_ERROR_CE0_MASK

#define I3C_CTRL_ERROR_CE0_MASK   0xfu

Definition at line 103 of file i3c_regs.h.

I3C_CTRL_ERROR_CE0_OFFSET

#define I3C_CTRL_ERROR_CE0_OFFSET   0

Definition at line 104 of file i3c_regs.h.

I3C_CTRL_ERROR_CE1_FIELD

#define I3C_CTRL_ERROR_CE1_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE1_MASK, .index = I3C_CTRL_ERROR_CE1_OFFSET })

Definition at line 109 of file i3c_regs.h.

I3C_CTRL_ERROR_CE1_MASK

#define I3C_CTRL_ERROR_CE1_MASK   0xfu

Definition at line 107 of file i3c_regs.h.

I3C_CTRL_ERROR_CE1_OFFSET

#define I3C_CTRL_ERROR_CE1_OFFSET   4

Definition at line 108 of file i3c_regs.h.

I3C_CTRL_ERROR_CE2_FIELD

#define I3C_CTRL_ERROR_CE2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE2_MASK, .index = I3C_CTRL_ERROR_CE2_OFFSET })

Definition at line 113 of file i3c_regs.h.

I3C_CTRL_ERROR_CE2_MASK

#define I3C_CTRL_ERROR_CE2_MASK   0xfu

Definition at line 111 of file i3c_regs.h.

I3C_CTRL_ERROR_CE2_OFFSET

#define I3C_CTRL_ERROR_CE2_OFFSET   8

Definition at line 112 of file i3c_regs.h.

I3C_CTRL_ERROR_CE3_FIELD

#define I3C_CTRL_ERROR_CE3_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE3_MASK, .index = I3C_CTRL_ERROR_CE3_OFFSET })

Definition at line 117 of file i3c_regs.h.

I3C_CTRL_ERROR_CE3_MASK

#define I3C_CTRL_ERROR_CE3_MASK   0xfu

Definition at line 115 of file i3c_regs.h.

I3C_CTRL_ERROR_CE3_OFFSET

#define I3C_CTRL_ERROR_CE3_OFFSET   12

Definition at line 116 of file i3c_regs.h.

I3C_CTRL_ERROR_REG_OFFSET

#define I3C_CTRL_ERROR_REG_OFFSET   0x18

Definition at line 101 of file i3c_regs.h.

I3C_CTRL_ERROR_REG_RESVAL

#define I3C_CTRL_ERROR_REG_RESVAL   0x0u

Definition at line 102 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_FIELD

#define I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_MASK, .index = I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_OFFSET })

Definition at line 444 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_MASK

#define I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 442 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_OFFSET

#define I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_OFFSET   16

Definition at line 443 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_FIELD

#define I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_MASK, .index = I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_OFFSET })

Definition at line 440 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_MASK

#define I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 438 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_OFFSET

#define I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 439 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_REG_OFFSET

#define I3C_CTRL_RXBUF_CONFIG_REG_OFFSET   0x7c

Definition at line 436 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_REG_RESVAL

#define I3C_CTRL_RXBUF_CONFIG_REG_RESVAL   0x60ff0080u

Definition at line 437 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_FIELD

#define I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_MASK, .index = I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_OFFSET })

Definition at line 448 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_MASK

#define I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_MASK   0x7u

Definition at line 446 of file i3c_regs.h.

I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_OFFSET

#define I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_OFFSET   28

Definition at line 447 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_FULL_BIT

#define I3C_CTRL_RXBUF_STATE_FULL_BIT   31

Definition at line 463 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_PRE_BIT

#define I3C_CTRL_RXBUF_STATE_PRE_BIT   30

Definition at line 462 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_REG_OFFSET

#define I3C_CTRL_RXBUF_STATE_REG_OFFSET   0x80

Definition at line 452 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_REG_RESVAL

#define I3C_CTRL_RXBUF_STATE_REG_RESVAL   0x800080u

Definition at line 453 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_RPTR_FIELD

#define I3C_CTRL_RXBUF_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_STATE_RPTR_MASK, .index = I3C_CTRL_RXBUF_STATE_RPTR_OFFSET })

Definition at line 460 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_RPTR_MASK

#define I3C_CTRL_RXBUF_STATE_RPTR_MASK   0x3ffu

Definition at line 458 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_RPTR_OFFSET

#define I3C_CTRL_RXBUF_STATE_RPTR_OFFSET   16

Definition at line 459 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_WPTR_FIELD

#define I3C_CTRL_RXBUF_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_STATE_WPTR_MASK, .index = I3C_CTRL_RXBUF_STATE_WPTR_OFFSET })

Definition at line 456 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_WPTR_MASK

#define I3C_CTRL_RXBUF_STATE_WPTR_MASK   0x3ffu

Definition at line 454 of file i3c_regs.h.

I3C_CTRL_RXBUF_STATE_WPTR_OFFSET

#define I3C_CTRL_RXBUF_STATE_WPTR_OFFSET   0

Definition at line 455 of file i3c_regs.h.

I3C_CTRL_STATUS_PRESENT_BIT

#define I3C_CTRL_STATUS_PRESENT_BIT   31

Definition at line 98 of file i3c_regs.h.

I3C_CTRL_STATUS_REG_OFFSET

#define I3C_CTRL_STATUS_REG_OFFSET   0x14

Definition at line 96 of file i3c_regs.h.

I3C_CTRL_STATUS_REG_RESVAL

#define I3C_CTRL_STATUS_REG_RESVAL   0x80000000u

Definition at line 97 of file i3c_regs.h.

I3C_CTRL_TIME_FM_REG_OFFSET

#define I3C_CTRL_TIME_FM_REG_OFFSET   0x58

Definition at line 305 of file i3c_regs.h.

I3C_CTRL_TIME_FM_REG_RESVAL

#define I3C_CTRL_TIME_FM_REG_RESVAL   0x3ff03ffu

Definition at line 306 of file i3c_regs.h.

I3C_CTRL_TIME_FM_SCLHI_DIV2_FIELD

#define I3C_CTRL_TIME_FM_SCLHI_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FM_SCLHI_DIV2_MASK, .index = I3C_CTRL_TIME_FM_SCLHI_DIV2_OFFSET })

Definition at line 313 of file i3c_regs.h.

I3C_CTRL_TIME_FM_SCLHI_DIV2_MASK

#define I3C_CTRL_TIME_FM_SCLHI_DIV2_MASK   0x3ffu

Definition at line 311 of file i3c_regs.h.

I3C_CTRL_TIME_FM_SCLHI_DIV2_OFFSET

#define I3C_CTRL_TIME_FM_SCLHI_DIV2_OFFSET   16

Definition at line 312 of file i3c_regs.h.

I3C_CTRL_TIME_FM_SCLLO_DIV2_FIELD

#define I3C_CTRL_TIME_FM_SCLLO_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FM_SCLLO_DIV2_MASK, .index = I3C_CTRL_TIME_FM_SCLLO_DIV2_OFFSET })

Definition at line 309 of file i3c_regs.h.

I3C_CTRL_TIME_FM_SCLLO_DIV2_MASK

#define I3C_CTRL_TIME_FM_SCLLO_DIV2_MASK   0x3ffu

Definition at line 307 of file i3c_regs.h.

I3C_CTRL_TIME_FM_SCLLO_DIV2_OFFSET

#define I3C_CTRL_TIME_FM_SCLLO_DIV2_OFFSET   0

Definition at line 308 of file i3c_regs.h.

I3C_CTRL_TIME_FMP_REG_OFFSET

#define I3C_CTRL_TIME_FMP_REG_OFFSET   0x54

Definition at line 293 of file i3c_regs.h.

I3C_CTRL_TIME_FMP_REG_RESVAL

#define I3C_CTRL_TIME_FMP_REG_RESVAL   0x3ff03ffu

Definition at line 294 of file i3c_regs.h.

I3C_CTRL_TIME_FMP_SCLHI_DIV2_FIELD

#define I3C_CTRL_TIME_FMP_SCLHI_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FMP_SCLHI_DIV2_MASK, .index = I3C_CTRL_TIME_FMP_SCLHI_DIV2_OFFSET })

Definition at line 301 of file i3c_regs.h.

I3C_CTRL_TIME_FMP_SCLHI_DIV2_MASK

#define I3C_CTRL_TIME_FMP_SCLHI_DIV2_MASK   0x3ffu

Definition at line 299 of file i3c_regs.h.

I3C_CTRL_TIME_FMP_SCLHI_DIV2_OFFSET

#define I3C_CTRL_TIME_FMP_SCLHI_DIV2_OFFSET   16

Definition at line 300 of file i3c_regs.h.

I3C_CTRL_TIME_FMP_SCLLO_DIV2_FIELD

#define I3C_CTRL_TIME_FMP_SCLLO_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FMP_SCLLO_DIV2_MASK, .index = I3C_CTRL_TIME_FMP_SCLLO_DIV2_OFFSET })

Definition at line 297 of file i3c_regs.h.

I3C_CTRL_TIME_FMP_SCLLO_DIV2_MASK

#define I3C_CTRL_TIME_FMP_SCLLO_DIV2_MASK   0x3ffu

Definition at line 295 of file i3c_regs.h.

I3C_CTRL_TIME_FMP_SCLLO_DIV2_OFFSET

#define I3C_CTRL_TIME_FMP_SCLLO_DIV2_OFFSET   0

Definition at line 296 of file i3c_regs.h.

I3C_CTRL_TIME_OD_REG_OFFSET

#define I3C_CTRL_TIME_OD_REG_OFFSET   0x38

Definition at line 208 of file i3c_regs.h.

I3C_CTRL_TIME_OD_REG_RESVAL

#define I3C_CTRL_TIME_OD_REG_RESVAL   0x3ff03ffu

Definition at line 209 of file i3c_regs.h.

I3C_CTRL_TIME_OD_SCLHI_DIV2_FIELD

#define I3C_CTRL_TIME_OD_SCLHI_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_OD_SCLHI_DIV2_MASK, .index = I3C_CTRL_TIME_OD_SCLHI_DIV2_OFFSET })

Definition at line 216 of file i3c_regs.h.

I3C_CTRL_TIME_OD_SCLHI_DIV2_MASK

#define I3C_CTRL_TIME_OD_SCLHI_DIV2_MASK   0x3ffu

Definition at line 214 of file i3c_regs.h.

I3C_CTRL_TIME_OD_SCLHI_DIV2_OFFSET

#define I3C_CTRL_TIME_OD_SCLHI_DIV2_OFFSET   16

Definition at line 215 of file i3c_regs.h.

I3C_CTRL_TIME_OD_SCLLO_DIV2_FIELD

#define I3C_CTRL_TIME_OD_SCLLO_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_OD_SCLLO_DIV2_MASK, .index = I3C_CTRL_TIME_OD_SCLLO_DIV2_OFFSET })

Definition at line 212 of file i3c_regs.h.

I3C_CTRL_TIME_OD_SCLLO_DIV2_MASK

#define I3C_CTRL_TIME_OD_SCLLO_DIV2_MASK   0x3ffu

Definition at line 210 of file i3c_regs.h.

I3C_CTRL_TIME_OD_SCLLO_DIV2_OFFSET

#define I3C_CTRL_TIME_OD_SCLLO_DIV2_OFFSET   0

Definition at line 211 of file i3c_regs.h.

I3C_CTRL_TIME_PP_HCEXT_BIT

#define I3C_CTRL_TIME_PP_HCEXT_BIT   15

Definition at line 226 of file i3c_regs.h.

I3C_CTRL_TIME_PP_REG_OFFSET

#define I3C_CTRL_TIME_PP_REG_OFFSET   0x3c

Definition at line 220 of file i3c_regs.h.

I3C_CTRL_TIME_PP_REG_RESVAL

#define I3C_CTRL_TIME_PP_REG_RESVAL   0x3ff83ffu

Definition at line 221 of file i3c_regs.h.

I3C_CTRL_TIME_PP_TCHH_FIELD

#define I3C_CTRL_TIME_PP_TCHH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_PP_TCHH_MASK, .index = I3C_CTRL_TIME_PP_TCHH_OFFSET })

Definition at line 224 of file i3c_regs.h.

I3C_CTRL_TIME_PP_TCHH_MASK

#define I3C_CTRL_TIME_PP_TCHH_MASK   0x3ffu

Definition at line 222 of file i3c_regs.h.

I3C_CTRL_TIME_PP_TCHH_OFFSET

#define I3C_CTRL_TIME_PP_TCHH_OFFSET   0

Definition at line 223 of file i3c_regs.h.

I3C_CTRL_TIME_PP_TCHS_FIELD

#define I3C_CTRL_TIME_PP_TCHS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_PP_TCHS_MASK, .index = I3C_CTRL_TIME_PP_TCHS_OFFSET })

Definition at line 229 of file i3c_regs.h.

I3C_CTRL_TIME_PP_TCHS_MASK

#define I3C_CTRL_TIME_PP_TCHS_MASK   0x3ffu

Definition at line 227 of file i3c_regs.h.

I3C_CTRL_TIME_PP_TCHS_OFFSET

#define I3C_CTRL_TIME_PP_TCHS_OFFSET   16

Definition at line 228 of file i3c_regs.h.

I3C_CTRL_TIME_SDR0_REG_OFFSET

#define I3C_CTRL_TIME_SDR0_REG_OFFSET   0x40

Definition at line 233 of file i3c_regs.h.

I3C_CTRL_TIME_SDR0_REG_RESVAL

#define I3C_CTRL_TIME_SDR0_REG_RESVAL   0x3ff03ffu

Definition at line 234 of file i3c_regs.h.

I3C_CTRL_TIME_SDR0_TCLH_FIELD

#define I3C_CTRL_TIME_SDR0_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR0_TCLH_MASK, .index = I3C_CTRL_TIME_SDR0_TCLH_OFFSET })

Definition at line 237 of file i3c_regs.h.

I3C_CTRL_TIME_SDR0_TCLH_MASK

#define I3C_CTRL_TIME_SDR0_TCLH_MASK   0x3ffu

Definition at line 235 of file i3c_regs.h.

I3C_CTRL_TIME_SDR0_TCLH_OFFSET

#define I3C_CTRL_TIME_SDR0_TCLH_OFFSET   0

Definition at line 236 of file i3c_regs.h.

I3C_CTRL_TIME_SDR0_TCLS_FIELD

#define I3C_CTRL_TIME_SDR0_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR0_TCLS_MASK, .index = I3C_CTRL_TIME_SDR0_TCLS_OFFSET })

Definition at line 241 of file i3c_regs.h.

I3C_CTRL_TIME_SDR0_TCLS_MASK

#define I3C_CTRL_TIME_SDR0_TCLS_MASK   0x3ffu

Definition at line 239 of file i3c_regs.h.

I3C_CTRL_TIME_SDR0_TCLS_OFFSET

#define I3C_CTRL_TIME_SDR0_TCLS_OFFSET   16

Definition at line 240 of file i3c_regs.h.

I3C_CTRL_TIME_SDR1_REG_OFFSET

#define I3C_CTRL_TIME_SDR1_REG_OFFSET   0x44

Definition at line 245 of file i3c_regs.h.

I3C_CTRL_TIME_SDR1_REG_RESVAL

#define I3C_CTRL_TIME_SDR1_REG_RESVAL   0x3ff03ffu

Definition at line 246 of file i3c_regs.h.

I3C_CTRL_TIME_SDR1_TCLH_FIELD

#define I3C_CTRL_TIME_SDR1_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR1_TCLH_MASK, .index = I3C_CTRL_TIME_SDR1_TCLH_OFFSET })

Definition at line 249 of file i3c_regs.h.

I3C_CTRL_TIME_SDR1_TCLH_MASK

#define I3C_CTRL_TIME_SDR1_TCLH_MASK   0x3ffu

Definition at line 247 of file i3c_regs.h.

I3C_CTRL_TIME_SDR1_TCLH_OFFSET

#define I3C_CTRL_TIME_SDR1_TCLH_OFFSET   0

Definition at line 248 of file i3c_regs.h.

I3C_CTRL_TIME_SDR1_TCLS_FIELD

#define I3C_CTRL_TIME_SDR1_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR1_TCLS_MASK, .index = I3C_CTRL_TIME_SDR1_TCLS_OFFSET })

Definition at line 253 of file i3c_regs.h.

I3C_CTRL_TIME_SDR1_TCLS_MASK

#define I3C_CTRL_TIME_SDR1_TCLS_MASK   0x3ffu

Definition at line 251 of file i3c_regs.h.

I3C_CTRL_TIME_SDR1_TCLS_OFFSET

#define I3C_CTRL_TIME_SDR1_TCLS_OFFSET   16

Definition at line 252 of file i3c_regs.h.

I3C_CTRL_TIME_SDR2_REG_OFFSET

#define I3C_CTRL_TIME_SDR2_REG_OFFSET   0x48

Definition at line 257 of file i3c_regs.h.

I3C_CTRL_TIME_SDR2_REG_RESVAL

#define I3C_CTRL_TIME_SDR2_REG_RESVAL   0x3ff03ffu

Definition at line 258 of file i3c_regs.h.

I3C_CTRL_TIME_SDR2_TCLH_FIELD

#define I3C_CTRL_TIME_SDR2_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR2_TCLH_MASK, .index = I3C_CTRL_TIME_SDR2_TCLH_OFFSET })

Definition at line 261 of file i3c_regs.h.

I3C_CTRL_TIME_SDR2_TCLH_MASK

#define I3C_CTRL_TIME_SDR2_TCLH_MASK   0x3ffu

Definition at line 259 of file i3c_regs.h.

I3C_CTRL_TIME_SDR2_TCLH_OFFSET

#define I3C_CTRL_TIME_SDR2_TCLH_OFFSET   0

Definition at line 260 of file i3c_regs.h.

I3C_CTRL_TIME_SDR2_TCLS_FIELD

#define I3C_CTRL_TIME_SDR2_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR2_TCLS_MASK, .index = I3C_CTRL_TIME_SDR2_TCLS_OFFSET })

Definition at line 265 of file i3c_regs.h.

I3C_CTRL_TIME_SDR2_TCLS_MASK

#define I3C_CTRL_TIME_SDR2_TCLS_MASK   0x3ffu

Definition at line 263 of file i3c_regs.h.

I3C_CTRL_TIME_SDR2_TCLS_OFFSET

#define I3C_CTRL_TIME_SDR2_TCLS_OFFSET   16

Definition at line 264 of file i3c_regs.h.

I3C_CTRL_TIME_SDR3_REG_OFFSET

#define I3C_CTRL_TIME_SDR3_REG_OFFSET   0x4c

Definition at line 269 of file i3c_regs.h.

I3C_CTRL_TIME_SDR3_REG_RESVAL

#define I3C_CTRL_TIME_SDR3_REG_RESVAL   0x3ff03ffu

Definition at line 270 of file i3c_regs.h.

I3C_CTRL_TIME_SDR3_TCLH_FIELD

#define I3C_CTRL_TIME_SDR3_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR3_TCLH_MASK, .index = I3C_CTRL_TIME_SDR3_TCLH_OFFSET })

Definition at line 273 of file i3c_regs.h.

I3C_CTRL_TIME_SDR3_TCLH_MASK

#define I3C_CTRL_TIME_SDR3_TCLH_MASK   0x3ffu

Definition at line 271 of file i3c_regs.h.

I3C_CTRL_TIME_SDR3_TCLH_OFFSET

#define I3C_CTRL_TIME_SDR3_TCLH_OFFSET   0

Definition at line 272 of file i3c_regs.h.

I3C_CTRL_TIME_SDR3_TCLS_FIELD

#define I3C_CTRL_TIME_SDR3_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR3_TCLS_MASK, .index = I3C_CTRL_TIME_SDR3_TCLS_OFFSET })

Definition at line 277 of file i3c_regs.h.

I3C_CTRL_TIME_SDR3_TCLS_MASK

#define I3C_CTRL_TIME_SDR3_TCLS_MASK   0x3ffu

Definition at line 275 of file i3c_regs.h.

I3C_CTRL_TIME_SDR3_TCLS_OFFSET

#define I3C_CTRL_TIME_SDR3_TCLS_OFFSET   16

Definition at line 276 of file i3c_regs.h.

I3C_CTRL_TIME_SDR4_REG_OFFSET

#define I3C_CTRL_TIME_SDR4_REG_OFFSET   0x50

Definition at line 281 of file i3c_regs.h.

I3C_CTRL_TIME_SDR4_REG_RESVAL

#define I3C_CTRL_TIME_SDR4_REG_RESVAL   0x3ff03ffu

Definition at line 282 of file i3c_regs.h.

I3C_CTRL_TIME_SDR4_TCLH_FIELD

#define I3C_CTRL_TIME_SDR4_TCLH_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR4_TCLH_MASK, .index = I3C_CTRL_TIME_SDR4_TCLH_OFFSET })

Definition at line 285 of file i3c_regs.h.

I3C_CTRL_TIME_SDR4_TCLH_MASK

#define I3C_CTRL_TIME_SDR4_TCLH_MASK   0x3ffu

Definition at line 283 of file i3c_regs.h.

I3C_CTRL_TIME_SDR4_TCLH_OFFSET

#define I3C_CTRL_TIME_SDR4_TCLH_OFFSET   0

Definition at line 284 of file i3c_regs.h.

I3C_CTRL_TIME_SDR4_TCLS_FIELD

#define I3C_CTRL_TIME_SDR4_TCLS_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR4_TCLS_MASK, .index = I3C_CTRL_TIME_SDR4_TCLS_OFFSET })

Definition at line 289 of file i3c_regs.h.

I3C_CTRL_TIME_SDR4_TCLS_MASK

#define I3C_CTRL_TIME_SDR4_TCLS_MASK   0x3ffu

Definition at line 287 of file i3c_regs.h.

I3C_CTRL_TIME_SDR4_TCLS_OFFSET

#define I3C_CTRL_TIME_SDR4_TCLS_OFFSET   16

Definition at line 288 of file i3c_regs.h.

I3C_CTRL_TIME_SP_REG_OFFSET

#define I3C_CTRL_TIME_SP_REG_OFFSET   0x34

Definition at line 196 of file i3c_regs.h.

I3C_CTRL_TIME_SP_REG_RESVAL

#define I3C_CTRL_TIME_SP_REG_RESVAL   0x3ff03ffu

Definition at line 197 of file i3c_regs.h.

I3C_CTRL_TIME_SP_TCAS_DIV2_FIELD

#define I3C_CTRL_TIME_SP_TCAS_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SP_TCAS_DIV2_MASK, .index = I3C_CTRL_TIME_SP_TCAS_DIV2_OFFSET })

Definition at line 204 of file i3c_regs.h.

I3C_CTRL_TIME_SP_TCAS_DIV2_MASK

#define I3C_CTRL_TIME_SP_TCAS_DIV2_MASK   0x3ffu

Definition at line 202 of file i3c_regs.h.

I3C_CTRL_TIME_SP_TCAS_DIV2_OFFSET

#define I3C_CTRL_TIME_SP_TCAS_DIV2_OFFSET   16

Definition at line 203 of file i3c_regs.h.

I3C_CTRL_TIME_SP_TCBP_DIV2_FIELD

#define I3C_CTRL_TIME_SP_TCBP_DIV2_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SP_TCBP_DIV2_MASK, .index = I3C_CTRL_TIME_SP_TCBP_DIV2_OFFSET })

Definition at line 200 of file i3c_regs.h.

I3C_CTRL_TIME_SP_TCBP_DIV2_MASK

#define I3C_CTRL_TIME_SP_TCBP_DIV2_MASK   0x3ffu

Definition at line 198 of file i3c_regs.h.

I3C_CTRL_TIME_SP_TCBP_DIV2_OFFSET

#define I3C_CTRL_TIME_SP_TCBP_DIV2_OFFSET   0

Definition at line 199 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_FIELD

#define I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_MASK, .index = I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_OFFSET })

Definition at line 414 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_MASK

#define I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 412 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_OFFSET

#define I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_OFFSET   16

Definition at line 413 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_FIELD

#define I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_MASK, .index = I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_OFFSET })

Definition at line 410 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_MASK

#define I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 408 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_OFFSET

#define I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 409 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_REG_OFFSET

#define I3C_CTRL_TXBUF_CONFIG_REG_OFFSET   0x74

Definition at line 406 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_REG_RESVAL

#define I3C_CTRL_TXBUF_CONFIG_REG_RESVAL   0x607f0000u

Definition at line 407 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_FIELD

#define I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_MASK, .index = I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_OFFSET })

Definition at line 418 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_MASK

#define I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_MASK   0x7u

Definition at line 416 of file i3c_regs.h.

I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_OFFSET

#define I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_OFFSET   28

Definition at line 417 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_FULL_BIT

#define I3C_CTRL_TXBUF_STATE_FULL_BIT   31

Definition at line 433 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_PRE_BIT

#define I3C_CTRL_TXBUF_STATE_PRE_BIT   30

Definition at line 432 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_REG_OFFSET

#define I3C_CTRL_TXBUF_STATE_REG_OFFSET   0x78

Definition at line 422 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_REG_RESVAL

#define I3C_CTRL_TXBUF_STATE_REG_RESVAL   0x0u

Definition at line 423 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_RPTR_FIELD

#define I3C_CTRL_TXBUF_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_STATE_RPTR_MASK, .index = I3C_CTRL_TXBUF_STATE_RPTR_OFFSET })

Definition at line 430 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_RPTR_MASK

#define I3C_CTRL_TXBUF_STATE_RPTR_MASK   0x3ffu

Definition at line 428 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_RPTR_OFFSET

#define I3C_CTRL_TXBUF_STATE_RPTR_OFFSET   16

Definition at line 429 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_WPTR_FIELD

#define I3C_CTRL_TXBUF_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_STATE_WPTR_MASK, .index = I3C_CTRL_TXBUF_STATE_WPTR_OFFSET })

Definition at line 426 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_WPTR_MASK

#define I3C_CTRL_TXBUF_STATE_WPTR_MASK   0x3ffu

Definition at line 424 of file i3c_regs.h.

I3C_CTRL_TXBUF_STATE_WPTR_OFFSET

#define I3C_CTRL_TXBUF_STATE_WPTR_OFFSET   0

Definition at line 425 of file i3c_regs.h.

I3C_DAT_REG_OFFSET

#define I3C_DAT_REG_OFFSET   0xa00

Definition at line 2603 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_FIELD

#define I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_MASK, .index = I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_OFFSET })

Definition at line 1054 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_MASK

#define I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_MASK   0xfu

Definition at line 1052 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_OFFSET

#define I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_OFFSET   28

Definition at line 1053 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_REG_OFFSET

#define I3C_DAT_SECTION_OFFSET_REG_OFFSET   0x1b0

Definition at line 1042 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_REG_RESVAL

#define I3C_DAT_SECTION_OFFSET_REG_RESVAL   0x20880u

Definition at line 1043 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_FIELD

#define I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_MASK, .index = I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_OFFSET })

Definition at line 1046 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_MASK

#define I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_MASK   0xfffu

Definition at line 1044 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_OFFSET

#define I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_OFFSET   0

Definition at line 1045 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_TABLE_SIZE_FIELD

#define I3C_DAT_SECTION_OFFSET_TABLE_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DAT_SECTION_OFFSET_TABLE_SIZE_MASK, .index = I3C_DAT_SECTION_OFFSET_TABLE_SIZE_OFFSET })

Definition at line 1050 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_TABLE_SIZE_MASK

#define I3C_DAT_SECTION_OFFSET_TABLE_SIZE_MASK   0x7fu

Definition at line 1048 of file i3c_regs.h.

I3C_DAT_SECTION_OFFSET_TABLE_SIZE_OFFSET

#define I3C_DAT_SECTION_OFFSET_TABLE_SIZE_OFFSET   12

Definition at line 1049 of file i3c_regs.h.

I3C_DAT_SIZE_BYTES

#define I3C_DAT_SIZE_BYTES   256

Definition at line 2605 of file i3c_regs.h.

I3C_DAT_SIZE_WORDS

#define I3C_DAT_SIZE_WORDS   64

Definition at line 2604 of file i3c_regs.h.

I3C_DATA_BUFFER_STATUS_LEVEL_REG_OFFSET

#define I3C_DATA_BUFFER_STATUS_LEVEL_REG_OFFSET   0x2c8

Definition at line 1385 of file i3c_regs.h.

I3C_DATA_BUFFER_STATUS_LEVEL_REG_RESVAL

#define I3C_DATA_BUFFER_STATUS_LEVEL_REG_RESVAL   0x80u

Definition at line 1386 of file i3c_regs.h.

I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_FIELD

#define I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_MASK, .index = I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_OFFSET })

Definition at line 1393 of file i3c_regs.h.

I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_MASK

#define I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_MASK   0xffu

Definition at line 1391 of file i3c_regs.h.

I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_OFFSET

#define I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_OFFSET   8

Definition at line 1392 of file i3c_regs.h.

I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_FIELD

#define I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_MASK, .index = I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_OFFSET })

Definition at line 1389 of file i3c_regs.h.

I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_MASK

#define I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_MASK   0xffu

Definition at line 1387 of file i3c_regs.h.

I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_OFFSET

#define I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_OFFSET   0

Definition at line 1388 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_REG_OFFSET

#define I3C_DATA_BUFFER_THLD_CTRL_REG_OFFSET   0x214

Definition at line 1176 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_REG_RESVAL

#define I3C_DATA_BUFFER_THLD_CTRL_REG_RESVAL   0x1010101u

Definition at line 1177 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_FIELD

#define I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_OFFSET })

Definition at line 1184 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_MASK

#define I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_MASK   0x7u

Definition at line 1182 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_OFFSET

#define I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_OFFSET   8

Definition at line 1183 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_FIELD

#define I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_OFFSET })

Definition at line 1192 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_MASK

#define I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_MASK   0x7u

Definition at line 1190 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_OFFSET

#define I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_OFFSET   24

Definition at line 1191 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_FIELD

#define I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_OFFSET })

Definition at line 1180 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_MASK

#define I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_MASK   0x7u

Definition at line 1178 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_OFFSET

#define I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_OFFSET   0

Definition at line 1179 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_FIELD

#define I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_OFFSET })

Definition at line 1188 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_MASK

#define I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_MASK   0x7u

Definition at line 1186 of file i3c_regs.h.

I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_OFFSET

#define I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_OFFSET   16

Definition at line 1187 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_ASX_TIMING_FIELD

#define I3C_DBR_ENGAGE_DBR_ASX_TIMING_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_ASX_TIMING_MASK, .index = I3C_DBR_ENGAGE_DBR_ASX_TIMING_OFFSET })

Definition at line 1345 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_ASX_TIMING_MASK

#define I3C_DBR_ENGAGE_DBR_ASX_TIMING_MASK   0x3u

Definition at line 1343 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_ASX_TIMING_OFFSET

#define I3C_DBR_ENGAGE_DBR_ASX_TIMING_OFFSET   8

Definition at line 1344 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_FIELD

#define I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_MASK, .index = I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_OFFSET })

Definition at line 1349 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_MASK

#define I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_MASK   0x7fu

Definition at line 1347 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_OFFSET

#define I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_OFFSET   16

Definition at line 1348 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_MODE_FIELD

#define I3C_DBR_ENGAGE_DBR_MODE_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_MODE_MASK, .index = I3C_DBR_ENGAGE_DBR_MODE_OFFSET })

Definition at line 1341 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_MODE_MASK

#define I3C_DBR_ENGAGE_DBR_MODE_MASK   0x7u

Definition at line 1339 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_MODE_OFFSET

#define I3C_DBR_ENGAGE_DBR_MODE_OFFSET   4

Definition at line 1340 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_VERIF_KEY_FIELD

#define I3C_DBR_ENGAGE_DBR_VERIF_KEY_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_VERIF_KEY_MASK, .index = I3C_DBR_ENGAGE_DBR_VERIF_KEY_OFFSET })

Definition at line 1337 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_VERIF_KEY_MASK

#define I3C_DBR_ENGAGE_DBR_VERIF_KEY_MASK   0xfu

Definition at line 1335 of file i3c_regs.h.

I3C_DBR_ENGAGE_DBR_VERIF_KEY_OFFSET

#define I3C_DBR_ENGAGE_DBR_VERIF_KEY_OFFSET   0

Definition at line 1336 of file i3c_regs.h.

I3C_DBR_ENGAGE_REG_OFFSET

#define I3C_DBR_ENGAGE_REG_OFFSET   0x2bc

Definition at line 1333 of file i3c_regs.h.

I3C_DBR_ENGAGE_REG_RESVAL

#define I3C_DBR_ENGAGE_REG_RESVAL   0x0u

Definition at line 1334 of file i3c_regs.h.

I3C_DBR_EXTCAP_HEADER_CAP_ID_FIELD

#define I3C_DBR_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_DBR_EXTCAP_HEADER_CAP_ID_OFFSET })

Definition at line 1325 of file i3c_regs.h.

I3C_DBR_EXTCAP_HEADER_CAP_ID_MASK

#define I3C_DBR_EXTCAP_HEADER_CAP_ID_MASK   0xffu

Definition at line 1323 of file i3c_regs.h.

I3C_DBR_EXTCAP_HEADER_CAP_ID_OFFSET

#define I3C_DBR_EXTCAP_HEADER_CAP_ID_OFFSET   0

Definition at line 1324 of file i3c_regs.h.

I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_FIELD

#define I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_OFFSET })

Definition at line 1329 of file i3c_regs.h.

I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_MASK

#define I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu

Definition at line 1327 of file i3c_regs.h.

I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_OFFSET

#define I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8

Definition at line 1328 of file i3c_regs.h.

I3C_DBR_EXTCAP_HEADER_REG_OFFSET

#define I3C_DBR_EXTCAP_HEADER_REG_OFFSET   0x2b8

Definition at line 1321 of file i3c_regs.h.

I3C_DBR_EXTCAP_HEADER_REG_RESVAL

#define I3C_DBR_EXTCAP_HEADER_REG_RESVAL   0x20bu

Definition at line 1322 of file i3c_regs.h.

I3C_DCT_REG_OFFSET

#define I3C_DCT_REG_OFFSET   0xc00

Definition at line 2607 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_FIELD

#define I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_MASK, .index = I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_OFFSET })

Definition at line 1074 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_MASK

#define I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_MASK   0xfu

Definition at line 1072 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_OFFSET

#define I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_OFFSET   28

Definition at line 1073 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_REG_OFFSET

#define I3C_DCT_SECTION_OFFSET_REG_OFFSET   0x1b4

Definition at line 1058 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_REG_RESVAL

#define I3C_DCT_SECTION_OFFSET_REG_RESVAL   0x20a80u

Definition at line 1059 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_TABLE_INDEX_FIELD

#define I3C_DCT_SECTION_OFFSET_TABLE_INDEX_FIELD    ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_TABLE_INDEX_MASK, .index = I3C_DCT_SECTION_OFFSET_TABLE_INDEX_OFFSET })

Definition at line 1070 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_TABLE_INDEX_MASK

#define I3C_DCT_SECTION_OFFSET_TABLE_INDEX_MASK   0x1fu

Definition at line 1068 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_TABLE_INDEX_OFFSET

#define I3C_DCT_SECTION_OFFSET_TABLE_INDEX_OFFSET   19

Definition at line 1069 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_FIELD

#define I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_MASK, .index = I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_OFFSET })

Definition at line 1062 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_MASK

#define I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_MASK   0xfffu

Definition at line 1060 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_OFFSET

#define I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_OFFSET   0

Definition at line 1061 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_TABLE_SIZE_FIELD

#define I3C_DCT_SECTION_OFFSET_TABLE_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_TABLE_SIZE_MASK, .index = I3C_DCT_SECTION_OFFSET_TABLE_SIZE_OFFSET })

Definition at line 1066 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_TABLE_SIZE_MASK

#define I3C_DCT_SECTION_OFFSET_TABLE_SIZE_MASK   0x7fu

Definition at line 1064 of file i3c_regs.h.

I3C_DCT_SECTION_OFFSET_TABLE_SIZE_OFFSET

#define I3C_DCT_SECTION_OFFSET_TABLE_SIZE_OFFSET   12

Definition at line 1065 of file i3c_regs.h.

I3C_DCT_SIZE_BYTES

#define I3C_DCT_SIZE_BYTES   512

Definition at line 2609 of file i3c_regs.h.

I3C_DCT_SIZE_WORDS

#define I3C_DCT_SIZE_WORDS   128

Definition at line 2608 of file i3c_regs.h.

I3C_DEBUG_EXTCAP_HEADER_CAP_ID_FIELD

#define I3C_DEBUG_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_DEBUG_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_DEBUG_EXTCAP_HEADER_CAP_ID_OFFSET })

Definition at line 1357 of file i3c_regs.h.

I3C_DEBUG_EXTCAP_HEADER_CAP_ID_MASK

#define I3C_DEBUG_EXTCAP_HEADER_CAP_ID_MASK   0xffu

Definition at line 1355 of file i3c_regs.h.

I3C_DEBUG_EXTCAP_HEADER_CAP_ID_OFFSET

#define I3C_DEBUG_EXTCAP_HEADER_CAP_ID_OFFSET   0

Definition at line 1356 of file i3c_regs.h.

I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_FIELD

#define I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_OFFSET })

Definition at line 1361 of file i3c_regs.h.

I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_MASK

#define I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu

Definition at line 1359 of file i3c_regs.h.

I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_OFFSET

#define I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8

Definition at line 1360 of file i3c_regs.h.

I3C_DEBUG_EXTCAP_HEADER_REG_OFFSET

#define I3C_DEBUG_EXTCAP_HEADER_REG_OFFSET   0x2c0

Definition at line 1353 of file i3c_regs.h.

I3C_DEBUG_EXTCAP_HEADER_REG_RESVAL

#define I3C_DEBUG_EXTCAP_HEADER_REG_RESVAL   0x60cu

Definition at line 1354 of file i3c_regs.h.

I3C_DEV_CTX_BASE_HI_REG_OFFSET

#define I3C_DEV_CTX_BASE_HI_REG_OFFSET   0x1e4

Definition at line 1139 of file i3c_regs.h.

I3C_DEV_CTX_BASE_HI_REG_RESVAL

#define I3C_DEV_CTX_BASE_HI_REG_RESVAL   0x0u

Definition at line 1140 of file i3c_regs.h.

I3C_DEV_CTX_BASE_LO_REG_OFFSET

#define I3C_DEV_CTX_BASE_LO_REG_OFFSET   0x1e0

Definition at line 1135 of file i3c_regs.h.

I3C_DEV_CTX_BASE_LO_REG_RESVAL

#define I3C_DEV_CTX_BASE_LO_REG_RESVAL   0x0u

Definition at line 1136 of file i3c_regs.h.

I3C_DEV_CTX_SG_BLP_BIT

#define I3C_DEV_CTX_SG_BLP_BIT   31

Definition at line 1149 of file i3c_regs.h.

I3C_DEV_CTX_SG_LIST_SIZE_FIELD

#define I3C_DEV_CTX_SG_LIST_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_DEV_CTX_SG_LIST_SIZE_MASK, .index = I3C_DEV_CTX_SG_LIST_SIZE_OFFSET })

Definition at line 1147 of file i3c_regs.h.

I3C_DEV_CTX_SG_LIST_SIZE_MASK

#define I3C_DEV_CTX_SG_LIST_SIZE_MASK   0xffffu

Definition at line 1145 of file i3c_regs.h.

I3C_DEV_CTX_SG_LIST_SIZE_OFFSET

#define I3C_DEV_CTX_SG_LIST_SIZE_OFFSET   0

Definition at line 1146 of file i3c_regs.h.

I3C_DEV_CTX_SG_REG_OFFSET

#define I3C_DEV_CTX_SG_REG_OFFSET   0x1e8

Definition at line 1143 of file i3c_regs.h.

I3C_DEV_CTX_SG_REG_RESVAL

#define I3C_DEV_CTX_SG_REG_RESVAL   0x0u

Definition at line 1144 of file i3c_regs.h.

I3C_EXT_CAPS_SECTION_OFFSET_REG_OFFSET

#define I3C_EXT_CAPS_SECTION_OFFSET_REG_OFFSET   0x1c0

Definition at line 1094 of file i3c_regs.h.

I3C_EXT_CAPS_SECTION_OFFSET_REG_RESVAL

#define I3C_EXT_CAPS_SECTION_OFFSET_REG_RESVAL   0x120u

Definition at line 1095 of file i3c_regs.h.

I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_FIELD

#define I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_MASK, .index = I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_OFFSET })

Definition at line 1098 of file i3c_regs.h.

I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_MASK

#define I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_MASK   0xffffu

Definition at line 1096 of file i3c_regs.h.

I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_OFFSET

#define I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_OFFSET   0

Definition at line 1097 of file i3c_regs.h.

I3C_HC_CAPABILITIES_AUTO_COMMAND_BIT

#define I3C_HC_CAPABILITIES_AUTO_COMMAND_BIT   3

Definition at line 974 of file i3c_regs.h.

I3C_HC_CAPABILITIES_CMD_CCC_DEFBYTE_BIT

#define I3C_HC_CAPABILITIES_CMD_CCC_DEFBYTE_BIT   10

Definition at line 978 of file i3c_regs.h.

I3C_HC_CAPABILITIES_CMD_SIZE_FIELD

#define I3C_HC_CAPABILITIES_CMD_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_HC_CAPABILITIES_CMD_SIZE_MASK, .index = I3C_HC_CAPABILITIES_CMD_SIZE_OFFSET })

Definition at line 984 of file i3c_regs.h.

I3C_HC_CAPABILITIES_CMD_SIZE_MASK

#define I3C_HC_CAPABILITIES_CMD_SIZE_MASK   0x3u

Definition at line 982 of file i3c_regs.h.

I3C_HC_CAPABILITIES_CMD_SIZE_OFFSET

#define I3C_HC_CAPABILITIES_CMD_SIZE_OFFSET   20

Definition at line 983 of file i3c_regs.h.

I3C_HC_CAPABILITIES_COMBO_COMMAND_BIT

#define I3C_HC_CAPABILITIES_COMBO_COMMAND_BIT   2

Definition at line 973 of file i3c_regs.h.

I3C_HC_CAPABILITIES_HDR_DDR_EN_BIT

#define I3C_HC_CAPABILITIES_HDR_DDR_EN_BIT   6

Definition at line 976 of file i3c_regs.h.

I3C_HC_CAPABILITIES_HDR_TS_EN_BIT

#define I3C_HC_CAPABILITIES_HDR_TS_EN_BIT   7

Definition at line 977 of file i3c_regs.h.

I3C_HC_CAPABILITIES_IBI_CREDIT_COUNT_EN_BIT

#define I3C_HC_CAPABILITIES_IBI_CREDIT_COUNT_EN_BIT   12

Definition at line 980 of file i3c_regs.h.

I3C_HC_CAPABILITIES_IBI_DATA_ABORT_EN_BIT

#define I3C_HC_CAPABILITIES_IBI_DATA_ABORT_EN_BIT   11

Definition at line 979 of file i3c_regs.h.

I3C_HC_CAPABILITIES_REG_OFFSET

#define I3C_HC_CAPABILITIES_REG_OFFSET   0x18c

Definition at line 971 of file i3c_regs.h.

I3C_HC_CAPABILITIES_REG_RESVAL

#define I3C_HC_CAPABILITIES_REG_RESVAL   0x448u

Definition at line 972 of file i3c_regs.h.

I3C_HC_CAPABILITIES_SCHEDULED_COMMANDS_EN_BIT

#define I3C_HC_CAPABILITIES_SCHEDULED_COMMANDS_EN_BIT   13

Definition at line 981 of file i3c_regs.h.

I3C_HC_CAPABILITIES_SG_CAPABILITY_CR_EN_BIT

#define I3C_HC_CAPABILITIES_SG_CAPABILITY_CR_EN_BIT   28

Definition at line 986 of file i3c_regs.h.

I3C_HC_CAPABILITIES_SG_CAPABILITY_DC_EN_BIT

#define I3C_HC_CAPABILITIES_SG_CAPABILITY_DC_EN_BIT   30

Definition at line 988 of file i3c_regs.h.

I3C_HC_CAPABILITIES_SG_CAPABILITY_IBI_EN_BIT

#define I3C_HC_CAPABILITIES_SG_CAPABILITY_IBI_EN_BIT   29

Definition at line 987 of file i3c_regs.h.

I3C_HC_CAPABILITIES_STANDBY_CR_CAP_BIT

#define I3C_HC_CAPABILITIES_STANDBY_CR_CAP_BIT   5

Definition at line 975 of file i3c_regs.h.

I3C_HC_CONTROL_ABORT_BIT

#define I3C_HC_CONTROL_ABORT_BIT   29

Definition at line 957 of file i3c_regs.h.

I3C_HC_CONTROL_AUTOCMD_DATA_RPT_BIT

#define I3C_HC_CONTROL_AUTOCMD_DATA_RPT_BIT   3

Definition at line 951 of file i3c_regs.h.

I3C_HC_CONTROL_BUS_ENABLE_BIT

#define I3C_HC_CONTROL_BUS_ENABLE_BIT   31

Definition at line 959 of file i3c_regs.h.

I3C_HC_CONTROL_DATA_BYTE_ORDER_MODE_BIT

#define I3C_HC_CONTROL_DATA_BYTE_ORDER_MODE_BIT   4

Definition at line 952 of file i3c_regs.h.

I3C_HC_CONTROL_HALT_ON_CMD_SEQ_TIMEOUT_BIT

#define I3C_HC_CONTROL_HALT_ON_CMD_SEQ_TIMEOUT_BIT   12

Definition at line 956 of file i3c_regs.h.

I3C_HC_CONTROL_HOT_JOIN_CTRL_BIT

#define I3C_HC_CONTROL_HOT_JOIN_CTRL_BIT   8

Definition at line 955 of file i3c_regs.h.

I3C_HC_CONTROL_I2C_DEV_PRESENT_BIT

#define I3C_HC_CONTROL_I2C_DEV_PRESENT_BIT   7

Definition at line 954 of file i3c_regs.h.

I3C_HC_CONTROL_IBA_INCLUDE_BIT

#define I3C_HC_CONTROL_IBA_INCLUDE_BIT   0

Definition at line 950 of file i3c_regs.h.

I3C_HC_CONTROL_MODE_SELECTOR_BIT

#define I3C_HC_CONTROL_MODE_SELECTOR_BIT   6

Definition at line 953 of file i3c_regs.h.

I3C_HC_CONTROL_REG_OFFSET

#define I3C_HC_CONTROL_REG_OFFSET   0x184

Definition at line 948 of file i3c_regs.h.

I3C_HC_CONTROL_REG_RESVAL

#define I3C_HC_CONTROL_REG_RESVAL   0x48u

Definition at line 949 of file i3c_regs.h.

I3C_HC_CONTROL_RESUME_BIT

#define I3C_HC_CONTROL_RESUME_BIT   30

Definition at line 958 of file i3c_regs.h.

I3C_HCI_PORTS_REG_OFFSET

#define I3C_HCI_PORTS_REG_OFFSET   0x200

Definition at line 1152 of file i3c_regs.h.

I3C_HCI_PORTS_SIZE_BYTES

#define I3C_HCI_PORTS_SIZE_BYTES   16

Definition at line 1154 of file i3c_regs.h.

I3C_HCI_PORTS_SIZE_WORDS

#define I3C_HCI_PORTS_SIZE_WORDS   4

Definition at line 1153 of file i3c_regs.h.

I3C_HCI_VERSION_REG_OFFSET

#define I3C_HCI_VERSION_REG_OFFSET   0x180

Definition at line 944 of file i3c_regs.h.

I3C_HCI_VERSION_REG_RESVAL

#define I3C_HCI_VERSION_REG_RESVAL   0x120u

Definition at line 945 of file i3c_regs.h.

I3C_IBI_CONFIG_MAX_ADDR_FIELD

#define I3C_IBI_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_CONFIG_MAX_ADDR_MASK, .index = I3C_IBI_CONFIG_MAX_ADDR_OFFSET })

Definition at line 534 of file i3c_regs.h.

I3C_IBI_CONFIG_MAX_ADDR_MASK

#define I3C_IBI_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 532 of file i3c_regs.h.

I3C_IBI_CONFIG_MAX_ADDR_OFFSET

#define I3C_IBI_CONFIG_MAX_ADDR_OFFSET   12

Definition at line 533 of file i3c_regs.h.

I3C_IBI_CONFIG_MIN_ADDR_FIELD

#define I3C_IBI_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_CONFIG_MIN_ADDR_MASK, .index = I3C_IBI_CONFIG_MIN_ADDR_OFFSET })

Definition at line 530 of file i3c_regs.h.

I3C_IBI_CONFIG_MIN_ADDR_MASK

#define I3C_IBI_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 528 of file i3c_regs.h.

I3C_IBI_CONFIG_MIN_ADDR_OFFSET

#define I3C_IBI_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 529 of file i3c_regs.h.

I3C_IBI_CONFIG_REG_OFFSET

#define I3C_IBI_CONFIG_REG_OFFSET   0x94

Definition at line 526 of file i3c_regs.h.

I3C_IBI_CONFIG_REG_RESVAL

#define I3C_IBI_CONFIG_REG_RESVAL   0x141af130u

Definition at line 527 of file i3c_regs.h.

I3C_IBI_CONFIG_SIZE_VAL_FIELD

#define I3C_IBI_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_CONFIG_SIZE_VAL_MASK, .index = I3C_IBI_CONFIG_SIZE_VAL_OFFSET })

Definition at line 538 of file i3c_regs.h.

I3C_IBI_CONFIG_SIZE_VAL_MASK

#define I3C_IBI_CONFIG_SIZE_VAL_MASK   0xffu

Definition at line 536 of file i3c_regs.h.

I3C_IBI_CONFIG_SIZE_VAL_OFFSET

#define I3C_IBI_CONFIG_SIZE_VAL_OFFSET   24

Definition at line 537 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_FIELD

#define I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_MASK, .index = I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_OFFSET })

Definition at line 1126 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_MASK

#define I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_MASK   0x3u

Definition at line 1124 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_OFFSET

#define I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_OFFSET   16

Definition at line 1125 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_IBI_DATA_ABORT_MON_BIT

#define I3C_IBI_DATA_ABORT_CTRL_IBI_DATA_ABORT_MON_BIT   31

Definition at line 1132 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_FIELD

#define I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_MASK, .index = I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_OFFSET })

Definition at line 1122 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_MASK

#define I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_MASK   0xffu

Definition at line 1120 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_OFFSET

#define I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_OFFSET   8

Definition at line 1121 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_FIELD

#define I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_MASK, .index = I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_OFFSET })

Definition at line 1130 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_MASK

#define I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_MASK   0x7u

Definition at line 1128 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_OFFSET

#define I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_OFFSET   18

Definition at line 1129 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_REG_OFFSET

#define I3C_IBI_DATA_ABORT_CTRL_REG_OFFSET   0x1dc

Definition at line 1118 of file i3c_regs.h.

I3C_IBI_DATA_ABORT_CTRL_REG_RESVAL

#define I3C_IBI_DATA_ABORT_CTRL_REG_RESVAL   0x0u

Definition at line 1119 of file i3c_regs.h.

I3C_IBI_NOTIFY_CTRL_NOTIFY_CRR_REJECTED_BIT

#define I3C_IBI_NOTIFY_CTRL_NOTIFY_CRR_REJECTED_BIT   1

Definition at line 1114 of file i3c_regs.h.

I3C_IBI_NOTIFY_CTRL_NOTIFY_HJ_REJECTED_BIT

#define I3C_IBI_NOTIFY_CTRL_NOTIFY_HJ_REJECTED_BIT   0

Definition at line 1113 of file i3c_regs.h.

I3C_IBI_NOTIFY_CTRL_NOTIFY_IBI_REJECTED_BIT

#define I3C_IBI_NOTIFY_CTRL_NOTIFY_IBI_REJECTED_BIT   3

Definition at line 1115 of file i3c_regs.h.

I3C_IBI_NOTIFY_CTRL_REG_OFFSET

#define I3C_IBI_NOTIFY_CTRL_REG_OFFSET   0x1d8

Definition at line 1111 of file i3c_regs.h.

I3C_IBI_NOTIFY_CTRL_REG_RESVAL

#define I3C_IBI_NOTIFY_CTRL_REG_RESVAL   0x0u

Definition at line 1112 of file i3c_regs.h.

I3C_IBI_STAT_CONFIG_MAX_ADDR_FIELD

#define I3C_IBI_STAT_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STAT_CONFIG_MAX_ADDR_MASK, .index = I3C_IBI_STAT_CONFIG_MAX_ADDR_OFFSET })

Definition at line 564 of file i3c_regs.h.

I3C_IBI_STAT_CONFIG_MAX_ADDR_MASK

#define I3C_IBI_STAT_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 562 of file i3c_regs.h.

I3C_IBI_STAT_CONFIG_MAX_ADDR_OFFSET

#define I3C_IBI_STAT_CONFIG_MAX_ADDR_OFFSET   12

Definition at line 563 of file i3c_regs.h.

I3C_IBI_STAT_CONFIG_MIN_ADDR_FIELD

#define I3C_IBI_STAT_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STAT_CONFIG_MIN_ADDR_MASK, .index = I3C_IBI_STAT_CONFIG_MIN_ADDR_OFFSET })

Definition at line 560 of file i3c_regs.h.

I3C_IBI_STAT_CONFIG_MIN_ADDR_MASK

#define I3C_IBI_STAT_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 558 of file i3c_regs.h.

I3C_IBI_STAT_CONFIG_MIN_ADDR_OFFSET

#define I3C_IBI_STAT_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 559 of file i3c_regs.h.

I3C_IBI_STAT_CONFIG_REG_OFFSET

#define I3C_IBI_STAT_CONFIG_REG_OFFSET   0x9c

Definition at line 556 of file i3c_regs.h.

I3C_IBI_STAT_CONFIG_REG_RESVAL

#define I3C_IBI_STAT_CONFIG_REG_RESVAL   0x1cf1b0u

Definition at line 557 of file i3c_regs.h.

I3C_IBI_STAT_STATE_FULL_BIT

#define I3C_IBI_STAT_STATE_FULL_BIT   31

Definition at line 579 of file i3c_regs.h.

I3C_IBI_STAT_STATE_PRE_BIT

#define I3C_IBI_STAT_STATE_PRE_BIT   30

Definition at line 578 of file i3c_regs.h.

I3C_IBI_STAT_STATE_REG_OFFSET

#define I3C_IBI_STAT_STATE_REG_OFFSET   0xa0

Definition at line 568 of file i3c_regs.h.

I3C_IBI_STAT_STATE_REG_RESVAL

#define I3C_IBI_STAT_STATE_REG_RESVAL   0x1b001b0u

Definition at line 569 of file i3c_regs.h.

I3C_IBI_STAT_STATE_RPTR_FIELD

#define I3C_IBI_STAT_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STAT_STATE_RPTR_MASK, .index = I3C_IBI_STAT_STATE_RPTR_OFFSET })

Definition at line 576 of file i3c_regs.h.

I3C_IBI_STAT_STATE_RPTR_MASK

#define I3C_IBI_STAT_STATE_RPTR_MASK   0x3ffu

Definition at line 574 of file i3c_regs.h.

I3C_IBI_STAT_STATE_RPTR_OFFSET

#define I3C_IBI_STAT_STATE_RPTR_OFFSET   16

Definition at line 575 of file i3c_regs.h.

I3C_IBI_STAT_STATE_WPTR_FIELD

#define I3C_IBI_STAT_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STAT_STATE_WPTR_MASK, .index = I3C_IBI_STAT_STATE_WPTR_OFFSET })

Definition at line 572 of file i3c_regs.h.

I3C_IBI_STAT_STATE_WPTR_MASK

#define I3C_IBI_STAT_STATE_WPTR_MASK   0x3ffu

Definition at line 570 of file i3c_regs.h.

I3C_IBI_STAT_STATE_WPTR_OFFSET

#define I3C_IBI_STAT_STATE_WPTR_OFFSET   0

Definition at line 571 of file i3c_regs.h.

I3C_IBI_STATE_FULL_BIT

#define I3C_IBI_STATE_FULL_BIT   31

Definition at line 553 of file i3c_regs.h.

I3C_IBI_STATE_PRE_BIT

#define I3C_IBI_STATE_PRE_BIT   30

Definition at line 552 of file i3c_regs.h.

I3C_IBI_STATE_REG_OFFSET

#define I3C_IBI_STATE_REG_OFFSET   0x98

Definition at line 542 of file i3c_regs.h.

I3C_IBI_STATE_REG_RESVAL

#define I3C_IBI_STATE_REG_RESVAL   0x1300130u

Definition at line 543 of file i3c_regs.h.

I3C_IBI_STATE_RPTR_FIELD

#define I3C_IBI_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STATE_RPTR_MASK, .index = I3C_IBI_STATE_RPTR_OFFSET })

Definition at line 550 of file i3c_regs.h.

I3C_IBI_STATE_RPTR_MASK

#define I3C_IBI_STATE_RPTR_MASK   0x3ffu

Definition at line 548 of file i3c_regs.h.

I3C_IBI_STATE_RPTR_OFFSET

#define I3C_IBI_STATE_RPTR_OFFSET   16

Definition at line 549 of file i3c_regs.h.

I3C_IBI_STATE_WPTR_FIELD

#define I3C_IBI_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_IBI_STATE_WPTR_MASK, .index = I3C_IBI_STATE_WPTR_OFFSET })

Definition at line 546 of file i3c_regs.h.

I3C_IBI_STATE_WPTR_MASK

#define I3C_IBI_STATE_WPTR_MASK   0x3ffu

Definition at line 544 of file i3c_regs.h.

I3C_IBI_STATE_WPTR_OFFSET

#define I3C_IBI_STATE_WPTR_OFFSET   0

Definition at line 545 of file i3c_regs.h.

I3C_ID_EXTCAP_HEADER_CAP_ID_FIELD

#define I3C_ID_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_ID_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_ID_EXTCAP_HEADER_CAP_ID_OFFSET })

Definition at line 1281 of file i3c_regs.h.

I3C_ID_EXTCAP_HEADER_CAP_ID_MASK

#define I3C_ID_EXTCAP_HEADER_CAP_ID_MASK   0xffu

Definition at line 1279 of file i3c_regs.h.

I3C_ID_EXTCAP_HEADER_CAP_ID_OFFSET

#define I3C_ID_EXTCAP_HEADER_CAP_ID_OFFSET   0

Definition at line 1280 of file i3c_regs.h.

I3C_ID_EXTCAP_HEADER_CAP_LENGTH_FIELD

#define I3C_ID_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_ID_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_ID_EXTCAP_HEADER_CAP_LENGTH_OFFSET })

Definition at line 1285 of file i3c_regs.h.

I3C_ID_EXTCAP_HEADER_CAP_LENGTH_MASK

#define I3C_ID_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu

Definition at line 1283 of file i3c_regs.h.

I3C_ID_EXTCAP_HEADER_CAP_LENGTH_OFFSET

#define I3C_ID_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8

Definition at line 1284 of file i3c_regs.h.

I3C_ID_EXTCAP_HEADER_REG_OFFSET

#define I3C_ID_EXTCAP_HEADER_REG_OFFSET   0x2a0

Definition at line 1277 of file i3c_regs.h.

I3C_ID_EXTCAP_HEADER_REG_RESVAL

#define I3C_ID_EXTCAP_HEADER_REG_RESVAL   0x401u

Definition at line 1278 of file i3c_regs.h.

I3C_INFO_BUF_DWORD_MAX_FIELD

#define I3C_INFO_BUF_DWORD_MAX_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_BUF_DWORD_MAX_MASK, .index = I3C_INFO_BUF_DWORD_MAX_OFFSET })

Definition at line 92 of file i3c_regs.h.

I3C_INFO_BUF_DWORD_MAX_MASK

#define I3C_INFO_BUF_DWORD_MAX_MASK   0x7ffu

Definition at line 90 of file i3c_regs.h.

I3C_INFO_BUF_DWORD_MAX_OFFSET

#define I3C_INFO_BUF_DWORD_MAX_OFFSET   18

Definition at line 91 of file i3c_regs.h.

I3C_INFO_DAT_ENTRY_MAX_FIELD

#define I3C_INFO_DAT_ENTRY_MAX_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_DAT_ENTRY_MAX_MASK, .index = I3C_INFO_DAT_ENTRY_MAX_OFFSET })

Definition at line 84 of file i3c_regs.h.

I3C_INFO_DAT_ENTRY_MAX_MASK

#define I3C_INFO_DAT_ENTRY_MAX_MASK   0x1fu

Definition at line 82 of file i3c_regs.h.

I3C_INFO_DAT_ENTRY_MAX_OFFSET

#define I3C_INFO_DAT_ENTRY_MAX_OFFSET   8

Definition at line 83 of file i3c_regs.h.

I3C_INFO_DCT_ENTRY_MAX_FIELD

#define I3C_INFO_DCT_ENTRY_MAX_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_DCT_ENTRY_MAX_MASK, .index = I3C_INFO_DCT_ENTRY_MAX_OFFSET })

Definition at line 88 of file i3c_regs.h.

I3C_INFO_DCT_ENTRY_MAX_MASK

#define I3C_INFO_DCT_ENTRY_MAX_MASK   0x1fu

Definition at line 86 of file i3c_regs.h.

I3C_INFO_DCT_ENTRY_MAX_OFFSET

#define I3C_INFO_DCT_ENTRY_MAX_OFFSET   13

Definition at line 87 of file i3c_regs.h.

I3C_INFO_REG_OFFSET

#define I3C_INFO_REG_OFFSET   0x10

Definition at line 72 of file i3c_regs.h.

I3C_INFO_REG_RESVAL

#define I3C_INFO_REG_RESVAL   0xfffff10u

Definition at line 73 of file i3c_regs.h.

I3C_INFO_REVISION_FIELD

#define I3C_INFO_REVISION_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_REVISION_MASK, .index = I3C_INFO_REVISION_OFFSET })

Definition at line 76 of file i3c_regs.h.

I3C_INFO_REVISION_MASK

#define I3C_INFO_REVISION_MASK   0xfu

Definition at line 74 of file i3c_regs.h.

I3C_INFO_REVISION_OFFSET

#define I3C_INFO_REVISION_OFFSET   0

Definition at line 75 of file i3c_regs.h.

I3C_INFO_VERSION_FIELD

#define I3C_INFO_VERSION_FIELD    ((bitfield_field32_t) { .mask = I3C_INFO_VERSION_MASK, .index = I3C_INFO_VERSION_OFFSET })

Definition at line 80 of file i3c_regs.h.

I3C_INFO_VERSION_MASK

#define I3C_INFO_VERSION_MASK   0xfu

Definition at line 78 of file i3c_regs.h.

I3C_INFO_VERSION_OFFSET

#define I3C_INFO_VERSION_OFFSET   4

Definition at line 79 of file i3c_regs.h.

I3C_INT_CTRL_CMDS_EN_ICC_SUPPORT_BIT

#define I3C_INT_CTRL_CMDS_EN_ICC_SUPPORT_BIT   0

Definition at line 1104 of file i3c_regs.h.

I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_FIELD

#define I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_FIELD    ((bitfield_field32_t) { .mask = I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_MASK, .index = I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_OFFSET })

Definition at line 1107 of file i3c_regs.h.

I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_MASK

#define I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_MASK   0x7fffu

Definition at line 1105 of file i3c_regs.h.

I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_OFFSET

#define I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_OFFSET   1

Definition at line 1106 of file i3c_regs.h.

I3C_INT_CTRL_CMDS_EN_REG_OFFSET

#define I3C_INT_CTRL_CMDS_EN_REG_OFFSET   0x1cc

Definition at line 1102 of file i3c_regs.h.

I3C_INT_CTRL_CMDS_EN_REG_RESVAL

#define I3C_INT_CTRL_CMDS_EN_REG_RESVAL   0x20f5u

Definition at line 1103 of file i3c_regs.h.

I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_FIELD

#define I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_MASK, .index = I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_OFFSET })

Definition at line 329 of file i3c_regs.h.

I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_MASK

#define I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_MASK   0xffu

Definition at line 327 of file i3c_regs.h.

I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_OFFSET

#define I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_OFFSET   16

Definition at line 328 of file i3c_regs.h.

I3C_INTERVAL_TIME0_DEAD_BUS_FIELD

#define I3C_INTERVAL_TIME0_DEAD_BUS_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_DEAD_BUS_MASK, .index = I3C_INTERVAL_TIME0_DEAD_BUS_OFFSET })

Definition at line 333 of file i3c_regs.h.

I3C_INTERVAL_TIME0_DEAD_BUS_MASK

#define I3C_INTERVAL_TIME0_DEAD_BUS_MASK   0xffu

Definition at line 331 of file i3c_regs.h.

I3C_INTERVAL_TIME0_DEAD_BUS_OFFSET

#define I3C_INTERVAL_TIME0_DEAD_BUS_OFFSET   24

Definition at line 332 of file i3c_regs.h.

I3C_INTERVAL_TIME0_READ_STALLED_FIELD

#define I3C_INTERVAL_TIME0_READ_STALLED_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_READ_STALLED_MASK, .index = I3C_INTERVAL_TIME0_READ_STALLED_OFFSET })

Definition at line 325 of file i3c_regs.h.

I3C_INTERVAL_TIME0_READ_STALLED_MASK

#define I3C_INTERVAL_TIME0_READ_STALLED_MASK   0xffu

Definition at line 323 of file i3c_regs.h.

I3C_INTERVAL_TIME0_READ_STALLED_OFFSET

#define I3C_INTERVAL_TIME0_READ_STALLED_OFFSET   8

Definition at line 324 of file i3c_regs.h.

I3C_INTERVAL_TIME0_REG_OFFSET

#define I3C_INTERVAL_TIME0_REG_OFFSET   0x5c

Definition at line 317 of file i3c_regs.h.

I3C_INTERVAL_TIME0_REG_RESVAL

#define I3C_INTERVAL_TIME0_REG_RESVAL   0x0u

Definition at line 318 of file i3c_regs.h.

I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_FIELD

#define I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_MASK, .index = I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_OFFSET })

Definition at line 321 of file i3c_regs.h.

I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_MASK

#define I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_MASK   0xffu

Definition at line 319 of file i3c_regs.h.

I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_OFFSET

#define I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_OFFSET   0

Definition at line 320 of file i3c_regs.h.

I3C_INTERVAL_TIME1_COMMAND_RETRY_FIELD

#define I3C_INTERVAL_TIME1_COMMAND_RETRY_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_COMMAND_RETRY_MASK, .index = I3C_INTERVAL_TIME1_COMMAND_RETRY_OFFSET })

Definition at line 341 of file i3c_regs.h.

I3C_INTERVAL_TIME1_COMMAND_RETRY_MASK

#define I3C_INTERVAL_TIME1_COMMAND_RETRY_MASK   0xffu

Definition at line 339 of file i3c_regs.h.

I3C_INTERVAL_TIME1_COMMAND_RETRY_OFFSET

#define I3C_INTERVAL_TIME1_COMMAND_RETRY_OFFSET   0

Definition at line 340 of file i3c_regs.h.

I3C_INTERVAL_TIME1_REG_OFFSET

#define I3C_INTERVAL_TIME1_REG_OFFSET   0x60

Definition at line 337 of file i3c_regs.h.

I3C_INTERVAL_TIME1_REG_RESVAL

#define I3C_INTERVAL_TIME1_REG_RESVAL   0x0u

Definition at line 338 of file i3c_regs.h.

I3C_INTERVAL_TIME1_TARG_BUS_IDLE_FIELD

#define I3C_INTERVAL_TIME1_TARG_BUS_IDLE_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_TARG_BUS_IDLE_MASK, .index = I3C_INTERVAL_TIME1_TARG_BUS_IDLE_OFFSET })

Definition at line 345 of file i3c_regs.h.

I3C_INTERVAL_TIME1_TARG_BUS_IDLE_MASK

#define I3C_INTERVAL_TIME1_TARG_BUS_IDLE_MASK   0xffu

Definition at line 343 of file i3c_regs.h.

I3C_INTERVAL_TIME1_TARG_BUS_IDLE_OFFSET

#define I3C_INTERVAL_TIME1_TARG_BUS_IDLE_OFFSET   8

Definition at line 344 of file i3c_regs.h.

I3C_INTERVAL_TIME1_TARG_TRX_RST_FIELD

#define I3C_INTERVAL_TIME1_TARG_TRX_RST_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_TARG_TRX_RST_MASK, .index = I3C_INTERVAL_TIME1_TARG_TRX_RST_OFFSET })

Definition at line 353 of file i3c_regs.h.

I3C_INTERVAL_TIME1_TARG_TRX_RST_MASK

#define I3C_INTERVAL_TIME1_TARG_TRX_RST_MASK   0xffu

Definition at line 351 of file i3c_regs.h.

I3C_INTERVAL_TIME1_TARG_TRX_RST_OFFSET

#define I3C_INTERVAL_TIME1_TARG_TRX_RST_OFFSET   24

Definition at line 352 of file i3c_regs.h.

I3C_INTERVAL_TIME1_TE0_RECOV_FIELD

#define I3C_INTERVAL_TIME1_TE0_RECOV_FIELD    ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_TE0_RECOV_MASK, .index = I3C_INTERVAL_TIME1_TE0_RECOV_OFFSET })

Definition at line 349 of file i3c_regs.h.

I3C_INTERVAL_TIME1_TE0_RECOV_MASK

#define I3C_INTERVAL_TIME1_TE0_RECOV_MASK   0xffu

Definition at line 347 of file i3c_regs.h.

I3C_INTERVAL_TIME1_TE0_RECOV_OFFSET

#define I3C_INTERVAL_TIME1_TE0_RECOV_OFFSET   16

Definition at line 348 of file i3c_regs.h.

I3C_INTR_COMMON_HCI_BIT

#define I3C_INTR_COMMON_HCI_BIT   0

Definition at line 44 of file i3c_regs.h.

I3C_INTR_COMMON_TARG_BIT

#define I3C_INTR_COMMON_TARG_BIT   1

Definition at line 45 of file i3c_regs.h.

I3C_INTR_ENABLE_HCI_BIT

#define I3C_INTR_ENABLE_HCI_BIT   0

Definition at line 56 of file i3c_regs.h.

I3C_INTR_ENABLE_REG_OFFSET

#define I3C_INTR_ENABLE_REG_OFFSET   0x4

Definition at line 54 of file i3c_regs.h.

I3C_INTR_ENABLE_REG_RESVAL

#define I3C_INTR_ENABLE_REG_RESVAL   0x0u

Definition at line 55 of file i3c_regs.h.

I3C_INTR_ENABLE_TARG_BIT

#define I3C_INTR_ENABLE_TARG_BIT   1

Definition at line 57 of file i3c_regs.h.

I3C_INTR_FORCE_HC_ERR_CMD_SEQ_TIMEOUT_FORCE_BIT

#define I3C_INTR_FORCE_HC_ERR_CMD_SEQ_TIMEOUT_FORCE_BIT   13

Definition at line 1038 of file i3c_regs.h.

I3C_INTR_FORCE_HC_INTERNAL_ERR_FORCE_BIT

#define I3C_INTR_FORCE_HC_INTERNAL_ERR_FORCE_BIT   10

Definition at line 1035 of file i3c_regs.h.

I3C_INTR_FORCE_HC_SEQ_CANCEL_FORCE_BIT

#define I3C_INTR_FORCE_HC_SEQ_CANCEL_FORCE_BIT   11

Definition at line 1036 of file i3c_regs.h.

I3C_INTR_FORCE_HC_WARN_CMD_SEQ_STALL_FORCE_BIT

#define I3C_INTR_FORCE_HC_WARN_CMD_SEQ_STALL_FORCE_BIT   12

Definition at line 1037 of file i3c_regs.h.

I3C_INTR_FORCE_REG_OFFSET

#define I3C_INTR_FORCE_REG_OFFSET   0x1ac

Definition at line 1033 of file i3c_regs.h.

I3C_INTR_FORCE_REG_RESVAL

#define I3C_INTR_FORCE_REG_RESVAL   0x0u

Definition at line 1034 of file i3c_regs.h.

I3C_INTR_FORCE_SCHED_CMD_MISSED_TICK_FORCE_BIT

#define I3C_INTR_FORCE_SCHED_CMD_MISSED_TICK_FORCE_BIT   14

Definition at line 1039 of file i3c_regs.h.

I3C_INTR_SIGNAL_ENABLE_HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN_BIT

#define I3C_INTR_SIGNAL_ENABLE_HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN_BIT   13

Definition at line 1029 of file i3c_regs.h.

I3C_INTR_SIGNAL_ENABLE_HC_INTERNAL_ERR_SIGNAL_EN_BIT

#define I3C_INTR_SIGNAL_ENABLE_HC_INTERNAL_ERR_SIGNAL_EN_BIT   10

Definition at line 1026 of file i3c_regs.h.

I3C_INTR_SIGNAL_ENABLE_HC_SEQ_CANCEL_SIGNAL_EN_BIT

#define I3C_INTR_SIGNAL_ENABLE_HC_SEQ_CANCEL_SIGNAL_EN_BIT   11

Definition at line 1027 of file i3c_regs.h.

I3C_INTR_SIGNAL_ENABLE_HC_WARN_CMD_SEQ_STALL_SIGNAL_EN_BIT

#define I3C_INTR_SIGNAL_ENABLE_HC_WARN_CMD_SEQ_STALL_SIGNAL_EN_BIT   12

Definition at line 1028 of file i3c_regs.h.

I3C_INTR_SIGNAL_ENABLE_REG_OFFSET

#define I3C_INTR_SIGNAL_ENABLE_REG_OFFSET   0x1a8

Definition at line 1024 of file i3c_regs.h.

I3C_INTR_SIGNAL_ENABLE_REG_RESVAL

#define I3C_INTR_SIGNAL_ENABLE_REG_RESVAL   0x0u

Definition at line 1025 of file i3c_regs.h.

I3C_INTR_SIGNAL_ENABLE_SCHED_CMD_MISSED_TICK_SIGNAL_EN_BIT

#define I3C_INTR_SIGNAL_ENABLE_SCHED_CMD_MISSED_TICK_SIGNAL_EN_BIT   14

Definition at line 1030 of file i3c_regs.h.

I3C_INTR_STATE_HCI_BIT

#define I3C_INTR_STATE_HCI_BIT   0

Definition at line 50 of file i3c_regs.h.

I3C_INTR_STATE_REG_OFFSET

#define I3C_INTR_STATE_REG_OFFSET   0x0

Definition at line 48 of file i3c_regs.h.

I3C_INTR_STATE_REG_RESVAL

#define I3C_INTR_STATE_REG_RESVAL   0x0u

Definition at line 49 of file i3c_regs.h.

I3C_INTR_STATE_TARG_BIT

#define I3C_INTR_STATE_TARG_BIT   1

Definition at line 51 of file i3c_regs.h.

I3C_INTR_STATUS_ENABLE_HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN_BIT

#define I3C_INTR_STATUS_ENABLE_HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN_BIT   13

Definition at line 1020 of file i3c_regs.h.

I3C_INTR_STATUS_ENABLE_HC_INTERNAL_ERR_STAT_EN_BIT

#define I3C_INTR_STATUS_ENABLE_HC_INTERNAL_ERR_STAT_EN_BIT   10

Definition at line 1017 of file i3c_regs.h.

I3C_INTR_STATUS_ENABLE_HC_SEQ_CANCEL_STAT_EN_BIT

#define I3C_INTR_STATUS_ENABLE_HC_SEQ_CANCEL_STAT_EN_BIT   11

Definition at line 1018 of file i3c_regs.h.

I3C_INTR_STATUS_ENABLE_HC_WARN_CMD_SEQ_STALL_STAT_EN_BIT

#define I3C_INTR_STATUS_ENABLE_HC_WARN_CMD_SEQ_STALL_STAT_EN_BIT   12

Definition at line 1019 of file i3c_regs.h.

I3C_INTR_STATUS_ENABLE_REG_OFFSET

#define I3C_INTR_STATUS_ENABLE_REG_OFFSET   0x1a4

Definition at line 1015 of file i3c_regs.h.

I3C_INTR_STATUS_ENABLE_REG_RESVAL

#define I3C_INTR_STATUS_ENABLE_REG_RESVAL   0x0u

Definition at line 1016 of file i3c_regs.h.

I3C_INTR_STATUS_ENABLE_SCHED_CMD_MISSED_TICK_STAT_EN_BIT

#define I3C_INTR_STATUS_ENABLE_SCHED_CMD_MISSED_TICK_STAT_EN_BIT   14

Definition at line 1021 of file i3c_regs.h.

I3C_INTR_STATUS_HC_ERR_CMD_SEQ_TIMEOUT_STAT_BIT

#define I3C_INTR_STATUS_HC_ERR_CMD_SEQ_TIMEOUT_STAT_BIT   13

Definition at line 1011 of file i3c_regs.h.

I3C_INTR_STATUS_HC_INTERNAL_ERR_STAT_BIT

#define I3C_INTR_STATUS_HC_INTERNAL_ERR_STAT_BIT   10

Definition at line 1008 of file i3c_regs.h.

I3C_INTR_STATUS_HC_SEQ_CANCEL_STAT_BIT

#define I3C_INTR_STATUS_HC_SEQ_CANCEL_STAT_BIT   11

Definition at line 1009 of file i3c_regs.h.

I3C_INTR_STATUS_HC_WARN_CMD_SEQ_STALL_STAT_BIT

#define I3C_INTR_STATUS_HC_WARN_CMD_SEQ_STALL_STAT_BIT   12

Definition at line 1010 of file i3c_regs.h.

I3C_INTR_STATUS_REG_OFFSET

#define I3C_INTR_STATUS_REG_OFFSET   0x1a0

Definition at line 1006 of file i3c_regs.h.

I3C_INTR_STATUS_REG_RESVAL

#define I3C_INTR_STATUS_REG_RESVAL   0x0u

Definition at line 1007 of file i3c_regs.h.

I3C_INTR_STATUS_SCHED_CMD_MISSED_TICK_STAT_BIT

#define I3C_INTR_STATUS_SCHED_CMD_MISSED_TICK_STAT_BIT   14

Definition at line 1012 of file i3c_regs.h.

I3C_INTR_TEST_HCI_BIT

#define I3C_INTR_TEST_HCI_BIT   0

Definition at line 62 of file i3c_regs.h.

I3C_INTR_TEST_REG_OFFSET

#define I3C_INTR_TEST_REG_OFFSET   0x8

Definition at line 60 of file i3c_regs.h.

I3C_INTR_TEST_REG_RESVAL

#define I3C_INTR_TEST_REG_RESVAL   0x0u

Definition at line 61 of file i3c_regs.h.

I3C_INTR_TEST_TARG_BIT

#define I3C_INTR_TEST_TARG_BIT   1

Definition at line 63 of file i3c_regs.h.

I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_FIELD

#define I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_FIELD    ((bitfield_field32_t) { .mask = I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_MASK, .index = I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_OFFSET })

Definition at line 1419 of file i3c_regs.h.

I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_MASK

#define I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_MASK   0xffu

Definition at line 1417 of file i3c_regs.h.

I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_OFFSET

#define I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_OFFSET   0

Definition at line 1418 of file i3c_regs.h.

I3C_MX_ERROR_COUNTERS_REG_OFFSET

#define I3C_MX_ERROR_COUNTERS_REG_OFFSET   0x2d0

Definition at line 1415 of file i3c_regs.h.

I3C_MX_ERROR_COUNTERS_REG_RESVAL

#define I3C_MX_ERROR_COUNTERS_REG_RESVAL   0x0u

Definition at line 1416 of file i3c_regs.h.

I3C_PARAM_MAX_GROUPS

#define I3C_PARAM_MAX_GROUPS   8

Definition at line 29 of file i3c_regs.h.

I3C_PARAM_MAX_TARGETS

#define I3C_PARAM_MAX_TARGETS   4

Definition at line 26 of file i3c_regs.h.

I3C_PARAM_NUM_ALERTS

#define I3C_PARAM_NUM_ALERTS   1

Definition at line 32 of file i3c_regs.h.

I3C_PARAM_NUM_ALERTS_PRIMARY

#define I3C_PARAM_NUM_ALERTS_PRIMARY   1

Definition at line 35 of file i3c_regs.h.

I3C_PARAM_NUM_ALERTS_SECONDARY

#define I3C_PARAM_NUM_ALERTS_SECONDARY   0

Definition at line 38 of file i3c_regs.h.

I3C_PARAM_NUM_D_A_T_WORDS

#define I3C_PARAM_NUM_D_A_T_WORDS   64

Definition at line 20 of file i3c_regs.h.

I3C_PARAM_NUM_D_C_T_WORDS

#define I3C_PARAM_NUM_D_C_T_WORDS   128

Definition at line 23 of file i3c_regs.h.

I3C_PARAM_REG_WIDTH

#define I3C_PARAM_REG_WIDTH   32

Definition at line 41 of file i3c_regs.h.

I3C_PHY_CONFIG_CTRL_DIRECT_DRIVE_EN_BIT

#define I3C_PHY_CONFIG_CTRL_DIRECT_DRIVE_EN_BIT   31

Definition at line 368 of file i3c_regs.h.

I3C_PHY_CONFIG_CTRL_SCL_BIT

#define I3C_PHY_CONFIG_CTRL_SCL_BIT   24

Definition at line 365 of file i3c_regs.h.

I3C_PHY_CONFIG_CTRL_SCL_PP_EN_BIT

#define I3C_PHY_CONFIG_CTRL_SCL_PP_EN_BIT   27

Definition at line 367 of file i3c_regs.h.

I3C_PHY_CONFIG_CTRL_SCL_PU_EN_BIT

#define I3C_PHY_CONFIG_CTRL_SCL_PU_EN_BIT   25

Definition at line 366 of file i3c_regs.h.

I3C_PHY_CONFIG_CTRL_SDA_BIT

#define I3C_PHY_CONFIG_CTRL_SDA_BIT   20

Definition at line 361 of file i3c_regs.h.

I3C_PHY_CONFIG_CTRL_SDA_OD_EN_BIT

#define I3C_PHY_CONFIG_CTRL_SDA_OD_EN_BIT   22

Definition at line 363 of file i3c_regs.h.

I3C_PHY_CONFIG_CTRL_SDA_PP_EN_BIT

#define I3C_PHY_CONFIG_CTRL_SDA_PP_EN_BIT   23

Definition at line 364 of file i3c_regs.h.

I3C_PHY_CONFIG_CTRL_SDA_PU_EN_BIT

#define I3C_PHY_CONFIG_CTRL_SDA_PU_EN_BIT   21

Definition at line 362 of file i3c_regs.h.

I3C_PHY_CONFIG_REG_OFFSET

#define I3C_PHY_CONFIG_REG_OFFSET   0x64

Definition at line 357 of file i3c_regs.h.

I3C_PHY_CONFIG_REG_RESVAL

#define I3C_PHY_CONFIG_REG_RESVAL   0x1100003u

Definition at line 358 of file i3c_regs.h.

I3C_PHY_CONFIG_SCL_HK_EN_BIT

#define I3C_PHY_CONFIG_SCL_HK_EN_BIT   0

Definition at line 359 of file i3c_regs.h.

I3C_PHY_CONFIG_SDA_HK_EN_BIT

#define I3C_PHY_CONFIG_SDA_HK_EN_BIT   1

Definition at line 360 of file i3c_regs.h.

I3C_PIO_CONTROL_ABORT_BIT

#define I3C_PIO_CONTROL_ABORT_BIT   2

Definition at line 1274 of file i3c_regs.h.

I3C_PIO_CONTROL_ENABLE_BIT

#define I3C_PIO_CONTROL_ENABLE_BIT   0

Definition at line 1272 of file i3c_regs.h.

I3C_PIO_CONTROL_REG_OFFSET

#define I3C_PIO_CONTROL_REG_OFFSET   0x230

Definition at line 1270 of file i3c_regs.h.

I3C_PIO_CONTROL_REG_RESVAL

#define I3C_PIO_CONTROL_REG_RESVAL   0x1u

Definition at line 1271 of file i3c_regs.h.

I3C_PIO_CONTROL_RS_BIT

#define I3C_PIO_CONTROL_RS_BIT   1

Definition at line 1273 of file i3c_regs.h.

I3C_PIO_INTR_FORCE_CMD_QUEUE_READY_FORCE_BIT

#define I3C_PIO_INTR_FORCE_CMD_QUEUE_READY_FORCE_BIT   3

Definition at line 1264 of file i3c_regs.h.

I3C_PIO_INTR_FORCE_IBI_THLD_FORCE_BIT

#define I3C_PIO_INTR_FORCE_IBI_THLD_FORCE_BIT   2

Definition at line 1263 of file i3c_regs.h.

I3C_PIO_INTR_FORCE_REG_OFFSET

#define I3C_PIO_INTR_FORCE_REG_OFFSET   0x22c

Definition at line 1259 of file i3c_regs.h.

I3C_PIO_INTR_FORCE_REG_RESVAL

#define I3C_PIO_INTR_FORCE_REG_RESVAL   0x0u

Definition at line 1260 of file i3c_regs.h.

I3C_PIO_INTR_FORCE_RESP_READY_FORCE_BIT

#define I3C_PIO_INTR_FORCE_RESP_READY_FORCE_BIT   4

Definition at line 1265 of file i3c_regs.h.

I3C_PIO_INTR_FORCE_RX_THLD_FORCE_BIT

#define I3C_PIO_INTR_FORCE_RX_THLD_FORCE_BIT   1

Definition at line 1262 of file i3c_regs.h.

I3C_PIO_INTR_FORCE_TRANSFER_ABORT_FORCE_BIT

#define I3C_PIO_INTR_FORCE_TRANSFER_ABORT_FORCE_BIT   5

Definition at line 1266 of file i3c_regs.h.

I3C_PIO_INTR_FORCE_TRANSFER_ERR_FORCE_BIT

#define I3C_PIO_INTR_FORCE_TRANSFER_ERR_FORCE_BIT   9

Definition at line 1267 of file i3c_regs.h.

I3C_PIO_INTR_FORCE_TX_THLD_FORCE_BIT

#define I3C_PIO_INTR_FORCE_TX_THLD_FORCE_BIT   0

Definition at line 1261 of file i3c_regs.h.

I3C_PIO_INTR_SIGNAL_ENABLE_CMD_QUEUE_READY_SIGNAL_EN_BIT

#define I3C_PIO_INTR_SIGNAL_ENABLE_CMD_QUEUE_READY_SIGNAL_EN_BIT   3

Definition at line 1253 of file i3c_regs.h.

I3C_PIO_INTR_SIGNAL_ENABLE_IBI_STATUS_THLD_SIGNAL_EN_BIT

#define I3C_PIO_INTR_SIGNAL_ENABLE_IBI_STATUS_THLD_SIGNAL_EN_BIT   2

Definition at line 1252 of file i3c_regs.h.

I3C_PIO_INTR_SIGNAL_ENABLE_REG_OFFSET

#define I3C_PIO_INTR_SIGNAL_ENABLE_REG_OFFSET   0x228

Definition at line 1248 of file i3c_regs.h.

I3C_PIO_INTR_SIGNAL_ENABLE_REG_RESVAL

#define I3C_PIO_INTR_SIGNAL_ENABLE_REG_RESVAL   0x0u

Definition at line 1249 of file i3c_regs.h.

I3C_PIO_INTR_SIGNAL_ENABLE_RESP_READY_SIGNAL_EN_BIT

#define I3C_PIO_INTR_SIGNAL_ENABLE_RESP_READY_SIGNAL_EN_BIT   4

Definition at line 1254 of file i3c_regs.h.

I3C_PIO_INTR_SIGNAL_ENABLE_RX_THLD_SIGNAL_EN_BIT

#define I3C_PIO_INTR_SIGNAL_ENABLE_RX_THLD_SIGNAL_EN_BIT   1

Definition at line 1251 of file i3c_regs.h.

I3C_PIO_INTR_SIGNAL_ENABLE_TRANSFER_ABORT_SIGNAL_EN_BIT

#define I3C_PIO_INTR_SIGNAL_ENABLE_TRANSFER_ABORT_SIGNAL_EN_BIT   5

Definition at line 1255 of file i3c_regs.h.

I3C_PIO_INTR_SIGNAL_ENABLE_TRANSFER_ERR_SIGNAL_EN_BIT

#define I3C_PIO_INTR_SIGNAL_ENABLE_TRANSFER_ERR_SIGNAL_EN_BIT   9

Definition at line 1256 of file i3c_regs.h.

I3C_PIO_INTR_SIGNAL_ENABLE_TX_THLD_SIGNAL_EN_BIT

#define I3C_PIO_INTR_SIGNAL_ENABLE_TX_THLD_SIGNAL_EN_BIT   0

Definition at line 1250 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_CMD_QUEUE_READY_STAT_BIT

#define I3C_PIO_INTR_STATUS_CMD_QUEUE_READY_STAT_BIT   3

Definition at line 1231 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_ENABLE_CMD_QUEUE_READY_STAT_EN_BIT

#define I3C_PIO_INTR_STATUS_ENABLE_CMD_QUEUE_READY_STAT_EN_BIT   3

Definition at line 1242 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_ENABLE_IBI_STATUS_THLD_STAT_EN_BIT

#define I3C_PIO_INTR_STATUS_ENABLE_IBI_STATUS_THLD_STAT_EN_BIT   2

Definition at line 1241 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_ENABLE_REG_OFFSET

#define I3C_PIO_INTR_STATUS_ENABLE_REG_OFFSET   0x224

Definition at line 1237 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_ENABLE_REG_RESVAL

#define I3C_PIO_INTR_STATUS_ENABLE_REG_RESVAL   0x0u

Definition at line 1238 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_ENABLE_RESP_READY_STAT_EN_BIT

#define I3C_PIO_INTR_STATUS_ENABLE_RESP_READY_STAT_EN_BIT   4

Definition at line 1243 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_ENABLE_RX_THLD_STAT_EN_BIT

#define I3C_PIO_INTR_STATUS_ENABLE_RX_THLD_STAT_EN_BIT   1

Definition at line 1240 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_ENABLE_TRANSFER_ABORT_STAT_EN_BIT

#define I3C_PIO_INTR_STATUS_ENABLE_TRANSFER_ABORT_STAT_EN_BIT   5

Definition at line 1244 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_ENABLE_TRANSFER_ERR_STAT_EN_BIT

#define I3C_PIO_INTR_STATUS_ENABLE_TRANSFER_ERR_STAT_EN_BIT   9

Definition at line 1245 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_ENABLE_TX_THLD_STAT_EN_BIT

#define I3C_PIO_INTR_STATUS_ENABLE_TX_THLD_STAT_EN_BIT   0

Definition at line 1239 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_IBI_STATUS_THLD_STAT_BIT

#define I3C_PIO_INTR_STATUS_IBI_STATUS_THLD_STAT_BIT   2

Definition at line 1230 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_REG_OFFSET

#define I3C_PIO_INTR_STATUS_REG_OFFSET   0x220

Definition at line 1226 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_REG_RESVAL

#define I3C_PIO_INTR_STATUS_REG_RESVAL   0x0u

Definition at line 1227 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_RESP_READY_STAT_BIT

#define I3C_PIO_INTR_STATUS_RESP_READY_STAT_BIT   4

Definition at line 1232 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_RX_THLD_STAT_BIT

#define I3C_PIO_INTR_STATUS_RX_THLD_STAT_BIT   1

Definition at line 1229 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_TRANSFER_ABORT_STAT_BIT

#define I3C_PIO_INTR_STATUS_TRANSFER_ABORT_STAT_BIT   5

Definition at line 1233 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_TRANSFER_ERR_STAT_BIT

#define I3C_PIO_INTR_STATUS_TRANSFER_ERR_STAT_BIT   9

Definition at line 1234 of file i3c_regs.h.

I3C_PIO_INTR_STATUS_TX_THLD_STAT_BIT

#define I3C_PIO_INTR_STATUS_TX_THLD_STAT_BIT   0

Definition at line 1228 of file i3c_regs.h.

I3C_PIO_SECTION_OFFSET_REG_OFFSET

#define I3C_PIO_SECTION_OFFSET_REG_OFFSET   0x1bc

Definition at line 1086 of file i3c_regs.h.

I3C_PIO_SECTION_OFFSET_REG_RESVAL

#define I3C_PIO_SECTION_OFFSET_REG_RESVAL   0x80u

Definition at line 1087 of file i3c_regs.h.

I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_FIELD

#define I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_MASK, .index = I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_OFFSET })

Definition at line 1090 of file i3c_regs.h.

I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_MASK

#define I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_MASK   0xffffu

Definition at line 1088 of file i3c_regs.h.

I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_OFFSET

#define I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_OFFSET   0

Definition at line 1089 of file i3c_regs.h.

I3C_PRESENT_STATE_AC_CURRENT_OWN_BIT

#define I3C_PRESENT_STATE_AC_CURRENT_OWN_BIT   2

Definition at line 1003 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_FIELD

#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_FIELD    ((bitfield_field32_t) { .mask = I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_MASK, .index = I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_OFFSET })

Definition at line 1407 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_MASK

#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_MASK   0x3fu

Definition at line 1405 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_OFFSET

#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_OFFSET   16

Definition at line 1406 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_FIELD

#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_FIELD    ((bitfield_field32_t) { .mask = I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_MASK, .index = I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_OFFSET })

Definition at line 1403 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_MASK

#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_MASK   0x3fu

Definition at line 1401 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_OFFSET

#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_OFFSET   8

Definition at line 1402 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_CMD_TID_FIELD

#define I3C_PRESENT_STATE_DEBUG_CMD_TID_FIELD    ((bitfield_field32_t) { .mask = I3C_PRESENT_STATE_DEBUG_CMD_TID_MASK, .index = I3C_PRESENT_STATE_DEBUG_CMD_TID_OFFSET })

Definition at line 1411 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_CMD_TID_MASK

#define I3C_PRESENT_STATE_DEBUG_CMD_TID_MASK   0xfu

Definition at line 1409 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_CMD_TID_OFFSET

#define I3C_PRESENT_STATE_DEBUG_CMD_TID_OFFSET   24

Definition at line 1410 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_REG_OFFSET

#define I3C_PRESENT_STATE_DEBUG_REG_OFFSET   0x2cc

Definition at line 1397 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_REG_RESVAL

#define I3C_PRESENT_STATE_DEBUG_REG_RESVAL   0x3u

Definition at line 1398 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_SCL_LINE_SIGNAL_LEVEL_BIT

#define I3C_PRESENT_STATE_DEBUG_SCL_LINE_SIGNAL_LEVEL_BIT   0

Definition at line 1399 of file i3c_regs.h.

I3C_PRESENT_STATE_DEBUG_SDA_LINE_SIGNAL_LEVEL_BIT

#define I3C_PRESENT_STATE_DEBUG_SDA_LINE_SIGNAL_LEVEL_BIT   1

Definition at line 1400 of file i3c_regs.h.

I3C_PRESENT_STATE_REG_OFFSET

#define I3C_PRESENT_STATE_REG_OFFSET   0x194

Definition at line 1001 of file i3c_regs.h.

I3C_PRESENT_STATE_REG_RESVAL

#define I3C_PRESENT_STATE_REG_RESVAL   0x0u

Definition at line 1002 of file i3c_regs.h.

I3C_QUEUE_SIZE_CR_QUEUE_SIZE_FIELD

#define I3C_QUEUE_SIZE_CR_QUEUE_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_CR_QUEUE_SIZE_MASK, .index = I3C_QUEUE_SIZE_CR_QUEUE_SIZE_OFFSET })

Definition at line 1200 of file i3c_regs.h.

I3C_QUEUE_SIZE_CR_QUEUE_SIZE_MASK

#define I3C_QUEUE_SIZE_CR_QUEUE_SIZE_MASK   0xffu

Definition at line 1198 of file i3c_regs.h.

I3C_QUEUE_SIZE_CR_QUEUE_SIZE_OFFSET

#define I3C_QUEUE_SIZE_CR_QUEUE_SIZE_OFFSET   0

Definition at line 1199 of file i3c_regs.h.

I3C_QUEUE_SIZE_IBI_STATUS_SIZE_FIELD

#define I3C_QUEUE_SIZE_IBI_STATUS_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_IBI_STATUS_SIZE_MASK, .index = I3C_QUEUE_SIZE_IBI_STATUS_SIZE_OFFSET })

Definition at line 1204 of file i3c_regs.h.

I3C_QUEUE_SIZE_IBI_STATUS_SIZE_MASK

#define I3C_QUEUE_SIZE_IBI_STATUS_SIZE_MASK   0xffu

Definition at line 1202 of file i3c_regs.h.

I3C_QUEUE_SIZE_IBI_STATUS_SIZE_OFFSET

#define I3C_QUEUE_SIZE_IBI_STATUS_SIZE_OFFSET   8

Definition at line 1203 of file i3c_regs.h.

I3C_QUEUE_SIZE_REG_OFFSET

#define I3C_QUEUE_SIZE_REG_OFFSET   0x218

Definition at line 1196 of file i3c_regs.h.

I3C_QUEUE_SIZE_REG_RESVAL

#define I3C_QUEUE_SIZE_REG_RESVAL   0x6061410u

Definition at line 1197 of file i3c_regs.h.

I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_FIELD

#define I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_MASK, .index = I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_OFFSET })

Definition at line 1208 of file i3c_regs.h.

I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_MASK

#define I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_MASK   0xffu

Definition at line 1206 of file i3c_regs.h.

I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_OFFSET

#define I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_OFFSET   16

Definition at line 1207 of file i3c_regs.h.

I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_FIELD

#define I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_MASK, .index = I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_OFFSET })

Definition at line 1212 of file i3c_regs.h.

I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_MASK

#define I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_MASK   0xffu

Definition at line 1210 of file i3c_regs.h.

I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_OFFSET

#define I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_OFFSET   24

Definition at line 1211 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_FIELD

#define I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_MASK, .index = I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_OFFSET })

Definition at line 1369 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_MASK

#define I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_MASK   0xffu

Definition at line 1367 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_OFFSET

#define I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_OFFSET   0

Definition at line 1368 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_FIELD

#define I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_MASK, .index = I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_OFFSET })

Definition at line 1377 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_MASK

#define I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_MASK   0xffu

Definition at line 1375 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_OFFSET

#define I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_OFFSET   16

Definition at line 1376 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_FIELD

#define I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_MASK, .index = I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_OFFSET })

Definition at line 1381 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_MASK

#define I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_MASK   0x1fu

Definition at line 1379 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_OFFSET

#define I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_OFFSET   24

Definition at line 1380 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_REG_OFFSET

#define I3C_QUEUE_STATUS_LEVEL_REG_OFFSET   0x2c4

Definition at line 1365 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_REG_RESVAL

#define I3C_QUEUE_STATUS_LEVEL_REG_RESVAL   0x10u

Definition at line 1366 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_FIELD

#define I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_MASK, .index = I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_OFFSET })

Definition at line 1373 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_MASK

#define I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_MASK   0xffu

Definition at line 1371 of file i3c_regs.h.

I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_OFFSET

#define I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_OFFSET   8

Definition at line 1372 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_FIELD

#define I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_MASK, .index = I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_OFFSET })

Definition at line 1160 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_MASK

#define I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_MASK   0xffu

Definition at line 1158 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_OFFSET

#define I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_OFFSET   0

Definition at line 1159 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_FIELD

#define I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_MASK, .index = I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_OFFSET })

Definition at line 1168 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_MASK

#define I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_MASK   0xffu

Definition at line 1166 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_OFFSET

#define I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_OFFSET   16

Definition at line 1167 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_FIELD

#define I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK, .index = I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET })

Definition at line 1172 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK

#define I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK   0xffu

Definition at line 1170 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET

#define I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET   24

Definition at line 1171 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_REG_OFFSET

#define I3C_QUEUE_THLD_CTRL_REG_OFFSET   0x210

Definition at line 1156 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_REG_RESVAL

#define I3C_QUEUE_THLD_CTRL_REG_RESVAL   0x1010101u

Definition at line 1157 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_FIELD

#define I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_MASK, .index = I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_OFFSET })

Definition at line 1164 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_MASK

#define I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_MASK   0xffu

Definition at line 1162 of file i3c_regs.h.

I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_OFFSET

#define I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_OFFSET   8

Definition at line 1163 of file i3c_regs.h.

I3C_RESET_CONTROL_CMD_QUEUE_RST_BIT

#define I3C_RESET_CONTROL_CMD_QUEUE_RST_BIT   1

Definition at line 994 of file i3c_regs.h.

I3C_RESET_CONTROL_IBI_QUEUE_RST_BIT

#define I3C_RESET_CONTROL_IBI_QUEUE_RST_BIT   5

Definition at line 998 of file i3c_regs.h.

I3C_RESET_CONTROL_REG_OFFSET

#define I3C_RESET_CONTROL_REG_OFFSET   0x190

Definition at line 991 of file i3c_regs.h.

I3C_RESET_CONTROL_REG_RESVAL

#define I3C_RESET_CONTROL_REG_RESVAL   0x0u

Definition at line 992 of file i3c_regs.h.

I3C_RESET_CONTROL_RESP_QUEUE_RST_BIT

#define I3C_RESET_CONTROL_RESP_QUEUE_RST_BIT   2

Definition at line 995 of file i3c_regs.h.

I3C_RESET_CONTROL_RX_FIFO_RST_BIT

#define I3C_RESET_CONTROL_RX_FIFO_RST_BIT   4

Definition at line 997 of file i3c_regs.h.

I3C_RESET_CONTROL_SOFT_RST_BIT

#define I3C_RESET_CONTROL_SOFT_RST_BIT   0

Definition at line 993 of file i3c_regs.h.

I3C_RESET_CONTROL_TX_FIFO_RST_BIT

#define I3C_RESET_CONTROL_TX_FIFO_RST_BIT   3

Definition at line 996 of file i3c_regs.h.

I3C_RESET_DET_CTRL_REG_OFFSET

#define I3C_RESET_DET_CTRL_REG_OFFSET   0x2c

Definition at line 180 of file i3c_regs.h.

I3C_RESET_DET_CTRL_REG_RESVAL

#define I3C_RESET_DET_CTRL_REG_RESVAL   0x0u

Definition at line 181 of file i3c_regs.h.

I3C_RESET_DET_CTRL_RST_PERIPH_EN_BIT

#define I3C_RESET_DET_CTRL_RST_PERIPH_EN_BIT   20

Definition at line 184 of file i3c_regs.h.

I3C_RESET_DET_CTRL_RST_TARGET_EN_BIT

#define I3C_RESET_DET_CTRL_RST_TARGET_EN_BIT   21

Definition at line 185 of file i3c_regs.h.

I3C_RESET_DET_CTRL_SLEEP_REQ_BIT

#define I3C_RESET_DET_CTRL_SLEEP_REQ_BIT   1

Definition at line 182 of file i3c_regs.h.

I3C_RESET_DET_CTRL_WAKE_ACK_BIT

#define I3C_RESET_DET_CTRL_WAKE_ACK_BIT   16

Definition at line 183 of file i3c_regs.h.

I3C_RESET_DET_STATUS_ACTIVE_BIT

#define I3C_RESET_DET_STATUS_ACTIVE_BIT   0

Definition at line 190 of file i3c_regs.h.

I3C_RESET_DET_STATUS_REG_OFFSET

#define I3C_RESET_DET_STATUS_REG_OFFSET   0x30

Definition at line 188 of file i3c_regs.h.

I3C_RESET_DET_STATUS_REG_RESVAL

#define I3C_RESET_DET_STATUS_REG_RESVAL   0x0u

Definition at line 189 of file i3c_regs.h.

I3C_RESET_DET_STATUS_RST_PERIPH_BIT

#define I3C_RESET_DET_STATUS_RST_PERIPH_BIT   2

Definition at line 192 of file i3c_regs.h.

I3C_RESET_DET_STATUS_RST_TARGET_BIT

#define I3C_RESET_DET_STATUS_RST_TARGET_BIT   3

Definition at line 193 of file i3c_regs.h.

I3C_RESET_DET_STATUS_WAKE_UP_BIT

#define I3C_RESET_DET_STATUS_WAKE_UP_BIT   1

Definition at line 191 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_FIELD

#define I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_MASK, .index = I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_OFFSET })

Definition at line 504 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_MASK

#define I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 502 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_OFFSET

#define I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_OFFSET   12

Definition at line 503 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_FIELD

#define I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_MASK, .index = I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_OFFSET })

Definition at line 500 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_MASK

#define I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 498 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_OFFSET

#define I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 499 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_REG_OFFSET

#define I3C_RESPONSE_QUEUE_CONFIG_REG_OFFSET   0x8c

Definition at line 496 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_REG_RESVAL

#define I3C_RESPONSE_QUEUE_CONFIG_REG_RESVAL   0x1012f120u

Definition at line 497 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_FIELD

#define I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_MASK, .index = I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_OFFSET })

Definition at line 508 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_MASK

#define I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_MASK   0xffu

Definition at line 506 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_OFFSET

#define I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_OFFSET   24

Definition at line 507 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_FULL_BIT

#define I3C_RESPONSE_QUEUE_STATE_FULL_BIT   31

Definition at line 523 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_PRE_BIT

#define I3C_RESPONSE_QUEUE_STATE_PRE_BIT   30

Definition at line 522 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_REG_OFFSET

#define I3C_RESPONSE_QUEUE_STATE_REG_OFFSET   0x90

Definition at line 512 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_REG_RESVAL

#define I3C_RESPONSE_QUEUE_STATE_REG_RESVAL   0x1200120u

Definition at line 513 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_RPTR_FIELD

#define I3C_RESPONSE_QUEUE_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_STATE_RPTR_MASK, .index = I3C_RESPONSE_QUEUE_STATE_RPTR_OFFSET })

Definition at line 520 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_RPTR_MASK

#define I3C_RESPONSE_QUEUE_STATE_RPTR_MASK   0x3ffu

Definition at line 518 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_RPTR_OFFSET

#define I3C_RESPONSE_QUEUE_STATE_RPTR_OFFSET   16

Definition at line 519 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_WPTR_FIELD

#define I3C_RESPONSE_QUEUE_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_STATE_WPTR_MASK, .index = I3C_RESPONSE_QUEUE_STATE_WPTR_OFFSET })

Definition at line 516 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_WPTR_MASK

#define I3C_RESPONSE_QUEUE_STATE_WPTR_MASK   0x3ffu

Definition at line 514 of file i3c_regs.h.

I3C_RESPONSE_QUEUE_STATE_WPTR_OFFSET

#define I3C_RESPONSE_QUEUE_STATE_WPTR_OFFSET   0

Definition at line 515 of file i3c_regs.h.

I3C_RING_HEADERS_SECTION_OFFSET_REG_OFFSET

#define I3C_RING_HEADERS_SECTION_OFFSET_REG_OFFSET   0x1b8

Definition at line 1078 of file i3c_regs.h.

I3C_RING_HEADERS_SECTION_OFFSET_REG_RESVAL

#define I3C_RING_HEADERS_SECTION_OFFSET_REG_RESVAL   0x0u

Definition at line 1079 of file i3c_regs.h.

I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_FIELD

#define I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_FIELD    ((bitfield_field32_t) { .mask = I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_MASK, .index = I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_OFFSET })

Definition at line 1082 of file i3c_regs.h.

I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_MASK

#define I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_MASK   0xffffu

Definition at line 1080 of file i3c_regs.h.

I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_OFFSET

#define I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_OFFSET   0

Definition at line 1081 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_ENTITY_ID_FIELD

#define I3C_SCHED_CMDS_DEBUG_ENTITY_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_ENTITY_ID_MASK, .index = I3C_SCHED_CMDS_DEBUG_ENTITY_ID_OFFSET })

Definition at line 1436 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_ENTITY_ID_MASK

#define I3C_SCHED_CMDS_DEBUG_ENTITY_ID_MASK   0xffu

Definition at line 1434 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_ENTITY_ID_OFFSET

#define I3C_SCHED_CMDS_DEBUG_ENTITY_ID_OFFSET   8

Definition at line 1435 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_ERR_OCCURRED_BIT

#define I3C_SCHED_CMDS_DEBUG_ERR_OCCURRED_BIT   21

Definition at line 1442 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_ERR_TYPE_BIT

#define I3C_SCHED_CMDS_DEBUG_ERR_TYPE_BIT   7

Definition at line 1433 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_INST_ID_FIELD

#define I3C_SCHED_CMDS_DEBUG_INST_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_INST_ID_MASK, .index = I3C_SCHED_CMDS_DEBUG_INST_ID_OFFSET })

Definition at line 1431 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_INST_ID_MASK

#define I3C_SCHED_CMDS_DEBUG_INST_ID_MASK   0x7u

Definition at line 1429 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_INST_ID_OFFSET

#define I3C_SCHED_CMDS_DEBUG_INST_ID_OFFSET   4

Definition at line 1430 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_REG_OFFSET

#define I3C_SCHED_CMDS_DEBUG_REG_OFFSET   0x2d4

Definition at line 1423 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_REG_RESVAL

#define I3C_SCHED_CMDS_DEBUG_REG_RESVAL   0x0u

Definition at line 1424 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_FIELD

#define I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_FIELD    ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_MASK, .index = I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_OFFSET })

Definition at line 1427 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_MASK

#define I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_MASK   0xfu

Definition at line 1425 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_OFFSET

#define I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_OFFSET   0

Definition at line 1426 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_FIELD

#define I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_FIELD    ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_MASK, .index = I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_OFFSET })

Definition at line 1440 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_MASK

#define I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_MASK   0x1fu

Definition at line 1438 of file i3c_regs.h.

I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_OFFSET

#define I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_OFFSET   16

Definition at line 1439 of file i3c_regs.h.

I3C_STBY_CR_CAPABILITIES_DAA_ENTDAA_SUPPORT_BIT

#define I3C_STBY_CR_CAPABILITIES_DAA_ENTDAA_SUPPORT_BIT   15

Definition at line 1500 of file i3c_regs.h.

I3C_STBY_CR_CAPABILITIES_DAA_SETAASA_SUPPORT_BIT

#define I3C_STBY_CR_CAPABILITIES_DAA_SETAASA_SUPPORT_BIT   13

Definition at line 1498 of file i3c_regs.h.

I3C_STBY_CR_CAPABILITIES_DAA_SETDASA_SUPPORT_BIT

#define I3C_STBY_CR_CAPABILITIES_DAA_SETDASA_SUPPORT_BIT   14

Definition at line 1499 of file i3c_regs.h.

I3C_STBY_CR_CAPABILITIES_REG_OFFSET

#define I3C_STBY_CR_CAPABILITIES_REG_OFFSET   0x2e4

Definition at line 1494 of file i3c_regs.h.

I3C_STBY_CR_CAPABILITIES_REG_RESVAL

#define I3C_STBY_CR_CAPABILITIES_REG_RESVAL   0xf020u

Definition at line 1495 of file i3c_regs.h.

I3C_STBY_CR_CAPABILITIES_SIMPLE_CRR_SUPPORT_BIT

#define I3C_STBY_CR_CAPABILITIES_SIMPLE_CRR_SUPPORT_BIT   5

Definition at line 1496 of file i3c_regs.h.

I3C_STBY_CR_CAPABILITIES_TARGET_XACT_SUPPORT_BIT

#define I3C_STBY_CR_CAPABILITIES_TARGET_XACT_SUPPORT_BIT   12

Definition at line 1497 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_FIELD

#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_MASK, .index = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_OFFSET })

Definition at line 1588 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_MASK

#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_MASK   0x7u

Definition at line 1586 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_OFFSET

#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_OFFSET   0

Definition at line 1587 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_FIELD

#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_MASK, .index = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_OFFSET })

Definition at line 1592 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_MASK

#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_MASK   0xfu

Definition at line 1590 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_OFFSET

#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_OFFSET   8

Definition at line 1591 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_GETCAPS_REG_OFFSET

#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_REG_OFFSET   0x308

Definition at line 1584 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_GETCAPS_REG_RESVAL

#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_REG_RESVAL   0x0u

Definition at line 1585 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_REG_OFFSET

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_REG_OFFSET   0x30c

Definition at line 1596 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_REG_RESVAL

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_REG_RESVAL   0x80000000u

Definition at line 1597 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_DYNAMIC_ADDR_BIT

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_DYNAMIC_ADDR_BIT   31

Definition at line 1610 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_FIELD

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_MASK, .index = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_OFFSET })

Definition at line 1604 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_MASK

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_MASK   0xffu

Definition at line 1602 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_OFFSET

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_OFFSET   8

Definition at line 1603 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_FIELD

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_MASK, .index = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_OFFSET })

Definition at line 1608 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_MASK

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_MASK   0xffu

Definition at line 1606 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_OFFSET

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_OFFSET   16

Definition at line 1607 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_FIELD

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_MASK, .index = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_OFFSET })

Definition at line 1600 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_MASK

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_MASK   0xffu

Definition at line 1598 of file i3c_regs.h.

I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_OFFSET

#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_OFFSET   0

Definition at line 1599 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_ACR_FSM_OP_SELECT_BIT

#define I3C_STBY_CR_CONTROL_ACR_FSM_OP_SELECT_BIT   2

Definition at line 1461 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_FIELD

#define I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_MASK, .index = I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_OFFSET })

Definition at line 1467 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_MASK

#define I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_MASK   0x7u

Definition at line 1465 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_OFFSET

#define I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_OFFSET   8

Definition at line 1466 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_CR_REQUEST_SEND_BIT

#define I3C_STBY_CR_CONTROL_CR_REQUEST_SEND_BIT   5

Definition at line 1464 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_DAA_ENTDAA_ENABLE_BIT

#define I3C_STBY_CR_CONTROL_DAA_ENTDAA_ENABLE_BIT   15

Definition at line 1472 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_DAA_SETAASA_ENABLE_BIT

#define I3C_STBY_CR_CONTROL_DAA_SETAASA_ENABLE_BIT   13

Definition at line 1470 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_DAA_SETDASA_ENABLE_BIT

#define I3C_STBY_CR_CONTROL_DAA_SETDASA_ENABLE_BIT   14

Definition at line 1471 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_HANDOFF_DEEP_SLEEP_BIT

#define I3C_STBY_CR_CONTROL_HANDOFF_DEEP_SLEEP_BIT   4

Definition at line 1463 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_HANDOFF_DELAY_NACK_BIT

#define I3C_STBY_CR_CONTROL_HANDOFF_DELAY_NACK_BIT   1

Definition at line 1460 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_PENDING_RX_NACK_BIT

#define I3C_STBY_CR_CONTROL_PENDING_RX_NACK_BIT   0

Definition at line 1459 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_PRIME_ACCEPT_GETACCCR_BIT

#define I3C_STBY_CR_CONTROL_PRIME_ACCEPT_GETACCCR_BIT   3

Definition at line 1462 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_REG_OFFSET

#define I3C_STBY_CR_CONTROL_REG_OFFSET   0x2dc

Definition at line 1457 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_REG_RESVAL

#define I3C_STBY_CR_CONTROL_REG_RESVAL   0x100cu

Definition at line 1458 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_RSTACT_DEFBYTE_02_BIT

#define I3C_STBY_CR_CONTROL_RSTACT_DEFBYTE_02_BIT   20

Definition at line 1473 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_FIELD

#define I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_MASK, .index = I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_OFFSET })

Definition at line 1476 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_MASK

#define I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_MASK   0x3u

Definition at line 1474 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_OFFSET

#define I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_OFFSET   30

Definition at line 1475 of file i3c_regs.h.

I3C_STBY_CR_CONTROL_TARGET_XACT_ENABLE_BIT

#define I3C_STBY_CR_CONTROL_TARGET_XACT_ENABLE_BIT   12

Definition at line 1469 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_FIELD

#define I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_MASK, .index = I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET })

Definition at line 1489 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_MASK

#define I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_MASK   0x7fu

Definition at line 1487 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET

#define I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET   16

Definition at line 1488 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_VALID_BIT

#define I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_VALID_BIT   31

Definition at line 1491 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_REG_OFFSET

#define I3C_STBY_CR_DEVICE_ADDR_REG_OFFSET   0x2e0

Definition at line 1480 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_REG_RESVAL

#define I3C_STBY_CR_DEVICE_ADDR_REG_RESVAL   0x0u

Definition at line 1481 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_FIELD

#define I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_MASK, .index = I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_OFFSET })

Definition at line 1484 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_MASK

#define I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_MASK   0x7fu

Definition at line 1482 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_OFFSET

#define I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_OFFSET   0

Definition at line 1483 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_VALID_BIT

#define I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_VALID_BIT   15

Definition at line 1486 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_FIELD

#define I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_OFFSET })

Definition at line 1529 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_MASK

#define I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_MASK   0x7u

Definition at line 1527 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_OFFSET

#define I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_OFFSET   29

Definition at line 1528 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_FIELD

#define I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_OFFSET })

Definition at line 1525 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_MASK

#define I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_MASK   0x1fu

Definition at line 1523 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_OFFSET

#define I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_OFFSET   24

Definition at line 1524 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_DCR_FIELD

#define I3C_STBY_CR_DEVICE_CHAR_DCR_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_DCR_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_DCR_OFFSET })

Definition at line 1521 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_DCR_MASK

#define I3C_STBY_CR_DEVICE_CHAR_DCR_MASK   0xffu

Definition at line 1519 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_DCR_OFFSET

#define I3C_STBY_CR_DEVICE_CHAR_DCR_OFFSET   16

Definition at line 1520 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_PID_HI_FIELD

#define I3C_STBY_CR_DEVICE_CHAR_PID_HI_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_PID_HI_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_PID_HI_OFFSET })

Definition at line 1517 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_PID_HI_MASK

#define I3C_STBY_CR_DEVICE_CHAR_PID_HI_MASK   0x7fffu

Definition at line 1515 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_PID_HI_OFFSET

#define I3C_STBY_CR_DEVICE_CHAR_PID_HI_OFFSET   1

Definition at line 1516 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_REG_OFFSET

#define I3C_STBY_CR_DEVICE_CHAR_REG_OFFSET   0x2f0

Definition at line 1513 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_CHAR_REG_RESVAL

#define I3C_STBY_CR_DEVICE_CHAR_REG_RESVAL   0x60000000u

Definition at line 1514 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_PID_LO_REG_OFFSET

#define I3C_STBY_CR_DEVICE_PID_LO_REG_OFFSET   0x2f4

Definition at line 1533 of file i3c_regs.h.

I3C_STBY_CR_DEVICE_PID_LO_REG_RESVAL

#define I3C_STBY_CR_DEVICE_PID_LO_REG_RESVAL   0x0u

Definition at line 1534 of file i3c_regs.h.

I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_FIELD

#define I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_OFFSET })

Definition at line 1449 of file i3c_regs.h.

I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_MASK

#define I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_MASK   0xffu

Definition at line 1447 of file i3c_regs.h.

I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_OFFSET

#define I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_OFFSET   0

Definition at line 1448 of file i3c_regs.h.

I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_FIELD

#define I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_OFFSET })

Definition at line 1453 of file i3c_regs.h.

I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_MASK

#define I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu

Definition at line 1451 of file i3c_regs.h.

I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_OFFSET

#define I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8

Definition at line 1452 of file i3c_regs.h.

I3C_STBY_CR_EXTCAP_HEADER_REG_OFFSET

#define I3C_STBY_CR_EXTCAP_HEADER_REG_OFFSET   0x2d8

Definition at line 1445 of file i3c_regs.h.

I3C_STBY_CR_EXTCAP_HEADER_REG_RESVAL

#define I3C_STBY_CR_EXTCAP_HEADER_REG_RESVAL   0xe12u

Definition at line 1446 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_CCC_FATAL_RSTDAA_ERR_FORCE_BIT

#define I3C_STBY_CR_INTR_FORCE_CCC_FATAL_RSTDAA_ERR_FORCE_BIT   19

Definition at line 1581 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_CCC_PARAM_MODIFIED_FORCE_BIT

#define I3C_STBY_CR_INTR_FORCE_CCC_PARAM_MODIFIED_FORCE_BIT   17

Definition at line 1579 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_CCC_UNHANDLED_NACK_FORCE_BIT

#define I3C_STBY_CR_INTR_FORCE_CCC_UNHANDLED_NACK_FORCE_BIT   18

Definition at line 1580 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_CRR_RESPONSE_FORCE_BIT

#define I3C_STBY_CR_INTR_FORCE_CRR_RESPONSE_FORCE_BIT   10

Definition at line 1573 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_REG_OFFSET

#define I3C_STBY_CR_INTR_FORCE_REG_OFFSET   0x304

Definition at line 1571 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_REG_RESVAL

#define I3C_STBY_CR_INTR_FORCE_REG_RESVAL   0x0u

Definition at line 1572 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_ERR_FORCE_BIT

#define I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_ERR_FORCE_BIT   14

Definition at line 1577 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_NACKED_FORCE_BIT

#define I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_NACKED_FORCE_BIT   12

Definition at line 1575 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_OK_FORCE_BIT

#define I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_OK_FORCE_BIT   13

Definition at line 1576 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_STBY_CR_DYN_ADDR_FORCE_BIT

#define I3C_STBY_CR_INTR_FORCE_STBY_CR_DYN_ADDR_FORCE_BIT   11

Definition at line 1574 of file i3c_regs.h.

I3C_STBY_CR_INTR_FORCE_STBY_CR_OP_RSTACT_FORCE_BIT

#define I3C_STBY_CR_INTR_FORCE_STBY_CR_OP_RSTACT_FORCE_BIT   16

Definition at line 1578 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_ERR_FAIL_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_ERR_FAIL_SIGNAL_EN_BIT   2

Definition at line 1558 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_ERR_M3_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_ERR_M3_SIGNAL_EN_BIT   3

Definition at line 1559 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_OK_PRIMED_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_OK_PRIMED_SIGNAL_EN_BIT   1

Definition at line 1557 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_OK_REMAIN_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_OK_REMAIN_SIGNAL_EN_BIT   0

Definition at line 1556 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_FATAL_RSTDAA_ERR_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_FATAL_RSTDAA_ERR_SIGNAL_EN_BIT   19

Definition at line 1568 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_PARAM_MODIFIED_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_PARAM_MODIFIED_SIGNAL_EN_BIT   17

Definition at line 1566 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_UNHANDLED_NACK_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_UNHANDLED_NACK_SIGNAL_EN_BIT   18

Definition at line 1567 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_CRR_RESPONSE_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_CRR_RESPONSE_SIGNAL_EN_BIT   10

Definition at line 1560 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_REG_OFFSET

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_REG_OFFSET   0x300

Definition at line 1554 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_REG_RESVAL

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_REG_RESVAL   0xc0000u

Definition at line 1555 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_ERR_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_ERR_SIGNAL_EN_BIT   14

Definition at line 1564 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_NACKED_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_NACKED_SIGNAL_EN_BIT   12

Definition at line 1562 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_OK_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_OK_SIGNAL_EN_BIT   13

Definition at line 1563 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_DYN_ADDR_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_DYN_ADDR_SIGNAL_EN_BIT   11

Definition at line 1561 of file i3c_regs.h.

I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_OP_RSTACT_SIGNAL_EN_BIT

#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_OP_RSTACT_SIGNAL_EN_BIT   16

Definition at line 1565 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_ERR_FAIL_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_ERR_FAIL_STAT_BIT   2

Definition at line 1541 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_ERR_M3_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_ERR_M3_STAT_BIT   3

Definition at line 1542 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_OK_PRIMED_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_OK_PRIMED_STAT_BIT   1

Definition at line 1540 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_OK_REMAIN_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_OK_REMAIN_STAT_BIT   0

Definition at line 1539 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_CCC_FATAL_RSTDAA_ERR_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_CCC_FATAL_RSTDAA_ERR_STAT_BIT   19

Definition at line 1551 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_CCC_PARAM_MODIFIED_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_CCC_PARAM_MODIFIED_STAT_BIT   17

Definition at line 1549 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_CCC_UNHANDLED_NACK_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_CCC_UNHANDLED_NACK_STAT_BIT   18

Definition at line 1550 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_CRR_RESPONSE_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_CRR_RESPONSE_STAT_BIT   10

Definition at line 1543 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_REG_OFFSET

#define I3C_STBY_CR_INTR_STATUS_REG_OFFSET   0x2f8

Definition at line 1537 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_REG_RESVAL

#define I3C_STBY_CR_INTR_STATUS_REG_RESVAL   0x0u

Definition at line 1538 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_ERR_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_ERR_STAT_BIT   14

Definition at line 1547 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_NACKED_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_NACKED_STAT_BIT   12

Definition at line 1545 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_OK_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_OK_STAT_BIT   13

Definition at line 1546 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_STBY_CR_DYN_ADDR_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_STBY_CR_DYN_ADDR_STAT_BIT   11

Definition at line 1544 of file i3c_regs.h.

I3C_STBY_CR_INTR_STATUS_STBY_CR_OP_RSTACT_STAT_BIT

#define I3C_STBY_CR_INTR_STATUS_STBY_CR_OP_RSTACT_STAT_BIT   16

Definition at line 1548 of file i3c_regs.h.

I3C_STBY_CR_STATUS_AC_CURRENT_OWN_BIT

#define I3C_STBY_CR_STATUS_AC_CURRENT_OWN_BIT   2

Definition at line 1505 of file i3c_regs.h.

I3C_STBY_CR_STATUS_HJ_REQ_STATUS_BIT

#define I3C_STBY_CR_STATUS_HJ_REQ_STATUS_BIT   8

Definition at line 1510 of file i3c_regs.h.

I3C_STBY_CR_STATUS_REG_OFFSET

#define I3C_STBY_CR_STATUS_REG_OFFSET   0x2ec

Definition at line 1503 of file i3c_regs.h.

I3C_STBY_CR_STATUS_REG_RESVAL

#define I3C_STBY_CR_STATUS_REG_RESVAL   0x0u

Definition at line 1504 of file i3c_regs.h.

I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_FIELD

#define I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_FIELD    ((bitfield_field32_t) { .mask = I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_MASK, .index = I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_OFFSET })

Definition at line 1508 of file i3c_regs.h.

I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_MASK

#define I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_MASK   0x7u

Definition at line 1506 of file i3c_regs.h.

I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_OFFSET

#define I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_OFFSET   5

Definition at line 1507 of file i3c_regs.h.

I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_FIELD

#define I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_MASK, .index = I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_OFFSET })

Definition at line 2200 of file i3c_regs.h.

I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_MASK

#define I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_MASK   0x7fu

Definition at line 2198 of file i3c_regs.h.

I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_OFFSET

#define I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_OFFSET   16

Definition at line 2199 of file i3c_regs.h.

I3C_TARG_ADDR_0_DYNAMIC_ADDR_VALID_0_BIT

#define I3C_TARG_ADDR_0_DYNAMIC_ADDR_VALID_0_BIT   31

Definition at line 2202 of file i3c_regs.h.

I3C_TARG_ADDR_0_REG_OFFSET

#define I3C_TARG_ADDR_0_REG_OFFSET   0x3ac

Definition at line 2191 of file i3c_regs.h.

I3C_TARG_ADDR_0_REG_RESVAL

#define I3C_TARG_ADDR_0_REG_RESVAL   0x0u

Definition at line 2192 of file i3c_regs.h.

I3C_TARG_ADDR_0_STATIC_ADDR_0_FIELD

#define I3C_TARG_ADDR_0_STATIC_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_0_STATIC_ADDR_0_MASK, .index = I3C_TARG_ADDR_0_STATIC_ADDR_0_OFFSET })

Definition at line 2195 of file i3c_regs.h.

I3C_TARG_ADDR_0_STATIC_ADDR_0_MASK

#define I3C_TARG_ADDR_0_STATIC_ADDR_0_MASK   0x7fu

Definition at line 2193 of file i3c_regs.h.

I3C_TARG_ADDR_0_STATIC_ADDR_0_OFFSET

#define I3C_TARG_ADDR_0_STATIC_ADDR_0_OFFSET   0

Definition at line 2194 of file i3c_regs.h.

I3C_TARG_ADDR_0_STATIC_ADDR_VALID_0_BIT

#define I3C_TARG_ADDR_0_STATIC_ADDR_VALID_0_BIT   15

Definition at line 2197 of file i3c_regs.h.

I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_FIELD

#define I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_MASK, .index = I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_OFFSET })

Definition at line 2214 of file i3c_regs.h.

I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_MASK

#define I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_MASK   0x7fu

Definition at line 2212 of file i3c_regs.h.

I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_OFFSET

#define I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_OFFSET   16

Definition at line 2213 of file i3c_regs.h.

I3C_TARG_ADDR_1_DYNAMIC_ADDR_VALID_1_BIT

#define I3C_TARG_ADDR_1_DYNAMIC_ADDR_VALID_1_BIT   31

Definition at line 2216 of file i3c_regs.h.

I3C_TARG_ADDR_1_REG_OFFSET

#define I3C_TARG_ADDR_1_REG_OFFSET   0x3b0

Definition at line 2205 of file i3c_regs.h.

I3C_TARG_ADDR_1_REG_RESVAL

#define I3C_TARG_ADDR_1_REG_RESVAL   0x0u

Definition at line 2206 of file i3c_regs.h.

I3C_TARG_ADDR_1_STATIC_ADDR_1_FIELD

#define I3C_TARG_ADDR_1_STATIC_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_1_STATIC_ADDR_1_MASK, .index = I3C_TARG_ADDR_1_STATIC_ADDR_1_OFFSET })

Definition at line 2209 of file i3c_regs.h.

I3C_TARG_ADDR_1_STATIC_ADDR_1_MASK

#define I3C_TARG_ADDR_1_STATIC_ADDR_1_MASK   0x7fu

Definition at line 2207 of file i3c_regs.h.

I3C_TARG_ADDR_1_STATIC_ADDR_1_OFFSET

#define I3C_TARG_ADDR_1_STATIC_ADDR_1_OFFSET   0

Definition at line 2208 of file i3c_regs.h.

I3C_TARG_ADDR_1_STATIC_ADDR_VALID_1_BIT

#define I3C_TARG_ADDR_1_STATIC_ADDR_VALID_1_BIT   15

Definition at line 2211 of file i3c_regs.h.

I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_FIELD

#define I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_MASK, .index = I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_OFFSET })

Definition at line 2228 of file i3c_regs.h.

I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_MASK

#define I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_MASK   0x7fu

Definition at line 2226 of file i3c_regs.h.

I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_OFFSET

#define I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_OFFSET   16

Definition at line 2227 of file i3c_regs.h.

I3C_TARG_ADDR_2_DYNAMIC_ADDR_VALID_2_BIT

#define I3C_TARG_ADDR_2_DYNAMIC_ADDR_VALID_2_BIT   31

Definition at line 2230 of file i3c_regs.h.

I3C_TARG_ADDR_2_REG_OFFSET

#define I3C_TARG_ADDR_2_REG_OFFSET   0x3b4

Definition at line 2219 of file i3c_regs.h.

I3C_TARG_ADDR_2_REG_RESVAL

#define I3C_TARG_ADDR_2_REG_RESVAL   0x0u

Definition at line 2220 of file i3c_regs.h.

I3C_TARG_ADDR_2_STATIC_ADDR_2_FIELD

#define I3C_TARG_ADDR_2_STATIC_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_2_STATIC_ADDR_2_MASK, .index = I3C_TARG_ADDR_2_STATIC_ADDR_2_OFFSET })

Definition at line 2223 of file i3c_regs.h.

I3C_TARG_ADDR_2_STATIC_ADDR_2_MASK

#define I3C_TARG_ADDR_2_STATIC_ADDR_2_MASK   0x7fu

Definition at line 2221 of file i3c_regs.h.

I3C_TARG_ADDR_2_STATIC_ADDR_2_OFFSET

#define I3C_TARG_ADDR_2_STATIC_ADDR_2_OFFSET   0

Definition at line 2222 of file i3c_regs.h.

I3C_TARG_ADDR_2_STATIC_ADDR_VALID_2_BIT

#define I3C_TARG_ADDR_2_STATIC_ADDR_VALID_2_BIT   15

Definition at line 2225 of file i3c_regs.h.

I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_FIELD

#define I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_MASK, .index = I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_OFFSET })

Definition at line 2242 of file i3c_regs.h.

I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_MASK

#define I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_MASK   0x7fu

Definition at line 2240 of file i3c_regs.h.

I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_OFFSET

#define I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_OFFSET   16

Definition at line 2241 of file i3c_regs.h.

I3C_TARG_ADDR_3_DYNAMIC_ADDR_VALID_3_BIT

#define I3C_TARG_ADDR_3_DYNAMIC_ADDR_VALID_3_BIT   31

Definition at line 2244 of file i3c_regs.h.

I3C_TARG_ADDR_3_REG_OFFSET

#define I3C_TARG_ADDR_3_REG_OFFSET   0x3b8

Definition at line 2233 of file i3c_regs.h.

I3C_TARG_ADDR_3_REG_RESVAL

#define I3C_TARG_ADDR_3_REG_RESVAL   0x0u

Definition at line 2234 of file i3c_regs.h.

I3C_TARG_ADDR_3_STATIC_ADDR_3_FIELD

#define I3C_TARG_ADDR_3_STATIC_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_3_STATIC_ADDR_3_MASK, .index = I3C_TARG_ADDR_3_STATIC_ADDR_3_OFFSET })

Definition at line 2237 of file i3c_regs.h.

I3C_TARG_ADDR_3_STATIC_ADDR_3_MASK

#define I3C_TARG_ADDR_3_STATIC_ADDR_3_MASK   0x7fu

Definition at line 2235 of file i3c_regs.h.

I3C_TARG_ADDR_3_STATIC_ADDR_3_OFFSET

#define I3C_TARG_ADDR_3_STATIC_ADDR_3_OFFSET   0

Definition at line 2236 of file i3c_regs.h.

I3C_TARG_ADDR_3_STATIC_ADDR_VALID_3_BIT

#define I3C_TARG_ADDR_3_STATIC_ADDR_VALID_3_BIT   15

Definition at line 2239 of file i3c_regs.h.

I3C_TARG_ADDR_DYNAMIC_ADDR_FIELD_WIDTH

#define I3C_TARG_ADDR_DYNAMIC_ADDR_FIELD_WIDTH   7

Definition at line 2186 of file i3c_regs.h.

I3C_TARG_ADDR_DYNAMIC_ADDR_VALID_FIELD_WIDTH

#define I3C_TARG_ADDR_DYNAMIC_ADDR_VALID_FIELD_WIDTH   1

Definition at line 2187 of file i3c_regs.h.

I3C_TARG_ADDR_MULTIREG_COUNT

#define I3C_TARG_ADDR_MULTIREG_COUNT   4

Definition at line 2188 of file i3c_regs.h.

I3C_TARG_ADDR_STATIC_ADDR_FIELD_WIDTH

#define I3C_TARG_ADDR_STATIC_ADDR_FIELD_WIDTH   7

Definition at line 2184 of file i3c_regs.h.

I3C_TARG_ADDR_STATIC_ADDR_VALID_FIELD_WIDTH

#define I3C_TARG_ADDR_STATIC_ADDR_VALID_FIELD_WIDTH   1

Definition at line 2185 of file i3c_regs.h.

I3C_TARG_ASYNC_CONFIG_MAX_ADDR_FIELD

#define I3C_TARG_ASYNC_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_ASYNC_CONFIG_MAX_ADDR_OFFSET })

Definition at line 926 of file i3c_regs.h.

I3C_TARG_ASYNC_CONFIG_MAX_ADDR_MASK

#define I3C_TARG_ASYNC_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 924 of file i3c_regs.h.

I3C_TARG_ASYNC_CONFIG_MAX_ADDR_OFFSET

#define I3C_TARG_ASYNC_CONFIG_MAX_ADDR_OFFSET   16

Definition at line 925 of file i3c_regs.h.

I3C_TARG_ASYNC_CONFIG_MIN_ADDR_FIELD

#define I3C_TARG_ASYNC_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_ASYNC_CONFIG_MIN_ADDR_OFFSET })

Definition at line 922 of file i3c_regs.h.

I3C_TARG_ASYNC_CONFIG_MIN_ADDR_MASK

#define I3C_TARG_ASYNC_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 920 of file i3c_regs.h.

I3C_TARG_ASYNC_CONFIG_MIN_ADDR_OFFSET

#define I3C_TARG_ASYNC_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 921 of file i3c_regs.h.

I3C_TARG_ASYNC_CONFIG_REG_OFFSET

#define I3C_TARG_ASYNC_CONFIG_REG_OFFSET   0x104

Definition at line 918 of file i3c_regs.h.

I3C_TARG_ASYNC_CONFIG_REG_RESVAL

#define I3C_TARG_ASYNC_CONFIG_REG_RESVAL   0x3ff03f0u

Definition at line 919 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_BCST_CCC_BIT

#define I3C_TARG_ASYNC_EVT_CONTROL_BCST_CCC_BIT   0

Definition at line 1721 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_BUS_EVENTS_BIT

#define I3C_TARG_ASYNC_EVT_CONTROL_BUS_EVENTS_BIT   7

Definition at line 1728 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_DIR_GET_CCC_BIT

#define I3C_TARG_ASYNC_EVT_CONTROL_DIR_GET_CCC_BIT   2

Definition at line 1723 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_DIR_SET_CCC_BIT

#define I3C_TARG_ASYNC_EVT_CONTROL_DIR_SET_CCC_BIT   1

Definition at line 1722 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_IBI_NOTIFY_BIT

#define I3C_TARG_ASYNC_EVT_CONTROL_IBI_NOTIFY_BIT   4

Definition at line 1725 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_IBI_SUSPEND_BIT

#define I3C_TARG_ASYNC_EVT_CONTROL_IBI_SUSPEND_BIT   6

Definition at line 1727 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_QUEUE_RESET_BIT

#define I3C_TARG_ASYNC_EVT_CONTROL_QUEUE_RESET_BIT   31

Definition at line 1729 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_REG_OFFSET

#define I3C_TARG_ASYNC_EVT_CONTROL_REG_OFFSET   0x328

Definition at line 1719 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_REG_RESVAL

#define I3C_TARG_ASYNC_EVT_CONTROL_REG_RESVAL   0x0u

Definition at line 1720 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_TX_NOTIFY_BIT

#define I3C_TARG_ASYNC_EVT_CONTROL_TX_NOTIFY_BIT   3

Definition at line 1724 of file i3c_regs.h.

I3C_TARG_ASYNC_EVT_CONTROL_TX_SUSPEND_BIT

#define I3C_TARG_ASYNC_EVT_CONTROL_TX_SUSPEND_BIT   5

Definition at line 1726 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_FULL_BIT

#define I3C_TARG_ASYNC_STATE_FULL_BIT   31

Definition at line 941 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_PRE_BIT

#define I3C_TARG_ASYNC_STATE_PRE_BIT   30

Definition at line 940 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_REG_OFFSET

#define I3C_TARG_ASYNC_STATE_REG_OFFSET   0x108

Definition at line 930 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_REG_RESVAL

#define I3C_TARG_ASYNC_STATE_REG_RESVAL   0x3f003f0u

Definition at line 931 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_RPTR_FIELD

#define I3C_TARG_ASYNC_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_STATE_RPTR_MASK, .index = I3C_TARG_ASYNC_STATE_RPTR_OFFSET })

Definition at line 938 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_RPTR_MASK

#define I3C_TARG_ASYNC_STATE_RPTR_MASK   0x3ffu

Definition at line 936 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_RPTR_OFFSET

#define I3C_TARG_ASYNC_STATE_RPTR_OFFSET   16

Definition at line 937 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_WPTR_FIELD

#define I3C_TARG_ASYNC_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_STATE_WPTR_MASK, .index = I3C_TARG_ASYNC_STATE_WPTR_OFFSET })

Definition at line 934 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_WPTR_MASK

#define I3C_TARG_ASYNC_STATE_WPTR_MASK   0x3ffu

Definition at line 932 of file i3c_regs.h.

I3C_TARG_ASYNC_STATE_WPTR_OFFSET

#define I3C_TARG_ASYNC_STATE_WPTR_OFFSET   0

Definition at line 933 of file i3c_regs.h.

I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_FIELD

#define I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_MASK, .index = I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_OFFSET })

Definition at line 1812 of file i3c_regs.h.

I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_MASK

#define I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_MASK   0xfffu

Definition at line 1810 of file i3c_regs.h.

I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_OFFSET

#define I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_OFFSET   16

Definition at line 1811 of file i3c_regs.h.

I3C_TARG_BUF_STATUS_LEVEL_REG_OFFSET

#define I3C_TARG_BUF_STATUS_LEVEL_REG_OFFSET   0x33c

Definition at line 1804 of file i3c_regs.h.

I3C_TARG_BUF_STATUS_LEVEL_REG_RESVAL

#define I3C_TARG_BUF_STATUS_LEVEL_REG_RESVAL   0x400000u

Definition at line 1805 of file i3c_regs.h.

I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_FIELD

#define I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_MASK, .index = I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_OFFSET })

Definition at line 1808 of file i3c_regs.h.

I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_MASK

#define I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_MASK   0xfffu

Definition at line 1806 of file i3c_regs.h.

I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_OFFSET

#define I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_OFFSET   0

Definition at line 1807 of file i3c_regs.h.

I3C_TARG_BUF_THLD_CTRL_REG_OFFSET

#define I3C_TARG_BUF_THLD_CTRL_REG_OFFSET   0x338

Definition at line 1792 of file i3c_regs.h.

I3C_TARG_BUF_THLD_CTRL_REG_RESVAL

#define I3C_TARG_BUF_THLD_CTRL_REG_RESVAL   0x10000001u

Definition at line 1793 of file i3c_regs.h.

I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_FIELD

#define I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_MASK, .index = I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_OFFSET })

Definition at line 1796 of file i3c_regs.h.

I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_MASK

#define I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_MASK   0xfffu

Definition at line 1794 of file i3c_regs.h.

I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_OFFSET

#define I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_OFFSET   0

Definition at line 1795 of file i3c_regs.h.

I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_FIELD

#define I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_MASK, .index = I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_OFFSET })

Definition at line 1800 of file i3c_regs.h.

I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_MASK

#define I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_MASK   0x7u

Definition at line 1798 of file i3c_regs.h.

I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_OFFSET

#define I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_OFFSET   28

Definition at line 1799 of file i3c_regs.h.

I3C_TARG_CAPS_0_REG_OFFSET

#define I3C_TARG_CAPS_0_REG_OFFSET   0x3dc

Definition at line 2346 of file i3c_regs.h.

I3C_TARG_CAPS_0_REG_RESVAL

#define I3C_TARG_CAPS_0_REG_RESVAL   0x0u

Definition at line 2347 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP1_SHARED_DET_0_BIT

#define I3C_TARG_CAPS_0_VTCAP1_SHARED_DET_0_BIT   5

Definition at line 2353 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP1_SIDE_FX_0_BIT

#define I3C_TARG_CAPS_0_VTCAP1_SIDE_FX_0_BIT   4

Definition at line 2352 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP1_TYPE_0_FIELD

#define I3C_TARG_CAPS_0_VTCAP1_TYPE_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_0_VTCAP1_TYPE_0_MASK, .index = I3C_TARG_CAPS_0_VTCAP1_TYPE_0_OFFSET })

Definition at line 2350 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP1_TYPE_0_MASK

#define I3C_TARG_CAPS_0_VTCAP1_TYPE_0_MASK   0x7u

Definition at line 2348 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP1_TYPE_0_OFFSET

#define I3C_TARG_CAPS_0_VTCAP1_TYPE_0_OFFSET   0

Definition at line 2349 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP2_ADDR_REMAP_0_BIT

#define I3C_TARG_CAPS_0_VTCAP2_ADDR_REMAP_0_BIT   10

Definition at line 2358 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_FIELD

#define I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_MASK, .index = I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_OFFSET })

Definition at line 2361 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_MASK

#define I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_MASK   0x3u

Definition at line 2359 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_OFFSET

#define I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_OFFSET   11

Definition at line 2360 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP2_IRQ_0_FIELD

#define I3C_TARG_CAPS_0_VTCAP2_IRQ_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_0_VTCAP2_IRQ_0_MASK, .index = I3C_TARG_CAPS_0_VTCAP2_IRQ_0_OFFSET })

Definition at line 2356 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP2_IRQ_0_MASK

#define I3C_TARG_CAPS_0_VTCAP2_IRQ_0_MASK   0x3u

Definition at line 2354 of file i3c_regs.h.

I3C_TARG_CAPS_0_VTCAP2_IRQ_0_OFFSET

#define I3C_TARG_CAPS_0_VTCAP2_IRQ_0_OFFSET   8

Definition at line 2355 of file i3c_regs.h.

I3C_TARG_CAPS_1_REG_OFFSET

#define I3C_TARG_CAPS_1_REG_OFFSET   0x3e0

Definition at line 2365 of file i3c_regs.h.

I3C_TARG_CAPS_1_REG_RESVAL

#define I3C_TARG_CAPS_1_REG_RESVAL   0x0u

Definition at line 2366 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP1_SHARED_DET_1_BIT

#define I3C_TARG_CAPS_1_VTCAP1_SHARED_DET_1_BIT   5

Definition at line 2372 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP1_SIDE_FX_1_BIT

#define I3C_TARG_CAPS_1_VTCAP1_SIDE_FX_1_BIT   4

Definition at line 2371 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP1_TYPE_1_FIELD

#define I3C_TARG_CAPS_1_VTCAP1_TYPE_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_1_VTCAP1_TYPE_1_MASK, .index = I3C_TARG_CAPS_1_VTCAP1_TYPE_1_OFFSET })

Definition at line 2369 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP1_TYPE_1_MASK

#define I3C_TARG_CAPS_1_VTCAP1_TYPE_1_MASK   0x7u

Definition at line 2367 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP1_TYPE_1_OFFSET

#define I3C_TARG_CAPS_1_VTCAP1_TYPE_1_OFFSET   0

Definition at line 2368 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP2_ADDR_REMAP_1_BIT

#define I3C_TARG_CAPS_1_VTCAP2_ADDR_REMAP_1_BIT   10

Definition at line 2377 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_FIELD

#define I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_MASK, .index = I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_OFFSET })

Definition at line 2380 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_MASK

#define I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_MASK   0x3u

Definition at line 2378 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_OFFSET

#define I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_OFFSET   11

Definition at line 2379 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP2_IRQ_1_FIELD

#define I3C_TARG_CAPS_1_VTCAP2_IRQ_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_1_VTCAP2_IRQ_1_MASK, .index = I3C_TARG_CAPS_1_VTCAP2_IRQ_1_OFFSET })

Definition at line 2375 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP2_IRQ_1_MASK

#define I3C_TARG_CAPS_1_VTCAP2_IRQ_1_MASK   0x3u

Definition at line 2373 of file i3c_regs.h.

I3C_TARG_CAPS_1_VTCAP2_IRQ_1_OFFSET

#define I3C_TARG_CAPS_1_VTCAP2_IRQ_1_OFFSET   8

Definition at line 2374 of file i3c_regs.h.

I3C_TARG_CAPS_2_REG_OFFSET

#define I3C_TARG_CAPS_2_REG_OFFSET   0x3e4

Definition at line 2384 of file i3c_regs.h.

I3C_TARG_CAPS_2_REG_RESVAL

#define I3C_TARG_CAPS_2_REG_RESVAL   0x0u

Definition at line 2385 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP1_SHARED_DET_2_BIT

#define I3C_TARG_CAPS_2_VTCAP1_SHARED_DET_2_BIT   5

Definition at line 2391 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP1_SIDE_FX_2_BIT

#define I3C_TARG_CAPS_2_VTCAP1_SIDE_FX_2_BIT   4

Definition at line 2390 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP1_TYPE_2_FIELD

#define I3C_TARG_CAPS_2_VTCAP1_TYPE_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_2_VTCAP1_TYPE_2_MASK, .index = I3C_TARG_CAPS_2_VTCAP1_TYPE_2_OFFSET })

Definition at line 2388 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP1_TYPE_2_MASK

#define I3C_TARG_CAPS_2_VTCAP1_TYPE_2_MASK   0x7u

Definition at line 2386 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP1_TYPE_2_OFFSET

#define I3C_TARG_CAPS_2_VTCAP1_TYPE_2_OFFSET   0

Definition at line 2387 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP2_ADDR_REMAP_2_BIT

#define I3C_TARG_CAPS_2_VTCAP2_ADDR_REMAP_2_BIT   10

Definition at line 2396 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_FIELD

#define I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_MASK, .index = I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_OFFSET })

Definition at line 2399 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_MASK

#define I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_MASK   0x3u

Definition at line 2397 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_OFFSET

#define I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_OFFSET   11

Definition at line 2398 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP2_IRQ_2_FIELD

#define I3C_TARG_CAPS_2_VTCAP2_IRQ_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_2_VTCAP2_IRQ_2_MASK, .index = I3C_TARG_CAPS_2_VTCAP2_IRQ_2_OFFSET })

Definition at line 2394 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP2_IRQ_2_MASK

#define I3C_TARG_CAPS_2_VTCAP2_IRQ_2_MASK   0x3u

Definition at line 2392 of file i3c_regs.h.

I3C_TARG_CAPS_2_VTCAP2_IRQ_2_OFFSET

#define I3C_TARG_CAPS_2_VTCAP2_IRQ_2_OFFSET   8

Definition at line 2393 of file i3c_regs.h.

I3C_TARG_CAPS_3_REG_OFFSET

#define I3C_TARG_CAPS_3_REG_OFFSET   0x3e8

Definition at line 2403 of file i3c_regs.h.

I3C_TARG_CAPS_3_REG_RESVAL

#define I3C_TARG_CAPS_3_REG_RESVAL   0x0u

Definition at line 2404 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP1_SHARED_DET_3_BIT

#define I3C_TARG_CAPS_3_VTCAP1_SHARED_DET_3_BIT   5

Definition at line 2410 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP1_SIDE_FX_3_BIT

#define I3C_TARG_CAPS_3_VTCAP1_SIDE_FX_3_BIT   4

Definition at line 2409 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP1_TYPE_3_FIELD

#define I3C_TARG_CAPS_3_VTCAP1_TYPE_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_3_VTCAP1_TYPE_3_MASK, .index = I3C_TARG_CAPS_3_VTCAP1_TYPE_3_OFFSET })

Definition at line 2407 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP1_TYPE_3_MASK

#define I3C_TARG_CAPS_3_VTCAP1_TYPE_3_MASK   0x7u

Definition at line 2405 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP1_TYPE_3_OFFSET

#define I3C_TARG_CAPS_3_VTCAP1_TYPE_3_OFFSET   0

Definition at line 2406 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP2_ADDR_REMAP_3_BIT

#define I3C_TARG_CAPS_3_VTCAP2_ADDR_REMAP_3_BIT   10

Definition at line 2415 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_FIELD

#define I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_MASK, .index = I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_OFFSET })

Definition at line 2418 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_MASK

#define I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_MASK   0x3u

Definition at line 2416 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_OFFSET

#define I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_OFFSET   11

Definition at line 2417 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP2_IRQ_3_FIELD

#define I3C_TARG_CAPS_3_VTCAP2_IRQ_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_3_VTCAP2_IRQ_3_MASK, .index = I3C_TARG_CAPS_3_VTCAP2_IRQ_3_OFFSET })

Definition at line 2413 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP2_IRQ_3_MASK

#define I3C_TARG_CAPS_3_VTCAP2_IRQ_3_MASK   0x3u

Definition at line 2411 of file i3c_regs.h.

I3C_TARG_CAPS_3_VTCAP2_IRQ_3_OFFSET

#define I3C_TARG_CAPS_3_VTCAP2_IRQ_3_OFFSET   8

Definition at line 2412 of file i3c_regs.h.

I3C_TARG_CAPS_MULTIREG_COUNT

#define I3C_TARG_CAPS_MULTIREG_COUNT   4

Definition at line 2343 of file i3c_regs.h.

I3C_TARG_CAPS_VTCAP1_SHARED_DET_FIELD_WIDTH

#define I3C_TARG_CAPS_VTCAP1_SHARED_DET_FIELD_WIDTH   1

Definition at line 2339 of file i3c_regs.h.

I3C_TARG_CAPS_VTCAP1_SIDE_FX_FIELD_WIDTH

#define I3C_TARG_CAPS_VTCAP1_SIDE_FX_FIELD_WIDTH   1

Definition at line 2338 of file i3c_regs.h.

I3C_TARG_CAPS_VTCAP1_TYPE_FIELD_WIDTH

#define I3C_TARG_CAPS_VTCAP1_TYPE_FIELD_WIDTH   3

Definition at line 2337 of file i3c_regs.h.

I3C_TARG_CAPS_VTCAP2_ADDR_REMAP_FIELD_WIDTH

#define I3C_TARG_CAPS_VTCAP2_ADDR_REMAP_FIELD_WIDTH   1

Definition at line 2341 of file i3c_regs.h.

I3C_TARG_CAPS_VTCAP2_BUS_CTX_FIELD_WIDTH

#define I3C_TARG_CAPS_VTCAP2_BUS_CTX_FIELD_WIDTH   2

Definition at line 2342 of file i3c_regs.h.

I3C_TARG_CAPS_VTCAP2_IRQ_FIELD_WIDTH

#define I3C_TARG_CAPS_VTCAP2_IRQ_FIELD_WIDTH   2

Definition at line 2340 of file i3c_regs.h.

I3C_TARG_CHAR_0_BCR_0_FIELD

#define I3C_TARG_CHAR_0_BCR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_0_BCR_0_MASK, .index = I3C_TARG_CHAR_0_BCR_0_OFFSET })

Definition at line 2265 of file i3c_regs.h.

I3C_TARG_CHAR_0_BCR_0_MASK

#define I3C_TARG_CHAR_0_BCR_0_MASK   0xffu

Definition at line 2263 of file i3c_regs.h.

I3C_TARG_CHAR_0_BCR_0_OFFSET

#define I3C_TARG_CHAR_0_BCR_0_OFFSET   24

Definition at line 2264 of file i3c_regs.h.

I3C_TARG_CHAR_0_DCR_0_FIELD

#define I3C_TARG_CHAR_0_DCR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_0_DCR_0_MASK, .index = I3C_TARG_CHAR_0_DCR_0_OFFSET })

Definition at line 2261 of file i3c_regs.h.

I3C_TARG_CHAR_0_DCR_0_MASK

#define I3C_TARG_CHAR_0_DCR_0_MASK   0xffu

Definition at line 2259 of file i3c_regs.h.

I3C_TARG_CHAR_0_DCR_0_OFFSET

#define I3C_TARG_CHAR_0_DCR_0_OFFSET   16

Definition at line 2260 of file i3c_regs.h.

I3C_TARG_CHAR_0_PID_HI_0_FIELD

#define I3C_TARG_CHAR_0_PID_HI_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_0_PID_HI_0_MASK, .index = I3C_TARG_CHAR_0_PID_HI_0_OFFSET })

Definition at line 2257 of file i3c_regs.h.

I3C_TARG_CHAR_0_PID_HI_0_MASK

#define I3C_TARG_CHAR_0_PID_HI_0_MASK   0xffffu

Definition at line 2255 of file i3c_regs.h.

I3C_TARG_CHAR_0_PID_HI_0_OFFSET

#define I3C_TARG_CHAR_0_PID_HI_0_OFFSET   0

Definition at line 2256 of file i3c_regs.h.

I3C_TARG_CHAR_0_REG_OFFSET

#define I3C_TARG_CHAR_0_REG_OFFSET   0x3bc

Definition at line 2253 of file i3c_regs.h.

I3C_TARG_CHAR_0_REG_RESVAL

#define I3C_TARG_CHAR_0_REG_RESVAL   0x3e000000u

Definition at line 2254 of file i3c_regs.h.

I3C_TARG_CHAR_1_BCR_1_FIELD

#define I3C_TARG_CHAR_1_BCR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_1_BCR_1_MASK, .index = I3C_TARG_CHAR_1_BCR_1_OFFSET })

Definition at line 2281 of file i3c_regs.h.

I3C_TARG_CHAR_1_BCR_1_MASK

#define I3C_TARG_CHAR_1_BCR_1_MASK   0xffu

Definition at line 2279 of file i3c_regs.h.

I3C_TARG_CHAR_1_BCR_1_OFFSET

#define I3C_TARG_CHAR_1_BCR_1_OFFSET   24

Definition at line 2280 of file i3c_regs.h.

I3C_TARG_CHAR_1_DCR_1_FIELD

#define I3C_TARG_CHAR_1_DCR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_1_DCR_1_MASK, .index = I3C_TARG_CHAR_1_DCR_1_OFFSET })

Definition at line 2277 of file i3c_regs.h.

I3C_TARG_CHAR_1_DCR_1_MASK

#define I3C_TARG_CHAR_1_DCR_1_MASK   0xffu

Definition at line 2275 of file i3c_regs.h.

I3C_TARG_CHAR_1_DCR_1_OFFSET

#define I3C_TARG_CHAR_1_DCR_1_OFFSET   16

Definition at line 2276 of file i3c_regs.h.

I3C_TARG_CHAR_1_PID_HI_1_FIELD

#define I3C_TARG_CHAR_1_PID_HI_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_1_PID_HI_1_MASK, .index = I3C_TARG_CHAR_1_PID_HI_1_OFFSET })

Definition at line 2273 of file i3c_regs.h.

I3C_TARG_CHAR_1_PID_HI_1_MASK

#define I3C_TARG_CHAR_1_PID_HI_1_MASK   0xffffu

Definition at line 2271 of file i3c_regs.h.

I3C_TARG_CHAR_1_PID_HI_1_OFFSET

#define I3C_TARG_CHAR_1_PID_HI_1_OFFSET   0

Definition at line 2272 of file i3c_regs.h.

I3C_TARG_CHAR_1_REG_OFFSET

#define I3C_TARG_CHAR_1_REG_OFFSET   0x3c0

Definition at line 2269 of file i3c_regs.h.

I3C_TARG_CHAR_1_REG_RESVAL

#define I3C_TARG_CHAR_1_REG_RESVAL   0x3e000000u

Definition at line 2270 of file i3c_regs.h.

I3C_TARG_CHAR_2_BCR_2_FIELD

#define I3C_TARG_CHAR_2_BCR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_2_BCR_2_MASK, .index = I3C_TARG_CHAR_2_BCR_2_OFFSET })

Definition at line 2297 of file i3c_regs.h.

I3C_TARG_CHAR_2_BCR_2_MASK

#define I3C_TARG_CHAR_2_BCR_2_MASK   0xffu

Definition at line 2295 of file i3c_regs.h.

I3C_TARG_CHAR_2_BCR_2_OFFSET

#define I3C_TARG_CHAR_2_BCR_2_OFFSET   24

Definition at line 2296 of file i3c_regs.h.

I3C_TARG_CHAR_2_DCR_2_FIELD

#define I3C_TARG_CHAR_2_DCR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_2_DCR_2_MASK, .index = I3C_TARG_CHAR_2_DCR_2_OFFSET })

Definition at line 2293 of file i3c_regs.h.

I3C_TARG_CHAR_2_DCR_2_MASK

#define I3C_TARG_CHAR_2_DCR_2_MASK   0xffu

Definition at line 2291 of file i3c_regs.h.

I3C_TARG_CHAR_2_DCR_2_OFFSET

#define I3C_TARG_CHAR_2_DCR_2_OFFSET   16

Definition at line 2292 of file i3c_regs.h.

I3C_TARG_CHAR_2_PID_HI_2_FIELD

#define I3C_TARG_CHAR_2_PID_HI_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_2_PID_HI_2_MASK, .index = I3C_TARG_CHAR_2_PID_HI_2_OFFSET })

Definition at line 2289 of file i3c_regs.h.

I3C_TARG_CHAR_2_PID_HI_2_MASK

#define I3C_TARG_CHAR_2_PID_HI_2_MASK   0xffffu

Definition at line 2287 of file i3c_regs.h.

I3C_TARG_CHAR_2_PID_HI_2_OFFSET

#define I3C_TARG_CHAR_2_PID_HI_2_OFFSET   0

Definition at line 2288 of file i3c_regs.h.

I3C_TARG_CHAR_2_REG_OFFSET

#define I3C_TARG_CHAR_2_REG_OFFSET   0x3c4

Definition at line 2285 of file i3c_regs.h.

I3C_TARG_CHAR_2_REG_RESVAL

#define I3C_TARG_CHAR_2_REG_RESVAL   0x3e000000u

Definition at line 2286 of file i3c_regs.h.

I3C_TARG_CHAR_3_BCR_3_FIELD

#define I3C_TARG_CHAR_3_BCR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_3_BCR_3_MASK, .index = I3C_TARG_CHAR_3_BCR_3_OFFSET })

Definition at line 2313 of file i3c_regs.h.

I3C_TARG_CHAR_3_BCR_3_MASK

#define I3C_TARG_CHAR_3_BCR_3_MASK   0xffu

Definition at line 2311 of file i3c_regs.h.

I3C_TARG_CHAR_3_BCR_3_OFFSET

#define I3C_TARG_CHAR_3_BCR_3_OFFSET   24

Definition at line 2312 of file i3c_regs.h.

I3C_TARG_CHAR_3_DCR_3_FIELD

#define I3C_TARG_CHAR_3_DCR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_3_DCR_3_MASK, .index = I3C_TARG_CHAR_3_DCR_3_OFFSET })

Definition at line 2309 of file i3c_regs.h.

I3C_TARG_CHAR_3_DCR_3_MASK

#define I3C_TARG_CHAR_3_DCR_3_MASK   0xffu

Definition at line 2307 of file i3c_regs.h.

I3C_TARG_CHAR_3_DCR_3_OFFSET

#define I3C_TARG_CHAR_3_DCR_3_OFFSET   16

Definition at line 2308 of file i3c_regs.h.

I3C_TARG_CHAR_3_PID_HI_3_FIELD

#define I3C_TARG_CHAR_3_PID_HI_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_3_PID_HI_3_MASK, .index = I3C_TARG_CHAR_3_PID_HI_3_OFFSET })

Definition at line 2305 of file i3c_regs.h.

I3C_TARG_CHAR_3_PID_HI_3_MASK

#define I3C_TARG_CHAR_3_PID_HI_3_MASK   0xffffu

Definition at line 2303 of file i3c_regs.h.

I3C_TARG_CHAR_3_PID_HI_3_OFFSET

#define I3C_TARG_CHAR_3_PID_HI_3_OFFSET   0

Definition at line 2304 of file i3c_regs.h.

I3C_TARG_CHAR_3_REG_OFFSET

#define I3C_TARG_CHAR_3_REG_OFFSET   0x3c8

Definition at line 2301 of file i3c_regs.h.

I3C_TARG_CHAR_3_REG_RESVAL

#define I3C_TARG_CHAR_3_REG_RESVAL   0x3e000000u

Definition at line 2302 of file i3c_regs.h.

I3C_TARG_CHAR_BCR_FIELD_WIDTH

#define I3C_TARG_CHAR_BCR_FIELD_WIDTH   8

Definition at line 2249 of file i3c_regs.h.

I3C_TARG_CHAR_DCR_FIELD_WIDTH

#define I3C_TARG_CHAR_DCR_FIELD_WIDTH   8

Definition at line 2248 of file i3c_regs.h.

I3C_TARG_CHAR_MULTIREG_COUNT

#define I3C_TARG_CHAR_MULTIREG_COUNT   4

Definition at line 2250 of file i3c_regs.h.

I3C_TARG_CHAR_PID_HI_FIELD_WIDTH

#define I3C_TARG_CHAR_PID_HI_FIELD_WIDTH   16

Definition at line 2247 of file i3c_regs.h.

I3C_TARG_CONTROL_CRHDLY1_AS_FIELD

#define I3C_TARG_CONTROL_CRHDLY1_AS_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_CONTROL_CRHDLY1_AS_MASK, .index = I3C_TARG_CONTROL_CRHDLY1_AS_OFFSET })

Definition at line 127 of file i3c_regs.h.

I3C_TARG_CONTROL_CRHDLY1_AS_MASK

#define I3C_TARG_CONTROL_CRHDLY1_AS_MASK   0x3u

Definition at line 125 of file i3c_regs.h.

I3C_TARG_CONTROL_CRHDLY1_AS_OFFSET

#define I3C_TARG_CONTROL_CRHDLY1_AS_OFFSET   2

Definition at line 126 of file i3c_regs.h.

I3C_TARG_CONTROL_CRHDLY1_SET_AS_BIT

#define I3C_TARG_CONTROL_CRHDLY1_SET_AS_BIT   4

Definition at line 129 of file i3c_regs.h.

I3C_TARG_CONTROL_EN_BIT

#define I3C_TARG_CONTROL_EN_BIT   0

Definition at line 123 of file i3c_regs.h.

I3C_TARG_CONTROL_EN_HDR_DDR_BIT

#define I3C_TARG_CONTROL_EN_HDR_DDR_BIT   8

Definition at line 130 of file i3c_regs.h.

I3C_TARG_CONTROL_HJ_REQUEST_BIT

#define I3C_TARG_CONTROL_HJ_REQUEST_BIT   30

Definition at line 131 of file i3c_regs.h.

I3C_TARG_CONTROL_REG_OFFSET

#define I3C_TARG_CONTROL_REG_OFFSET   0x1c

Definition at line 121 of file i3c_regs.h.

I3C_TARG_CONTROL_REG_RESVAL

#define I3C_TARG_CONTROL_REG_RESVAL   0x102u

Definition at line 122 of file i3c_regs.h.

I3C_TARG_CONTROL_STBY_CR_SUPPORT_BIT

#define I3C_TARG_CONTROL_STBY_CR_SUPPORT_BIT   1

Definition at line 124 of file i3c_regs.h.

I3C_TARG_CONTROL_SW_RESET_BIT

#define I3C_TARG_CONTROL_SW_RESET_BIT   31

Definition at line 132 of file i3c_regs.h.

I3C_TARG_ENABLE_ENABLE_0_BIT

#define I3C_TARG_ENABLE_ENABLE_0_BIT   0

Definition at line 1953 of file i3c_regs.h.

I3C_TARG_ENABLE_ENABLE_1_BIT

#define I3C_TARG_ENABLE_ENABLE_1_BIT   1

Definition at line 1954 of file i3c_regs.h.

I3C_TARG_ENABLE_ENABLE_2_BIT

#define I3C_TARG_ENABLE_ENABLE_2_BIT   2

Definition at line 1955 of file i3c_regs.h.

I3C_TARG_ENABLE_ENABLE_3_BIT

#define I3C_TARG_ENABLE_ENABLE_3_BIT   3

Definition at line 1956 of file i3c_regs.h.

I3C_TARG_ENABLE_ENABLE_FIELD_WIDTH

#define I3C_TARG_ENABLE_ENABLE_FIELD_WIDTH   1

Definition at line 1947 of file i3c_regs.h.

I3C_TARG_ENABLE_MULTIREG_COUNT

#define I3C_TARG_ENABLE_MULTIREG_COUNT   1

Definition at line 1948 of file i3c_regs.h.

I3C_TARG_ENABLE_REG_OFFSET

#define I3C_TARG_ENABLE_REG_OFFSET   0x368

Definition at line 1951 of file i3c_regs.h.

I3C_TARG_ENABLE_REG_RESVAL

#define I3C_TARG_ENABLE_REG_RESVAL   0x0u

Definition at line 1952 of file i3c_regs.h.

I3C_TARG_ERROR_DBR_FIELD

#define I3C_TARG_ERROR_DBR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_DBR_MASK, .index = I3C_TARG_ERROR_DBR_OFFSET })

Definition at line 1764 of file i3c_regs.h.

I3C_TARG_ERROR_DBR_MASK

#define I3C_TARG_ERROR_DBR_MASK   0xfu

Definition at line 1762 of file i3c_regs.h.

I3C_TARG_ERROR_DBR_OFFSET

#define I3C_TARG_ERROR_DBR_OFFSET   28

Definition at line 1763 of file i3c_regs.h.

I3C_TARG_ERROR_REG_OFFSET

#define I3C_TARG_ERROR_REG_OFFSET   0x32c

Definition at line 1732 of file i3c_regs.h.

I3C_TARG_ERROR_REG_RESVAL

#define I3C_TARG_ERROR_REG_RESVAL   0x0u

Definition at line 1733 of file i3c_regs.h.

I3C_TARG_ERROR_TE0_FIELD

#define I3C_TARG_ERROR_TE0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE0_MASK, .index = I3C_TARG_ERROR_TE0_OFFSET })

Definition at line 1736 of file i3c_regs.h.

I3C_TARG_ERROR_TE0_MASK

#define I3C_TARG_ERROR_TE0_MASK   0xfu

Definition at line 1734 of file i3c_regs.h.

I3C_TARG_ERROR_TE0_OFFSET

#define I3C_TARG_ERROR_TE0_OFFSET   0

Definition at line 1735 of file i3c_regs.h.

I3C_TARG_ERROR_TE1_FIELD

#define I3C_TARG_ERROR_TE1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE1_MASK, .index = I3C_TARG_ERROR_TE1_OFFSET })

Definition at line 1740 of file i3c_regs.h.

I3C_TARG_ERROR_TE1_MASK

#define I3C_TARG_ERROR_TE1_MASK   0xfu

Definition at line 1738 of file i3c_regs.h.

I3C_TARG_ERROR_TE1_OFFSET

#define I3C_TARG_ERROR_TE1_OFFSET   4

Definition at line 1739 of file i3c_regs.h.

I3C_TARG_ERROR_TE2_FIELD

#define I3C_TARG_ERROR_TE2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE2_MASK, .index = I3C_TARG_ERROR_TE2_OFFSET })

Definition at line 1744 of file i3c_regs.h.

I3C_TARG_ERROR_TE2_MASK

#define I3C_TARG_ERROR_TE2_MASK   0xfu

Definition at line 1742 of file i3c_regs.h.

I3C_TARG_ERROR_TE2_OFFSET

#define I3C_TARG_ERROR_TE2_OFFSET   8

Definition at line 1743 of file i3c_regs.h.

I3C_TARG_ERROR_TE3_FIELD

#define I3C_TARG_ERROR_TE3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE3_MASK, .index = I3C_TARG_ERROR_TE3_OFFSET })

Definition at line 1748 of file i3c_regs.h.

I3C_TARG_ERROR_TE3_MASK

#define I3C_TARG_ERROR_TE3_MASK   0xfu

Definition at line 1746 of file i3c_regs.h.

I3C_TARG_ERROR_TE3_OFFSET

#define I3C_TARG_ERROR_TE3_OFFSET   12

Definition at line 1747 of file i3c_regs.h.

I3C_TARG_ERROR_TE4_FIELD

#define I3C_TARG_ERROR_TE4_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE4_MASK, .index = I3C_TARG_ERROR_TE4_OFFSET })

Definition at line 1752 of file i3c_regs.h.

I3C_TARG_ERROR_TE4_MASK

#define I3C_TARG_ERROR_TE4_MASK   0xfu

Definition at line 1750 of file i3c_regs.h.

I3C_TARG_ERROR_TE4_OFFSET

#define I3C_TARG_ERROR_TE4_OFFSET   16

Definition at line 1751 of file i3c_regs.h.

I3C_TARG_ERROR_TE5_FIELD

#define I3C_TARG_ERROR_TE5_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE5_MASK, .index = I3C_TARG_ERROR_TE5_OFFSET })

Definition at line 1756 of file i3c_regs.h.

I3C_TARG_ERROR_TE5_MASK

#define I3C_TARG_ERROR_TE5_MASK   0xfu

Definition at line 1754 of file i3c_regs.h.

I3C_TARG_ERROR_TE5_OFFSET

#define I3C_TARG_ERROR_TE5_OFFSET   20

Definition at line 1755 of file i3c_regs.h.

I3C_TARG_ERROR_TE6_FIELD

#define I3C_TARG_ERROR_TE6_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE6_MASK, .index = I3C_TARG_ERROR_TE6_OFFSET })

Definition at line 1760 of file i3c_regs.h.

I3C_TARG_ERROR_TE6_MASK

#define I3C_TARG_ERROR_TE6_MASK   0xfu

Definition at line 1758 of file i3c_regs.h.

I3C_TARG_ERROR_TE6_OFFSET

#define I3C_TARG_ERROR_TE6_OFFSET   24

Definition at line 1759 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_0_ENCR_0_BIT

#define I3C_TARG_EVENT_ENABLE_0_ENCR_0_BIT   1

Definition at line 1902 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_0_ENHJ_0_BIT

#define I3C_TARG_EVENT_ENABLE_0_ENHJ_0_BIT   2

Definition at line 1903 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_0_ENINT_0_BIT

#define I3C_TARG_EVENT_ENABLE_0_ENINT_0_BIT   0

Definition at line 1901 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_0_REG_OFFSET

#define I3C_TARG_EVENT_ENABLE_0_REG_OFFSET   0x354

Definition at line 1899 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_0_REG_RESVAL

#define I3C_TARG_EVENT_ENABLE_0_REG_RESVAL   0x7u

Definition at line 1900 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_1_ENCR_1_BIT

#define I3C_TARG_EVENT_ENABLE_1_ENCR_1_BIT   1

Definition at line 1909 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_1_ENHJ_1_BIT

#define I3C_TARG_EVENT_ENABLE_1_ENHJ_1_BIT   2

Definition at line 1910 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_1_ENINT_1_BIT

#define I3C_TARG_EVENT_ENABLE_1_ENINT_1_BIT   0

Definition at line 1908 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_1_REG_OFFSET

#define I3C_TARG_EVENT_ENABLE_1_REG_OFFSET   0x358

Definition at line 1906 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_1_REG_RESVAL

#define I3C_TARG_EVENT_ENABLE_1_REG_RESVAL   0x7u

Definition at line 1907 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_2_ENCR_2_BIT

#define I3C_TARG_EVENT_ENABLE_2_ENCR_2_BIT   1

Definition at line 1916 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_2_ENHJ_2_BIT

#define I3C_TARG_EVENT_ENABLE_2_ENHJ_2_BIT   2

Definition at line 1917 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_2_ENINT_2_BIT

#define I3C_TARG_EVENT_ENABLE_2_ENINT_2_BIT   0

Definition at line 1915 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_2_REG_OFFSET

#define I3C_TARG_EVENT_ENABLE_2_REG_OFFSET   0x35c

Definition at line 1913 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_2_REG_RESVAL

#define I3C_TARG_EVENT_ENABLE_2_REG_RESVAL   0x7u

Definition at line 1914 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_3_ENCR_3_BIT

#define I3C_TARG_EVENT_ENABLE_3_ENCR_3_BIT   1

Definition at line 1923 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_3_ENHJ_3_BIT

#define I3C_TARG_EVENT_ENABLE_3_ENHJ_3_BIT   2

Definition at line 1924 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_3_ENINT_3_BIT

#define I3C_TARG_EVENT_ENABLE_3_ENINT_3_BIT   0

Definition at line 1922 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_3_REG_OFFSET

#define I3C_TARG_EVENT_ENABLE_3_REG_OFFSET   0x360

Definition at line 1920 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_3_REG_RESVAL

#define I3C_TARG_EVENT_ENABLE_3_REG_RESVAL   0x7u

Definition at line 1921 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_ENCR_FIELD_WIDTH

#define I3C_TARG_EVENT_ENABLE_ENCR_FIELD_WIDTH   1

Definition at line 1894 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_ENHJ_FIELD_WIDTH

#define I3C_TARG_EVENT_ENABLE_ENHJ_FIELD_WIDTH   1

Definition at line 1895 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_ENINT_FIELD_WIDTH

#define I3C_TARG_EVENT_ENABLE_ENINT_FIELD_WIDTH   1

Definition at line 1893 of file i3c_regs.h.

I3C_TARG_EVENT_ENABLE_MULTIREG_COUNT

#define I3C_TARG_EVENT_ENABLE_MULTIREG_COUNT   4

Definition at line 1896 of file i3c_regs.h.

I3C_TARG_GROUP_0_GROUP_ADDR_0_FIELD

#define I3C_TARG_GROUP_0_GROUP_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_0_GROUP_ADDR_0_MASK, .index = I3C_TARG_GROUP_0_GROUP_ADDR_0_OFFSET })

Definition at line 1968 of file i3c_regs.h.

I3C_TARG_GROUP_0_GROUP_ADDR_0_MASK

#define I3C_TARG_GROUP_0_GROUP_ADDR_0_MASK   0x7fu

Definition at line 1966 of file i3c_regs.h.

I3C_TARG_GROUP_0_GROUP_ADDR_0_OFFSET

#define I3C_TARG_GROUP_0_GROUP_ADDR_0_OFFSET   0

Definition at line 1967 of file i3c_regs.h.

I3C_TARG_GROUP_0_REG_OFFSET

#define I3C_TARG_GROUP_0_REG_OFFSET   0x36c

Definition at line 1964 of file i3c_regs.h.

I3C_TARG_GROUP_0_REG_RESVAL

#define I3C_TARG_GROUP_0_REG_RESVAL   0x0u

Definition at line 1965 of file i3c_regs.h.

I3C_TARG_GROUP_0_TARGETS_0_FIELD

#define I3C_TARG_GROUP_0_TARGETS_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_0_TARGETS_0_MASK, .index = I3C_TARG_GROUP_0_TARGETS_0_OFFSET })

Definition at line 1972 of file i3c_regs.h.

I3C_TARG_GROUP_0_TARGETS_0_MASK

#define I3C_TARG_GROUP_0_TARGETS_0_MASK   0xfu

Definition at line 1970 of file i3c_regs.h.

I3C_TARG_GROUP_0_TARGETS_0_OFFSET

#define I3C_TARG_GROUP_0_TARGETS_0_OFFSET   8

Definition at line 1971 of file i3c_regs.h.

I3C_TARG_GROUP_1_GROUP_ADDR_1_FIELD

#define I3C_TARG_GROUP_1_GROUP_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_1_GROUP_ADDR_1_MASK, .index = I3C_TARG_GROUP_1_GROUP_ADDR_1_OFFSET })

Definition at line 1980 of file i3c_regs.h.

I3C_TARG_GROUP_1_GROUP_ADDR_1_MASK

#define I3C_TARG_GROUP_1_GROUP_ADDR_1_MASK   0x7fu

Definition at line 1978 of file i3c_regs.h.

I3C_TARG_GROUP_1_GROUP_ADDR_1_OFFSET

#define I3C_TARG_GROUP_1_GROUP_ADDR_1_OFFSET   0

Definition at line 1979 of file i3c_regs.h.

I3C_TARG_GROUP_1_REG_OFFSET

#define I3C_TARG_GROUP_1_REG_OFFSET   0x370

Definition at line 1976 of file i3c_regs.h.

I3C_TARG_GROUP_1_REG_RESVAL

#define I3C_TARG_GROUP_1_REG_RESVAL   0x0u

Definition at line 1977 of file i3c_regs.h.

I3C_TARG_GROUP_1_TARGETS_1_FIELD

#define I3C_TARG_GROUP_1_TARGETS_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_1_TARGETS_1_MASK, .index = I3C_TARG_GROUP_1_TARGETS_1_OFFSET })

Definition at line 1984 of file i3c_regs.h.

I3C_TARG_GROUP_1_TARGETS_1_MASK

#define I3C_TARG_GROUP_1_TARGETS_1_MASK   0xfu

Definition at line 1982 of file i3c_regs.h.

I3C_TARG_GROUP_1_TARGETS_1_OFFSET

#define I3C_TARG_GROUP_1_TARGETS_1_OFFSET   8

Definition at line 1983 of file i3c_regs.h.

I3C_TARG_GROUP_2_GROUP_ADDR_2_FIELD

#define I3C_TARG_GROUP_2_GROUP_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_2_GROUP_ADDR_2_MASK, .index = I3C_TARG_GROUP_2_GROUP_ADDR_2_OFFSET })

Definition at line 1992 of file i3c_regs.h.

I3C_TARG_GROUP_2_GROUP_ADDR_2_MASK

#define I3C_TARG_GROUP_2_GROUP_ADDR_2_MASK   0x7fu

Definition at line 1990 of file i3c_regs.h.

I3C_TARG_GROUP_2_GROUP_ADDR_2_OFFSET

#define I3C_TARG_GROUP_2_GROUP_ADDR_2_OFFSET   0

Definition at line 1991 of file i3c_regs.h.

I3C_TARG_GROUP_2_REG_OFFSET

#define I3C_TARG_GROUP_2_REG_OFFSET   0x374

Definition at line 1988 of file i3c_regs.h.

I3C_TARG_GROUP_2_REG_RESVAL

#define I3C_TARG_GROUP_2_REG_RESVAL   0x0u

Definition at line 1989 of file i3c_regs.h.

I3C_TARG_GROUP_2_TARGETS_2_FIELD

#define I3C_TARG_GROUP_2_TARGETS_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_2_TARGETS_2_MASK, .index = I3C_TARG_GROUP_2_TARGETS_2_OFFSET })

Definition at line 1996 of file i3c_regs.h.

I3C_TARG_GROUP_2_TARGETS_2_MASK

#define I3C_TARG_GROUP_2_TARGETS_2_MASK   0xfu

Definition at line 1994 of file i3c_regs.h.

I3C_TARG_GROUP_2_TARGETS_2_OFFSET

#define I3C_TARG_GROUP_2_TARGETS_2_OFFSET   8

Definition at line 1995 of file i3c_regs.h.

I3C_TARG_GROUP_3_GROUP_ADDR_3_FIELD

#define I3C_TARG_GROUP_3_GROUP_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_3_GROUP_ADDR_3_MASK, .index = I3C_TARG_GROUP_3_GROUP_ADDR_3_OFFSET })

Definition at line 2004 of file i3c_regs.h.

I3C_TARG_GROUP_3_GROUP_ADDR_3_MASK

#define I3C_TARG_GROUP_3_GROUP_ADDR_3_MASK   0x7fu

Definition at line 2002 of file i3c_regs.h.

I3C_TARG_GROUP_3_GROUP_ADDR_3_OFFSET

#define I3C_TARG_GROUP_3_GROUP_ADDR_3_OFFSET   0

Definition at line 2003 of file i3c_regs.h.

I3C_TARG_GROUP_3_REG_OFFSET

#define I3C_TARG_GROUP_3_REG_OFFSET   0x378

Definition at line 2000 of file i3c_regs.h.

I3C_TARG_GROUP_3_REG_RESVAL

#define I3C_TARG_GROUP_3_REG_RESVAL   0x0u

Definition at line 2001 of file i3c_regs.h.

I3C_TARG_GROUP_3_TARGETS_3_FIELD

#define I3C_TARG_GROUP_3_TARGETS_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_3_TARGETS_3_MASK, .index = I3C_TARG_GROUP_3_TARGETS_3_OFFSET })

Definition at line 2008 of file i3c_regs.h.

I3C_TARG_GROUP_3_TARGETS_3_MASK

#define I3C_TARG_GROUP_3_TARGETS_3_MASK   0xfu

Definition at line 2006 of file i3c_regs.h.

I3C_TARG_GROUP_3_TARGETS_3_OFFSET

#define I3C_TARG_GROUP_3_TARGETS_3_OFFSET   8

Definition at line 2007 of file i3c_regs.h.

I3C_TARG_GROUP_4_GROUP_ADDR_4_FIELD

#define I3C_TARG_GROUP_4_GROUP_ADDR_4_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_4_GROUP_ADDR_4_MASK, .index = I3C_TARG_GROUP_4_GROUP_ADDR_4_OFFSET })

Definition at line 2016 of file i3c_regs.h.

I3C_TARG_GROUP_4_GROUP_ADDR_4_MASK

#define I3C_TARG_GROUP_4_GROUP_ADDR_4_MASK   0x7fu

Definition at line 2014 of file i3c_regs.h.

I3C_TARG_GROUP_4_GROUP_ADDR_4_OFFSET

#define I3C_TARG_GROUP_4_GROUP_ADDR_4_OFFSET   0

Definition at line 2015 of file i3c_regs.h.

I3C_TARG_GROUP_4_REG_OFFSET

#define I3C_TARG_GROUP_4_REG_OFFSET   0x37c

Definition at line 2012 of file i3c_regs.h.

I3C_TARG_GROUP_4_REG_RESVAL

#define I3C_TARG_GROUP_4_REG_RESVAL   0x0u

Definition at line 2013 of file i3c_regs.h.

I3C_TARG_GROUP_4_TARGETS_4_FIELD

#define I3C_TARG_GROUP_4_TARGETS_4_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_4_TARGETS_4_MASK, .index = I3C_TARG_GROUP_4_TARGETS_4_OFFSET })

Definition at line 2020 of file i3c_regs.h.

I3C_TARG_GROUP_4_TARGETS_4_MASK

#define I3C_TARG_GROUP_4_TARGETS_4_MASK   0xfu

Definition at line 2018 of file i3c_regs.h.

I3C_TARG_GROUP_4_TARGETS_4_OFFSET

#define I3C_TARG_GROUP_4_TARGETS_4_OFFSET   8

Definition at line 2019 of file i3c_regs.h.

I3C_TARG_GROUP_5_GROUP_ADDR_5_FIELD

#define I3C_TARG_GROUP_5_GROUP_ADDR_5_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_5_GROUP_ADDR_5_MASK, .index = I3C_TARG_GROUP_5_GROUP_ADDR_5_OFFSET })

Definition at line 2028 of file i3c_regs.h.

I3C_TARG_GROUP_5_GROUP_ADDR_5_MASK

#define I3C_TARG_GROUP_5_GROUP_ADDR_5_MASK   0x7fu

Definition at line 2026 of file i3c_regs.h.

I3C_TARG_GROUP_5_GROUP_ADDR_5_OFFSET

#define I3C_TARG_GROUP_5_GROUP_ADDR_5_OFFSET   0

Definition at line 2027 of file i3c_regs.h.

I3C_TARG_GROUP_5_REG_OFFSET

#define I3C_TARG_GROUP_5_REG_OFFSET   0x380

Definition at line 2024 of file i3c_regs.h.

I3C_TARG_GROUP_5_REG_RESVAL

#define I3C_TARG_GROUP_5_REG_RESVAL   0x0u

Definition at line 2025 of file i3c_regs.h.

I3C_TARG_GROUP_5_TARGETS_5_FIELD

#define I3C_TARG_GROUP_5_TARGETS_5_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_5_TARGETS_5_MASK, .index = I3C_TARG_GROUP_5_TARGETS_5_OFFSET })

Definition at line 2032 of file i3c_regs.h.

I3C_TARG_GROUP_5_TARGETS_5_MASK

#define I3C_TARG_GROUP_5_TARGETS_5_MASK   0xfu

Definition at line 2030 of file i3c_regs.h.

I3C_TARG_GROUP_5_TARGETS_5_OFFSET

#define I3C_TARG_GROUP_5_TARGETS_5_OFFSET   8

Definition at line 2031 of file i3c_regs.h.

I3C_TARG_GROUP_6_GROUP_ADDR_6_FIELD

#define I3C_TARG_GROUP_6_GROUP_ADDR_6_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_6_GROUP_ADDR_6_MASK, .index = I3C_TARG_GROUP_6_GROUP_ADDR_6_OFFSET })

Definition at line 2040 of file i3c_regs.h.

I3C_TARG_GROUP_6_GROUP_ADDR_6_MASK

#define I3C_TARG_GROUP_6_GROUP_ADDR_6_MASK   0x7fu

Definition at line 2038 of file i3c_regs.h.

I3C_TARG_GROUP_6_GROUP_ADDR_6_OFFSET

#define I3C_TARG_GROUP_6_GROUP_ADDR_6_OFFSET   0

Definition at line 2039 of file i3c_regs.h.

I3C_TARG_GROUP_6_REG_OFFSET

#define I3C_TARG_GROUP_6_REG_OFFSET   0x384

Definition at line 2036 of file i3c_regs.h.

I3C_TARG_GROUP_6_REG_RESVAL

#define I3C_TARG_GROUP_6_REG_RESVAL   0x0u

Definition at line 2037 of file i3c_regs.h.

I3C_TARG_GROUP_6_TARGETS_6_FIELD

#define I3C_TARG_GROUP_6_TARGETS_6_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_6_TARGETS_6_MASK, .index = I3C_TARG_GROUP_6_TARGETS_6_OFFSET })

Definition at line 2044 of file i3c_regs.h.

I3C_TARG_GROUP_6_TARGETS_6_MASK

#define I3C_TARG_GROUP_6_TARGETS_6_MASK   0xfu

Definition at line 2042 of file i3c_regs.h.

I3C_TARG_GROUP_6_TARGETS_6_OFFSET

#define I3C_TARG_GROUP_6_TARGETS_6_OFFSET   8

Definition at line 2043 of file i3c_regs.h.

I3C_TARG_GROUP_7_GROUP_ADDR_7_FIELD

#define I3C_TARG_GROUP_7_GROUP_ADDR_7_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_7_GROUP_ADDR_7_MASK, .index = I3C_TARG_GROUP_7_GROUP_ADDR_7_OFFSET })

Definition at line 2052 of file i3c_regs.h.

I3C_TARG_GROUP_7_GROUP_ADDR_7_MASK

#define I3C_TARG_GROUP_7_GROUP_ADDR_7_MASK   0x7fu

Definition at line 2050 of file i3c_regs.h.

I3C_TARG_GROUP_7_GROUP_ADDR_7_OFFSET

#define I3C_TARG_GROUP_7_GROUP_ADDR_7_OFFSET   0

Definition at line 2051 of file i3c_regs.h.

I3C_TARG_GROUP_7_REG_OFFSET

#define I3C_TARG_GROUP_7_REG_OFFSET   0x388

Definition at line 2048 of file i3c_regs.h.

I3C_TARG_GROUP_7_REG_RESVAL

#define I3C_TARG_GROUP_7_REG_RESVAL   0x0u

Definition at line 2049 of file i3c_regs.h.

I3C_TARG_GROUP_7_TARGETS_7_FIELD

#define I3C_TARG_GROUP_7_TARGETS_7_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_7_TARGETS_7_MASK, .index = I3C_TARG_GROUP_7_TARGETS_7_OFFSET })

Definition at line 2056 of file i3c_regs.h.

I3C_TARG_GROUP_7_TARGETS_7_MASK

#define I3C_TARG_GROUP_7_TARGETS_7_MASK   0xfu

Definition at line 2054 of file i3c_regs.h.

I3C_TARG_GROUP_7_TARGETS_7_OFFSET

#define I3C_TARG_GROUP_7_TARGETS_7_OFFSET   8

Definition at line 2055 of file i3c_regs.h.

I3C_TARG_GROUP_GROUP_ADDR_FIELD_WIDTH

#define I3C_TARG_GROUP_GROUP_ADDR_FIELD_WIDTH   7

Definition at line 1959 of file i3c_regs.h.

I3C_TARG_GROUP_MULTIREG_COUNT

#define I3C_TARG_GROUP_MULTIREG_COUNT   8

Definition at line 1961 of file i3c_regs.h.

I3C_TARG_GROUP_TARGETS_FIELD_WIDTH

#define I3C_TARG_GROUP_TARGETS_FIELD_WIDTH   4

Definition at line 1960 of file i3c_regs.h.

I3C_TARG_IBI_CONFIG_MAX_ADDR_FIELD

#define I3C_TARG_IBI_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_IBI_CONFIG_MAX_ADDR_OFFSET })

Definition at line 732 of file i3c_regs.h.

I3C_TARG_IBI_CONFIG_MAX_ADDR_MASK

#define I3C_TARG_IBI_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 730 of file i3c_regs.h.

I3C_TARG_IBI_CONFIG_MAX_ADDR_OFFSET

#define I3C_TARG_IBI_CONFIG_MAX_ADDR_OFFSET   16

Definition at line 731 of file i3c_regs.h.

I3C_TARG_IBI_CONFIG_MIN_ADDR_FIELD

#define I3C_TARG_IBI_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_IBI_CONFIG_MIN_ADDR_OFFSET })

Definition at line 728 of file i3c_regs.h.

I3C_TARG_IBI_CONFIG_MIN_ADDR_MASK

#define I3C_TARG_IBI_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 726 of file i3c_regs.h.

I3C_TARG_IBI_CONFIG_MIN_ADDR_OFFSET

#define I3C_TARG_IBI_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 727 of file i3c_regs.h.

I3C_TARG_IBI_CONFIG_REG_OFFSET

#define I3C_TARG_IBI_CONFIG_REG_OFFSET   0xcc

Definition at line 724 of file i3c_regs.h.

I3C_TARG_IBI_CONFIG_REG_RESVAL

#define I3C_TARG_IBI_CONFIG_REG_RESVAL   0x3af0370u

Definition at line 725 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_0_FIELD

#define I3C_TARG_IBI_LEN_IBI_LEN_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_0_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_0_OFFSET })

Definition at line 1877 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_0_MASK

#define I3C_TARG_IBI_LEN_IBI_LEN_0_MASK   0xffu

Definition at line 1875 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_0_OFFSET

#define I3C_TARG_IBI_LEN_IBI_LEN_0_OFFSET   0

Definition at line 1876 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_1_FIELD

#define I3C_TARG_IBI_LEN_IBI_LEN_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_1_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_1_OFFSET })

Definition at line 1881 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_1_MASK

#define I3C_TARG_IBI_LEN_IBI_LEN_1_MASK   0xffu

Definition at line 1879 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_1_OFFSET

#define I3C_TARG_IBI_LEN_IBI_LEN_1_OFFSET   8

Definition at line 1880 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_2_FIELD

#define I3C_TARG_IBI_LEN_IBI_LEN_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_2_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_2_OFFSET })

Definition at line 1885 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_2_MASK

#define I3C_TARG_IBI_LEN_IBI_LEN_2_MASK   0xffu

Definition at line 1883 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_2_OFFSET

#define I3C_TARG_IBI_LEN_IBI_LEN_2_OFFSET   16

Definition at line 1884 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_3_FIELD

#define I3C_TARG_IBI_LEN_IBI_LEN_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_3_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_3_OFFSET })

Definition at line 1889 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_3_MASK

#define I3C_TARG_IBI_LEN_IBI_LEN_3_MASK   0xffu

Definition at line 1887 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_3_OFFSET

#define I3C_TARG_IBI_LEN_IBI_LEN_3_OFFSET   24

Definition at line 1888 of file i3c_regs.h.

I3C_TARG_IBI_LEN_IBI_LEN_FIELD_WIDTH

#define I3C_TARG_IBI_LEN_IBI_LEN_FIELD_WIDTH   8

Definition at line 1869 of file i3c_regs.h.

I3C_TARG_IBI_LEN_MULTIREG_COUNT

#define I3C_TARG_IBI_LEN_MULTIREG_COUNT   1

Definition at line 1870 of file i3c_regs.h.

I3C_TARG_IBI_LEN_REG_OFFSET

#define I3C_TARG_IBI_LEN_REG_OFFSET   0x350

Definition at line 1873 of file i3c_regs.h.

I3C_TARG_IBI_LEN_REG_RESVAL

#define I3C_TARG_IBI_LEN_REG_RESVAL   0xffffffffu

Definition at line 1874 of file i3c_regs.h.

I3C_TARG_IBI_STATE_FULL_BIT

#define I3C_TARG_IBI_STATE_FULL_BIT   31

Definition at line 747 of file i3c_regs.h.

I3C_TARG_IBI_STATE_PRE_BIT

#define I3C_TARG_IBI_STATE_PRE_BIT   30

Definition at line 746 of file i3c_regs.h.

I3C_TARG_IBI_STATE_REG_OFFSET

#define I3C_TARG_IBI_STATE_REG_OFFSET   0xd0

Definition at line 736 of file i3c_regs.h.

I3C_TARG_IBI_STATE_REG_RESVAL

#define I3C_TARG_IBI_STATE_REG_RESVAL   0x3700370u

Definition at line 737 of file i3c_regs.h.

I3C_TARG_IBI_STATE_RPTR_FIELD

#define I3C_TARG_IBI_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_STATE_RPTR_MASK, .index = I3C_TARG_IBI_STATE_RPTR_OFFSET })

Definition at line 744 of file i3c_regs.h.

I3C_TARG_IBI_STATE_RPTR_MASK

#define I3C_TARG_IBI_STATE_RPTR_MASK   0x3ffu

Definition at line 742 of file i3c_regs.h.

I3C_TARG_IBI_STATE_RPTR_OFFSET

#define I3C_TARG_IBI_STATE_RPTR_OFFSET   16

Definition at line 743 of file i3c_regs.h.

I3C_TARG_IBI_STATE_WPTR_FIELD

#define I3C_TARG_IBI_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBI_STATE_WPTR_MASK, .index = I3C_TARG_IBI_STATE_WPTR_OFFSET })

Definition at line 740 of file i3c_regs.h.

I3C_TARG_IBI_STATE_WPTR_MASK

#define I3C_TARG_IBI_STATE_WPTR_MASK   0x3ffu

Definition at line 738 of file i3c_regs.h.

I3C_TARG_IBI_STATE_WPTR_OFFSET

#define I3C_TARG_IBI_STATE_WPTR_OFFSET   0

Definition at line 739 of file i3c_regs.h.

I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_FIELD

#define I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_OFFSET })

Definition at line 900 of file i3c_regs.h.

I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_MASK

#define I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 898 of file i3c_regs.h.

I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_OFFSET

#define I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_OFFSET   16

Definition at line 899 of file i3c_regs.h.

I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_FIELD

#define I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_OFFSET })

Definition at line 896 of file i3c_regs.h.

I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_MASK

#define I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 894 of file i3c_regs.h.

I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_OFFSET

#define I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 895 of file i3c_regs.h.

I3C_TARG_IBIDESC_CONFIG_REG_OFFSET

#define I3C_TARG_IBIDESC_CONFIG_REG_OFFSET   0xfc

Definition at line 892 of file i3c_regs.h.

I3C_TARG_IBIDESC_CONFIG_REG_RESVAL

#define I3C_TARG_IBIDESC_CONFIG_REG_RESVAL   0x3ef03e0u

Definition at line 893 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_FULL_BIT

#define I3C_TARG_IBIDESC_STATE_FULL_BIT   31

Definition at line 915 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_PRE_BIT

#define I3C_TARG_IBIDESC_STATE_PRE_BIT   30

Definition at line 914 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_REG_OFFSET

#define I3C_TARG_IBIDESC_STATE_REG_OFFSET   0x100

Definition at line 904 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_REG_RESVAL

#define I3C_TARG_IBIDESC_STATE_REG_RESVAL   0x3e003e0u

Definition at line 905 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_RPTR_FIELD

#define I3C_TARG_IBIDESC_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_STATE_RPTR_MASK, .index = I3C_TARG_IBIDESC_STATE_RPTR_OFFSET })

Definition at line 912 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_RPTR_MASK

#define I3C_TARG_IBIDESC_STATE_RPTR_MASK   0x3ffu

Definition at line 910 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_RPTR_OFFSET

#define I3C_TARG_IBIDESC_STATE_RPTR_OFFSET   16

Definition at line 911 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_WPTR_FIELD

#define I3C_TARG_IBIDESC_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_STATE_WPTR_MASK, .index = I3C_TARG_IBIDESC_STATE_WPTR_OFFSET })

Definition at line 908 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_WPTR_MASK

#define I3C_TARG_IBIDESC_STATE_WPTR_MASK   0x3ffu

Definition at line 906 of file i3c_regs.h.

I3C_TARG_IBIDESC_STATE_WPTR_OFFSET

#define I3C_TARG_IBIDESC_STATE_WPTR_OFFSET   0

Definition at line 907 of file i3c_regs.h.

I3C_TARG_INFO_0_AS_0_FIELD

#define I3C_TARG_INFO_0_AS_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_INFO_0_AS_0_MASK, .index = I3C_TARG_INFO_0_AS_0_OFFSET })

Definition at line 2436 of file i3c_regs.h.

I3C_TARG_INFO_0_AS_0_MASK

#define I3C_TARG_INFO_0_AS_0_MASK   0x3u

Definition at line 2434 of file i3c_regs.h.

I3C_TARG_INFO_0_AS_0_OFFSET

#define I3C_TARG_INFO_0_AS_0_OFFSET   0

Definition at line 2435 of file i3c_regs.h.

I3C_TARG_INFO_0_ENDXFER_CAND_CRC_EARLY_0_BIT

#define I3C_TARG_INFO_0_ENDXFER_CAND_CRC_EARLY_0_BIT   13

Definition at line 2443 of file i3c_regs.h.

I3C_TARG_INFO_0_ENDXFER_CAND_WR_EARLY_TERM_0_BIT

#define I3C_TARG_INFO_0_ENDXFER_CAND_WR_EARLY_TERM_0_BIT   12

Definition at line 2442 of file i3c_regs.h.

I3C_TARG_INFO_0_ENDXFER_CAND_WR_NACK_0_BIT

#define I3C_TARG_INFO_0_ENDXFER_CAND_WR_NACK_0_BIT   11

Definition at line 2441 of file i3c_regs.h.

I3C_TARG_INFO_0_ENDXFER_CRC_EARLY_0_BIT

#define I3C_TARG_INFO_0_ENDXFER_CRC_EARLY_0_BIT   5

Definition at line 2440 of file i3c_regs.h.

I3C_TARG_INFO_0_ENDXFER_WR_EARLY_TERM_0_BIT

#define I3C_TARG_INFO_0_ENDXFER_WR_EARLY_TERM_0_BIT   4

Definition at line 2439 of file i3c_regs.h.

I3C_TARG_INFO_0_ENDXFER_WR_NACK_0_BIT

#define I3C_TARG_INFO_0_ENDXFER_WR_NACK_0_BIT   3

Definition at line 2438 of file i3c_regs.h.

I3C_TARG_INFO_0_REG_OFFSET

#define I3C_TARG_INFO_0_REG_OFFSET   0x3ec

Definition at line 2432 of file i3c_regs.h.

I3C_TARG_INFO_0_REG_RESVAL

#define I3C_TARG_INFO_0_REG_RESVAL   0x2020u

Definition at line 2433 of file i3c_regs.h.

I3C_TARG_INFO_1_AS_1_FIELD

#define I3C_TARG_INFO_1_AS_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_INFO_1_AS_1_MASK, .index = I3C_TARG_INFO_1_AS_1_OFFSET })

Definition at line 2450 of file i3c_regs.h.

I3C_TARG_INFO_1_AS_1_MASK

#define I3C_TARG_INFO_1_AS_1_MASK   0x3u

Definition at line 2448 of file i3c_regs.h.

I3C_TARG_INFO_1_AS_1_OFFSET

#define I3C_TARG_INFO_1_AS_1_OFFSET   0

Definition at line 2449 of file i3c_regs.h.

I3C_TARG_INFO_1_ENDXFER_CAND_CRC_EARLY_1_BIT

#define I3C_TARG_INFO_1_ENDXFER_CAND_CRC_EARLY_1_BIT   13

Definition at line 2457 of file i3c_regs.h.

I3C_TARG_INFO_1_ENDXFER_CAND_WR_EARLY_TERM_1_BIT

#define I3C_TARG_INFO_1_ENDXFER_CAND_WR_EARLY_TERM_1_BIT   12

Definition at line 2456 of file i3c_regs.h.

I3C_TARG_INFO_1_ENDXFER_CAND_WR_NACK_1_BIT

#define I3C_TARG_INFO_1_ENDXFER_CAND_WR_NACK_1_BIT   11

Definition at line 2455 of file i3c_regs.h.

I3C_TARG_INFO_1_ENDXFER_CRC_EARLY_1_BIT

#define I3C_TARG_INFO_1_ENDXFER_CRC_EARLY_1_BIT   5

Definition at line 2454 of file i3c_regs.h.

I3C_TARG_INFO_1_ENDXFER_WR_EARLY_TERM_1_BIT

#define I3C_TARG_INFO_1_ENDXFER_WR_EARLY_TERM_1_BIT   4

Definition at line 2453 of file i3c_regs.h.

I3C_TARG_INFO_1_ENDXFER_WR_NACK_1_BIT

#define I3C_TARG_INFO_1_ENDXFER_WR_NACK_1_BIT   3

Definition at line 2452 of file i3c_regs.h.

I3C_TARG_INFO_1_REG_OFFSET

#define I3C_TARG_INFO_1_REG_OFFSET   0x3f0

Definition at line 2446 of file i3c_regs.h.

I3C_TARG_INFO_1_REG_RESVAL

#define I3C_TARG_INFO_1_REG_RESVAL   0x2020u

Definition at line 2447 of file i3c_regs.h.

I3C_TARG_INFO_2_AS_2_FIELD

#define I3C_TARG_INFO_2_AS_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_INFO_2_AS_2_MASK, .index = I3C_TARG_INFO_2_AS_2_OFFSET })

Definition at line 2464 of file i3c_regs.h.

I3C_TARG_INFO_2_AS_2_MASK

#define I3C_TARG_INFO_2_AS_2_MASK   0x3u

Definition at line 2462 of file i3c_regs.h.

I3C_TARG_INFO_2_AS_2_OFFSET

#define I3C_TARG_INFO_2_AS_2_OFFSET   0

Definition at line 2463 of file i3c_regs.h.

I3C_TARG_INFO_2_ENDXFER_CAND_CRC_EARLY_2_BIT

#define I3C_TARG_INFO_2_ENDXFER_CAND_CRC_EARLY_2_BIT   13

Definition at line 2471 of file i3c_regs.h.

I3C_TARG_INFO_2_ENDXFER_CAND_WR_EARLY_TERM_2_BIT

#define I3C_TARG_INFO_2_ENDXFER_CAND_WR_EARLY_TERM_2_BIT   12

Definition at line 2470 of file i3c_regs.h.

I3C_TARG_INFO_2_ENDXFER_CAND_WR_NACK_2_BIT

#define I3C_TARG_INFO_2_ENDXFER_CAND_WR_NACK_2_BIT   11

Definition at line 2469 of file i3c_regs.h.

I3C_TARG_INFO_2_ENDXFER_CRC_EARLY_2_BIT

#define I3C_TARG_INFO_2_ENDXFER_CRC_EARLY_2_BIT   5

Definition at line 2468 of file i3c_regs.h.

I3C_TARG_INFO_2_ENDXFER_WR_EARLY_TERM_2_BIT

#define I3C_TARG_INFO_2_ENDXFER_WR_EARLY_TERM_2_BIT   4

Definition at line 2467 of file i3c_regs.h.

I3C_TARG_INFO_2_ENDXFER_WR_NACK_2_BIT

#define I3C_TARG_INFO_2_ENDXFER_WR_NACK_2_BIT   3

Definition at line 2466 of file i3c_regs.h.

I3C_TARG_INFO_2_REG_OFFSET

#define I3C_TARG_INFO_2_REG_OFFSET   0x3f4

Definition at line 2460 of file i3c_regs.h.

I3C_TARG_INFO_2_REG_RESVAL

#define I3C_TARG_INFO_2_REG_RESVAL   0x2020u

Definition at line 2461 of file i3c_regs.h.

I3C_TARG_INFO_3_AS_3_FIELD

#define I3C_TARG_INFO_3_AS_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_INFO_3_AS_3_MASK, .index = I3C_TARG_INFO_3_AS_3_OFFSET })

Definition at line 2478 of file i3c_regs.h.

I3C_TARG_INFO_3_AS_3_MASK

#define I3C_TARG_INFO_3_AS_3_MASK   0x3u

Definition at line 2476 of file i3c_regs.h.

I3C_TARG_INFO_3_AS_3_OFFSET

#define I3C_TARG_INFO_3_AS_3_OFFSET   0

Definition at line 2477 of file i3c_regs.h.

I3C_TARG_INFO_3_ENDXFER_CAND_CRC_EARLY_3_BIT

#define I3C_TARG_INFO_3_ENDXFER_CAND_CRC_EARLY_3_BIT   13

Definition at line 2485 of file i3c_regs.h.

I3C_TARG_INFO_3_ENDXFER_CAND_WR_EARLY_TERM_3_BIT

#define I3C_TARG_INFO_3_ENDXFER_CAND_WR_EARLY_TERM_3_BIT   12

Definition at line 2484 of file i3c_regs.h.

I3C_TARG_INFO_3_ENDXFER_CAND_WR_NACK_3_BIT

#define I3C_TARG_INFO_3_ENDXFER_CAND_WR_NACK_3_BIT   11

Definition at line 2483 of file i3c_regs.h.

I3C_TARG_INFO_3_ENDXFER_CRC_EARLY_3_BIT

#define I3C_TARG_INFO_3_ENDXFER_CRC_EARLY_3_BIT   5

Definition at line 2482 of file i3c_regs.h.

I3C_TARG_INFO_3_ENDXFER_WR_EARLY_TERM_3_BIT

#define I3C_TARG_INFO_3_ENDXFER_WR_EARLY_TERM_3_BIT   4

Definition at line 2481 of file i3c_regs.h.

I3C_TARG_INFO_3_ENDXFER_WR_NACK_3_BIT

#define I3C_TARG_INFO_3_ENDXFER_WR_NACK_3_BIT   3

Definition at line 2480 of file i3c_regs.h.

I3C_TARG_INFO_3_REG_OFFSET

#define I3C_TARG_INFO_3_REG_OFFSET   0x3f8

Definition at line 2474 of file i3c_regs.h.

I3C_TARG_INFO_3_REG_RESVAL

#define I3C_TARG_INFO_3_REG_RESVAL   0x2020u

Definition at line 2475 of file i3c_regs.h.

I3C_TARG_INFO_AS_FIELD_WIDTH

#define I3C_TARG_INFO_AS_FIELD_WIDTH   2

Definition at line 2422 of file i3c_regs.h.

I3C_TARG_INFO_ENDXFER_CAND_CRC_EARLY_FIELD_WIDTH

#define I3C_TARG_INFO_ENDXFER_CAND_CRC_EARLY_FIELD_WIDTH   1

Definition at line 2428 of file i3c_regs.h.

I3C_TARG_INFO_ENDXFER_CAND_WR_EARLY_TERM_FIELD_WIDTH

#define I3C_TARG_INFO_ENDXFER_CAND_WR_EARLY_TERM_FIELD_WIDTH   1

Definition at line 2427 of file i3c_regs.h.

I3C_TARG_INFO_ENDXFER_CAND_WR_NACK_FIELD_WIDTH

#define I3C_TARG_INFO_ENDXFER_CAND_WR_NACK_FIELD_WIDTH   1

Definition at line 2426 of file i3c_regs.h.

I3C_TARG_INFO_ENDXFER_CRC_EARLY_FIELD_WIDTH

#define I3C_TARG_INFO_ENDXFER_CRC_EARLY_FIELD_WIDTH   1

Definition at line 2425 of file i3c_regs.h.

I3C_TARG_INFO_ENDXFER_WR_EARLY_TERM_FIELD_WIDTH

#define I3C_TARG_INFO_ENDXFER_WR_EARLY_TERM_FIELD_WIDTH   1

Definition at line 2424 of file i3c_regs.h.

I3C_TARG_INFO_ENDXFER_WR_NACK_FIELD_WIDTH

#define I3C_TARG_INFO_ENDXFER_WR_NACK_FIELD_WIDTH   1

Definition at line 2423 of file i3c_regs.h.

I3C_TARG_INFO_MULTIREG_COUNT

#define I3C_TARG_INFO_MULTIREG_COUNT   4

Definition at line 2429 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_ASYNC_EVT_OVF_FORCE_BIT

#define I3C_TARG_INTR_FORCE_ASYNC_EVT_OVF_FORCE_BIT   6

Definition at line 1693 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_ASYNC_EVT_READY_FORCE_BIT

#define I3C_TARG_INTR_FORCE_ASYNC_EVT_READY_FORCE_BIT   2

Definition at line 1689 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_IBI_THLD_FORCE_BIT

#define I3C_TARG_INTR_FORCE_IBI_THLD_FORCE_BIT   1

Definition at line 1688 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_REG_OFFSET

#define I3C_TARG_INTR_FORCE_REG_OFFSET   0x320

Definition at line 1685 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_REG_RESVAL

#define I3C_TARG_INTR_FORCE_REG_RESVAL   0x0u

Definition at line 1686 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_RX_BUFFER_OVF_FORCE_BIT

#define I3C_TARG_INTR_FORCE_RX_BUFFER_OVF_FORCE_BIT   5

Definition at line 1692 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_RX_DESC_READY_FORCE_BIT

#define I3C_TARG_INTR_FORCE_RX_DESC_READY_FORCE_BIT   0

Definition at line 1687 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TE_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TE_FORCE_BIT   31

Definition at line 1702 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TRANSFER_ABORT_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TRANSFER_ABORT_FORCE_BIT   3

Definition at line 1690 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TRANSFER_ERR_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TRANSFER_ERR_FORCE_BIT   4

Definition at line 1691 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TX0_DESC_READY_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TX0_DESC_READY_FORCE_BIT   16

Definition at line 1698 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TX0_THLD_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TX0_THLD_FORCE_BIT   8

Definition at line 1694 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TX1_DESC_READY_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TX1_DESC_READY_FORCE_BIT   17

Definition at line 1699 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TX1_THLD_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TX1_THLD_FORCE_BIT   9

Definition at line 1695 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TX2_DESC_READY_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TX2_DESC_READY_FORCE_BIT   18

Definition at line 1700 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TX2_THLD_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TX2_THLD_FORCE_BIT   10

Definition at line 1696 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TX3_DESC_READY_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TX3_DESC_READY_FORCE_BIT   19

Definition at line 1701 of file i3c_regs.h.

I3C_TARG_INTR_FORCE_TX3_THLD_FORCE_BIT

#define I3C_TARG_INTR_FORCE_TX3_THLD_FORCE_BIT   11

Definition at line 1697 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_ASYNC_EVT_OVF_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_ASYNC_EVT_OVF_SIGNAL_EN_BIT   6

Definition at line 1673 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_ASYNC_EVT_READY_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_ASYNC_EVT_READY_SIGNAL_EN_BIT   2

Definition at line 1669 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_IBI_STATUS_THLD_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_IBI_STATUS_THLD_SIGNAL_EN_BIT   1

Definition at line 1668 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_REG_OFFSET

#define I3C_TARG_INTR_SIGNAL_ENABLE_REG_OFFSET   0x31c

Definition at line 1665 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_REG_RESVAL

#define I3C_TARG_INTR_SIGNAL_ENABLE_REG_RESVAL   0x0u

Definition at line 1666 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_RX_BUFFER_OVF_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_RX_BUFFER_OVF_SIGNAL_EN_BIT   5

Definition at line 1672 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_RX_DESC_READY_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_RX_DESC_READY_SIGNAL_EN_BIT   0

Definition at line 1667 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TE_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TE_SIGNAL_EN_BIT   31

Definition at line 1682 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TRANSFER_ABORT_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TRANSFER_ABORT_SIGNAL_EN_BIT   3

Definition at line 1670 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TRANSFER_ERR_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TRANSFER_ERR_SIGNAL_EN_BIT   4

Definition at line 1671 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TX0_DESC_READY_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TX0_DESC_READY_SIGNAL_EN_BIT   16

Definition at line 1678 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TX0_THLD_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TX0_THLD_SIGNAL_EN_BIT   8

Definition at line 1674 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TX1_DESC_READY_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TX1_DESC_READY_SIGNAL_EN_BIT   17

Definition at line 1679 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TX1_THLD_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TX1_THLD_SIGNAL_EN_BIT   9

Definition at line 1675 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TX2_DESC_READY_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TX2_DESC_READY_SIGNAL_EN_BIT   18

Definition at line 1680 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TX2_THLD_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TX2_THLD_SIGNAL_EN_BIT   10

Definition at line 1676 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TX3_DESC_READY_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TX3_DESC_READY_SIGNAL_EN_BIT   19

Definition at line 1681 of file i3c_regs.h.

I3C_TARG_INTR_SIGNAL_ENABLE_TX3_THLD_SIGNAL_EN_BIT

#define I3C_TARG_INTR_SIGNAL_ENABLE_TX3_THLD_SIGNAL_EN_BIT   11

Definition at line 1677 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ASYNC_EVT_OVF_STAT_BIT

#define I3C_TARG_INTR_STATUS_ASYNC_EVT_OVF_STAT_BIT   6

Definition at line 1633 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ASYNC_EVT_READY_STAT_BIT

#define I3C_TARG_INTR_STATUS_ASYNC_EVT_READY_STAT_BIT   2

Definition at line 1629 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_ASYNC_EVT_OVF_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_ASYNC_EVT_OVF_STAT_EN_BIT   6

Definition at line 1653 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_ASYNC_EVT_READY_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_ASYNC_EVT_READY_STAT_EN_BIT   2

Definition at line 1649 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_IBI_STATUS_THLD_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_IBI_STATUS_THLD_STAT_EN_BIT   1

Definition at line 1648 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_REG_OFFSET

#define I3C_TARG_INTR_STATUS_ENABLE_REG_OFFSET   0x318

Definition at line 1645 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_REG_RESVAL

#define I3C_TARG_INTR_STATUS_ENABLE_REG_RESVAL   0x0u

Definition at line 1646 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_RX_BUFFER_OVF_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_RX_BUFFER_OVF_STAT_EN_BIT   5

Definition at line 1652 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_RX_DESC_READY_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_RX_DESC_READY_STAT_EN_BIT   0

Definition at line 1647 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TE_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TE_STAT_EN_BIT   31

Definition at line 1662 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TRANSFER_ABORT_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TRANSFER_ABORT_STAT_EN_BIT   3

Definition at line 1650 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TRANSFER_ERR_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TRANSFER_ERR_STAT_EN_BIT   4

Definition at line 1651 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TX0_DESC_READY_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TX0_DESC_READY_STAT_EN_BIT   16

Definition at line 1658 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TX0_THLD_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TX0_THLD_STAT_EN_BIT   8

Definition at line 1654 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TX1_DESC_READY_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TX1_DESC_READY_STAT_EN_BIT   17

Definition at line 1659 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TX1_THLD_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TX1_THLD_STAT_EN_BIT   9

Definition at line 1655 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TX2_DESC_READY_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TX2_DESC_READY_STAT_EN_BIT   18

Definition at line 1660 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TX2_THLD_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TX2_THLD_STAT_EN_BIT   10

Definition at line 1656 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TX3_DESC_READY_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TX3_DESC_READY_STAT_EN_BIT   19

Definition at line 1661 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_ENABLE_TX3_THLD_STAT_EN_BIT

#define I3C_TARG_INTR_STATUS_ENABLE_TX3_THLD_STAT_EN_BIT   11

Definition at line 1657 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_IBI_STATUS_THLD_STAT_BIT

#define I3C_TARG_INTR_STATUS_IBI_STATUS_THLD_STAT_BIT   1

Definition at line 1628 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_REG_OFFSET

#define I3C_TARG_INTR_STATUS_REG_OFFSET   0x314

Definition at line 1625 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_REG_RESVAL

#define I3C_TARG_INTR_STATUS_REG_RESVAL   0x0u

Definition at line 1626 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_RX_BUFFER_OVF_STAT_BIT

#define I3C_TARG_INTR_STATUS_RX_BUFFER_OVF_STAT_BIT   5

Definition at line 1632 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_RX_DESC_READY_STAT_BIT

#define I3C_TARG_INTR_STATUS_RX_DESC_READY_STAT_BIT   0

Definition at line 1627 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TE_STAT_BIT

#define I3C_TARG_INTR_STATUS_TE_STAT_BIT   31

Definition at line 1642 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TRANSFER_ABORT_STAT_BIT

#define I3C_TARG_INTR_STATUS_TRANSFER_ABORT_STAT_BIT   3

Definition at line 1630 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TRANSFER_ERR_STAT_BIT

#define I3C_TARG_INTR_STATUS_TRANSFER_ERR_STAT_BIT   4

Definition at line 1631 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TX0_DESC_READY_STAT_BIT

#define I3C_TARG_INTR_STATUS_TX0_DESC_READY_STAT_BIT   16

Definition at line 1638 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TX0_THLD_STAT_BIT

#define I3C_TARG_INTR_STATUS_TX0_THLD_STAT_BIT   8

Definition at line 1634 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TX1_DESC_READY_STAT_BIT

#define I3C_TARG_INTR_STATUS_TX1_DESC_READY_STAT_BIT   17

Definition at line 1639 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TX1_THLD_STAT_BIT

#define I3C_TARG_INTR_STATUS_TX1_THLD_STAT_BIT   9

Definition at line 1635 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TX2_DESC_READY_STAT_BIT

#define I3C_TARG_INTR_STATUS_TX2_DESC_READY_STAT_BIT   18

Definition at line 1640 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TX2_THLD_STAT_BIT

#define I3C_TARG_INTR_STATUS_TX2_THLD_STAT_BIT   10

Definition at line 1636 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TX3_DESC_READY_STAT_BIT

#define I3C_TARG_INTR_STATUS_TX3_DESC_READY_STAT_BIT   19

Definition at line 1641 of file i3c_regs.h.

I3C_TARG_INTR_STATUS_TX3_THLD_STAT_BIT

#define I3C_TARG_INTR_STATUS_TX3_THLD_STAT_BIT   11

Definition at line 1637 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_MAXRD_0_FIELD

#define I3C_TARG_MAX_RDWR_0_MAXRD_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_MAXRD_0_MASK, .index = I3C_TARG_MAX_RDWR_0_MAXRD_0_OFFSET })

Definition at line 2499 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_MAXRD_0_MASK

#define I3C_TARG_MAX_RDWR_0_MAXRD_0_MASK   0x7fu

Definition at line 2497 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_MAXRD_0_OFFSET

#define I3C_TARG_MAX_RDWR_0_MAXRD_0_OFFSET   0

Definition at line 2498 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_MAXWR_0_FIELD

#define I3C_TARG_MAX_RDWR_0_MAXWR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_MAXWR_0_MASK, .index = I3C_TARG_MAX_RDWR_0_MAXWR_0_OFFSET })

Definition at line 2503 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_MAXWR_0_MASK

#define I3C_TARG_MAX_RDWR_0_MAXWR_0_MASK   0xffu

Definition at line 2501 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_MAXWR_0_OFFSET

#define I3C_TARG_MAX_RDWR_0_MAXWR_0_OFFSET   8

Definition at line 2502 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_FIELD

#define I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_MASK, .index = I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_OFFSET })

Definition at line 2511 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_MASK

#define I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_MASK   0xfu

Definition at line 2509 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_OFFSET

#define I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_OFFSET   28

Definition at line 2510 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_FIELD

#define I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_MASK, .index = I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_OFFSET })

Definition at line 2507 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_MASK

#define I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_MASK   0xfffu

Definition at line 2505 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_OFFSET

#define I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_OFFSET   16

Definition at line 2506 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_REG_OFFSET

#define I3C_TARG_MAX_RDWR_0_REG_OFFSET   0x3fc

Definition at line 2495 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_0_REG_RESVAL

#define I3C_TARG_MAX_RDWR_0_REG_RESVAL   0x10000u

Definition at line 2496 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_MAXRD_1_FIELD

#define I3C_TARG_MAX_RDWR_1_MAXRD_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_MAXRD_1_MASK, .index = I3C_TARG_MAX_RDWR_1_MAXRD_1_OFFSET })

Definition at line 2519 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_MAXRD_1_MASK

#define I3C_TARG_MAX_RDWR_1_MAXRD_1_MASK   0x7fu

Definition at line 2517 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_MAXRD_1_OFFSET

#define I3C_TARG_MAX_RDWR_1_MAXRD_1_OFFSET   0

Definition at line 2518 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_MAXWR_1_FIELD

#define I3C_TARG_MAX_RDWR_1_MAXWR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_MAXWR_1_MASK, .index = I3C_TARG_MAX_RDWR_1_MAXWR_1_OFFSET })

Definition at line 2523 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_MAXWR_1_MASK

#define I3C_TARG_MAX_RDWR_1_MAXWR_1_MASK   0xffu

Definition at line 2521 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_MAXWR_1_OFFSET

#define I3C_TARG_MAX_RDWR_1_MAXWR_1_OFFSET   8

Definition at line 2522 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_FIELD

#define I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_MASK, .index = I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_OFFSET })

Definition at line 2531 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_MASK

#define I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_MASK   0xfu

Definition at line 2529 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_OFFSET

#define I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_OFFSET   28

Definition at line 2530 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_FIELD

#define I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_MASK, .index = I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_OFFSET })

Definition at line 2527 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_MASK

#define I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_MASK   0xfffu

Definition at line 2525 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_OFFSET

#define I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_OFFSET   16

Definition at line 2526 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_REG_OFFSET

#define I3C_TARG_MAX_RDWR_1_REG_OFFSET   0x400

Definition at line 2515 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_1_REG_RESVAL

#define I3C_TARG_MAX_RDWR_1_REG_RESVAL   0x10000u

Definition at line 2516 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_MAXRD_2_FIELD

#define I3C_TARG_MAX_RDWR_2_MAXRD_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_MAXRD_2_MASK, .index = I3C_TARG_MAX_RDWR_2_MAXRD_2_OFFSET })

Definition at line 2539 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_MAXRD_2_MASK

#define I3C_TARG_MAX_RDWR_2_MAXRD_2_MASK   0x7fu

Definition at line 2537 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_MAXRD_2_OFFSET

#define I3C_TARG_MAX_RDWR_2_MAXRD_2_OFFSET   0

Definition at line 2538 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_MAXWR_2_FIELD

#define I3C_TARG_MAX_RDWR_2_MAXWR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_MAXWR_2_MASK, .index = I3C_TARG_MAX_RDWR_2_MAXWR_2_OFFSET })

Definition at line 2543 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_MAXWR_2_MASK

#define I3C_TARG_MAX_RDWR_2_MAXWR_2_MASK   0xffu

Definition at line 2541 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_MAXWR_2_OFFSET

#define I3C_TARG_MAX_RDWR_2_MAXWR_2_OFFSET   8

Definition at line 2542 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_FIELD

#define I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_MASK, .index = I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_OFFSET })

Definition at line 2551 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_MASK

#define I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_MASK   0xfu

Definition at line 2549 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_OFFSET

#define I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_OFFSET   28

Definition at line 2550 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_FIELD

#define I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_MASK, .index = I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_OFFSET })

Definition at line 2547 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_MASK

#define I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_MASK   0xfffu

Definition at line 2545 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_OFFSET

#define I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_OFFSET   16

Definition at line 2546 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_REG_OFFSET

#define I3C_TARG_MAX_RDWR_2_REG_OFFSET   0x404

Definition at line 2535 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_2_REG_RESVAL

#define I3C_TARG_MAX_RDWR_2_REG_RESVAL   0x10000u

Definition at line 2536 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_MAXRD_3_FIELD

#define I3C_TARG_MAX_RDWR_3_MAXRD_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_MAXRD_3_MASK, .index = I3C_TARG_MAX_RDWR_3_MAXRD_3_OFFSET })

Definition at line 2559 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_MAXRD_3_MASK

#define I3C_TARG_MAX_RDWR_3_MAXRD_3_MASK   0x7fu

Definition at line 2557 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_MAXRD_3_OFFSET

#define I3C_TARG_MAX_RDWR_3_MAXRD_3_OFFSET   0

Definition at line 2558 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_MAXWR_3_FIELD

#define I3C_TARG_MAX_RDWR_3_MAXWR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_MAXWR_3_MASK, .index = I3C_TARG_MAX_RDWR_3_MAXWR_3_OFFSET })

Definition at line 2563 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_MAXWR_3_MASK

#define I3C_TARG_MAX_RDWR_3_MAXWR_3_MASK   0xffu

Definition at line 2561 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_MAXWR_3_OFFSET

#define I3C_TARG_MAX_RDWR_3_MAXWR_3_OFFSET   8

Definition at line 2562 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_FIELD

#define I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_MASK, .index = I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_OFFSET })

Definition at line 2571 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_MASK

#define I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_MASK   0xfu

Definition at line 2569 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_OFFSET

#define I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_OFFSET   28

Definition at line 2570 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_FIELD

#define I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_MASK, .index = I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_OFFSET })

Definition at line 2567 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_MASK

#define I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_MASK   0xfffu

Definition at line 2565 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_OFFSET

#define I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_OFFSET   16

Definition at line 2566 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_REG_OFFSET

#define I3C_TARG_MAX_RDWR_3_REG_OFFSET   0x408

Definition at line 2555 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_3_REG_RESVAL

#define I3C_TARG_MAX_RDWR_3_REG_RESVAL   0x10000u

Definition at line 2556 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_MAXRD_FIELD_WIDTH

#define I3C_TARG_MAX_RDWR_MAXRD_FIELD_WIDTH   7

Definition at line 2488 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_MAXWR_FIELD_WIDTH

#define I3C_TARG_MAX_RDWR_MAXWR_FIELD_WIDTH   8

Definition at line 2489 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_MULTIREG_COUNT

#define I3C_TARG_MAX_RDWR_MULTIREG_COUNT   4

Definition at line 2492 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_RDTURN_SCALE_FIELD_WIDTH

#define I3C_TARG_MAX_RDWR_RDTURN_SCALE_FIELD_WIDTH   4

Definition at line 2491 of file i3c_regs.h.

I3C_TARG_MAX_RDWR_RDTURN_VAL_FIELD_WIDTH

#define I3C_TARG_MAX_RDWR_RDTURN_VAL_FIELD_WIDTH   12

Definition at line 2490 of file i3c_regs.h.

I3C_TARG_PID_LO_0_REG_OFFSET

#define I3C_TARG_PID_LO_0_REG_OFFSET   0x3cc

Definition at line 2321 of file i3c_regs.h.

I3C_TARG_PID_LO_0_REG_RESVAL

#define I3C_TARG_PID_LO_0_REG_RESVAL   0x0u

Definition at line 2322 of file i3c_regs.h.

I3C_TARG_PID_LO_1_REG_OFFSET

#define I3C_TARG_PID_LO_1_REG_OFFSET   0x3d0

Definition at line 2325 of file i3c_regs.h.

I3C_TARG_PID_LO_1_REG_RESVAL

#define I3C_TARG_PID_LO_1_REG_RESVAL   0x0u

Definition at line 2326 of file i3c_regs.h.

I3C_TARG_PID_LO_2_REG_OFFSET

#define I3C_TARG_PID_LO_2_REG_OFFSET   0x3d4

Definition at line 2329 of file i3c_regs.h.

I3C_TARG_PID_LO_2_REG_RESVAL

#define I3C_TARG_PID_LO_2_REG_RESVAL   0x0u

Definition at line 2330 of file i3c_regs.h.

I3C_TARG_PID_LO_3_REG_OFFSET

#define I3C_TARG_PID_LO_3_REG_OFFSET   0x3d8

Definition at line 2333 of file i3c_regs.h.

I3C_TARG_PID_LO_3_REG_RESVAL

#define I3C_TARG_PID_LO_3_REG_RESVAL   0x0u

Definition at line 2334 of file i3c_regs.h.

I3C_TARG_PID_LO_MULTIREG_COUNT

#define I3C_TARG_PID_LO_MULTIREG_COUNT   4

Definition at line 2318 of file i3c_regs.h.

I3C_TARG_PID_LO_PID_LO_FIELD_WIDTH

#define I3C_TARG_PID_LO_PID_LO_FIELD_WIDTH   32

Definition at line 2317 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_ABORT_FIELD

#define I3C_TARG_PIO_CONTROL_ABORT_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_PIO_CONTROL_ABORT_MASK, .index = I3C_TARG_PIO_CONTROL_ABORT_OFFSET })

Definition at line 1715 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_ABORT_MASK

#define I3C_TARG_PIO_CONTROL_ABORT_MASK   0xfu

Definition at line 1713 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_ABORT_OFFSET

#define I3C_TARG_PIO_CONTROL_ABORT_OFFSET   24

Definition at line 1714 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_IBI_ABORT_BIT

#define I3C_TARG_PIO_CONTROL_IBI_ABORT_BIT   1

Definition at line 1708 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_IBI_SUSPENDED_BIT

#define I3C_TARG_PIO_CONTROL_IBI_SUSPENDED_BIT   0

Definition at line 1707 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_REG_OFFSET

#define I3C_TARG_PIO_CONTROL_REG_OFFSET   0x324

Definition at line 1705 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_REG_RESVAL

#define I3C_TARG_PIO_CONTROL_REG_RESVAL   0x0u

Definition at line 1706 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_SUSPENDED_FIELD

#define I3C_TARG_PIO_CONTROL_SUSPENDED_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_PIO_CONTROL_SUSPENDED_MASK, .index = I3C_TARG_PIO_CONTROL_SUSPENDED_OFFSET })

Definition at line 1711 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_SUSPENDED_MASK

#define I3C_TARG_PIO_CONTROL_SUSPENDED_MASK   0xfu

Definition at line 1709 of file i3c_regs.h.

I3C_TARG_PIO_CONTROL_SUSPENDED_OFFSET

#define I3C_TARG_PIO_CONTROL_SUSPENDED_OFFSET   16

Definition at line 1710 of file i3c_regs.h.

I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_FIELD

#define I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_MASK, .index = I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_OFFSET })

Definition at line 1788 of file i3c_regs.h.

I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_MASK

#define I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_MASK   0xfffu

Definition at line 1786 of file i3c_regs.h.

I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_OFFSET

#define I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_OFFSET   16

Definition at line 1787 of file i3c_regs.h.

I3C_TARG_QUEUE_STATUS_LEVEL_REG_OFFSET

#define I3C_TARG_QUEUE_STATUS_LEVEL_REG_OFFSET   0x334

Definition at line 1780 of file i3c_regs.h.

I3C_TARG_QUEUE_STATUS_LEVEL_REG_RESVAL

#define I3C_TARG_QUEUE_STATUS_LEVEL_REG_RESVAL   0x0u

Definition at line 1781 of file i3c_regs.h.

I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_FIELD

#define I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_MASK, .index = I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_OFFSET })

Definition at line 1784 of file i3c_regs.h.

I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_MASK

#define I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_MASK   0xffu

Definition at line 1782 of file i3c_regs.h.

I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_OFFSET

#define I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_OFFSET   0

Definition at line 1783 of file i3c_regs.h.

I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_FIELD

#define I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK, .index = I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET })

Definition at line 1776 of file i3c_regs.h.

I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK

#define I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK   0xffu

Definition at line 1774 of file i3c_regs.h.

I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET

#define I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET   24

Definition at line 1775 of file i3c_regs.h.

I3C_TARG_QUEUE_THLD_CTRL_REG_OFFSET

#define I3C_TARG_QUEUE_THLD_CTRL_REG_OFFSET   0x330

Definition at line 1768 of file i3c_regs.h.

I3C_TARG_QUEUE_THLD_CTRL_REG_RESVAL

#define I3C_TARG_QUEUE_THLD_CTRL_REG_RESVAL   0x1000100u

Definition at line 1769 of file i3c_regs.h.

I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_FIELD

#define I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_MASK, .index = I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_OFFSET })

Definition at line 1772 of file i3c_regs.h.

I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_MASK

#define I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_MASK   0xffu

Definition at line 1770 of file i3c_regs.h.

I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_OFFSET

#define I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_OFFSET   8

Definition at line 1771 of file i3c_regs.h.

I3C_TARG_RW_LEN_0_MRL_0_FIELD

#define I3C_TARG_RW_LEN_0_MRL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_0_MRL_0_MASK, .index = I3C_TARG_RW_LEN_0_MRL_0_OFFSET })

Definition at line 1825 of file i3c_regs.h.

I3C_TARG_RW_LEN_0_MRL_0_MASK

#define I3C_TARG_RW_LEN_0_MRL_0_MASK   0xffffu

Definition at line 1823 of file i3c_regs.h.

I3C_TARG_RW_LEN_0_MRL_0_OFFSET

#define I3C_TARG_RW_LEN_0_MRL_0_OFFSET   0

Definition at line 1824 of file i3c_regs.h.

I3C_TARG_RW_LEN_0_MWL_0_FIELD

#define I3C_TARG_RW_LEN_0_MWL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_0_MWL_0_MASK, .index = I3C_TARG_RW_LEN_0_MWL_0_OFFSET })

Definition at line 1829 of file i3c_regs.h.

I3C_TARG_RW_LEN_0_MWL_0_MASK

#define I3C_TARG_RW_LEN_0_MWL_0_MASK   0xffffu

Definition at line 1827 of file i3c_regs.h.

I3C_TARG_RW_LEN_0_MWL_0_OFFSET

#define I3C_TARG_RW_LEN_0_MWL_0_OFFSET   16

Definition at line 1828 of file i3c_regs.h.

I3C_TARG_RW_LEN_0_REG_OFFSET

#define I3C_TARG_RW_LEN_0_REG_OFFSET   0x340

Definition at line 1821 of file i3c_regs.h.

I3C_TARG_RW_LEN_0_REG_RESVAL

#define I3C_TARG_RW_LEN_0_REG_RESVAL   0xffffffffu

Definition at line 1822 of file i3c_regs.h.

I3C_TARG_RW_LEN_1_MRL_1_FIELD

#define I3C_TARG_RW_LEN_1_MRL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_1_MRL_1_MASK, .index = I3C_TARG_RW_LEN_1_MRL_1_OFFSET })

Definition at line 1837 of file i3c_regs.h.

I3C_TARG_RW_LEN_1_MRL_1_MASK

#define I3C_TARG_RW_LEN_1_MRL_1_MASK   0xffffu

Definition at line 1835 of file i3c_regs.h.

I3C_TARG_RW_LEN_1_MRL_1_OFFSET

#define I3C_TARG_RW_LEN_1_MRL_1_OFFSET   0

Definition at line 1836 of file i3c_regs.h.

I3C_TARG_RW_LEN_1_MWL_1_FIELD

#define I3C_TARG_RW_LEN_1_MWL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_1_MWL_1_MASK, .index = I3C_TARG_RW_LEN_1_MWL_1_OFFSET })

Definition at line 1841 of file i3c_regs.h.

I3C_TARG_RW_LEN_1_MWL_1_MASK

#define I3C_TARG_RW_LEN_1_MWL_1_MASK   0xffffu

Definition at line 1839 of file i3c_regs.h.

I3C_TARG_RW_LEN_1_MWL_1_OFFSET

#define I3C_TARG_RW_LEN_1_MWL_1_OFFSET   16

Definition at line 1840 of file i3c_regs.h.

I3C_TARG_RW_LEN_1_REG_OFFSET

#define I3C_TARG_RW_LEN_1_REG_OFFSET   0x344

Definition at line 1833 of file i3c_regs.h.

I3C_TARG_RW_LEN_1_REG_RESVAL

#define I3C_TARG_RW_LEN_1_REG_RESVAL   0xffffffffu

Definition at line 1834 of file i3c_regs.h.

I3C_TARG_RW_LEN_2_MRL_2_FIELD

#define I3C_TARG_RW_LEN_2_MRL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_2_MRL_2_MASK, .index = I3C_TARG_RW_LEN_2_MRL_2_OFFSET })

Definition at line 1849 of file i3c_regs.h.

I3C_TARG_RW_LEN_2_MRL_2_MASK

#define I3C_TARG_RW_LEN_2_MRL_2_MASK   0xffffu

Definition at line 1847 of file i3c_regs.h.

I3C_TARG_RW_LEN_2_MRL_2_OFFSET

#define I3C_TARG_RW_LEN_2_MRL_2_OFFSET   0

Definition at line 1848 of file i3c_regs.h.

I3C_TARG_RW_LEN_2_MWL_2_FIELD

#define I3C_TARG_RW_LEN_2_MWL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_2_MWL_2_MASK, .index = I3C_TARG_RW_LEN_2_MWL_2_OFFSET })

Definition at line 1853 of file i3c_regs.h.

I3C_TARG_RW_LEN_2_MWL_2_MASK

#define I3C_TARG_RW_LEN_2_MWL_2_MASK   0xffffu

Definition at line 1851 of file i3c_regs.h.

I3C_TARG_RW_LEN_2_MWL_2_OFFSET

#define I3C_TARG_RW_LEN_2_MWL_2_OFFSET   16

Definition at line 1852 of file i3c_regs.h.

I3C_TARG_RW_LEN_2_REG_OFFSET

#define I3C_TARG_RW_LEN_2_REG_OFFSET   0x348

Definition at line 1845 of file i3c_regs.h.

I3C_TARG_RW_LEN_2_REG_RESVAL

#define I3C_TARG_RW_LEN_2_REG_RESVAL   0xffffffffu

Definition at line 1846 of file i3c_regs.h.

I3C_TARG_RW_LEN_3_MRL_3_FIELD

#define I3C_TARG_RW_LEN_3_MRL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_3_MRL_3_MASK, .index = I3C_TARG_RW_LEN_3_MRL_3_OFFSET })

Definition at line 1861 of file i3c_regs.h.

I3C_TARG_RW_LEN_3_MRL_3_MASK

#define I3C_TARG_RW_LEN_3_MRL_3_MASK   0xffffu

Definition at line 1859 of file i3c_regs.h.

I3C_TARG_RW_LEN_3_MRL_3_OFFSET

#define I3C_TARG_RW_LEN_3_MRL_3_OFFSET   0

Definition at line 1860 of file i3c_regs.h.

I3C_TARG_RW_LEN_3_MWL_3_FIELD

#define I3C_TARG_RW_LEN_3_MWL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_3_MWL_3_MASK, .index = I3C_TARG_RW_LEN_3_MWL_3_OFFSET })

Definition at line 1865 of file i3c_regs.h.

I3C_TARG_RW_LEN_3_MWL_3_MASK

#define I3C_TARG_RW_LEN_3_MWL_3_MASK   0xffffu

Definition at line 1863 of file i3c_regs.h.

I3C_TARG_RW_LEN_3_MWL_3_OFFSET

#define I3C_TARG_RW_LEN_3_MWL_3_OFFSET   16

Definition at line 1864 of file i3c_regs.h.

I3C_TARG_RW_LEN_3_REG_OFFSET

#define I3C_TARG_RW_LEN_3_REG_OFFSET   0x34c

Definition at line 1857 of file i3c_regs.h.

I3C_TARG_RW_LEN_3_REG_RESVAL

#define I3C_TARG_RW_LEN_3_REG_RESVAL   0xffffffffu

Definition at line 1858 of file i3c_regs.h.

I3C_TARG_RW_LEN_MRL_FIELD_WIDTH

#define I3C_TARG_RW_LEN_MRL_FIELD_WIDTH   16

Definition at line 1816 of file i3c_regs.h.

I3C_TARG_RW_LEN_MULTIREG_COUNT

#define I3C_TARG_RW_LEN_MULTIREG_COUNT   4

Definition at line 1818 of file i3c_regs.h.

I3C_TARG_RW_LEN_MWL_FIELD_WIDTH

#define I3C_TARG_RW_LEN_MWL_FIELD_WIDTH   16

Definition at line 1817 of file i3c_regs.h.

I3C_TARG_RXBUF_CONFIG_MAX_ADDR_FIELD

#define I3C_TARG_RXBUF_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_RXBUF_CONFIG_MAX_ADDR_OFFSET })

Definition at line 706 of file i3c_regs.h.

I3C_TARG_RXBUF_CONFIG_MAX_ADDR_MASK

#define I3C_TARG_RXBUF_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 704 of file i3c_regs.h.

I3C_TARG_RXBUF_CONFIG_MAX_ADDR_OFFSET

#define I3C_TARG_RXBUF_CONFIG_MAX_ADDR_OFFSET   16

Definition at line 705 of file i3c_regs.h.

I3C_TARG_RXBUF_CONFIG_MIN_ADDR_FIELD

#define I3C_TARG_RXBUF_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_RXBUF_CONFIG_MIN_ADDR_OFFSET })

Definition at line 702 of file i3c_regs.h.

I3C_TARG_RXBUF_CONFIG_MIN_ADDR_MASK

#define I3C_TARG_RXBUF_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 700 of file i3c_regs.h.

I3C_TARG_RXBUF_CONFIG_MIN_ADDR_OFFSET

#define I3C_TARG_RXBUF_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 701 of file i3c_regs.h.

I3C_TARG_RXBUF_CONFIG_REG_OFFSET

#define I3C_TARG_RXBUF_CONFIG_REG_OFFSET   0xc4

Definition at line 698 of file i3c_regs.h.

I3C_TARG_RXBUF_CONFIG_REG_RESVAL

#define I3C_TARG_RXBUF_CONFIG_REG_RESVAL   0x36f02d0u

Definition at line 699 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_FULL_BIT

#define I3C_TARG_RXBUF_STATE_FULL_BIT   31

Definition at line 721 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_PRE_BIT

#define I3C_TARG_RXBUF_STATE_PRE_BIT   30

Definition at line 720 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_REG_OFFSET

#define I3C_TARG_RXBUF_STATE_REG_OFFSET   0xc8

Definition at line 710 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_REG_RESVAL

#define I3C_TARG_RXBUF_STATE_REG_RESVAL   0x2d002d0u

Definition at line 711 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_RPTR_FIELD

#define I3C_TARG_RXBUF_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_STATE_RPTR_MASK, .index = I3C_TARG_RXBUF_STATE_RPTR_OFFSET })

Definition at line 718 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_RPTR_MASK

#define I3C_TARG_RXBUF_STATE_RPTR_MASK   0x3ffu

Definition at line 716 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_RPTR_OFFSET

#define I3C_TARG_RXBUF_STATE_RPTR_OFFSET   16

Definition at line 717 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_WPTR_FIELD

#define I3C_TARG_RXBUF_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_STATE_WPTR_MASK, .index = I3C_TARG_RXBUF_STATE_WPTR_OFFSET })

Definition at line 714 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_WPTR_MASK

#define I3C_TARG_RXBUF_STATE_WPTR_MASK   0x3ffu

Definition at line 712 of file i3c_regs.h.

I3C_TARG_RXBUF_STATE_WPTR_OFFSET

#define I3C_TARG_RXBUF_STATE_WPTR_OFFSET   0

Definition at line 713 of file i3c_regs.h.

I3C_TARG_RXDESC_CONFIG_MAX_ADDR_FIELD

#define I3C_TARG_RXDESC_CONFIG_MAX_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_RXDESC_CONFIG_MAX_ADDR_OFFSET })

Definition at line 874 of file i3c_regs.h.

I3C_TARG_RXDESC_CONFIG_MAX_ADDR_MASK

#define I3C_TARG_RXDESC_CONFIG_MAX_ADDR_MASK   0x3ffu

Definition at line 872 of file i3c_regs.h.

I3C_TARG_RXDESC_CONFIG_MAX_ADDR_OFFSET

#define I3C_TARG_RXDESC_CONFIG_MAX_ADDR_OFFSET   16

Definition at line 873 of file i3c_regs.h.

I3C_TARG_RXDESC_CONFIG_MIN_ADDR_FIELD

#define I3C_TARG_RXDESC_CONFIG_MIN_ADDR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_RXDESC_CONFIG_MIN_ADDR_OFFSET })

Definition at line 870 of file i3c_regs.h.

I3C_TARG_RXDESC_CONFIG_MIN_ADDR_MASK

#define I3C_TARG_RXDESC_CONFIG_MIN_ADDR_MASK   0x3ffu

Definition at line 868 of file i3c_regs.h.

I3C_TARG_RXDESC_CONFIG_MIN_ADDR_OFFSET

#define I3C_TARG_RXDESC_CONFIG_MIN_ADDR_OFFSET   0

Definition at line 869 of file i3c_regs.h.

I3C_TARG_RXDESC_CONFIG_REG_OFFSET

#define I3C_TARG_RXDESC_CONFIG_REG_OFFSET   0xf4

Definition at line 866 of file i3c_regs.h.

I3C_TARG_RXDESC_CONFIG_REG_RESVAL

#define I3C_TARG_RXDESC_CONFIG_REG_RESVAL   0x3df03d0u

Definition at line 867 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_FULL_BIT

#define I3C_TARG_RXDESC_STATE_FULL_BIT   31

Definition at line 889 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_PRE_BIT

#define I3C_TARG_RXDESC_STATE_PRE_BIT   30

Definition at line 888 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_REG_OFFSET

#define I3C_TARG_RXDESC_STATE_REG_OFFSET   0xf8

Definition at line 878 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_REG_RESVAL

#define I3C_TARG_RXDESC_STATE_REG_RESVAL   0x3d003d0u

Definition at line 879 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_RPTR_FIELD

#define I3C_TARG_RXDESC_STATE_RPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_STATE_RPTR_MASK, .index = I3C_TARG_RXDESC_STATE_RPTR_OFFSET })

Definition at line 886 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_RPTR_MASK

#define I3C_TARG_RXDESC_STATE_RPTR_MASK   0x3ffu

Definition at line 884 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_RPTR_OFFSET

#define I3C_TARG_RXDESC_STATE_RPTR_OFFSET   16

Definition at line 885 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_WPTR_FIELD

#define I3C_TARG_RXDESC_STATE_WPTR_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_STATE_WPTR_MASK, .index = I3C_TARG_RXDESC_STATE_WPTR_OFFSET })

Definition at line 882 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_WPTR_MASK

#define I3C_TARG_RXDESC_STATE_WPTR_MASK   0x3ffu

Definition at line 880 of file i3c_regs.h.

I3C_TARG_RXDESC_STATE_WPTR_OFFSET

#define I3C_TARG_RXDESC_STATE_WPTR_OFFSET   0

Definition at line 881 of file i3c_regs.h.

I3C_TARG_SINK_CONTROL_BUFFER_FIELD

#define I3C_TARG_SINK_CONTROL_BUFFER_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_SINK_CONTROL_BUFFER_MASK, .index = I3C_TARG_SINK_CONTROL_BUFFER_OFFSET })

Definition at line 161 of file i3c_regs.h.

I3C_TARG_SINK_CONTROL_BUFFER_MASK

#define I3C_TARG_SINK_CONTROL_BUFFER_MASK   0x7u

Definition at line 159 of file i3c_regs.h.

I3C_TARG_SINK_CONTROL_BUFFER_OFFSET

#define I3C_TARG_SINK_CONTROL_BUFFER_OFFSET   12

Definition at line 160 of file i3c_regs.h.

I3C_TARG_SINK_CONTROL_LENGTH_FIELD

#define I3C_TARG_SINK_CONTROL_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_SINK_CONTROL_LENGTH_MASK, .index = I3C_TARG_SINK_CONTROL_LENGTH_OFFSET })

Definition at line 165 of file i3c_regs.h.

I3C_TARG_SINK_CONTROL_LENGTH_MASK

#define I3C_TARG_SINK_CONTROL_LENGTH_MASK   0x7ffu

Definition at line 163 of file i3c_regs.h.

I3C_TARG_SINK_CONTROL_LENGTH_OFFSET

#define I3C_TARG_SINK_CONTROL_LENGTH_OFFSET   16

Definition at line 164 of file i3c_regs.h.

I3C_TARG_SINK_CONTROL_REG_OFFSET

#define I3C_TARG_SINK_CONTROL_REG_OFFSET   0x24

Definition at line 157 of file i3c_regs.h.

I3C_TARG_SINK_CONTROL_REG_RESVAL

#define I3C_TARG_SINK_CONTROL_REG_RESVAL   0x0u

Definition at line 158 of file i3c_regs.h.

I3C_TARG_SINK_CONTROL_START_BIT

#define I3C_TARG_SINK_CONTROL_START_BIT   31

Definition at line 167 of file i3c_regs.h.

I3C_TARG_SINK_STATUS_ACTIVE_BIT

#define I3C_TARG_SINK_STATUS_ACTIVE_BIT   0

Definition at line 172 of file i3c_regs.h.

I3C_TARG_SINK_STATUS_ERROR_BIT

#define I3C_TARG_SINK_STATUS_ERROR_BIT   1

Definition at line 173 of file i3c_regs.h.

I3C_TARG_SINK_STATUS_LENGTH_FIELD

#define I3C_TARG_SINK_STATUS_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_SINK_STATUS_LENGTH_MASK, .index = I3C_TARG_SINK_STATUS_LENGTH_OFFSET })

Definition at line 176 of file i3c_regs.h.

I3C_TARG_SINK_STATUS_LENGTH_MASK

#define I3C_TARG_SINK_STATUS_LENGTH_MASK   0x7ffu

Definition at line 174 of file i3c_regs.h.

I3C_TARG_SINK_STATUS_LENGTH_OFFSET

#define I3C_TARG_SINK_STATUS_LENGTH_OFFSET   16

Definition at line 175 of file i3c_regs.h.

I3C_TARG_SINK_STATUS_REG_OFFSET

#define I3C_TARG_SINK_STATUS_REG_OFFSET   0x28

Definition at line 170 of file i3c_regs.h.

I3C_TARG_SINK_STATUS_REG_RESVAL

#define I3C_TARG_SINK_STATUS_REG_RESVAL   0x0u

Definition at line 171 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_BUS_AVAIL_BIT

#define I3C_TARG_STATE_DEBUG_BUS_AVAIL_BIT   8

Definition at line 1931 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_BUS_IDLE_BIT

#define I3C_TARG_STATE_DEBUG_BUS_IDLE_BIT   9

Definition at line 1932 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_BUS_MODE_FIELD

#define I3C_TARG_STATE_DEBUG_BUS_MODE_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATE_DEBUG_BUS_MODE_MASK, .index = I3C_TARG_STATE_DEBUG_BUS_MODE_OFFSET })

Definition at line 1935 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_BUS_MODE_MASK

#define I3C_TARG_STATE_DEBUG_BUS_MODE_MASK   0xfu

Definition at line 1933 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_BUS_MODE_OFFSET

#define I3C_TARG_STATE_DEBUG_BUS_MODE_OFFSET   12

Definition at line 1934 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_FSM_STATE_FIELD

#define I3C_TARG_STATE_DEBUG_FSM_STATE_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATE_DEBUG_FSM_STATE_MASK, .index = I3C_TARG_STATE_DEBUG_FSM_STATE_OFFSET })

Definition at line 1939 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_FSM_STATE_MASK

#define I3C_TARG_STATE_DEBUG_FSM_STATE_MASK   0xffu

Definition at line 1937 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_FSM_STATE_OFFSET

#define I3C_TARG_STATE_DEBUG_FSM_STATE_OFFSET   16

Definition at line 1938 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_REG_OFFSET

#define I3C_TARG_STATE_DEBUG_REG_OFFSET   0x364

Definition at line 1927 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_REG_RESVAL

#define I3C_TARG_STATE_DEBUG_REG_RESVAL   0x3u

Definition at line 1928 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_SCL_LINE_SIGNAL_LEVEL_BIT

#define I3C_TARG_STATE_DEBUG_SCL_LINE_SIGNAL_LEVEL_BIT   0

Definition at line 1929 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_SDA_LINE_SIGNAL_LEVEL_BIT

#define I3C_TARG_STATE_DEBUG_SDA_LINE_SIGNAL_LEVEL_BIT   1

Definition at line 1930 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_TRX_STATE_FIELD

#define I3C_TARG_STATE_DEBUG_TRX_STATE_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATE_DEBUG_TRX_STATE_MASK, .index = I3C_TARG_STATE_DEBUG_TRX_STATE_OFFSET })

Definition at line 1943 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_TRX_STATE_MASK

#define I3C_TARG_STATE_DEBUG_TRX_STATE_MASK   0xffu

Definition at line 1941 of file i3c_regs.h.

I3C_TARG_STATE_DEBUG_TRX_STATE_OFFSET

#define I3C_TARG_STATE_DEBUG_TRX_STATE_OFFSET   24

Definition at line 1942 of file i3c_regs.h.

I3C_TARG_STATUS_ACTIVE_BIT

#define I3C_TARG_STATUS_ACTIVE_BIT   30

Definition at line 153 of file i3c_regs.h.

I3C_TARG_STATUS_CONNECTED_BIT

#define I3C_TARG_STATUS_CONNECTED_BIT   29

Definition at line 152 of file i3c_regs.h.

I3C_TARG_STATUS_EXT_INFO_FIELD

#define I3C_TARG_STATUS_EXT_INFO_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATUS_EXT_INFO_MASK, .index = I3C_TARG_STATUS_EXT_INFO_OFFSET })

Definition at line 139 of file i3c_regs.h.

I3C_TARG_STATUS_EXT_INFO_MASK

#define I3C_TARG_STATUS_EXT_INFO_MASK   0x7fffu

Definition at line 137 of file i3c_regs.h.

I3C_TARG_STATUS_EXT_INFO_OFFSET

#define I3C_TARG_STATUS_EXT_INFO_OFFSET   0

Definition at line 138 of file i3c_regs.h.

I3C_TARG_STATUS_EXT_PRESENT_BIT

#define I3C_TARG_STATUS_EXT_PRESENT_BIT   15

Definition at line 141 of file i3c_regs.h.

I3C_TARG_STATUS_NUM_TARGETS_FIELD

#define I3C_TARG_STATUS_NUM_TARGETS_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATUS_NUM_TARGETS_MASK, .index = I3C_TARG_STATUS_NUM_TARGETS_OFFSET })

Definition at line 148 of file i3c_regs.h.

I3C_TARG_STATUS_NUM_TARGETS_MASK

#define I3C_TARG_STATUS_NUM_TARGETS_MASK   0x7u

Definition at line 146 of file i3c_regs.h.

I3C_TARG_STATUS_NUM_TARGETS_OFFSET

#define I3C_TARG_STATUS_NUM_TARGETS_OFFSET   24

Definition at line 147 of file i3c_regs.h.

I3C_TARG_STATUS_PRESENT_BIT

#define I3C_TARG_STATUS_PRESENT_BIT   31

Definition at line 154 of file i3c_regs.h.

I3C_TARG_STATUS_PROTOCOL_ERROR_BIT

#define I3C_TARG_STATUS_PROTOCOL_ERROR_BIT   28

Definition at line 151 of file i3c_regs.h.

I3C_TARG_STATUS_REG_OFFSET

#define I3C_TARG_STATUS_REG_OFFSET   0x20

Definition at line 135 of file i3c_regs.h.

I3C_TARG_STATUS_REG_RESVAL

#define I3C_TARG_STATUS_REG_RESVAL   0x82000000u

Definition at line 136 of file i3c_regs.h.

I3C_TARG_STATUS_RSTACT_FIELD

#define I3C_TARG_STATUS_RSTACT_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_STATUS_RSTACT_MASK, .index = I3C_TARG_STATUS_RSTACT_OFFSET })

Definition at line 144 of file i3c_regs.h.

I3C_TARG_STATUS_RSTACT_MASK

#define I3C_TARG_STATUS_RSTACT_MASK   0xffu

Definition at line 142 of file i3c_regs.h.

I3C_TARG_STATUS_RSTACT_OFFSET

#define I3C_TARG_STATUS_RSTACT_OFFSET   16

Definition at line 143 of file i3c_regs.h.

I3C_TARG_STATUS_VTM_BIT

#define I3C_TARG_STATUS_VTM_BIT   27

Definition at line 150 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_REG_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_REG_OFFSET   0x39c

Definition at line 2136 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_REG_RESVAL

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_REG_RESVAL   0x80040u

Definition at line 2137 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_FIELD

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_OFFSET })

Definition at line 2140 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_MASK

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_MASK   0xfffu

Definition at line 2138 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_OFFSET   0

Definition at line 2139 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_FIELD

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_OFFSET })

Definition at line 2144 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_MASK

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_MASK   0xffu

Definition at line 2142 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_OFFSET   16

Definition at line 2143 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_REG_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_REG_OFFSET   0x3a0

Definition at line 2148 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_REG_RESVAL

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_REG_RESVAL   0x80040u

Definition at line 2149 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_FIELD

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_OFFSET })

Definition at line 2152 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_MASK

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_MASK   0xfffu

Definition at line 2150 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_OFFSET   0

Definition at line 2151 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_FIELD

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_OFFSET })

Definition at line 2156 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_MASK

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_MASK   0xffu

Definition at line 2154 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_OFFSET   16

Definition at line 2155 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_REG_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_REG_OFFSET   0x3a4

Definition at line 2160 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_REG_RESVAL

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_REG_RESVAL   0x80040u

Definition at line 2161 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_FIELD

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_OFFSET })

Definition at line 2164 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_MASK

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_MASK   0xfffu

Definition at line 2162 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_OFFSET   0

Definition at line 2163 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_FIELD

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_OFFSET })

Definition at line 2168 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_MASK

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_MASK   0xffu

Definition at line 2166 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_OFFSET   16

Definition at line 2167 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_REG_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_REG_OFFSET   0x3a8

Definition at line 2172 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_REG_RESVAL

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_REG_RESVAL   0x80040u

Definition at line 2173 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_FIELD

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_OFFSET })

Definition at line 2176 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_MASK

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_MASK   0xfffu

Definition at line 2174 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_OFFSET   0

Definition at line 2175 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_FIELD

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_OFFSET })

Definition at line 2180 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_MASK

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_MASK   0xffu

Definition at line 2178 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_OFFSET

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_OFFSET   16

Definition at line 2179 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_MULTIREG_COUNT

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_MULTIREG_COUNT   4

Definition at line 2133 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_TX_BUF_FREE_LVL_FIELD_WIDTH

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_TX_BUF_FREE_LVL_FIELD_WIDTH   12

Definition at line 2131 of file i3c_regs.h.

I3C_TARG_TX_QUEUE_STATUS_LEVEL_TX_DESC_FREE_LVL_FIELD_WIDTH

#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_TX_DESC_FREE_LVL_FIELD_WIDTH   8

Definition at line 2132 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_REG_OFFSET

#define I3C_TARG_TX_THLD_CTRL_0_REG_OFFSET   0x38c

Definition at line 2066 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_REG_RESVAL

#define I3C_TARG_TX_THLD_CTRL_0_REG_RESVAL   0x10010001u

Definition at line 2067 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_FIELD

#define I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_MASK, .index = I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_OFFSET })

Definition at line 2070 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_MASK

#define I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_MASK   0xfffu

Definition at line 2068 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_OFFSET

#define I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_OFFSET   0

Definition at line 2069 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_FIELD

#define I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_MASK, .index = I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_OFFSET })

Definition at line 2074 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_MASK

#define I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_MASK   0xffu

Definition at line 2072 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_OFFSET

#define I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_OFFSET   16

Definition at line 2073 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_FIELD

#define I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_MASK, .index = I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_OFFSET })

Definition at line 2078 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_MASK

#define I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_MASK   0xfu

Definition at line 2076 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_OFFSET

#define I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_OFFSET   28

Definition at line 2077 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_REG_OFFSET

#define I3C_TARG_TX_THLD_CTRL_1_REG_OFFSET   0x390

Definition at line 2082 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_REG_RESVAL

#define I3C_TARG_TX_THLD_CTRL_1_REG_RESVAL   0x10010001u

Definition at line 2083 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_FIELD

#define I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_MASK, .index = I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_OFFSET })

Definition at line 2086 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_MASK

#define I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_MASK   0xfffu

Definition at line 2084 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_OFFSET

#define I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_OFFSET   0

Definition at line 2085 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_FIELD

#define I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_MASK, .index = I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_OFFSET })

Definition at line 2090 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_MASK

#define I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_MASK   0xffu

Definition at line 2088 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_OFFSET

#define I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_OFFSET   16

Definition at line 2089 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_FIELD

#define I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_MASK, .index = I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_OFFSET })

Definition at line 2094 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_MASK

#define I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_MASK   0xfu

Definition at line 2092 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_OFFSET

#define I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_OFFSET   28

Definition at line 2093 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_REG_OFFSET

#define I3C_TARG_TX_THLD_CTRL_2_REG_OFFSET   0x394

Definition at line 2098 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_REG_RESVAL

#define I3C_TARG_TX_THLD_CTRL_2_REG_RESVAL   0x10010001u

Definition at line 2099 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_FIELD

#define I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_MASK, .index = I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_OFFSET })

Definition at line 2102 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_MASK

#define I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_MASK   0xfffu

Definition at line 2100 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_OFFSET

#define I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_OFFSET   0

Definition at line 2101 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_FIELD

#define I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_MASK, .index = I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_OFFSET })

Definition at line 2106 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_MASK

#define I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_MASK   0xffu

Definition at line 2104 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_OFFSET

#define I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_OFFSET   16

Definition at line 2105 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_FIELD

#define I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_MASK, .index = I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_OFFSET })

Definition at line 2110 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_MASK

#define I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_MASK   0xfu

Definition at line 2108 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_OFFSET

#define I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_OFFSET   28

Definition at line 2109 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_REG_OFFSET

#define I3C_TARG_TX_THLD_CTRL_3_REG_OFFSET   0x398

Definition at line 2114 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_REG_RESVAL

#define I3C_TARG_TX_THLD_CTRL_3_REG_RESVAL   0x10010001u

Definition at line 2115 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_FIELD

#define I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_MASK, .index = I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_OFFSET })

Definition at line 2118 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_MASK

#define I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_MASK   0xfffu

Definition at line 2116 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_OFFSET

#define I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_OFFSET   0

Definition at line 2117 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_FIELD

#define I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_MASK, .index = I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_OFFSET })

Definition at line 2122 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_MASK

#define I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_MASK   0xffu

Definition at line 2120 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_OFFSET

#define I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_OFFSET   16

Definition at line 2121 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_FIELD

#define I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_MASK, .index = I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_OFFSET })

Definition at line 2126 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_MASK

#define I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_MASK   0xfu

Definition at line 2124 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_OFFSET

#define I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_OFFSET   28

Definition at line 2125 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_MULTIREG_COUNT

#define I3C_TARG_TX_THLD_CTRL_MULTIREG_COUNT   4

Definition at line 2063 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_TX_BUF_FREE_THLD_FIELD_WIDTH

#define I3C_TARG_TX_THLD_CTRL_TX_BUF_FREE_THLD_FIELD_WIDTH   12

Definition at line 2060 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_TX_DESC_EMPTY_THLD_FIELD_WIDTH

#define I3C_TARG_TX_THLD_CTRL_TX_DESC_EMPTY_THLD_FIELD_WIDTH   8

Definition at line 2061 of file i3c_regs.h.

I3C_TARG_TX_THLD_CTRL_TX_START_THLD_FIELD_WIDTH

#define I3C_TARG_TX_THLD_CTRL_TX_START_THLD_FIELD_WIDTH   4

Definition at line 2062 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_FIELD

#define I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_MASK, .index = I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_OFFSET })

Definition at line 595 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_MASK

#define I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_MASK   0x3ffu

Definition at line 593 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_OFFSET

#define I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_OFFSET   16

Definition at line 594 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_FIELD

#define I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_MASK, .index = I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_OFFSET })

Definition at line 591 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_MASK

#define I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_MASK   0x3ffu

Definition at line 589 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_OFFSET

#define I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_OFFSET   0

Definition at line 590 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_0_REG_OFFSET

#define I3C_TARG_TXBUF_CONFIG_0_REG_OFFSET   0xa4

Definition at line 587 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_0_REG_RESVAL

#define I3C_TARG_TXBUF_CONFIG_0_REG_RESVAL   0x20f01d0u

Definition at line 588 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_FIELD

#define I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_MASK, .index = I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_OFFSET })

Definition at line 607 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_MASK

#define I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_MASK   0x3ffu

Definition at line 605 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_OFFSET

#define I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_OFFSET   16

Definition at line 606 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_FIELD

#define I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_MASK, .index = I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_OFFSET })

Definition at line 603 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_MASK

#define I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_MASK   0x3ffu

Definition at line 601 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_OFFSET

#define I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_OFFSET   0

Definition at line 602 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_1_REG_OFFSET

#define I3C_TARG_TXBUF_CONFIG_1_REG_OFFSET   0xa8

Definition at line 599 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_1_REG_RESVAL

#define I3C_TARG_TXBUF_CONFIG_1_REG_RESVAL   0x24f0210u

Definition at line 600 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_FIELD

#define I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_MASK, .index = I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_OFFSET })

Definition at line 619 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_MASK

#define I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_MASK   0x3ffu

Definition at line 617 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_OFFSET

#define I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_OFFSET   16

Definition at line 618 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_FIELD

#define I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_MASK, .index = I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_OFFSET })

Definition at line 615 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_MASK

#define I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_MASK   0x3ffu

Definition at line 613 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_OFFSET

#define I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_OFFSET   0

Definition at line 614 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_2_REG_OFFSET

#define I3C_TARG_TXBUF_CONFIG_2_REG_OFFSET   0xac

Definition at line 611 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_2_REG_RESVAL

#define I3C_TARG_TXBUF_CONFIG_2_REG_RESVAL   0x28f0250u

Definition at line 612 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_FIELD

#define I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_MASK, .index = I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_OFFSET })

Definition at line 631 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_MASK

#define I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_MASK   0x3ffu

Definition at line 629 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_OFFSET

#define I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_OFFSET   16

Definition at line 630 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_FIELD

#define I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_MASK, .index = I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_OFFSET })

Definition at line 627 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_MASK

#define I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_MASK   0x3ffu

Definition at line 625 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_OFFSET

#define I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_OFFSET   0

Definition at line 626 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_3_REG_OFFSET

#define I3C_TARG_TXBUF_CONFIG_3_REG_OFFSET   0xb0

Definition at line 623 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_3_REG_RESVAL

#define I3C_TARG_TXBUF_CONFIG_3_REG_RESVAL   0x2cf0290u

Definition at line 624 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_MAX_ADDR_FIELD_WIDTH

#define I3C_TARG_TXBUF_CONFIG_MAX_ADDR_FIELD_WIDTH   10

Definition at line 583 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_MIN_ADDR_FIELD_WIDTH

#define I3C_TARG_TXBUF_CONFIG_MIN_ADDR_FIELD_WIDTH   10

Definition at line 582 of file i3c_regs.h.

I3C_TARG_TXBUF_CONFIG_MULTIREG_COUNT

#define I3C_TARG_TXBUF_CONFIG_MULTIREG_COUNT   4

Definition at line 584 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_FULL_0_BIT

#define I3C_TARG_TXBUF_STATE_0_FULL_0_BIT   31

Definition at line 653 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_PRE_0_BIT

#define I3C_TARG_TXBUF_STATE_0_PRE_0_BIT   30

Definition at line 652 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_REG_OFFSET

#define I3C_TARG_TXBUF_STATE_0_REG_OFFSET   0xb4

Definition at line 642 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_REG_RESVAL

#define I3C_TARG_TXBUF_STATE_0_REG_RESVAL   0x1d001d0u

Definition at line 643 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_RPTR_0_FIELD

#define I3C_TARG_TXBUF_STATE_0_RPTR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_0_RPTR_0_MASK, .index = I3C_TARG_TXBUF_STATE_0_RPTR_0_OFFSET })

Definition at line 650 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_RPTR_0_MASK

#define I3C_TARG_TXBUF_STATE_0_RPTR_0_MASK   0x3ffu

Definition at line 648 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_RPTR_0_OFFSET

#define I3C_TARG_TXBUF_STATE_0_RPTR_0_OFFSET   16

Definition at line 649 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_WPTR_0_FIELD

#define I3C_TARG_TXBUF_STATE_0_WPTR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_0_WPTR_0_MASK, .index = I3C_TARG_TXBUF_STATE_0_WPTR_0_OFFSET })

Definition at line 646 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_WPTR_0_MASK

#define I3C_TARG_TXBUF_STATE_0_WPTR_0_MASK   0x3ffu

Definition at line 644 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_0_WPTR_0_OFFSET

#define I3C_TARG_TXBUF_STATE_0_WPTR_0_OFFSET   0

Definition at line 645 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_FULL_1_BIT

#define I3C_TARG_TXBUF_STATE_1_FULL_1_BIT   31

Definition at line 667 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_PRE_1_BIT

#define I3C_TARG_TXBUF_STATE_1_PRE_1_BIT   30

Definition at line 666 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_REG_OFFSET

#define I3C_TARG_TXBUF_STATE_1_REG_OFFSET   0xb8

Definition at line 656 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_REG_RESVAL

#define I3C_TARG_TXBUF_STATE_1_REG_RESVAL   0x2100210u

Definition at line 657 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_RPTR_1_FIELD

#define I3C_TARG_TXBUF_STATE_1_RPTR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_1_RPTR_1_MASK, .index = I3C_TARG_TXBUF_STATE_1_RPTR_1_OFFSET })

Definition at line 664 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_RPTR_1_MASK

#define I3C_TARG_TXBUF_STATE_1_RPTR_1_MASK   0x3ffu

Definition at line 662 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_RPTR_1_OFFSET

#define I3C_TARG_TXBUF_STATE_1_RPTR_1_OFFSET   16

Definition at line 663 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_WPTR_1_FIELD

#define I3C_TARG_TXBUF_STATE_1_WPTR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_1_WPTR_1_MASK, .index = I3C_TARG_TXBUF_STATE_1_WPTR_1_OFFSET })

Definition at line 660 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_WPTR_1_MASK

#define I3C_TARG_TXBUF_STATE_1_WPTR_1_MASK   0x3ffu

Definition at line 658 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_1_WPTR_1_OFFSET

#define I3C_TARG_TXBUF_STATE_1_WPTR_1_OFFSET   0

Definition at line 659 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_FULL_2_BIT

#define I3C_TARG_TXBUF_STATE_2_FULL_2_BIT   31

Definition at line 681 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_PRE_2_BIT

#define I3C_TARG_TXBUF_STATE_2_PRE_2_BIT   30

Definition at line 680 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_REG_OFFSET

#define I3C_TARG_TXBUF_STATE_2_REG_OFFSET   0xbc

Definition at line 670 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_REG_RESVAL

#define I3C_TARG_TXBUF_STATE_2_REG_RESVAL   0x2500250u

Definition at line 671 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_RPTR_2_FIELD

#define I3C_TARG_TXBUF_STATE_2_RPTR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_2_RPTR_2_MASK, .index = I3C_TARG_TXBUF_STATE_2_RPTR_2_OFFSET })

Definition at line 678 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_RPTR_2_MASK

#define I3C_TARG_TXBUF_STATE_2_RPTR_2_MASK   0x3ffu

Definition at line 676 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_RPTR_2_OFFSET

#define I3C_TARG_TXBUF_STATE_2_RPTR_2_OFFSET   16

Definition at line 677 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_WPTR_2_FIELD

#define I3C_TARG_TXBUF_STATE_2_WPTR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_2_WPTR_2_MASK, .index = I3C_TARG_TXBUF_STATE_2_WPTR_2_OFFSET })

Definition at line 674 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_WPTR_2_MASK

#define I3C_TARG_TXBUF_STATE_2_WPTR_2_MASK   0x3ffu

Definition at line 672 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_2_WPTR_2_OFFSET

#define I3C_TARG_TXBUF_STATE_2_WPTR_2_OFFSET   0

Definition at line 673 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_FULL_3_BIT

#define I3C_TARG_TXBUF_STATE_3_FULL_3_BIT   31

Definition at line 695 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_PRE_3_BIT

#define I3C_TARG_TXBUF_STATE_3_PRE_3_BIT   30

Definition at line 694 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_REG_OFFSET

#define I3C_TARG_TXBUF_STATE_3_REG_OFFSET   0xc0

Definition at line 684 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_REG_RESVAL

#define I3C_TARG_TXBUF_STATE_3_REG_RESVAL   0x2900290u

Definition at line 685 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_RPTR_3_FIELD

#define I3C_TARG_TXBUF_STATE_3_RPTR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_3_RPTR_3_MASK, .index = I3C_TARG_TXBUF_STATE_3_RPTR_3_OFFSET })

Definition at line 692 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_RPTR_3_MASK

#define I3C_TARG_TXBUF_STATE_3_RPTR_3_MASK   0x3ffu

Definition at line 690 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_RPTR_3_OFFSET

#define I3C_TARG_TXBUF_STATE_3_RPTR_3_OFFSET   16

Definition at line 691 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_WPTR_3_FIELD

#define I3C_TARG_TXBUF_STATE_3_WPTR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_3_WPTR_3_MASK, .index = I3C_TARG_TXBUF_STATE_3_WPTR_3_OFFSET })

Definition at line 688 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_WPTR_3_MASK

#define I3C_TARG_TXBUF_STATE_3_WPTR_3_MASK   0x3ffu

Definition at line 686 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_3_WPTR_3_OFFSET

#define I3C_TARG_TXBUF_STATE_3_WPTR_3_OFFSET   0

Definition at line 687 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_FULL_FIELD_WIDTH

#define I3C_TARG_TXBUF_STATE_FULL_FIELD_WIDTH   1

Definition at line 638 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_MULTIREG_COUNT

#define I3C_TARG_TXBUF_STATE_MULTIREG_COUNT   4

Definition at line 639 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_PRE_FIELD_WIDTH

#define I3C_TARG_TXBUF_STATE_PRE_FIELD_WIDTH   1

Definition at line 637 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_RPTR_FIELD_WIDTH

#define I3C_TARG_TXBUF_STATE_RPTR_FIELD_WIDTH   10

Definition at line 636 of file i3c_regs.h.

I3C_TARG_TXBUF_STATE_WPTR_FIELD_WIDTH

#define I3C_TARG_TXBUF_STATE_WPTR_FIELD_WIDTH   10

Definition at line 635 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_FIELD

#define I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_MASK, .index = I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_OFFSET })

Definition at line 763 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_MASK

#define I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_MASK   0x3ffu

Definition at line 761 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_OFFSET

#define I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_OFFSET   16

Definition at line 762 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_FIELD

#define I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_MASK, .index = I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_OFFSET })

Definition at line 759 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_MASK

#define I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_MASK   0x3ffu

Definition at line 757 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_OFFSET

#define I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_OFFSET   0

Definition at line 758 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_0_REG_OFFSET

#define I3C_TARG_TXDESC_CONFIG_0_REG_OFFSET   0xd4

Definition at line 755 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_0_REG_RESVAL

#define I3C_TARG_TXDESC_CONFIG_0_REG_RESVAL   0x3b703b0u

Definition at line 756 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_FIELD

#define I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_MASK, .index = I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_OFFSET })

Definition at line 775 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_MASK

#define I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_MASK   0x3ffu

Definition at line 773 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_OFFSET

#define I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_OFFSET   16

Definition at line 774 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_FIELD

#define I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_MASK, .index = I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_OFFSET })

Definition at line 771 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_MASK

#define I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_MASK   0x3ffu

Definition at line 769 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_OFFSET

#define I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_OFFSET   0

Definition at line 770 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_1_REG_OFFSET

#define I3C_TARG_TXDESC_CONFIG_1_REG_OFFSET   0xd8

Definition at line 767 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_1_REG_RESVAL

#define I3C_TARG_TXDESC_CONFIG_1_REG_RESVAL   0x3bf03b8u

Definition at line 768 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_FIELD

#define I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_MASK, .index = I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_OFFSET })

Definition at line 787 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_MASK

#define I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_MASK   0x3ffu

Definition at line 785 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_OFFSET

#define I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_OFFSET   16

Definition at line 786 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_FIELD

#define I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_MASK, .index = I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_OFFSET })

Definition at line 783 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_MASK

#define I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_MASK   0x3ffu

Definition at line 781 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_OFFSET

#define I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_OFFSET   0

Definition at line 782 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_2_REG_OFFSET

#define I3C_TARG_TXDESC_CONFIG_2_REG_OFFSET   0xdc

Definition at line 779 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_2_REG_RESVAL

#define I3C_TARG_TXDESC_CONFIG_2_REG_RESVAL   0x3c703c0u

Definition at line 780 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_FIELD

#define I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_MASK, .index = I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_OFFSET })

Definition at line 799 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_MASK

#define I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_MASK   0x3ffu

Definition at line 797 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_OFFSET

#define I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_OFFSET   16

Definition at line 798 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_FIELD

#define I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_MASK, .index = I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_OFFSET })

Definition at line 795 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_MASK

#define I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_MASK   0x3ffu

Definition at line 793 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_OFFSET

#define I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_OFFSET   0

Definition at line 794 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_3_REG_OFFSET

#define I3C_TARG_TXDESC_CONFIG_3_REG_OFFSET   0xe0

Definition at line 791 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_3_REG_RESVAL

#define I3C_TARG_TXDESC_CONFIG_3_REG_RESVAL   0x3cf03c8u

Definition at line 792 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_MAX_ADDR_FIELD_WIDTH

#define I3C_TARG_TXDESC_CONFIG_MAX_ADDR_FIELD_WIDTH   10

Definition at line 751 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_MIN_ADDR_FIELD_WIDTH

#define I3C_TARG_TXDESC_CONFIG_MIN_ADDR_FIELD_WIDTH   10

Definition at line 750 of file i3c_regs.h.

I3C_TARG_TXDESC_CONFIG_MULTIREG_COUNT

#define I3C_TARG_TXDESC_CONFIG_MULTIREG_COUNT   4

Definition at line 752 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_FULL_0_BIT

#define I3C_TARG_TXDESC_STATE_0_FULL_0_BIT   31

Definition at line 821 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_PRE_0_BIT

#define I3C_TARG_TXDESC_STATE_0_PRE_0_BIT   30

Definition at line 820 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_REG_OFFSET

#define I3C_TARG_TXDESC_STATE_0_REG_OFFSET   0xe4

Definition at line 810 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_REG_RESVAL

#define I3C_TARG_TXDESC_STATE_0_REG_RESVAL   0x3b003b0u

Definition at line 811 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_RPTR_0_FIELD

#define I3C_TARG_TXDESC_STATE_0_RPTR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_0_RPTR_0_MASK, .index = I3C_TARG_TXDESC_STATE_0_RPTR_0_OFFSET })

Definition at line 818 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_RPTR_0_MASK

#define I3C_TARG_TXDESC_STATE_0_RPTR_0_MASK   0x3ffu

Definition at line 816 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_RPTR_0_OFFSET

#define I3C_TARG_TXDESC_STATE_0_RPTR_0_OFFSET   16

Definition at line 817 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_WPTR_0_FIELD

#define I3C_TARG_TXDESC_STATE_0_WPTR_0_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_0_WPTR_0_MASK, .index = I3C_TARG_TXDESC_STATE_0_WPTR_0_OFFSET })

Definition at line 814 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_WPTR_0_MASK

#define I3C_TARG_TXDESC_STATE_0_WPTR_0_MASK   0x3ffu

Definition at line 812 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_0_WPTR_0_OFFSET

#define I3C_TARG_TXDESC_STATE_0_WPTR_0_OFFSET   0

Definition at line 813 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_FULL_1_BIT

#define I3C_TARG_TXDESC_STATE_1_FULL_1_BIT   31

Definition at line 835 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_PRE_1_BIT

#define I3C_TARG_TXDESC_STATE_1_PRE_1_BIT   30

Definition at line 834 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_REG_OFFSET

#define I3C_TARG_TXDESC_STATE_1_REG_OFFSET   0xe8

Definition at line 824 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_REG_RESVAL

#define I3C_TARG_TXDESC_STATE_1_REG_RESVAL   0x3b803b8u

Definition at line 825 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_RPTR_1_FIELD

#define I3C_TARG_TXDESC_STATE_1_RPTR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_1_RPTR_1_MASK, .index = I3C_TARG_TXDESC_STATE_1_RPTR_1_OFFSET })

Definition at line 832 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_RPTR_1_MASK

#define I3C_TARG_TXDESC_STATE_1_RPTR_1_MASK   0x3ffu

Definition at line 830 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_RPTR_1_OFFSET

#define I3C_TARG_TXDESC_STATE_1_RPTR_1_OFFSET   16

Definition at line 831 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_WPTR_1_FIELD

#define I3C_TARG_TXDESC_STATE_1_WPTR_1_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_1_WPTR_1_MASK, .index = I3C_TARG_TXDESC_STATE_1_WPTR_1_OFFSET })

Definition at line 828 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_WPTR_1_MASK

#define I3C_TARG_TXDESC_STATE_1_WPTR_1_MASK   0x3ffu

Definition at line 826 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_1_WPTR_1_OFFSET

#define I3C_TARG_TXDESC_STATE_1_WPTR_1_OFFSET   0

Definition at line 827 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_FULL_2_BIT

#define I3C_TARG_TXDESC_STATE_2_FULL_2_BIT   31

Definition at line 849 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_PRE_2_BIT

#define I3C_TARG_TXDESC_STATE_2_PRE_2_BIT   30

Definition at line 848 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_REG_OFFSET

#define I3C_TARG_TXDESC_STATE_2_REG_OFFSET   0xec

Definition at line 838 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_REG_RESVAL

#define I3C_TARG_TXDESC_STATE_2_REG_RESVAL   0x3c003c0u

Definition at line 839 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_RPTR_2_FIELD

#define I3C_TARG_TXDESC_STATE_2_RPTR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_2_RPTR_2_MASK, .index = I3C_TARG_TXDESC_STATE_2_RPTR_2_OFFSET })

Definition at line 846 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_RPTR_2_MASK

#define I3C_TARG_TXDESC_STATE_2_RPTR_2_MASK   0x3ffu

Definition at line 844 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_RPTR_2_OFFSET

#define I3C_TARG_TXDESC_STATE_2_RPTR_2_OFFSET   16

Definition at line 845 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_WPTR_2_FIELD

#define I3C_TARG_TXDESC_STATE_2_WPTR_2_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_2_WPTR_2_MASK, .index = I3C_TARG_TXDESC_STATE_2_WPTR_2_OFFSET })

Definition at line 842 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_WPTR_2_MASK

#define I3C_TARG_TXDESC_STATE_2_WPTR_2_MASK   0x3ffu

Definition at line 840 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_2_WPTR_2_OFFSET

#define I3C_TARG_TXDESC_STATE_2_WPTR_2_OFFSET   0

Definition at line 841 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_FULL_3_BIT

#define I3C_TARG_TXDESC_STATE_3_FULL_3_BIT   31

Definition at line 863 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_PRE_3_BIT

#define I3C_TARG_TXDESC_STATE_3_PRE_3_BIT   30

Definition at line 862 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_REG_OFFSET

#define I3C_TARG_TXDESC_STATE_3_REG_OFFSET   0xf0

Definition at line 852 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_REG_RESVAL

#define I3C_TARG_TXDESC_STATE_3_REG_RESVAL   0x3c803c8u

Definition at line 853 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_RPTR_3_FIELD

#define I3C_TARG_TXDESC_STATE_3_RPTR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_3_RPTR_3_MASK, .index = I3C_TARG_TXDESC_STATE_3_RPTR_3_OFFSET })

Definition at line 860 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_RPTR_3_MASK

#define I3C_TARG_TXDESC_STATE_3_RPTR_3_MASK   0x3ffu

Definition at line 858 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_RPTR_3_OFFSET

#define I3C_TARG_TXDESC_STATE_3_RPTR_3_OFFSET   16

Definition at line 859 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_WPTR_3_FIELD

#define I3C_TARG_TXDESC_STATE_3_WPTR_3_FIELD    ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_3_WPTR_3_MASK, .index = I3C_TARG_TXDESC_STATE_3_WPTR_3_OFFSET })

Definition at line 856 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_WPTR_3_MASK

#define I3C_TARG_TXDESC_STATE_3_WPTR_3_MASK   0x3ffu

Definition at line 854 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_3_WPTR_3_OFFSET

#define I3C_TARG_TXDESC_STATE_3_WPTR_3_OFFSET   0

Definition at line 855 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_FULL_FIELD_WIDTH

#define I3C_TARG_TXDESC_STATE_FULL_FIELD_WIDTH   1

Definition at line 806 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_MULTIREG_COUNT

#define I3C_TARG_TXDESC_STATE_MULTIREG_COUNT   4

Definition at line 807 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_PRE_FIELD_WIDTH

#define I3C_TARG_TXDESC_STATE_PRE_FIELD_WIDTH   1

Definition at line 805 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_RPTR_FIELD_WIDTH

#define I3C_TARG_TXDESC_STATE_RPTR_FIELD_WIDTH   10

Definition at line 804 of file i3c_regs.h.

I3C_TARG_TXDESC_STATE_WPTR_FIELD_WIDTH

#define I3C_TARG_TXDESC_STATE_WPTR_FIELD_WIDTH   10

Definition at line 803 of file i3c_regs.h.

I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_FIELD

#define I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_OFFSET })

Definition at line 2583 of file i3c_regs.h.

I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_MASK

#define I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_MASK   0xffu

Definition at line 2581 of file i3c_regs.h.

I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_OFFSET

#define I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_OFFSET   0

Definition at line 2582 of file i3c_regs.h.

I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_FIELD

#define I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_OFFSET })

Definition at line 2587 of file i3c_regs.h.

I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_MASK

#define I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu

Definition at line 2585 of file i3c_regs.h.

I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_OFFSET

#define I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8

Definition at line 2586 of file i3c_regs.h.

I3C_TARGEXT_EXTCAP_HEADER_REG_OFFSET

#define I3C_TARGEXT_EXTCAP_HEADER_REG_OFFSET   0x474

Definition at line 2579 of file i3c_regs.h.

I3C_TARGEXT_EXTCAP_HEADER_REG_RESVAL

#define I3C_TARGEXT_EXTCAP_HEADER_REG_RESVAL   0x1c0u

Definition at line 2580 of file i3c_regs.h.

I3C_TERM_EXTCAP_HEADER_CAP_ID_FIELD

#define I3C_TERM_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_TERM_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_TERM_EXTCAP_HEADER_CAP_ID_OFFSET })

Definition at line 2595 of file i3c_regs.h.

I3C_TERM_EXTCAP_HEADER_CAP_ID_MASK

#define I3C_TERM_EXTCAP_HEADER_CAP_ID_MASK   0xffu

Definition at line 2593 of file i3c_regs.h.

I3C_TERM_EXTCAP_HEADER_CAP_ID_OFFSET

#define I3C_TERM_EXTCAP_HEADER_CAP_ID_OFFSET   0

Definition at line 2594 of file i3c_regs.h.

I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_FIELD

#define I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_OFFSET })

Definition at line 2599 of file i3c_regs.h.

I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_MASK

#define I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu

Definition at line 2597 of file i3c_regs.h.

I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_OFFSET

#define I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8

Definition at line 2598 of file i3c_regs.h.

I3C_TERM_EXTCAP_HEADER_REG_OFFSET

#define I3C_TERM_EXTCAP_HEADER_REG_OFFSET   0x478

Definition at line 2591 of file i3c_regs.h.

I3C_TERM_EXTCAP_HEADER_REG_RESVAL

#define I3C_TERM_EXTCAP_HEADER_REG_RESVAL   0x100u

Definition at line 2592 of file i3c_regs.h.

I3C_TTI_EXTCAP_HEADER_CAP_ID_FIELD

#define I3C_TTI_EXTCAP_HEADER_CAP_ID_FIELD    ((bitfield_field32_t) { .mask = I3C_TTI_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_TTI_EXTCAP_HEADER_CAP_ID_OFFSET })

Definition at line 1617 of file i3c_regs.h.

I3C_TTI_EXTCAP_HEADER_CAP_ID_MASK

#define I3C_TTI_EXTCAP_HEADER_CAP_ID_MASK   0xffu

Definition at line 1615 of file i3c_regs.h.

I3C_TTI_EXTCAP_HEADER_CAP_ID_OFFSET

#define I3C_TTI_EXTCAP_HEADER_CAP_ID_OFFSET   0

Definition at line 1616 of file i3c_regs.h.

I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_FIELD

#define I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_FIELD    ((bitfield_field32_t) { .mask = I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_OFFSET })

Definition at line 1621 of file i3c_regs.h.

I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_MASK

#define I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_MASK   0xffffu

Definition at line 1619 of file i3c_regs.h.

I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_OFFSET

#define I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_OFFSET   8

Definition at line 1620 of file i3c_regs.h.

I3C_TTI_EXTCAP_HEADER_REG_OFFSET

#define I3C_TTI_EXTCAP_HEADER_REG_OFFSET   0x310

Definition at line 1613 of file i3c_regs.h.

I3C_TTI_EXTCAP_HEADER_REG_RESVAL

#define I3C_TTI_EXTCAP_HEADER_REG_RESVAL   0x59c8u

Definition at line 1614 of file i3c_regs.h.

I3C_TTI_PORTS_REG_OFFSET

#define I3C_TTI_PORTS_REG_OFFSET   0x440

Definition at line 2575 of file i3c_regs.h.

I3C_TTI_PORTS_SIZE_BYTES

#define I3C_TTI_PORTS_SIZE_BYTES   52

Definition at line 2577 of file i3c_regs.h.

I3C_TTI_PORTS_SIZE_WORDS

#define I3C_TTI_PORTS_SIZE_WORDS   13

Definition at line 2576 of file i3c_regs.h.