i3c_regs.h

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/**
 * @file
 * @brief Generated register defines for i3c
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _I3C_REG_DEFS_
#define _I3C_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Size of the Device Address Table in bus words.
#define I3C_PARAM_NUM_D_A_T_WORDS 64
 
// Size of the Device Characteristics Table in bus words.
#define I3C_PARAM_NUM_D_C_T_WORDS 128
 
// The maximum number of Virtual Targets supported.
#define I3C_PARAM_MAX_TARGETS 4
 
// The maximum number of Group Addresses supported on the Target side.
#define I3C_PARAM_MAX_GROUPS 8
 
// Number of alerts
#define I3C_PARAM_NUM_ALERTS 1
 
// Number of alerts in the primary partition
#define I3C_PARAM_NUM_ALERTS_PRIMARY 1
 
// Number of alerts in the secondary partition
#define I3C_PARAM_NUM_ALERTS_SECONDARY 0
 
// Register width
#define I3C_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define I3C_INTR_COMMON_HCI_BIT 0
#define I3C_INTR_COMMON_TARG_BIT 1
 
// Interrupt State Register
#define I3C_INTR_STATE_REG_OFFSET 0x0
#define I3C_INTR_STATE_REG_RESVAL 0x0u
#define I3C_INTR_STATE_HCI_BIT 0
#define I3C_INTR_STATE_TARG_BIT 1
 
// Interrupt Enable Register
#define I3C_INTR_ENABLE_REG_OFFSET 0x4
#define I3C_INTR_ENABLE_REG_RESVAL 0x0u
#define I3C_INTR_ENABLE_HCI_BIT 0
#define I3C_INTR_ENABLE_TARG_BIT 1
 
// Interrupt Test Register
#define I3C_INTR_TEST_REG_OFFSET 0x8
#define I3C_INTR_TEST_REG_RESVAL 0x0u
#define I3C_INTR_TEST_HCI_BIT 0
#define I3C_INTR_TEST_TARG_BIT 1
 
// Alert Test Register
#define I3C_ALERT_TEST_REG_OFFSET 0xc
#define I3C_ALERT_TEST_REG_RESVAL 0x80000000u
#define I3C_ALERT_TEST_FATAL_FAULT_BIT 0
#define I3C_ALERT_TEST_REGWEN_BIT 31
 
// IP block information, allowing software to adapt dynamically.
#define I3C_INFO_REG_OFFSET 0x10
#define I3C_INFO_REG_RESVAL 0xfffff10u
#define I3C_INFO_REVISION_MASK 0xfu
#define I3C_INFO_REVISION_OFFSET 0
#define I3C_INFO_REVISION_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INFO_REVISION_MASK, .index = I3C_INFO_REVISION_OFFSET })
#define I3C_INFO_VERSION_MASK 0xfu
#define I3C_INFO_VERSION_OFFSET 4
#define I3C_INFO_VERSION_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INFO_VERSION_MASK, .index = I3C_INFO_VERSION_OFFSET })
#define I3C_INFO_DAT_ENTRY_MAX_MASK 0x1fu
#define I3C_INFO_DAT_ENTRY_MAX_OFFSET 8
#define I3C_INFO_DAT_ENTRY_MAX_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INFO_DAT_ENTRY_MAX_MASK, .index = I3C_INFO_DAT_ENTRY_MAX_OFFSET })
#define I3C_INFO_DCT_ENTRY_MAX_MASK 0x1fu
#define I3C_INFO_DCT_ENTRY_MAX_OFFSET 13
#define I3C_INFO_DCT_ENTRY_MAX_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INFO_DCT_ENTRY_MAX_MASK, .index = I3C_INFO_DCT_ENTRY_MAX_OFFSET })
#define I3C_INFO_BUF_DWORD_MAX_MASK 0x7ffu
#define I3C_INFO_BUF_DWORD_MAX_OFFSET 18
#define I3C_INFO_BUF_DWORD_MAX_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INFO_BUF_DWORD_MAX_MASK, .index = I3C_INFO_BUF_DWORD_MAX_OFFSET })
 
// Controller-side Status register.
#define I3C_CTRL_STATUS_REG_OFFSET 0x14
#define I3C_CTRL_STATUS_REG_RESVAL 0x80000000u
#define I3C_CTRL_STATUS_PRESENT_BIT 31
 
// Controller Error counts.
#define I3C_CTRL_ERROR_REG_OFFSET 0x18
#define I3C_CTRL_ERROR_REG_RESVAL 0x0u
#define I3C_CTRL_ERROR_CE0_MASK 0xfu
#define I3C_CTRL_ERROR_CE0_OFFSET 0
#define I3C_CTRL_ERROR_CE0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE0_MASK, .index = I3C_CTRL_ERROR_CE0_OFFSET })
#define I3C_CTRL_ERROR_CE1_MASK 0xfu
#define I3C_CTRL_ERROR_CE1_OFFSET 4
#define I3C_CTRL_ERROR_CE1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE1_MASK, .index = I3C_CTRL_ERROR_CE1_OFFSET })
#define I3C_CTRL_ERROR_CE2_MASK 0xfu
#define I3C_CTRL_ERROR_CE2_OFFSET 8
#define I3C_CTRL_ERROR_CE2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE2_MASK, .index = I3C_CTRL_ERROR_CE2_OFFSET })
#define I3C_CTRL_ERROR_CE3_MASK 0xfu
#define I3C_CTRL_ERROR_CE3_OFFSET 12
#define I3C_CTRL_ERROR_CE3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_ERROR_CE3_MASK, .index = I3C_CTRL_ERROR_CE3_OFFSET })
 
// Target Control register.
#define I3C_TARG_CONTROL_REG_OFFSET 0x1c
#define I3C_TARG_CONTROL_REG_RESVAL 0x102u
#define I3C_TARG_CONTROL_EN_BIT 0
#define I3C_TARG_CONTROL_STBY_CR_SUPPORT_BIT 1
#define I3C_TARG_CONTROL_CRHDLY1_AS_MASK 0x3u
#define I3C_TARG_CONTROL_CRHDLY1_AS_OFFSET 2
#define I3C_TARG_CONTROL_CRHDLY1_AS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CONTROL_CRHDLY1_AS_MASK, .index = I3C_TARG_CONTROL_CRHDLY1_AS_OFFSET })
#define I3C_TARG_CONTROL_CRHDLY1_SET_AS_BIT 4
#define I3C_TARG_CONTROL_EN_HDR_DDR_BIT 8
#define I3C_TARG_CONTROL_HJ_REQUEST_BIT 30
#define I3C_TARG_CONTROL_SW_RESET_BIT 31
 
// Target-side Status register
#define I3C_TARG_STATUS_REG_OFFSET 0x20
#define I3C_TARG_STATUS_REG_RESVAL 0x82000000u
#define I3C_TARG_STATUS_EXT_INFO_MASK 0x7fffu
#define I3C_TARG_STATUS_EXT_INFO_OFFSET 0
#define I3C_TARG_STATUS_EXT_INFO_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_STATUS_EXT_INFO_MASK, .index = I3C_TARG_STATUS_EXT_INFO_OFFSET })
#define I3C_TARG_STATUS_EXT_PRESENT_BIT 15
#define I3C_TARG_STATUS_RSTACT_MASK 0xffu
#define I3C_TARG_STATUS_RSTACT_OFFSET 16
#define I3C_TARG_STATUS_RSTACT_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_STATUS_RSTACT_MASK, .index = I3C_TARG_STATUS_RSTACT_OFFSET })
#define I3C_TARG_STATUS_NUM_TARGETS_MASK 0x7u
#define I3C_TARG_STATUS_NUM_TARGETS_OFFSET 24
#define I3C_TARG_STATUS_NUM_TARGETS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_STATUS_NUM_TARGETS_MASK, .index = I3C_TARG_STATUS_NUM_TARGETS_OFFSET })
#define I3C_TARG_STATUS_VTM_BIT 27
#define I3C_TARG_STATUS_PROTOCOL_ERROR_BIT 28
#define I3C_TARG_STATUS_CONNECTED_BIT 29
#define I3C_TARG_STATUS_ACTIVE_BIT 30
#define I3C_TARG_STATUS_PRESENT_BIT 31
 
// Target data sink control.
#define I3C_TARG_SINK_CONTROL_REG_OFFSET 0x24
#define I3C_TARG_SINK_CONTROL_REG_RESVAL 0x0u
#define I3C_TARG_SINK_CONTROL_BUFFER_MASK 0x7u
#define I3C_TARG_SINK_CONTROL_BUFFER_OFFSET 12
#define I3C_TARG_SINK_CONTROL_BUFFER_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_SINK_CONTROL_BUFFER_MASK, .index = I3C_TARG_SINK_CONTROL_BUFFER_OFFSET })
#define I3C_TARG_SINK_CONTROL_LENGTH_MASK 0x7ffu
#define I3C_TARG_SINK_CONTROL_LENGTH_OFFSET 16
#define I3C_TARG_SINK_CONTROL_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_SINK_CONTROL_LENGTH_MASK, .index = I3C_TARG_SINK_CONTROL_LENGTH_OFFSET })
#define I3C_TARG_SINK_CONTROL_START_BIT 31
 
// Target data sink status.
#define I3C_TARG_SINK_STATUS_REG_OFFSET 0x28
#define I3C_TARG_SINK_STATUS_REG_RESVAL 0x0u
#define I3C_TARG_SINK_STATUS_ACTIVE_BIT 0
#define I3C_TARG_SINK_STATUS_ERROR_BIT 1
#define I3C_TARG_SINK_STATUS_LENGTH_MASK 0x7ffu
#define I3C_TARG_SINK_STATUS_LENGTH_OFFSET 16
#define I3C_TARG_SINK_STATUS_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_SINK_STATUS_LENGTH_MASK, .index = I3C_TARG_SINK_STATUS_LENGTH_OFFSET })
 
// Reset detector control.
#define I3C_RESET_DET_CTRL_REG_OFFSET 0x2c
#define I3C_RESET_DET_CTRL_REG_RESVAL 0x0u
#define I3C_RESET_DET_CTRL_SLEEP_REQ_BIT 1
#define I3C_RESET_DET_CTRL_WAKE_ACK_BIT 16
#define I3C_RESET_DET_CTRL_RST_PERIPH_EN_BIT 20
#define I3C_RESET_DET_CTRL_RST_TARGET_EN_BIT 21
 
// Reset detector status.
#define I3C_RESET_DET_STATUS_REG_OFFSET 0x30
#define I3C_RESET_DET_STATUS_REG_RESVAL 0x0u
#define I3C_RESET_DET_STATUS_ACTIVE_BIT 0
#define I3C_RESET_DET_STATUS_WAKE_UP_BIT 1
#define I3C_RESET_DET_STATUS_RST_PERIPH_BIT 2
#define I3C_RESET_DET_STATUS_RST_TARGET_BIT 3
 
// Controller Timing Parameters for Start and stoP.
#define I3C_CTRL_TIME_SP_REG_OFFSET 0x34
#define I3C_CTRL_TIME_SP_REG_RESVAL 0x3ff03ffu
#define I3C_CTRL_TIME_SP_TCBP_DIV2_MASK 0x3ffu
#define I3C_CTRL_TIME_SP_TCBP_DIV2_OFFSET 0
#define I3C_CTRL_TIME_SP_TCBP_DIV2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SP_TCBP_DIV2_MASK, .index = I3C_CTRL_TIME_SP_TCBP_DIV2_OFFSET })
#define I3C_CTRL_TIME_SP_TCAS_DIV2_MASK 0x3ffu
#define I3C_CTRL_TIME_SP_TCAS_DIV2_OFFSET 16
#define I3C_CTRL_TIME_SP_TCAS_DIV2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SP_TCAS_DIV2_MASK, .index = I3C_CTRL_TIME_SP_TCAS_DIV2_OFFSET })
 
// Controller Timing Parameters for Open Drain signaling.
#define I3C_CTRL_TIME_OD_REG_OFFSET 0x38
#define I3C_CTRL_TIME_OD_REG_RESVAL 0x3ff03ffu
#define I3C_CTRL_TIME_OD_SCLLO_DIV2_MASK 0x3ffu
#define I3C_CTRL_TIME_OD_SCLLO_DIV2_OFFSET 0
#define I3C_CTRL_TIME_OD_SCLLO_DIV2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_OD_SCLLO_DIV2_MASK, .index = I3C_CTRL_TIME_OD_SCLLO_DIV2_OFFSET })
#define I3C_CTRL_TIME_OD_SCLHI_DIV2_MASK 0x3ffu
#define I3C_CTRL_TIME_OD_SCLHI_DIV2_OFFSET 16
#define I3C_CTRL_TIME_OD_SCLHI_DIV2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_OD_SCLHI_DIV2_MASK, .index = I3C_CTRL_TIME_OD_SCLHI_DIV2_OFFSET })
 
// Controller Timing Parameters for SDR/HDR-DDR Push-Pull SCL High signaling.
#define I3C_CTRL_TIME_PP_REG_OFFSET 0x3c
#define I3C_CTRL_TIME_PP_REG_RESVAL 0x3ff83ffu
#define I3C_CTRL_TIME_PP_TCHH_MASK 0x3ffu
#define I3C_CTRL_TIME_PP_TCHH_OFFSET 0
#define I3C_CTRL_TIME_PP_TCHH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_PP_TCHH_MASK, .index = I3C_CTRL_TIME_PP_TCHH_OFFSET })
#define I3C_CTRL_TIME_PP_HCEXT_BIT 15
#define I3C_CTRL_TIME_PP_TCHS_MASK 0x3ffu
#define I3C_CTRL_TIME_PP_TCHS_OFFSET 16
#define I3C_CTRL_TIME_PP_TCHS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_PP_TCHS_MASK, .index = I3C_CTRL_TIME_PP_TCHS_OFFSET })
 
// Controller Timing Parameters for SDR0/HDR-DDR Push-Pull SCL Low signaling.
#define I3C_CTRL_TIME_SDR0_REG_OFFSET 0x40
#define I3C_CTRL_TIME_SDR0_REG_RESVAL 0x3ff03ffu
#define I3C_CTRL_TIME_SDR0_TCLH_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR0_TCLH_OFFSET 0
#define I3C_CTRL_TIME_SDR0_TCLH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR0_TCLH_MASK, .index = I3C_CTRL_TIME_SDR0_TCLH_OFFSET })
#define I3C_CTRL_TIME_SDR0_TCLS_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR0_TCLS_OFFSET 16
#define I3C_CTRL_TIME_SDR0_TCLS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR0_TCLS_MASK, .index = I3C_CTRL_TIME_SDR0_TCLS_OFFSET })
 
// Controller Timing Parameters for SDR1 Push-Pull SCL Low signaling.
#define I3C_CTRL_TIME_SDR1_REG_OFFSET 0x44
#define I3C_CTRL_TIME_SDR1_REG_RESVAL 0x3ff03ffu
#define I3C_CTRL_TIME_SDR1_TCLH_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR1_TCLH_OFFSET 0
#define I3C_CTRL_TIME_SDR1_TCLH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR1_TCLH_MASK, .index = I3C_CTRL_TIME_SDR1_TCLH_OFFSET })
#define I3C_CTRL_TIME_SDR1_TCLS_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR1_TCLS_OFFSET 16
#define I3C_CTRL_TIME_SDR1_TCLS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR1_TCLS_MASK, .index = I3C_CTRL_TIME_SDR1_TCLS_OFFSET })
 
// Controller Timing Parameters for SDR2 Push-Pull SCL Low signaling.
#define I3C_CTRL_TIME_SDR2_REG_OFFSET 0x48
#define I3C_CTRL_TIME_SDR2_REG_RESVAL 0x3ff03ffu
#define I3C_CTRL_TIME_SDR2_TCLH_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR2_TCLH_OFFSET 0
#define I3C_CTRL_TIME_SDR2_TCLH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR2_TCLH_MASK, .index = I3C_CTRL_TIME_SDR2_TCLH_OFFSET })
#define I3C_CTRL_TIME_SDR2_TCLS_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR2_TCLS_OFFSET 16
#define I3C_CTRL_TIME_SDR2_TCLS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR2_TCLS_MASK, .index = I3C_CTRL_TIME_SDR2_TCLS_OFFSET })
 
// Controller Timing Parameters for SDR3 Push-Pull SCL Low signaling.
#define I3C_CTRL_TIME_SDR3_REG_OFFSET 0x4c
#define I3C_CTRL_TIME_SDR3_REG_RESVAL 0x3ff03ffu
#define I3C_CTRL_TIME_SDR3_TCLH_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR3_TCLH_OFFSET 0
#define I3C_CTRL_TIME_SDR3_TCLH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR3_TCLH_MASK, .index = I3C_CTRL_TIME_SDR3_TCLH_OFFSET })
#define I3C_CTRL_TIME_SDR3_TCLS_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR3_TCLS_OFFSET 16
#define I3C_CTRL_TIME_SDR3_TCLS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR3_TCLS_MASK, .index = I3C_CTRL_TIME_SDR3_TCLS_OFFSET })
 
// Controller Timing Parameters for SDR4 Push-Pull SCL Low signaling.
#define I3C_CTRL_TIME_SDR4_REG_OFFSET 0x50
#define I3C_CTRL_TIME_SDR4_REG_RESVAL 0x3ff03ffu
#define I3C_CTRL_TIME_SDR4_TCLH_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR4_TCLH_OFFSET 0
#define I3C_CTRL_TIME_SDR4_TCLH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR4_TCLH_MASK, .index = I3C_CTRL_TIME_SDR4_TCLH_OFFSET })
#define I3C_CTRL_TIME_SDR4_TCLS_MASK 0x3ffu
#define I3C_CTRL_TIME_SDR4_TCLS_OFFSET 16
#define I3C_CTRL_TIME_SDR4_TCLS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_SDR4_TCLS_MASK, .index = I3C_CTRL_TIME_SDR4_TCLS_OFFSET })
 
// Controller Timing Parameters for I2C Fast Mode Plus signaling.
#define I3C_CTRL_TIME_FMP_REG_OFFSET 0x54
#define I3C_CTRL_TIME_FMP_REG_RESVAL 0x3ff03ffu
#define I3C_CTRL_TIME_FMP_SCLLO_DIV2_MASK 0x3ffu
#define I3C_CTRL_TIME_FMP_SCLLO_DIV2_OFFSET 0
#define I3C_CTRL_TIME_FMP_SCLLO_DIV2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FMP_SCLLO_DIV2_MASK, .index = I3C_CTRL_TIME_FMP_SCLLO_DIV2_OFFSET })
#define I3C_CTRL_TIME_FMP_SCLHI_DIV2_MASK 0x3ffu
#define I3C_CTRL_TIME_FMP_SCLHI_DIV2_OFFSET 16
#define I3C_CTRL_TIME_FMP_SCLHI_DIV2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FMP_SCLHI_DIV2_MASK, .index = I3C_CTRL_TIME_FMP_SCLHI_DIV2_OFFSET })
 
// Controller Timing Parameters for I2C Fast Mode signaling.
#define I3C_CTRL_TIME_FM_REG_OFFSET 0x58
#define I3C_CTRL_TIME_FM_REG_RESVAL 0x3ff03ffu
#define I3C_CTRL_TIME_FM_SCLLO_DIV2_MASK 0x3ffu
#define I3C_CTRL_TIME_FM_SCLLO_DIV2_OFFSET 0
#define I3C_CTRL_TIME_FM_SCLLO_DIV2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FM_SCLLO_DIV2_MASK, .index = I3C_CTRL_TIME_FM_SCLLO_DIV2_OFFSET })
#define I3C_CTRL_TIME_FM_SCLHI_DIV2_MASK 0x3ffu
#define I3C_CTRL_TIME_FM_SCLHI_DIV2_OFFSET 16
#define I3C_CTRL_TIME_FM_SCLHI_DIV2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TIME_FM_SCLHI_DIV2_MASK, .index = I3C_CTRL_TIME_FM_SCLHI_DIV2_OFFSET })
 
// Interval Timers 0 register.
#define I3C_INTERVAL_TIME0_REG_OFFSET 0x5c
#define I3C_INTERVAL_TIME0_REG_RESVAL 0x0u
#define I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_MASK 0xffu
#define I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_OFFSET 0
#define I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_MASK, .index = I3C_INTERVAL_TIME0_TARG_BUS_AVAIL_OFFSET })
#define I3C_INTERVAL_TIME0_READ_STALLED_MASK 0xffu
#define I3C_INTERVAL_TIME0_READ_STALLED_OFFSET 8
#define I3C_INTERVAL_TIME0_READ_STALLED_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_READ_STALLED_MASK, .index = I3C_INTERVAL_TIME0_READ_STALLED_OFFSET })
#define I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_MASK 0xffu
#define I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_OFFSET 16
#define I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_MASK, .index = I3C_INTERVAL_TIME0_CTRL_BUS_AVAIL_OFFSET })
#define I3C_INTERVAL_TIME0_DEAD_BUS_MASK 0xffu
#define I3C_INTERVAL_TIME0_DEAD_BUS_OFFSET 24
#define I3C_INTERVAL_TIME0_DEAD_BUS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME0_DEAD_BUS_MASK, .index = I3C_INTERVAL_TIME0_DEAD_BUS_OFFSET })
 
// Interval Timers 1 register.
#define I3C_INTERVAL_TIME1_REG_OFFSET 0x60
#define I3C_INTERVAL_TIME1_REG_RESVAL 0x0u
#define I3C_INTERVAL_TIME1_COMMAND_RETRY_MASK 0xffu
#define I3C_INTERVAL_TIME1_COMMAND_RETRY_OFFSET 0
#define I3C_INTERVAL_TIME1_COMMAND_RETRY_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_COMMAND_RETRY_MASK, .index = I3C_INTERVAL_TIME1_COMMAND_RETRY_OFFSET })
#define I3C_INTERVAL_TIME1_TARG_BUS_IDLE_MASK 0xffu
#define I3C_INTERVAL_TIME1_TARG_BUS_IDLE_OFFSET 8
#define I3C_INTERVAL_TIME1_TARG_BUS_IDLE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_TARG_BUS_IDLE_MASK, .index = I3C_INTERVAL_TIME1_TARG_BUS_IDLE_OFFSET })
#define I3C_INTERVAL_TIME1_TE0_RECOV_MASK 0xffu
#define I3C_INTERVAL_TIME1_TE0_RECOV_OFFSET 16
#define I3C_INTERVAL_TIME1_TE0_RECOV_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_TE0_RECOV_MASK, .index = I3C_INTERVAL_TIME1_TE0_RECOV_OFFSET })
#define I3C_INTERVAL_TIME1_TARG_TRX_RST_MASK 0xffu
#define I3C_INTERVAL_TIME1_TARG_TRX_RST_OFFSET 24
#define I3C_INTERVAL_TIME1_TARG_TRX_RST_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INTERVAL_TIME1_TARG_TRX_RST_MASK, .index = I3C_INTERVAL_TIME1_TARG_TRX_RST_OFFSET })
 
// PHY configuration
#define I3C_PHY_CONFIG_REG_OFFSET 0x64
#define I3C_PHY_CONFIG_REG_RESVAL 0x1100003u
#define I3C_PHY_CONFIG_SCL_HK_EN_BIT 0
#define I3C_PHY_CONFIG_SDA_HK_EN_BIT 1
#define I3C_PHY_CONFIG_CTRL_SDA_BIT 20
#define I3C_PHY_CONFIG_CTRL_SDA_PU_EN_BIT 21
#define I3C_PHY_CONFIG_CTRL_SDA_OD_EN_BIT 22
#define I3C_PHY_CONFIG_CTRL_SDA_PP_EN_BIT 23
#define I3C_PHY_CONFIG_CTRL_SCL_BIT 24
#define I3C_PHY_CONFIG_CTRL_SCL_PU_EN_BIT 25
#define I3C_PHY_CONFIG_CTRL_SCL_PP_EN_BIT 27
#define I3C_PHY_CONFIG_CTRL_DIRECT_DRIVE_EN_BIT 31
 
// Blocked target addresses.
#define I3C_BLOCKED_ADDR_REG_OFFSET 0x68
#define I3C_BLOCKED_ADDR_REG_RESVAL 0x7f007fu
#define I3C_BLOCKED_ADDR_ADDR0_MASK 0x7fu
#define I3C_BLOCKED_ADDR_ADDR0_OFFSET 0
#define I3C_BLOCKED_ADDR_ADDR0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_ADDR0_MASK, .index = I3C_BLOCKED_ADDR_ADDR0_OFFSET })
#define I3C_BLOCKED_ADDR_MASK0_MASK 0x7fu
#define I3C_BLOCKED_ADDR_MASK0_OFFSET 8
#define I3C_BLOCKED_ADDR_MASK0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_MASK0_MASK, .index = I3C_BLOCKED_ADDR_MASK0_OFFSET })
#define I3C_BLOCKED_ADDR_ADDR1_MASK 0x7fu
#define I3C_BLOCKED_ADDR_ADDR1_OFFSET 16
#define I3C_BLOCKED_ADDR_ADDR1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_ADDR1_MASK, .index = I3C_BLOCKED_ADDR_ADDR1_OFFSET })
#define I3C_BLOCKED_ADDR_MASK1_MASK 0x7fu
#define I3C_BLOCKED_ADDR_MASK1_OFFSET 24
#define I3C_BLOCKED_ADDR_MASK1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_BLOCKED_ADDR_MASK1_MASK, .index = I3C_BLOCKED_ADDR_MASK1_OFFSET })
 
// Buffer control
#define I3C_BUFFER_CTRL_REG_OFFSET 0x6c
#define I3C_BUFFER_CTRL_REG_RESVAL 0x0u
#define I3C_BUFFER_CTRL_SW_ADDR_HI_MASK 0x3u
#define I3C_BUFFER_CTRL_SW_ADDR_HI_OFFSET 28
#define I3C_BUFFER_CTRL_SW_ADDR_HI_FIELD \
  ((bitfield_field32_t) { .mask = I3C_BUFFER_CTRL_SW_ADDR_HI_MASK, .index = I3C_BUFFER_CTRL_SW_ADDR_HI_OFFSET })
#define I3C_BUFFER_CTRL_CLEAR_BIT 31
 
// Buffer status
#define I3C_BUFFER_STATUS_REG_OFFSET 0x70
#define I3C_BUFFER_STATUS_REG_RESVAL 0x0u
#define I3C_BUFFER_STATUS_TTIQ_ERR_BIT 30
#define I3C_BUFFER_STATUS_HCIQ_ERR_BIT 31
 
// Controller TX Buffer Configuration
#define I3C_CTRL_TXBUF_CONFIG_REG_OFFSET 0x74
#define I3C_CTRL_TXBUF_CONFIG_REG_RESVAL 0x607f0000u
#define I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_MASK, .index = I3C_CTRL_TXBUF_CONFIG_MIN_ADDR_OFFSET })
#define I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_OFFSET 16
#define I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_MASK, .index = I3C_CTRL_TXBUF_CONFIG_MAX_ADDR_OFFSET })
#define I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_MASK 0x7u
#define I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_OFFSET 28
#define I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_MASK, .index = I3C_CTRL_TXBUF_CONFIG_SIZE_VAL_OFFSET })
 
// Controller TX Buffer State.
#define I3C_CTRL_TXBUF_STATE_REG_OFFSET 0x78
#define I3C_CTRL_TXBUF_STATE_REG_RESVAL 0x0u
#define I3C_CTRL_TXBUF_STATE_WPTR_MASK 0x3ffu
#define I3C_CTRL_TXBUF_STATE_WPTR_OFFSET 0
#define I3C_CTRL_TXBUF_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_STATE_WPTR_MASK, .index = I3C_CTRL_TXBUF_STATE_WPTR_OFFSET })
#define I3C_CTRL_TXBUF_STATE_RPTR_MASK 0x3ffu
#define I3C_CTRL_TXBUF_STATE_RPTR_OFFSET 16
#define I3C_CTRL_TXBUF_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_TXBUF_STATE_RPTR_MASK, .index = I3C_CTRL_TXBUF_STATE_RPTR_OFFSET })
#define I3C_CTRL_TXBUF_STATE_PRE_BIT 30
#define I3C_CTRL_TXBUF_STATE_FULL_BIT 31
 
// Controller RX Buffer Configuration
#define I3C_CTRL_RXBUF_CONFIG_REG_OFFSET 0x7c
#define I3C_CTRL_RXBUF_CONFIG_REG_RESVAL 0x60ff0080u
#define I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_MASK, .index = I3C_CTRL_RXBUF_CONFIG_MIN_ADDR_OFFSET })
#define I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_OFFSET 16
#define I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_MASK, .index = I3C_CTRL_RXBUF_CONFIG_MAX_ADDR_OFFSET })
#define I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_MASK 0x7u
#define I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_OFFSET 28
#define I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_MASK, .index = I3C_CTRL_RXBUF_CONFIG_SIZE_VAL_OFFSET })
 
// Controller RX Buffer State.
#define I3C_CTRL_RXBUF_STATE_REG_OFFSET 0x80
#define I3C_CTRL_RXBUF_STATE_REG_RESVAL 0x800080u
#define I3C_CTRL_RXBUF_STATE_WPTR_MASK 0x3ffu
#define I3C_CTRL_RXBUF_STATE_WPTR_OFFSET 0
#define I3C_CTRL_RXBUF_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_STATE_WPTR_MASK, .index = I3C_CTRL_RXBUF_STATE_WPTR_OFFSET })
#define I3C_CTRL_RXBUF_STATE_RPTR_MASK 0x3ffu
#define I3C_CTRL_RXBUF_STATE_RPTR_OFFSET 16
#define I3C_CTRL_RXBUF_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_RXBUF_STATE_RPTR_MASK, .index = I3C_CTRL_RXBUF_STATE_RPTR_OFFSET })
#define I3C_CTRL_RXBUF_STATE_PRE_BIT 30
#define I3C_CTRL_RXBUF_STATE_FULL_BIT 31
 
// Command Queue Configuration.
#define I3C_COMMAND_QUEUE_CONFIG_REG_OFFSET 0x84
#define I3C_COMMAND_QUEUE_CONFIG_REG_RESVAL 0x1011f100u
#define I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_MASK, .index = I3C_COMMAND_QUEUE_CONFIG_MIN_ADDR_OFFSET })
#define I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_OFFSET 12
#define I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_MASK, .index = I3C_COMMAND_QUEUE_CONFIG_MAX_ADDR_OFFSET })
#define I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_MASK 0xffu
#define I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_OFFSET 24
#define I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_MASK, .index = I3C_COMMAND_QUEUE_CONFIG_SIZE_VAL_OFFSET })
 
// Command Queue State.
#define I3C_COMMAND_QUEUE_STATE_REG_OFFSET 0x88
#define I3C_COMMAND_QUEUE_STATE_REG_RESVAL 0x1000100u
#define I3C_COMMAND_QUEUE_STATE_WPTR_MASK 0x3ffu
#define I3C_COMMAND_QUEUE_STATE_WPTR_OFFSET 0
#define I3C_COMMAND_QUEUE_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_STATE_WPTR_MASK, .index = I3C_COMMAND_QUEUE_STATE_WPTR_OFFSET })
#define I3C_COMMAND_QUEUE_STATE_RPTR_MASK 0x3ffu
#define I3C_COMMAND_QUEUE_STATE_RPTR_OFFSET 16
#define I3C_COMMAND_QUEUE_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_COMMAND_QUEUE_STATE_RPTR_MASK, .index = I3C_COMMAND_QUEUE_STATE_RPTR_OFFSET })
#define I3C_COMMAND_QUEUE_STATE_PRE_BIT 30
#define I3C_COMMAND_QUEUE_STATE_FULL_BIT 31
 
// Response Queue Configuration.
#define I3C_RESPONSE_QUEUE_CONFIG_REG_OFFSET 0x8c
#define I3C_RESPONSE_QUEUE_CONFIG_REG_RESVAL 0x1012f120u
#define I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_MASK, .index = I3C_RESPONSE_QUEUE_CONFIG_MIN_ADDR_OFFSET })
#define I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_OFFSET 12
#define I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_MASK, .index = I3C_RESPONSE_QUEUE_CONFIG_MAX_ADDR_OFFSET })
#define I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_MASK 0xffu
#define I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_OFFSET 24
#define I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_MASK, .index = I3C_RESPONSE_QUEUE_CONFIG_SIZE_VAL_OFFSET })
 
// Response Queue State.
#define I3C_RESPONSE_QUEUE_STATE_REG_OFFSET 0x90
#define I3C_RESPONSE_QUEUE_STATE_REG_RESVAL 0x1200120u
#define I3C_RESPONSE_QUEUE_STATE_WPTR_MASK 0x3ffu
#define I3C_RESPONSE_QUEUE_STATE_WPTR_OFFSET 0
#define I3C_RESPONSE_QUEUE_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_STATE_WPTR_MASK, .index = I3C_RESPONSE_QUEUE_STATE_WPTR_OFFSET })
#define I3C_RESPONSE_QUEUE_STATE_RPTR_MASK 0x3ffu
#define I3C_RESPONSE_QUEUE_STATE_RPTR_OFFSET 16
#define I3C_RESPONSE_QUEUE_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_RESPONSE_QUEUE_STATE_RPTR_MASK, .index = I3C_RESPONSE_QUEUE_STATE_RPTR_OFFSET })
#define I3C_RESPONSE_QUEUE_STATE_PRE_BIT 30
#define I3C_RESPONSE_QUEUE_STATE_FULL_BIT 31
 
// In-Band Interrupt Queue Configuration.
#define I3C_IBI_CONFIG_REG_OFFSET 0x94
#define I3C_IBI_CONFIG_REG_RESVAL 0x141af130u
#define I3C_IBI_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_IBI_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_IBI_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_CONFIG_MIN_ADDR_MASK, .index = I3C_IBI_CONFIG_MIN_ADDR_OFFSET })
#define I3C_IBI_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_IBI_CONFIG_MAX_ADDR_OFFSET 12
#define I3C_IBI_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_CONFIG_MAX_ADDR_MASK, .index = I3C_IBI_CONFIG_MAX_ADDR_OFFSET })
#define I3C_IBI_CONFIG_SIZE_VAL_MASK 0xffu
#define I3C_IBI_CONFIG_SIZE_VAL_OFFSET 24
#define I3C_IBI_CONFIG_SIZE_VAL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_CONFIG_SIZE_VAL_MASK, .index = I3C_IBI_CONFIG_SIZE_VAL_OFFSET })
 
// In-Band Interrupt Queue State.
#define I3C_IBI_STATE_REG_OFFSET 0x98
#define I3C_IBI_STATE_REG_RESVAL 0x1300130u
#define I3C_IBI_STATE_WPTR_MASK 0x3ffu
#define I3C_IBI_STATE_WPTR_OFFSET 0
#define I3C_IBI_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_STATE_WPTR_MASK, .index = I3C_IBI_STATE_WPTR_OFFSET })
#define I3C_IBI_STATE_RPTR_MASK 0x3ffu
#define I3C_IBI_STATE_RPTR_OFFSET 16
#define I3C_IBI_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_STATE_RPTR_MASK, .index = I3C_IBI_STATE_RPTR_OFFSET })
#define I3C_IBI_STATE_PRE_BIT 30
#define I3C_IBI_STATE_FULL_BIT 31
 
// In-Band Status Descriptor FIFO Configuration.
#define I3C_IBI_STAT_CONFIG_REG_OFFSET 0x9c
#define I3C_IBI_STAT_CONFIG_REG_RESVAL 0x1cf1b0u
#define I3C_IBI_STAT_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_IBI_STAT_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_IBI_STAT_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_STAT_CONFIG_MIN_ADDR_MASK, .index = I3C_IBI_STAT_CONFIG_MIN_ADDR_OFFSET })
#define I3C_IBI_STAT_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_IBI_STAT_CONFIG_MAX_ADDR_OFFSET 12
#define I3C_IBI_STAT_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_STAT_CONFIG_MAX_ADDR_MASK, .index = I3C_IBI_STAT_CONFIG_MAX_ADDR_OFFSET })
 
// In-Band Status Descriptor FIFO State.
#define I3C_IBI_STAT_STATE_REG_OFFSET 0xa0
#define I3C_IBI_STAT_STATE_REG_RESVAL 0x1b001b0u
#define I3C_IBI_STAT_STATE_WPTR_MASK 0x3ffu
#define I3C_IBI_STAT_STATE_WPTR_OFFSET 0
#define I3C_IBI_STAT_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_STAT_STATE_WPTR_MASK, .index = I3C_IBI_STAT_STATE_WPTR_OFFSET })
#define I3C_IBI_STAT_STATE_RPTR_MASK 0x3ffu
#define I3C_IBI_STAT_STATE_RPTR_OFFSET 16
#define I3C_IBI_STAT_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_STAT_STATE_RPTR_MASK, .index = I3C_IBI_STAT_STATE_RPTR_OFFSET })
#define I3C_IBI_STAT_STATE_PRE_BIT 30
#define I3C_IBI_STAT_STATE_FULL_BIT 31
 
// Target TX Buffer Configuration. (common parameters)
#define I3C_TARG_TXBUF_CONFIG_MIN_ADDR_FIELD_WIDTH 10
#define I3C_TARG_TXBUF_CONFIG_MAX_ADDR_FIELD_WIDTH 10
#define I3C_TARG_TXBUF_CONFIG_MULTIREG_COUNT 4
 
// Target TX Buffer Configuration.
#define I3C_TARG_TXBUF_CONFIG_0_REG_OFFSET 0xa4
#define I3C_TARG_TXBUF_CONFIG_0_REG_RESVAL 0x20f01d0u
#define I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_MASK 0x3ffu
#define I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_OFFSET 0
#define I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_MASK, .index = I3C_TARG_TXBUF_CONFIG_0_MIN_ADDR_0_OFFSET })
#define I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_MASK 0x3ffu
#define I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_OFFSET 16
#define I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_MASK, .index = I3C_TARG_TXBUF_CONFIG_0_MAX_ADDR_0_OFFSET })
 
// Target TX Buffer Configuration.
#define I3C_TARG_TXBUF_CONFIG_1_REG_OFFSET 0xa8
#define I3C_TARG_TXBUF_CONFIG_1_REG_RESVAL 0x24f0210u
#define I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_MASK 0x3ffu
#define I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_OFFSET 0
#define I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_MASK, .index = I3C_TARG_TXBUF_CONFIG_1_MIN_ADDR_1_OFFSET })
#define I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_MASK 0x3ffu
#define I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_OFFSET 16
#define I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_MASK, .index = I3C_TARG_TXBUF_CONFIG_1_MAX_ADDR_1_OFFSET })
 
// Target TX Buffer Configuration.
#define I3C_TARG_TXBUF_CONFIG_2_REG_OFFSET 0xac
#define I3C_TARG_TXBUF_CONFIG_2_REG_RESVAL 0x28f0250u
#define I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_MASK 0x3ffu
#define I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_OFFSET 0
#define I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_MASK, .index = I3C_TARG_TXBUF_CONFIG_2_MIN_ADDR_2_OFFSET })
#define I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_MASK 0x3ffu
#define I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_OFFSET 16
#define I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_MASK, .index = I3C_TARG_TXBUF_CONFIG_2_MAX_ADDR_2_OFFSET })
 
// Target TX Buffer Configuration.
#define I3C_TARG_TXBUF_CONFIG_3_REG_OFFSET 0xb0
#define I3C_TARG_TXBUF_CONFIG_3_REG_RESVAL 0x2cf0290u
#define I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_MASK 0x3ffu
#define I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_OFFSET 0
#define I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_MASK, .index = I3C_TARG_TXBUF_CONFIG_3_MIN_ADDR_3_OFFSET })
#define I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_MASK 0x3ffu
#define I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_OFFSET 16
#define I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_MASK, .index = I3C_TARG_TXBUF_CONFIG_3_MAX_ADDR_3_OFFSET })
 
// Target 0 TX Buffer State. (common parameters)
#define I3C_TARG_TXBUF_STATE_WPTR_FIELD_WIDTH 10
#define I3C_TARG_TXBUF_STATE_RPTR_FIELD_WIDTH 10
#define I3C_TARG_TXBUF_STATE_PRE_FIELD_WIDTH 1
#define I3C_TARG_TXBUF_STATE_FULL_FIELD_WIDTH 1
#define I3C_TARG_TXBUF_STATE_MULTIREG_COUNT 4
 
// Target 0 TX Buffer State.
#define I3C_TARG_TXBUF_STATE_0_REG_OFFSET 0xb4
#define I3C_TARG_TXBUF_STATE_0_REG_RESVAL 0x1d001d0u
#define I3C_TARG_TXBUF_STATE_0_WPTR_0_MASK 0x3ffu
#define I3C_TARG_TXBUF_STATE_0_WPTR_0_OFFSET 0
#define I3C_TARG_TXBUF_STATE_0_WPTR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_0_WPTR_0_MASK, .index = I3C_TARG_TXBUF_STATE_0_WPTR_0_OFFSET })
#define I3C_TARG_TXBUF_STATE_0_RPTR_0_MASK 0x3ffu
#define I3C_TARG_TXBUF_STATE_0_RPTR_0_OFFSET 16
#define I3C_TARG_TXBUF_STATE_0_RPTR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_0_RPTR_0_MASK, .index = I3C_TARG_TXBUF_STATE_0_RPTR_0_OFFSET })
#define I3C_TARG_TXBUF_STATE_0_PRE_0_BIT 30
#define I3C_TARG_TXBUF_STATE_0_FULL_0_BIT 31
 
// Target 0 TX Buffer State.
#define I3C_TARG_TXBUF_STATE_1_REG_OFFSET 0xb8
#define I3C_TARG_TXBUF_STATE_1_REG_RESVAL 0x2100210u
#define I3C_TARG_TXBUF_STATE_1_WPTR_1_MASK 0x3ffu
#define I3C_TARG_TXBUF_STATE_1_WPTR_1_OFFSET 0
#define I3C_TARG_TXBUF_STATE_1_WPTR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_1_WPTR_1_MASK, .index = I3C_TARG_TXBUF_STATE_1_WPTR_1_OFFSET })
#define I3C_TARG_TXBUF_STATE_1_RPTR_1_MASK 0x3ffu
#define I3C_TARG_TXBUF_STATE_1_RPTR_1_OFFSET 16
#define I3C_TARG_TXBUF_STATE_1_RPTR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_1_RPTR_1_MASK, .index = I3C_TARG_TXBUF_STATE_1_RPTR_1_OFFSET })
#define I3C_TARG_TXBUF_STATE_1_PRE_1_BIT 30
#define I3C_TARG_TXBUF_STATE_1_FULL_1_BIT 31
 
// Target 0 TX Buffer State.
#define I3C_TARG_TXBUF_STATE_2_REG_OFFSET 0xbc
#define I3C_TARG_TXBUF_STATE_2_REG_RESVAL 0x2500250u
#define I3C_TARG_TXBUF_STATE_2_WPTR_2_MASK 0x3ffu
#define I3C_TARG_TXBUF_STATE_2_WPTR_2_OFFSET 0
#define I3C_TARG_TXBUF_STATE_2_WPTR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_2_WPTR_2_MASK, .index = I3C_TARG_TXBUF_STATE_2_WPTR_2_OFFSET })
#define I3C_TARG_TXBUF_STATE_2_RPTR_2_MASK 0x3ffu
#define I3C_TARG_TXBUF_STATE_2_RPTR_2_OFFSET 16
#define I3C_TARG_TXBUF_STATE_2_RPTR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_2_RPTR_2_MASK, .index = I3C_TARG_TXBUF_STATE_2_RPTR_2_OFFSET })
#define I3C_TARG_TXBUF_STATE_2_PRE_2_BIT 30
#define I3C_TARG_TXBUF_STATE_2_FULL_2_BIT 31
 
// Target 0 TX Buffer State.
#define I3C_TARG_TXBUF_STATE_3_REG_OFFSET 0xc0
#define I3C_TARG_TXBUF_STATE_3_REG_RESVAL 0x2900290u
#define I3C_TARG_TXBUF_STATE_3_WPTR_3_MASK 0x3ffu
#define I3C_TARG_TXBUF_STATE_3_WPTR_3_OFFSET 0
#define I3C_TARG_TXBUF_STATE_3_WPTR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_3_WPTR_3_MASK, .index = I3C_TARG_TXBUF_STATE_3_WPTR_3_OFFSET })
#define I3C_TARG_TXBUF_STATE_3_RPTR_3_MASK 0x3ffu
#define I3C_TARG_TXBUF_STATE_3_RPTR_3_OFFSET 16
#define I3C_TARG_TXBUF_STATE_3_RPTR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXBUF_STATE_3_RPTR_3_MASK, .index = I3C_TARG_TXBUF_STATE_3_RPTR_3_OFFSET })
#define I3C_TARG_TXBUF_STATE_3_PRE_3_BIT 30
#define I3C_TARG_TXBUF_STATE_3_FULL_3_BIT 31
 
// Target RX Buffer Configuration
#define I3C_TARG_RXBUF_CONFIG_REG_OFFSET 0xc4
#define I3C_TARG_RXBUF_CONFIG_REG_RESVAL 0x36f02d0u
#define I3C_TARG_RXBUF_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_TARG_RXBUF_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_TARG_RXBUF_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_RXBUF_CONFIG_MIN_ADDR_OFFSET })
#define I3C_TARG_RXBUF_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_TARG_RXBUF_CONFIG_MAX_ADDR_OFFSET 16
#define I3C_TARG_RXBUF_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_RXBUF_CONFIG_MAX_ADDR_OFFSET })
 
// Target RX Buffer State.
#define I3C_TARG_RXBUF_STATE_REG_OFFSET 0xc8
#define I3C_TARG_RXBUF_STATE_REG_RESVAL 0x2d002d0u
#define I3C_TARG_RXBUF_STATE_WPTR_MASK 0x3ffu
#define I3C_TARG_RXBUF_STATE_WPTR_OFFSET 0
#define I3C_TARG_RXBUF_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_STATE_WPTR_MASK, .index = I3C_TARG_RXBUF_STATE_WPTR_OFFSET })
#define I3C_TARG_RXBUF_STATE_RPTR_MASK 0x3ffu
#define I3C_TARG_RXBUF_STATE_RPTR_OFFSET 16
#define I3C_TARG_RXBUF_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RXBUF_STATE_RPTR_MASK, .index = I3C_TARG_RXBUF_STATE_RPTR_OFFSET })
#define I3C_TARG_RXBUF_STATE_PRE_BIT 30
#define I3C_TARG_RXBUF_STATE_FULL_BIT 31
 
// Target In-Band Interrupt Payload Queue Configuration
#define I3C_TARG_IBI_CONFIG_REG_OFFSET 0xcc
#define I3C_TARG_IBI_CONFIG_REG_RESVAL 0x3af0370u
#define I3C_TARG_IBI_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_TARG_IBI_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_TARG_IBI_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBI_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_IBI_CONFIG_MIN_ADDR_OFFSET })
#define I3C_TARG_IBI_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_TARG_IBI_CONFIG_MAX_ADDR_OFFSET 16
#define I3C_TARG_IBI_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBI_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_IBI_CONFIG_MAX_ADDR_OFFSET })
 
// Target In-Band Interrupt Payload Queue State.
#define I3C_TARG_IBI_STATE_REG_OFFSET 0xd0
#define I3C_TARG_IBI_STATE_REG_RESVAL 0x3700370u
#define I3C_TARG_IBI_STATE_WPTR_MASK 0x3ffu
#define I3C_TARG_IBI_STATE_WPTR_OFFSET 0
#define I3C_TARG_IBI_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBI_STATE_WPTR_MASK, .index = I3C_TARG_IBI_STATE_WPTR_OFFSET })
#define I3C_TARG_IBI_STATE_RPTR_MASK 0x3ffu
#define I3C_TARG_IBI_STATE_RPTR_OFFSET 16
#define I3C_TARG_IBI_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBI_STATE_RPTR_MASK, .index = I3C_TARG_IBI_STATE_RPTR_OFFSET })
#define I3C_TARG_IBI_STATE_PRE_BIT 30
#define I3C_TARG_IBI_STATE_FULL_BIT 31
 
// Target Transmission Descriptor Queue Configuration. (common parameters)
#define I3C_TARG_TXDESC_CONFIG_MIN_ADDR_FIELD_WIDTH 10
#define I3C_TARG_TXDESC_CONFIG_MAX_ADDR_FIELD_WIDTH 10
#define I3C_TARG_TXDESC_CONFIG_MULTIREG_COUNT 4
 
// Target Transmission Descriptor Queue Configuration.
#define I3C_TARG_TXDESC_CONFIG_0_REG_OFFSET 0xd4
#define I3C_TARG_TXDESC_CONFIG_0_REG_RESVAL 0x3b703b0u
#define I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_MASK 0x3ffu
#define I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_OFFSET 0
#define I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_MASK, .index = I3C_TARG_TXDESC_CONFIG_0_MIN_ADDR_0_OFFSET })
#define I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_MASK 0x3ffu
#define I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_OFFSET 16
#define I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_MASK, .index = I3C_TARG_TXDESC_CONFIG_0_MAX_ADDR_0_OFFSET })
 
// Target Transmission Descriptor Queue Configuration.
#define I3C_TARG_TXDESC_CONFIG_1_REG_OFFSET 0xd8
#define I3C_TARG_TXDESC_CONFIG_1_REG_RESVAL 0x3bf03b8u
#define I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_MASK 0x3ffu
#define I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_OFFSET 0
#define I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_MASK, .index = I3C_TARG_TXDESC_CONFIG_1_MIN_ADDR_1_OFFSET })
#define I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_MASK 0x3ffu
#define I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_OFFSET 16
#define I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_MASK, .index = I3C_TARG_TXDESC_CONFIG_1_MAX_ADDR_1_OFFSET })
 
// Target Transmission Descriptor Queue Configuration.
#define I3C_TARG_TXDESC_CONFIG_2_REG_OFFSET 0xdc
#define I3C_TARG_TXDESC_CONFIG_2_REG_RESVAL 0x3c703c0u
#define I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_MASK 0x3ffu
#define I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_OFFSET 0
#define I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_MASK, .index = I3C_TARG_TXDESC_CONFIG_2_MIN_ADDR_2_OFFSET })
#define I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_MASK 0x3ffu
#define I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_OFFSET 16
#define I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_MASK, .index = I3C_TARG_TXDESC_CONFIG_2_MAX_ADDR_2_OFFSET })
 
// Target Transmission Descriptor Queue Configuration.
#define I3C_TARG_TXDESC_CONFIG_3_REG_OFFSET 0xe0
#define I3C_TARG_TXDESC_CONFIG_3_REG_RESVAL 0x3cf03c8u
#define I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_MASK 0x3ffu
#define I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_OFFSET 0
#define I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_MASK, .index = I3C_TARG_TXDESC_CONFIG_3_MIN_ADDR_3_OFFSET })
#define I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_MASK 0x3ffu
#define I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_OFFSET 16
#define I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_MASK, .index = I3C_TARG_TXDESC_CONFIG_3_MAX_ADDR_3_OFFSET })
 
// Target Transmission Descriptor Queue State. (common parameters)
#define I3C_TARG_TXDESC_STATE_WPTR_FIELD_WIDTH 10
#define I3C_TARG_TXDESC_STATE_RPTR_FIELD_WIDTH 10
#define I3C_TARG_TXDESC_STATE_PRE_FIELD_WIDTH 1
#define I3C_TARG_TXDESC_STATE_FULL_FIELD_WIDTH 1
#define I3C_TARG_TXDESC_STATE_MULTIREG_COUNT 4
 
// Target Transmission Descriptor Queue State.
#define I3C_TARG_TXDESC_STATE_0_REG_OFFSET 0xe4
#define I3C_TARG_TXDESC_STATE_0_REG_RESVAL 0x3b003b0u
#define I3C_TARG_TXDESC_STATE_0_WPTR_0_MASK 0x3ffu
#define I3C_TARG_TXDESC_STATE_0_WPTR_0_OFFSET 0
#define I3C_TARG_TXDESC_STATE_0_WPTR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_0_WPTR_0_MASK, .index = I3C_TARG_TXDESC_STATE_0_WPTR_0_OFFSET })
#define I3C_TARG_TXDESC_STATE_0_RPTR_0_MASK 0x3ffu
#define I3C_TARG_TXDESC_STATE_0_RPTR_0_OFFSET 16
#define I3C_TARG_TXDESC_STATE_0_RPTR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_0_RPTR_0_MASK, .index = I3C_TARG_TXDESC_STATE_0_RPTR_0_OFFSET })
#define I3C_TARG_TXDESC_STATE_0_PRE_0_BIT 30
#define I3C_TARG_TXDESC_STATE_0_FULL_0_BIT 31
 
// Target Transmission Descriptor Queue State.
#define I3C_TARG_TXDESC_STATE_1_REG_OFFSET 0xe8
#define I3C_TARG_TXDESC_STATE_1_REG_RESVAL 0x3b803b8u
#define I3C_TARG_TXDESC_STATE_1_WPTR_1_MASK 0x3ffu
#define I3C_TARG_TXDESC_STATE_1_WPTR_1_OFFSET 0
#define I3C_TARG_TXDESC_STATE_1_WPTR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_1_WPTR_1_MASK, .index = I3C_TARG_TXDESC_STATE_1_WPTR_1_OFFSET })
#define I3C_TARG_TXDESC_STATE_1_RPTR_1_MASK 0x3ffu
#define I3C_TARG_TXDESC_STATE_1_RPTR_1_OFFSET 16
#define I3C_TARG_TXDESC_STATE_1_RPTR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_1_RPTR_1_MASK, .index = I3C_TARG_TXDESC_STATE_1_RPTR_1_OFFSET })
#define I3C_TARG_TXDESC_STATE_1_PRE_1_BIT 30
#define I3C_TARG_TXDESC_STATE_1_FULL_1_BIT 31
 
// Target Transmission Descriptor Queue State.
#define I3C_TARG_TXDESC_STATE_2_REG_OFFSET 0xec
#define I3C_TARG_TXDESC_STATE_2_REG_RESVAL 0x3c003c0u
#define I3C_TARG_TXDESC_STATE_2_WPTR_2_MASK 0x3ffu
#define I3C_TARG_TXDESC_STATE_2_WPTR_2_OFFSET 0
#define I3C_TARG_TXDESC_STATE_2_WPTR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_2_WPTR_2_MASK, .index = I3C_TARG_TXDESC_STATE_2_WPTR_2_OFFSET })
#define I3C_TARG_TXDESC_STATE_2_RPTR_2_MASK 0x3ffu
#define I3C_TARG_TXDESC_STATE_2_RPTR_2_OFFSET 16
#define I3C_TARG_TXDESC_STATE_2_RPTR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_2_RPTR_2_MASK, .index = I3C_TARG_TXDESC_STATE_2_RPTR_2_OFFSET })
#define I3C_TARG_TXDESC_STATE_2_PRE_2_BIT 30
#define I3C_TARG_TXDESC_STATE_2_FULL_2_BIT 31
 
// Target Transmission Descriptor Queue State.
#define I3C_TARG_TXDESC_STATE_3_REG_OFFSET 0xf0
#define I3C_TARG_TXDESC_STATE_3_REG_RESVAL 0x3c803c8u
#define I3C_TARG_TXDESC_STATE_3_WPTR_3_MASK 0x3ffu
#define I3C_TARG_TXDESC_STATE_3_WPTR_3_OFFSET 0
#define I3C_TARG_TXDESC_STATE_3_WPTR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_3_WPTR_3_MASK, .index = I3C_TARG_TXDESC_STATE_3_WPTR_3_OFFSET })
#define I3C_TARG_TXDESC_STATE_3_RPTR_3_MASK 0x3ffu
#define I3C_TARG_TXDESC_STATE_3_RPTR_3_OFFSET 16
#define I3C_TARG_TXDESC_STATE_3_RPTR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TXDESC_STATE_3_RPTR_3_MASK, .index = I3C_TARG_TXDESC_STATE_3_RPTR_3_OFFSET })
#define I3C_TARG_TXDESC_STATE_3_PRE_3_BIT 30
#define I3C_TARG_TXDESC_STATE_3_FULL_3_BIT 31
 
// Target Reception Descriptor Queue Configuration.
#define I3C_TARG_RXDESC_CONFIG_REG_OFFSET 0xf4
#define I3C_TARG_RXDESC_CONFIG_REG_RESVAL 0x3df03d0u
#define I3C_TARG_RXDESC_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_TARG_RXDESC_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_TARG_RXDESC_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_RXDESC_CONFIG_MIN_ADDR_OFFSET })
#define I3C_TARG_RXDESC_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_TARG_RXDESC_CONFIG_MAX_ADDR_OFFSET 16
#define I3C_TARG_RXDESC_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_RXDESC_CONFIG_MAX_ADDR_OFFSET })
 
// Target Reception Descriptor Queue State.
#define I3C_TARG_RXDESC_STATE_REG_OFFSET 0xf8
#define I3C_TARG_RXDESC_STATE_REG_RESVAL 0x3d003d0u
#define I3C_TARG_RXDESC_STATE_WPTR_MASK 0x3ffu
#define I3C_TARG_RXDESC_STATE_WPTR_OFFSET 0
#define I3C_TARG_RXDESC_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_STATE_WPTR_MASK, .index = I3C_TARG_RXDESC_STATE_WPTR_OFFSET })
#define I3C_TARG_RXDESC_STATE_RPTR_MASK 0x3ffu
#define I3C_TARG_RXDESC_STATE_RPTR_OFFSET 16
#define I3C_TARG_RXDESC_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RXDESC_STATE_RPTR_MASK, .index = I3C_TARG_RXDESC_STATE_RPTR_OFFSET })
#define I3C_TARG_RXDESC_STATE_PRE_BIT 30
#define I3C_TARG_RXDESC_STATE_FULL_BIT 31
 
// Target In-Band Interrupt Descriptor Queue Configuration.
#define I3C_TARG_IBIDESC_CONFIG_REG_OFFSET 0xfc
#define I3C_TARG_IBIDESC_CONFIG_REG_RESVAL 0x3ef03e0u
#define I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_IBIDESC_CONFIG_MIN_ADDR_OFFSET })
#define I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_OFFSET 16
#define I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_IBIDESC_CONFIG_MAX_ADDR_OFFSET })
 
// Target In-Band Interrupt Descriptor Queue State.
#define I3C_TARG_IBIDESC_STATE_REG_OFFSET 0x100
#define I3C_TARG_IBIDESC_STATE_REG_RESVAL 0x3e003e0u
#define I3C_TARG_IBIDESC_STATE_WPTR_MASK 0x3ffu
#define I3C_TARG_IBIDESC_STATE_WPTR_OFFSET 0
#define I3C_TARG_IBIDESC_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_STATE_WPTR_MASK, .index = I3C_TARG_IBIDESC_STATE_WPTR_OFFSET })
#define I3C_TARG_IBIDESC_STATE_RPTR_MASK 0x3ffu
#define I3C_TARG_IBIDESC_STATE_RPTR_OFFSET 16
#define I3C_TARG_IBIDESC_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBIDESC_STATE_RPTR_MASK, .index = I3C_TARG_IBIDESC_STATE_RPTR_OFFSET })
#define I3C_TARG_IBIDESC_STATE_PRE_BIT 30
#define I3C_TARG_IBIDESC_STATE_FULL_BIT 31
 
// Target Asynchronous Event Queue Configuration.
#define I3C_TARG_ASYNC_CONFIG_REG_OFFSET 0x104
#define I3C_TARG_ASYNC_CONFIG_REG_RESVAL 0x3ff03f0u
#define I3C_TARG_ASYNC_CONFIG_MIN_ADDR_MASK 0x3ffu
#define I3C_TARG_ASYNC_CONFIG_MIN_ADDR_OFFSET 0
#define I3C_TARG_ASYNC_CONFIG_MIN_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_CONFIG_MIN_ADDR_MASK, .index = I3C_TARG_ASYNC_CONFIG_MIN_ADDR_OFFSET })
#define I3C_TARG_ASYNC_CONFIG_MAX_ADDR_MASK 0x3ffu
#define I3C_TARG_ASYNC_CONFIG_MAX_ADDR_OFFSET 16
#define I3C_TARG_ASYNC_CONFIG_MAX_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_CONFIG_MAX_ADDR_MASK, .index = I3C_TARG_ASYNC_CONFIG_MAX_ADDR_OFFSET })
 
// Target Asynchronous Event Queue State.
#define I3C_TARG_ASYNC_STATE_REG_OFFSET 0x108
#define I3C_TARG_ASYNC_STATE_REG_RESVAL 0x3f003f0u
#define I3C_TARG_ASYNC_STATE_WPTR_MASK 0x3ffu
#define I3C_TARG_ASYNC_STATE_WPTR_OFFSET 0
#define I3C_TARG_ASYNC_STATE_WPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_STATE_WPTR_MASK, .index = I3C_TARG_ASYNC_STATE_WPTR_OFFSET })
#define I3C_TARG_ASYNC_STATE_RPTR_MASK 0x3ffu
#define I3C_TARG_ASYNC_STATE_RPTR_OFFSET 16
#define I3C_TARG_ASYNC_STATE_RPTR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ASYNC_STATE_RPTR_MASK, .index = I3C_TARG_ASYNC_STATE_RPTR_OFFSET })
#define I3C_TARG_ASYNC_STATE_PRE_BIT 30
#define I3C_TARG_ASYNC_STATE_FULL_BIT 31
 
// HCI Version.
#define I3C_HCI_VERSION_REG_OFFSET 0x180
#define I3C_HCI_VERSION_REG_RESVAL 0x120u
 
// Host Controller Control.
#define I3C_HC_CONTROL_REG_OFFSET 0x184
#define I3C_HC_CONTROL_REG_RESVAL 0x48u
#define I3C_HC_CONTROL_IBA_INCLUDE_BIT 0
#define I3C_HC_CONTROL_AUTOCMD_DATA_RPT_BIT 3
#define I3C_HC_CONTROL_DATA_BYTE_ORDER_MODE_BIT 4
#define I3C_HC_CONTROL_MODE_SELECTOR_BIT 6
#define I3C_HC_CONTROL_I2C_DEV_PRESENT_BIT 7
#define I3C_HC_CONTROL_HOT_JOIN_CTRL_BIT 8
#define I3C_HC_CONTROL_HALT_ON_CMD_SEQ_TIMEOUT_BIT 12
#define I3C_HC_CONTROL_ABORT_BIT 29
#define I3C_HC_CONTROL_RESUME_BIT 30
#define I3C_HC_CONTROL_BUS_ENABLE_BIT 31
 
// Controller Device Address.
#define I3C_CONTROLLER_DEVICE_ADDR_REG_OFFSET 0x188
#define I3C_CONTROLLER_DEVICE_ADDR_REG_RESVAL 0x0u
#define I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_MASK 0x7fu
#define I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET 16
#define I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_MASK, .index = I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET })
#define I3C_CONTROLLER_DEVICE_ADDR_DYNAMIC_ADDR_VALID_BIT 31
 
// Host Controller Capabilities.
#define I3C_HC_CAPABILITIES_REG_OFFSET 0x18c
#define I3C_HC_CAPABILITIES_REG_RESVAL 0x448u
#define I3C_HC_CAPABILITIES_COMBO_COMMAND_BIT 2
#define I3C_HC_CAPABILITIES_AUTO_COMMAND_BIT 3
#define I3C_HC_CAPABILITIES_STANDBY_CR_CAP_BIT 5
#define I3C_HC_CAPABILITIES_HDR_DDR_EN_BIT 6
#define I3C_HC_CAPABILITIES_HDR_TS_EN_BIT 7
#define I3C_HC_CAPABILITIES_CMD_CCC_DEFBYTE_BIT 10
#define I3C_HC_CAPABILITIES_IBI_DATA_ABORT_EN_BIT 11
#define I3C_HC_CAPABILITIES_IBI_CREDIT_COUNT_EN_BIT 12
#define I3C_HC_CAPABILITIES_SCHEDULED_COMMANDS_EN_BIT 13
#define I3C_HC_CAPABILITIES_CMD_SIZE_MASK 0x3u
#define I3C_HC_CAPABILITIES_CMD_SIZE_OFFSET 20
#define I3C_HC_CAPABILITIES_CMD_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_HC_CAPABILITIES_CMD_SIZE_MASK, .index = I3C_HC_CAPABILITIES_CMD_SIZE_OFFSET })
#define I3C_HC_CAPABILITIES_SG_CAPABILITY_CR_EN_BIT 28
#define I3C_HC_CAPABILITIES_SG_CAPABILITY_IBI_EN_BIT 29
#define I3C_HC_CAPABILITIES_SG_CAPABILITY_DC_EN_BIT 30
 
// Reset Control.
#define I3C_RESET_CONTROL_REG_OFFSET 0x190
#define I3C_RESET_CONTROL_REG_RESVAL 0x0u
#define I3C_RESET_CONTROL_SOFT_RST_BIT 0
#define I3C_RESET_CONTROL_CMD_QUEUE_RST_BIT 1
#define I3C_RESET_CONTROL_RESP_QUEUE_RST_BIT 2
#define I3C_RESET_CONTROL_TX_FIFO_RST_BIT 3
#define I3C_RESET_CONTROL_RX_FIFO_RST_BIT 4
#define I3C_RESET_CONTROL_IBI_QUEUE_RST_BIT 5
 
// Present State.
#define I3C_PRESENT_STATE_REG_OFFSET 0x194
#define I3C_PRESENT_STATE_REG_RESVAL 0x0u
#define I3C_PRESENT_STATE_AC_CURRENT_OWN_BIT 2
 
// Interrupt Status.
#define I3C_INTR_STATUS_REG_OFFSET 0x1a0
#define I3C_INTR_STATUS_REG_RESVAL 0x0u
#define I3C_INTR_STATUS_HC_INTERNAL_ERR_STAT_BIT 10
#define I3C_INTR_STATUS_HC_SEQ_CANCEL_STAT_BIT 11
#define I3C_INTR_STATUS_HC_WARN_CMD_SEQ_STALL_STAT_BIT 12
#define I3C_INTR_STATUS_HC_ERR_CMD_SEQ_TIMEOUT_STAT_BIT 13
#define I3C_INTR_STATUS_SCHED_CMD_MISSED_TICK_STAT_BIT 14
 
// Interrupt Status Enable.
#define I3C_INTR_STATUS_ENABLE_REG_OFFSET 0x1a4
#define I3C_INTR_STATUS_ENABLE_REG_RESVAL 0x0u
#define I3C_INTR_STATUS_ENABLE_HC_INTERNAL_ERR_STAT_EN_BIT 10
#define I3C_INTR_STATUS_ENABLE_HC_SEQ_CANCEL_STAT_EN_BIT 11
#define I3C_INTR_STATUS_ENABLE_HC_WARN_CMD_SEQ_STALL_STAT_EN_BIT 12
#define I3C_INTR_STATUS_ENABLE_HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN_BIT 13
#define I3C_INTR_STATUS_ENABLE_SCHED_CMD_MISSED_TICK_STAT_EN_BIT 14
 
// Interrupt Signal Enable.
#define I3C_INTR_SIGNAL_ENABLE_REG_OFFSET 0x1a8
#define I3C_INTR_SIGNAL_ENABLE_REG_RESVAL 0x0u
#define I3C_INTR_SIGNAL_ENABLE_HC_INTERNAL_ERR_SIGNAL_EN_BIT 10
#define I3C_INTR_SIGNAL_ENABLE_HC_SEQ_CANCEL_SIGNAL_EN_BIT 11
#define I3C_INTR_SIGNAL_ENABLE_HC_WARN_CMD_SEQ_STALL_SIGNAL_EN_BIT 12
#define I3C_INTR_SIGNAL_ENABLE_HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN_BIT 13
#define I3C_INTR_SIGNAL_ENABLE_SCHED_CMD_MISSED_TICK_SIGNAL_EN_BIT 14
 
// Interrupt Force.
#define I3C_INTR_FORCE_REG_OFFSET 0x1ac
#define I3C_INTR_FORCE_REG_RESVAL 0x0u
#define I3C_INTR_FORCE_HC_INTERNAL_ERR_FORCE_BIT 10
#define I3C_INTR_FORCE_HC_SEQ_CANCEL_FORCE_BIT 11
#define I3C_INTR_FORCE_HC_WARN_CMD_SEQ_STALL_FORCE_BIT 12
#define I3C_INTR_FORCE_HC_ERR_CMD_SEQ_TIMEOUT_FORCE_BIT 13
#define I3C_INTR_FORCE_SCHED_CMD_MISSED_TICK_FORCE_BIT 14
 
// Device Address Table Section Offset.
#define I3C_DAT_SECTION_OFFSET_REG_OFFSET 0x1b0
#define I3C_DAT_SECTION_OFFSET_REG_RESVAL 0x20880u
#define I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_MASK 0xfffu
#define I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_OFFSET 0
#define I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_MASK, .index = I3C_DAT_SECTION_OFFSET_TABLE_OFFSET_OFFSET })
#define I3C_DAT_SECTION_OFFSET_TABLE_SIZE_MASK 0x7fu
#define I3C_DAT_SECTION_OFFSET_TABLE_SIZE_OFFSET 12
#define I3C_DAT_SECTION_OFFSET_TABLE_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DAT_SECTION_OFFSET_TABLE_SIZE_MASK, .index = I3C_DAT_SECTION_OFFSET_TABLE_SIZE_OFFSET })
#define I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_MASK 0xfu
#define I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_OFFSET 28
#define I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_MASK, .index = I3C_DAT_SECTION_OFFSET_ENTRY_SIZE_OFFSET })
 
// Device Characteristics Table Section Offset.
#define I3C_DCT_SECTION_OFFSET_REG_OFFSET 0x1b4
#define I3C_DCT_SECTION_OFFSET_REG_RESVAL 0x20a80u
#define I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_MASK 0xfffu
#define I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_OFFSET 0
#define I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_MASK, .index = I3C_DCT_SECTION_OFFSET_TABLE_OFFSET_OFFSET })
#define I3C_DCT_SECTION_OFFSET_TABLE_SIZE_MASK 0x7fu
#define I3C_DCT_SECTION_OFFSET_TABLE_SIZE_OFFSET 12
#define I3C_DCT_SECTION_OFFSET_TABLE_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_TABLE_SIZE_MASK, .index = I3C_DCT_SECTION_OFFSET_TABLE_SIZE_OFFSET })
#define I3C_DCT_SECTION_OFFSET_TABLE_INDEX_MASK 0x1fu
#define I3C_DCT_SECTION_OFFSET_TABLE_INDEX_OFFSET 19
#define I3C_DCT_SECTION_OFFSET_TABLE_INDEX_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_TABLE_INDEX_MASK, .index = I3C_DCT_SECTION_OFFSET_TABLE_INDEX_OFFSET })
#define I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_MASK 0xfu
#define I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_OFFSET 28
#define I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_MASK, .index = I3C_DCT_SECTION_OFFSET_ENTRY_SIZE_OFFSET })
 
// Ring Headers Section Offset.
#define I3C_RING_HEADERS_SECTION_OFFSET_REG_OFFSET 0x1b8
#define I3C_RING_HEADERS_SECTION_OFFSET_REG_RESVAL 0x0u
#define I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_MASK 0xffffu
#define I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_OFFSET 0
#define I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_FIELD \
  ((bitfield_field32_t) { .mask = I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_MASK, .index = I3C_RING_HEADERS_SECTION_OFFSET_SECTION_OFFSET_OFFSET })
 
// PIO Section Offset.
#define I3C_PIO_SECTION_OFFSET_REG_OFFSET 0x1bc
#define I3C_PIO_SECTION_OFFSET_REG_RESVAL 0x80u
#define I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_MASK 0xffffu
#define I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_OFFSET 0
#define I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_FIELD \
  ((bitfield_field32_t) { .mask = I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_MASK, .index = I3C_PIO_SECTION_OFFSET_SECTION_OFFSET_OFFSET })
 
// Extended Capabilities Section Offset.
#define I3C_EXT_CAPS_SECTION_OFFSET_REG_OFFSET 0x1c0
#define I3C_EXT_CAPS_SECTION_OFFSET_REG_RESVAL 0x120u
#define I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_MASK 0xffffu
#define I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_OFFSET 0
#define I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_FIELD \
  ((bitfield_field32_t) { .mask = I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_MASK, .index = I3C_EXT_CAPS_SECTION_OFFSET_SECTION_OFFSET_OFFSET })
 
// Internal Control Command Subtype Support.
#define I3C_INT_CTRL_CMDS_EN_REG_OFFSET 0x1cc
#define I3C_INT_CTRL_CMDS_EN_REG_RESVAL 0x20f5u
#define I3C_INT_CTRL_CMDS_EN_ICC_SUPPORT_BIT 0
#define I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_MASK 0x7fffu
#define I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_OFFSET 1
#define I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_FIELD \
  ((bitfield_field32_t) { .mask = I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_MASK, .index = I3C_INT_CTRL_CMDS_EN_MIPI_CMDS_SUPPORTED_OFFSET })
 
// IBI Notify Control.
#define I3C_IBI_NOTIFY_CTRL_REG_OFFSET 0x1d8
#define I3C_IBI_NOTIFY_CTRL_REG_RESVAL 0x0u
#define I3C_IBI_NOTIFY_CTRL_NOTIFY_HJ_REJECTED_BIT 0
#define I3C_IBI_NOTIFY_CTRL_NOTIFY_CRR_REJECTED_BIT 1
#define I3C_IBI_NOTIFY_CTRL_NOTIFY_IBI_REJECTED_BIT 3
 
// IBI Data Abort Control.
#define I3C_IBI_DATA_ABORT_CTRL_REG_OFFSET 0x1dc
#define I3C_IBI_DATA_ABORT_CTRL_REG_RESVAL 0x0u
#define I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_MASK 0xffu
#define I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_OFFSET 8
#define I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_MASK, .index = I3C_IBI_DATA_ABORT_CTRL_MATCH_IBI_ID_OFFSET })
#define I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_MASK 0x3u
#define I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_OFFSET 16
#define I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_MASK, .index = I3C_IBI_DATA_ABORT_CTRL_AFTER_N_CHUNKS_OFFSET })
#define I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_MASK 0x7u
#define I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_OFFSET 18
#define I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_MASK, .index = I3C_IBI_DATA_ABORT_CTRL_MATCH_STATUS_TYPE_OFFSET })
#define I3C_IBI_DATA_ABORT_CTRL_IBI_DATA_ABORT_MON_BIT 31
 
// Device Context Base Address Low.
#define I3C_DEV_CTX_BASE_LO_REG_OFFSET 0x1e0
#define I3C_DEV_CTX_BASE_LO_REG_RESVAL 0x0u
 
// Device Context Base Address High.
#define I3C_DEV_CTX_BASE_HI_REG_OFFSET 0x1e4
#define I3C_DEV_CTX_BASE_HI_REG_RESVAL 0x0u
 
// Device Context Scatter-Gather Support.
#define I3C_DEV_CTX_SG_REG_OFFSET 0x1e8
#define I3C_DEV_CTX_SG_REG_RESVAL 0x0u
#define I3C_DEV_CTX_SG_LIST_SIZE_MASK 0xffffu
#define I3C_DEV_CTX_SG_LIST_SIZE_OFFSET 0
#define I3C_DEV_CTX_SG_LIST_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DEV_CTX_SG_LIST_SIZE_MASK, .index = I3C_DEV_CTX_SG_LIST_SIZE_OFFSET })
#define I3C_DEV_CTX_SG_BLP_BIT 31
 
// Memory area: HCI ports, occupying successive word addresses:
#define I3C_HCI_PORTS_REG_OFFSET 0x200
#define I3C_HCI_PORTS_SIZE_WORDS 4
#define I3C_HCI_PORTS_SIZE_BYTES 16
// Queue Threshold Control.
#define I3C_QUEUE_THLD_CTRL_REG_OFFSET 0x210
#define I3C_QUEUE_THLD_CTRL_REG_RESVAL 0x1010101u
#define I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_MASK 0xffu
#define I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_OFFSET 0
#define I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_MASK, .index = I3C_QUEUE_THLD_CTRL_CMD_EMPTY_BUF_THLD_OFFSET })
#define I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_MASK 0xffu
#define I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_OFFSET 8
#define I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_MASK, .index = I3C_QUEUE_THLD_CTRL_RESP_BUF_THLD_OFFSET })
#define I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_MASK 0xffu
#define I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_OFFSET 16
#define I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_MASK, .index = I3C_QUEUE_THLD_CTRL_IBI_DATA_SEGMENT_SIZE_OFFSET })
#define I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK 0xffu
#define I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET 24
#define I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK, .index = I3C_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET })
 
// Transfer Data Buffer Threshold Control.
#define I3C_DATA_BUFFER_THLD_CTRL_REG_OFFSET 0x214
#define I3C_DATA_BUFFER_THLD_CTRL_REG_RESVAL 0x1010101u
#define I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_MASK 0x7u
#define I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_OFFSET 0
#define I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_TX_BUF_THLD_OFFSET })
#define I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_MASK 0x7u
#define I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_OFFSET 8
#define I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_RX_BUF_THLD_OFFSET })
#define I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_MASK 0x7u
#define I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_OFFSET 16
#define I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_TX_START_THLD_OFFSET })
#define I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_MASK 0x7u
#define I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_OFFSET 24
#define I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_MASK, .index = I3C_DATA_BUFFER_THLD_CTRL_RX_START_THLD_OFFSET })
 
// Queue Size.
#define I3C_QUEUE_SIZE_REG_OFFSET 0x218
#define I3C_QUEUE_SIZE_REG_RESVAL 0x6061410u
#define I3C_QUEUE_SIZE_CR_QUEUE_SIZE_MASK 0xffu
#define I3C_QUEUE_SIZE_CR_QUEUE_SIZE_OFFSET 0
#define I3C_QUEUE_SIZE_CR_QUEUE_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_CR_QUEUE_SIZE_MASK, .index = I3C_QUEUE_SIZE_CR_QUEUE_SIZE_OFFSET })
#define I3C_QUEUE_SIZE_IBI_STATUS_SIZE_MASK 0xffu
#define I3C_QUEUE_SIZE_IBI_STATUS_SIZE_OFFSET 8
#define I3C_QUEUE_SIZE_IBI_STATUS_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_IBI_STATUS_SIZE_MASK, .index = I3C_QUEUE_SIZE_IBI_STATUS_SIZE_OFFSET })
#define I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_MASK 0xffu
#define I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_OFFSET 16
#define I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_MASK, .index = I3C_QUEUE_SIZE_RX_DATA_BUFFER_SIZE_OFFSET })
#define I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_MASK 0xffu
#define I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_OFFSET 24
#define I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_MASK, .index = I3C_QUEUE_SIZE_TX_DATA_BUFFER_SIZE_OFFSET })
 
// Alternate Queue Size.
#define I3C_ALT_QUEUE_SIZE_REG_OFFSET 0x21c
#define I3C_ALT_QUEUE_SIZE_REG_RESVAL 0x11000010u
#define I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_MASK 0xffu
#define I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_OFFSET 0
#define I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_MASK, .index = I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_SIZE_OFFSET })
#define I3C_ALT_QUEUE_SIZE_ALT_RESP_QUEUE_EN_BIT 24
#define I3C_ALT_QUEUE_SIZE_EXT_IBI_QUEUE_EN_BIT 28
 
// PIO Interrupt Status.
#define I3C_PIO_INTR_STATUS_REG_OFFSET 0x220
#define I3C_PIO_INTR_STATUS_REG_RESVAL 0x0u
#define I3C_PIO_INTR_STATUS_TX_THLD_STAT_BIT 0
#define I3C_PIO_INTR_STATUS_RX_THLD_STAT_BIT 1
#define I3C_PIO_INTR_STATUS_IBI_STATUS_THLD_STAT_BIT 2
#define I3C_PIO_INTR_STATUS_CMD_QUEUE_READY_STAT_BIT 3
#define I3C_PIO_INTR_STATUS_RESP_READY_STAT_BIT 4
#define I3C_PIO_INTR_STATUS_TRANSFER_ABORT_STAT_BIT 5
#define I3C_PIO_INTR_STATUS_TRANSFER_ERR_STAT_BIT 9
 
// PIO Interrupt Status Enable.
#define I3C_PIO_INTR_STATUS_ENABLE_REG_OFFSET 0x224
#define I3C_PIO_INTR_STATUS_ENABLE_REG_RESVAL 0x0u
#define I3C_PIO_INTR_STATUS_ENABLE_TX_THLD_STAT_EN_BIT 0
#define I3C_PIO_INTR_STATUS_ENABLE_RX_THLD_STAT_EN_BIT 1
#define I3C_PIO_INTR_STATUS_ENABLE_IBI_STATUS_THLD_STAT_EN_BIT 2
#define I3C_PIO_INTR_STATUS_ENABLE_CMD_QUEUE_READY_STAT_EN_BIT 3
#define I3C_PIO_INTR_STATUS_ENABLE_RESP_READY_STAT_EN_BIT 4
#define I3C_PIO_INTR_STATUS_ENABLE_TRANSFER_ABORT_STAT_EN_BIT 5
#define I3C_PIO_INTR_STATUS_ENABLE_TRANSFER_ERR_STAT_EN_BIT 9
 
// PIO Interrupt Signal Enable.
#define I3C_PIO_INTR_SIGNAL_ENABLE_REG_OFFSET 0x228
#define I3C_PIO_INTR_SIGNAL_ENABLE_REG_RESVAL 0x0u
#define I3C_PIO_INTR_SIGNAL_ENABLE_TX_THLD_SIGNAL_EN_BIT 0
#define I3C_PIO_INTR_SIGNAL_ENABLE_RX_THLD_SIGNAL_EN_BIT 1
#define I3C_PIO_INTR_SIGNAL_ENABLE_IBI_STATUS_THLD_SIGNAL_EN_BIT 2
#define I3C_PIO_INTR_SIGNAL_ENABLE_CMD_QUEUE_READY_SIGNAL_EN_BIT 3
#define I3C_PIO_INTR_SIGNAL_ENABLE_RESP_READY_SIGNAL_EN_BIT 4
#define I3C_PIO_INTR_SIGNAL_ENABLE_TRANSFER_ABORT_SIGNAL_EN_BIT 5
#define I3C_PIO_INTR_SIGNAL_ENABLE_TRANSFER_ERR_SIGNAL_EN_BIT 9
 
// PIO Interrupt Force.
#define I3C_PIO_INTR_FORCE_REG_OFFSET 0x22c
#define I3C_PIO_INTR_FORCE_REG_RESVAL 0x0u
#define I3C_PIO_INTR_FORCE_TX_THLD_FORCE_BIT 0
#define I3C_PIO_INTR_FORCE_RX_THLD_FORCE_BIT 1
#define I3C_PIO_INTR_FORCE_IBI_THLD_FORCE_BIT 2
#define I3C_PIO_INTR_FORCE_CMD_QUEUE_READY_FORCE_BIT 3
#define I3C_PIO_INTR_FORCE_RESP_READY_FORCE_BIT 4
#define I3C_PIO_INTR_FORCE_TRANSFER_ABORT_FORCE_BIT 5
#define I3C_PIO_INTR_FORCE_TRANSFER_ERR_FORCE_BIT 9
 
// PIO Control.
#define I3C_PIO_CONTROL_REG_OFFSET 0x230
#define I3C_PIO_CONTROL_REG_RESVAL 0x1u
#define I3C_PIO_CONTROL_ENABLE_BIT 0
#define I3C_PIO_CONTROL_RS_BIT 1
#define I3C_PIO_CONTROL_ABORT_BIT 2
 
// Hardware Identification Extended Capability Header
#define I3C_ID_EXTCAP_HEADER_REG_OFFSET 0x2a0
#define I3C_ID_EXTCAP_HEADER_REG_RESVAL 0x401u
#define I3C_ID_EXTCAP_HEADER_CAP_ID_MASK 0xffu
#define I3C_ID_EXTCAP_HEADER_CAP_ID_OFFSET 0
#define I3C_ID_EXTCAP_HEADER_CAP_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_ID_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_ID_EXTCAP_HEADER_CAP_ID_OFFSET })
#define I3C_ID_EXTCAP_HEADER_CAP_LENGTH_MASK 0xffffu
#define I3C_ID_EXTCAP_HEADER_CAP_LENGTH_OFFSET 8
#define I3C_ID_EXTCAP_HEADER_CAP_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_ID_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_ID_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
 
// Component Manufacturer.
#define I3C_COMP_MANUFACTURER_REG_OFFSET 0x2a4
#define I3C_COMP_MANUFACTURER_REG_RESVAL 0x0u
 
// Component Version.
#define I3C_COMP_VERSION_REG_OFFSET 0x2a8
#define I3C_COMP_VERSION_REG_RESVAL 0x0u
 
// Component Type.
#define I3C_COMP_TYPE_REG_OFFSET 0x2ac
#define I3C_COMP_TYPE_REG_RESVAL 0x0u
 
// Controller Config Extended Capability Header
#define I3C_CTRL_CFG_EXTCAP_HEADER_REG_OFFSET 0x2b0
#define I3C_CTRL_CFG_EXTCAP_HEADER_REG_RESVAL 0x202u
#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_MASK 0xffu
#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_OFFSET 0
#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_ID_OFFSET })
#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_MASK 0xffffu
#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_OFFSET 8
#define I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_CTRL_CFG_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
 
// Controller Config.
#define I3C_CONTROLLER_CONFIG_REG_OFFSET 0x2b4
#define I3C_CONTROLLER_CONFIG_REG_RESVAL 0x10u
#define I3C_CONTROLLER_CONFIG_OPERATION_MODE_MASK 0x3u
#define I3C_CONTROLLER_CONFIG_OPERATION_MODE_OFFSET 4
#define I3C_CONTROLLER_CONFIG_OPERATION_MODE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_CONTROLLER_CONFIG_OPERATION_MODE_MASK, .index = I3C_CONTROLLER_CONFIG_OPERATION_MODE_OFFSET })
 
// Dead Bus Recovery Extended Capability Header
#define I3C_DBR_EXTCAP_HEADER_REG_OFFSET 0x2b8
#define I3C_DBR_EXTCAP_HEADER_REG_RESVAL 0x20bu
#define I3C_DBR_EXTCAP_HEADER_CAP_ID_MASK 0xffu
#define I3C_DBR_EXTCAP_HEADER_CAP_ID_OFFSET 0
#define I3C_DBR_EXTCAP_HEADER_CAP_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DBR_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_DBR_EXTCAP_HEADER_CAP_ID_OFFSET })
#define I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_MASK 0xffffu
#define I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_OFFSET 8
#define I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_DBR_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
 
// Dead Bus Recovery Engage.
#define I3C_DBR_ENGAGE_REG_OFFSET 0x2bc
#define I3C_DBR_ENGAGE_REG_RESVAL 0x0u
#define I3C_DBR_ENGAGE_DBR_VERIF_KEY_MASK 0xfu
#define I3C_DBR_ENGAGE_DBR_VERIF_KEY_OFFSET 0
#define I3C_DBR_ENGAGE_DBR_VERIF_KEY_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_VERIF_KEY_MASK, .index = I3C_DBR_ENGAGE_DBR_VERIF_KEY_OFFSET })
#define I3C_DBR_ENGAGE_DBR_MODE_MASK 0x7u
#define I3C_DBR_ENGAGE_DBR_MODE_OFFSET 4
#define I3C_DBR_ENGAGE_DBR_MODE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_MODE_MASK, .index = I3C_DBR_ENGAGE_DBR_MODE_OFFSET })
#define I3C_DBR_ENGAGE_DBR_ASX_TIMING_MASK 0x3u
#define I3C_DBR_ENGAGE_DBR_ASX_TIMING_OFFSET 8
#define I3C_DBR_ENGAGE_DBR_ASX_TIMING_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_ASX_TIMING_MASK, .index = I3C_DBR_ENGAGE_DBR_ASX_TIMING_OFFSET })
#define I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_MASK 0x7fu
#define I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_OFFSET 16
#define I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_MASK, .index = I3C_DBR_ENGAGE_DBR_IBI_ADDRESS_OFFSET })
 
// Debug Specific Extended Capability Header
#define I3C_DEBUG_EXTCAP_HEADER_REG_OFFSET 0x2c0
#define I3C_DEBUG_EXTCAP_HEADER_REG_RESVAL 0x60cu
#define I3C_DEBUG_EXTCAP_HEADER_CAP_ID_MASK 0xffu
#define I3C_DEBUG_EXTCAP_HEADER_CAP_ID_OFFSET 0
#define I3C_DEBUG_EXTCAP_HEADER_CAP_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DEBUG_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_DEBUG_EXTCAP_HEADER_CAP_ID_OFFSET })
#define I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_MASK 0xffffu
#define I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_OFFSET 8
#define I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_DEBUG_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
 
// Queue Status Level
#define I3C_QUEUE_STATUS_LEVEL_REG_OFFSET 0x2c4
#define I3C_QUEUE_STATUS_LEVEL_REG_RESVAL 0x10u
#define I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_MASK 0xffu
#define I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_OFFSET 0
#define I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_MASK, .index = I3C_QUEUE_STATUS_LEVEL_CMD_QUEUE_FREE_LVL_OFFSET })
#define I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_MASK 0xffu
#define I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_OFFSET 8
#define I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_MASK, .index = I3C_QUEUE_STATUS_LEVEL_RESPONSE_BUFFER_LVL_OFFSET })
#define I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_MASK 0xffu
#define I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_OFFSET 16
#define I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_MASK, .index = I3C_QUEUE_STATUS_LEVEL_IBI_BUFFER_LVL_OFFSET })
#define I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_MASK 0x1fu
#define I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_OFFSET 24
#define I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_FIELD \
  ((bitfield_field32_t) { .mask = I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_MASK, .index = I3C_QUEUE_STATUS_LEVEL_IBI_STATUS_CNT_OFFSET })
 
// Data Buffer Status Level
#define I3C_DATA_BUFFER_STATUS_LEVEL_REG_OFFSET 0x2c8
#define I3C_DATA_BUFFER_STATUS_LEVEL_REG_RESVAL 0x80u
#define I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_MASK 0xffu
#define I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_OFFSET 0
#define I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_MASK, .index = I3C_DATA_BUFFER_STATUS_LEVEL_TX_BUF_FREE_LVL_OFFSET })
#define I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_MASK 0xffu
#define I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_OFFSET 8
#define I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_MASK, .index = I3C_DATA_BUFFER_STATUS_LEVEL_RX_BUF_LVL_OFFSET })
 
// Present State Debug
#define I3C_PRESENT_STATE_DEBUG_REG_OFFSET 0x2cc
#define I3C_PRESENT_STATE_DEBUG_REG_RESVAL 0x3u
#define I3C_PRESENT_STATE_DEBUG_SCL_LINE_SIGNAL_LEVEL_BIT 0
#define I3C_PRESENT_STATE_DEBUG_SDA_LINE_SIGNAL_LEVEL_BIT 1
#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_MASK 0x3fu
#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_OFFSET 8
#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_MASK, .index = I3C_PRESENT_STATE_DEBUG_BCL_TFR_STATUS_OFFSET })
#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_MASK 0x3fu
#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_OFFSET 16
#define I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_MASK, .index = I3C_PRESENT_STATE_DEBUG_BCL_TFR_ST_STATUS_OFFSET })
#define I3C_PRESENT_STATE_DEBUG_CMD_TID_MASK 0xfu
#define I3C_PRESENT_STATE_DEBUG_CMD_TID_OFFSET 24
#define I3C_PRESENT_STATE_DEBUG_CMD_TID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_PRESENT_STATE_DEBUG_CMD_TID_MASK, .index = I3C_PRESENT_STATE_DEBUG_CMD_TID_OFFSET })
 
// Controller Error Counters.
#define I3C_MX_ERROR_COUNTERS_REG_OFFSET 0x2d0
#define I3C_MX_ERROR_COUNTERS_REG_RESVAL 0x0u
#define I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_MASK 0xffu
#define I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_OFFSET 0
#define I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_MASK, .index = I3C_MX_ERROR_COUNTERS_CE2_ERROR_COUNT_OFFSET })
 
// Scheduled Commands Debug
#define I3C_SCHED_CMDS_DEBUG_REG_OFFSET 0x2d4
#define I3C_SCHED_CMDS_DEBUG_REG_RESVAL 0x0u
#define I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_MASK 0xfu
#define I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_OFFSET 0
#define I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_FIELD \
  ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_MASK, .index = I3C_SCHED_CMDS_DEBUG_SCHED_HANDLER_OFFSET })
#define I3C_SCHED_CMDS_DEBUG_INST_ID_MASK 0x7u
#define I3C_SCHED_CMDS_DEBUG_INST_ID_OFFSET 4
#define I3C_SCHED_CMDS_DEBUG_INST_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_INST_ID_MASK, .index = I3C_SCHED_CMDS_DEBUG_INST_ID_OFFSET })
#define I3C_SCHED_CMDS_DEBUG_ERR_TYPE_BIT 7
#define I3C_SCHED_CMDS_DEBUG_ENTITY_ID_MASK 0xffu
#define I3C_SCHED_CMDS_DEBUG_ENTITY_ID_OFFSET 8
#define I3C_SCHED_CMDS_DEBUG_ENTITY_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_ENTITY_ID_MASK, .index = I3C_SCHED_CMDS_DEBUG_ENTITY_ID_OFFSET })
#define I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_MASK 0x1fu
#define I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_OFFSET 16
#define I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_MASK, .index = I3C_SCHED_CMDS_DEBUG_TICK_INTERVAL_OFFSET })
#define I3C_SCHED_CMDS_DEBUG_ERR_OCCURRED_BIT 21
 
// Standby Controller Extended Capability Header
#define I3C_STBY_CR_EXTCAP_HEADER_REG_OFFSET 0x2d8
#define I3C_STBY_CR_EXTCAP_HEADER_REG_RESVAL 0xe12u
#define I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_MASK 0xffu
#define I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_OFFSET 0
#define I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_STBY_CR_EXTCAP_HEADER_CAP_ID_OFFSET })
#define I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_MASK 0xffffu
#define I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_OFFSET 8
#define I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_STBY_CR_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
 
// Standby Controller Control
#define I3C_STBY_CR_CONTROL_REG_OFFSET 0x2dc
#define I3C_STBY_CR_CONTROL_REG_RESVAL 0x100cu
#define I3C_STBY_CR_CONTROL_PENDING_RX_NACK_BIT 0
#define I3C_STBY_CR_CONTROL_HANDOFF_DELAY_NACK_BIT 1
#define I3C_STBY_CR_CONTROL_ACR_FSM_OP_SELECT_BIT 2
#define I3C_STBY_CR_CONTROL_PRIME_ACCEPT_GETACCCR_BIT 3
#define I3C_STBY_CR_CONTROL_HANDOFF_DEEP_SLEEP_BIT 4
#define I3C_STBY_CR_CONTROL_CR_REQUEST_SEND_BIT 5
#define I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_MASK 0x7u
#define I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_OFFSET 8
#define I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_MASK, .index = I3C_STBY_CR_CONTROL_BCAST_CCC_IBI_RING_OFFSET })
#define I3C_STBY_CR_CONTROL_TARGET_XACT_ENABLE_BIT 12
#define I3C_STBY_CR_CONTROL_DAA_SETAASA_ENABLE_BIT 13
#define I3C_STBY_CR_CONTROL_DAA_SETDASA_ENABLE_BIT 14
#define I3C_STBY_CR_CONTROL_DAA_ENTDAA_ENABLE_BIT 15
#define I3C_STBY_CR_CONTROL_RSTACT_DEFBYTE_02_BIT 20
#define I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_MASK 0x3u
#define I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_OFFSET 30
#define I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_MASK, .index = I3C_STBY_CR_CONTROL_STBY_CR_ENABLE_INIT_OFFSET })
 
// Standby Controller Device Address
#define I3C_STBY_CR_DEVICE_ADDR_REG_OFFSET 0x2e0
#define I3C_STBY_CR_DEVICE_ADDR_REG_RESVAL 0x0u
#define I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_MASK 0x7fu
#define I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_OFFSET 0
#define I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_MASK, .index = I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_OFFSET })
#define I3C_STBY_CR_DEVICE_ADDR_STATIC_ADDR_VALID_BIT 15
#define I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_MASK 0x7fu
#define I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET 16
#define I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_MASK, .index = I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_OFFSET })
#define I3C_STBY_CR_DEVICE_ADDR_DYNAMIC_ADDR_VALID_BIT 31
 
// Standby Controller Capabilities
#define I3C_STBY_CR_CAPABILITIES_REG_OFFSET 0x2e4
#define I3C_STBY_CR_CAPABILITIES_REG_RESVAL 0xf020u
#define I3C_STBY_CR_CAPABILITIES_SIMPLE_CRR_SUPPORT_BIT 5
#define I3C_STBY_CR_CAPABILITIES_TARGET_XACT_SUPPORT_BIT 12
#define I3C_STBY_CR_CAPABILITIES_DAA_SETAASA_SUPPORT_BIT 13
#define I3C_STBY_CR_CAPABILITIES_DAA_SETDASA_SUPPORT_BIT 14
#define I3C_STBY_CR_CAPABILITIES_DAA_ENTDAA_SUPPORT_BIT 15
 
// Standby Controller Status
#define I3C_STBY_CR_STATUS_REG_OFFSET 0x2ec
#define I3C_STBY_CR_STATUS_REG_RESVAL 0x0u
#define I3C_STBY_CR_STATUS_AC_CURRENT_OWN_BIT 2
#define I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_MASK 0x7u
#define I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_OFFSET 5
#define I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_MASK, .index = I3C_STBY_CR_STATUS_SIMPLE_CRR_STATUS_OFFSET })
#define I3C_STBY_CR_STATUS_HJ_REQ_STATUS_BIT 8
 
// Standby Controller Device Characteristics
#define I3C_STBY_CR_DEVICE_CHAR_REG_OFFSET 0x2f0
#define I3C_STBY_CR_DEVICE_CHAR_REG_RESVAL 0x60000000u
#define I3C_STBY_CR_DEVICE_CHAR_PID_HI_MASK 0x7fffu
#define I3C_STBY_CR_DEVICE_CHAR_PID_HI_OFFSET 1
#define I3C_STBY_CR_DEVICE_CHAR_PID_HI_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_PID_HI_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_PID_HI_OFFSET })
#define I3C_STBY_CR_DEVICE_CHAR_DCR_MASK 0xffu
#define I3C_STBY_CR_DEVICE_CHAR_DCR_OFFSET 16
#define I3C_STBY_CR_DEVICE_CHAR_DCR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_DCR_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_DCR_OFFSET })
#define I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_MASK 0x1fu
#define I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_OFFSET 24
#define I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_BCR_VAR_OFFSET })
#define I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_MASK 0x7u
#define I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_OFFSET 29
#define I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_MASK, .index = I3C_STBY_CR_DEVICE_CHAR_BCR_FIXED_OFFSET })
 
// Standby Controller PID Low
#define I3C_STBY_CR_DEVICE_PID_LO_REG_OFFSET 0x2f4
#define I3C_STBY_CR_DEVICE_PID_LO_REG_RESVAL 0x0u
 
// Standby Controller Interrupt Status
#define I3C_STBY_CR_INTR_STATUS_REG_OFFSET 0x2f8
#define I3C_STBY_CR_INTR_STATUS_REG_RESVAL 0x0u
#define I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_OK_REMAIN_STAT_BIT 0
#define I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_OK_PRIMED_STAT_BIT 1
#define I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_ERR_FAIL_STAT_BIT 2
#define I3C_STBY_CR_INTR_STATUS_ACR_HANDOFF_ERR_M3_STAT_BIT 3
#define I3C_STBY_CR_INTR_STATUS_CRR_RESPONSE_STAT_BIT 10
#define I3C_STBY_CR_INTR_STATUS_STBY_CR_DYN_ADDR_STAT_BIT 11
#define I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_NACKED_STAT_BIT 12
#define I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_OK_STAT_BIT 13
#define I3C_STBY_CR_INTR_STATUS_STBY_CR_ACCEPT_ERR_STAT_BIT 14
#define I3C_STBY_CR_INTR_STATUS_STBY_CR_OP_RSTACT_STAT_BIT 16
#define I3C_STBY_CR_INTR_STATUS_CCC_PARAM_MODIFIED_STAT_BIT 17
#define I3C_STBY_CR_INTR_STATUS_CCC_UNHANDLED_NACK_STAT_BIT 18
#define I3C_STBY_CR_INTR_STATUS_CCC_FATAL_RSTDAA_ERR_STAT_BIT 19
 
// Standby Controller Interrupt Signal Enable
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_REG_OFFSET 0x300
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_REG_RESVAL 0xc0000u
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_OK_REMAIN_SIGNAL_EN_BIT 0
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_OK_PRIMED_SIGNAL_EN_BIT 1
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_ERR_FAIL_SIGNAL_EN_BIT 2
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_ACR_HANDOFF_ERR_M3_SIGNAL_EN_BIT 3
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_CRR_RESPONSE_SIGNAL_EN_BIT 10
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_DYN_ADDR_SIGNAL_EN_BIT 11
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_NACKED_SIGNAL_EN_BIT 12
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_OK_SIGNAL_EN_BIT 13
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_ACCEPT_ERR_SIGNAL_EN_BIT 14
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_STBY_CR_OP_RSTACT_SIGNAL_EN_BIT 16
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_PARAM_MODIFIED_SIGNAL_EN_BIT 17
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_UNHANDLED_NACK_SIGNAL_EN_BIT 18
#define I3C_STBY_CR_INTR_SIGNAL_ENABLE_CCC_FATAL_RSTDAA_ERR_SIGNAL_EN_BIT 19
 
// Standby Controller Interrupt Force
#define I3C_STBY_CR_INTR_FORCE_REG_OFFSET 0x304
#define I3C_STBY_CR_INTR_FORCE_REG_RESVAL 0x0u
#define I3C_STBY_CR_INTR_FORCE_CRR_RESPONSE_FORCE_BIT 10
#define I3C_STBY_CR_INTR_FORCE_STBY_CR_DYN_ADDR_FORCE_BIT 11
#define I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_NACKED_FORCE_BIT 12
#define I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_OK_FORCE_BIT 13
#define I3C_STBY_CR_INTR_FORCE_STBY_CR_ACCEPT_ERR_FORCE_BIT 14
#define I3C_STBY_CR_INTR_FORCE_STBY_CR_OP_RSTACT_FORCE_BIT 16
#define I3C_STBY_CR_INTR_FORCE_CCC_PARAM_MODIFIED_FORCE_BIT 17
#define I3C_STBY_CR_INTR_FORCE_CCC_UNHANDLED_NACK_FORCE_BIT 18
#define I3C_STBY_CR_INTR_FORCE_CCC_FATAL_RSTDAA_ERR_FORCE_BIT 19
 
// Standby Controller CCC Auto-Response Config Get Capabilities
#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_REG_OFFSET 0x308
#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_REG_RESVAL 0x0u
#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_MASK 0x7u
#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_OFFSET 0
#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_MASK, .index = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP1_BUS_CONFIG_OFFSET })
#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_MASK 0xfu
#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_OFFSET 8
#define I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_MASK, .index = I3C_STBY_CR_CCC_CONFIG_GETCAPS_F2_CRCAP2_DEV_INTERACT_OFFSET })
 
// Standby Controller CCC Auto-Response Config Target Reset Action
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_REG_OFFSET 0x30c
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_REG_RESVAL 0x80000000u
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_MASK 0xffu
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_OFFSET 0
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_MASK, .index = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RST_ACTION_OFFSET })
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_MASK 0xffu
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_OFFSET 8
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_MASK, .index = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_PERIPHERAL_OFFSET })
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_MASK 0xffu
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_OFFSET 16
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_FIELD \
  ((bitfield_field32_t) { .mask = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_MASK, .index = I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_TIME_TARGET_OFFSET })
#define I3C_STBY_CR_CCC_CONFIG_RSTACT_PARAMS_RESET_DYNAMIC_ADDR_BIT 31
 
// Target Transaction Interface Extended Capability Header
#define I3C_TTI_EXTCAP_HEADER_REG_OFFSET 0x310
#define I3C_TTI_EXTCAP_HEADER_REG_RESVAL 0x59c8u
#define I3C_TTI_EXTCAP_HEADER_CAP_ID_MASK 0xffu
#define I3C_TTI_EXTCAP_HEADER_CAP_ID_OFFSET 0
#define I3C_TTI_EXTCAP_HEADER_CAP_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TTI_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_TTI_EXTCAP_HEADER_CAP_ID_OFFSET })
#define I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_MASK 0xffffu
#define I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_OFFSET 8
#define I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_TTI_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
 
// Target Interrupt Status.
#define I3C_TARG_INTR_STATUS_REG_OFFSET 0x314
#define I3C_TARG_INTR_STATUS_REG_RESVAL 0x0u
#define I3C_TARG_INTR_STATUS_RX_DESC_READY_STAT_BIT 0
#define I3C_TARG_INTR_STATUS_IBI_STATUS_THLD_STAT_BIT 1
#define I3C_TARG_INTR_STATUS_ASYNC_EVT_READY_STAT_BIT 2
#define I3C_TARG_INTR_STATUS_TRANSFER_ABORT_STAT_BIT 3
#define I3C_TARG_INTR_STATUS_TRANSFER_ERR_STAT_BIT 4
#define I3C_TARG_INTR_STATUS_RX_BUFFER_OVF_STAT_BIT 5
#define I3C_TARG_INTR_STATUS_ASYNC_EVT_OVF_STAT_BIT 6
#define I3C_TARG_INTR_STATUS_TX0_THLD_STAT_BIT 8
#define I3C_TARG_INTR_STATUS_TX1_THLD_STAT_BIT 9
#define I3C_TARG_INTR_STATUS_TX2_THLD_STAT_BIT 10
#define I3C_TARG_INTR_STATUS_TX3_THLD_STAT_BIT 11
#define I3C_TARG_INTR_STATUS_TX0_DESC_READY_STAT_BIT 16
#define I3C_TARG_INTR_STATUS_TX1_DESC_READY_STAT_BIT 17
#define I3C_TARG_INTR_STATUS_TX2_DESC_READY_STAT_BIT 18
#define I3C_TARG_INTR_STATUS_TX3_DESC_READY_STAT_BIT 19
#define I3C_TARG_INTR_STATUS_TE_STAT_BIT 31
 
// Target Interrupt Status Enable.
#define I3C_TARG_INTR_STATUS_ENABLE_REG_OFFSET 0x318
#define I3C_TARG_INTR_STATUS_ENABLE_REG_RESVAL 0x0u
#define I3C_TARG_INTR_STATUS_ENABLE_RX_DESC_READY_STAT_EN_BIT 0
#define I3C_TARG_INTR_STATUS_ENABLE_IBI_STATUS_THLD_STAT_EN_BIT 1
#define I3C_TARG_INTR_STATUS_ENABLE_ASYNC_EVT_READY_STAT_EN_BIT 2
#define I3C_TARG_INTR_STATUS_ENABLE_TRANSFER_ABORT_STAT_EN_BIT 3
#define I3C_TARG_INTR_STATUS_ENABLE_TRANSFER_ERR_STAT_EN_BIT 4
#define I3C_TARG_INTR_STATUS_ENABLE_RX_BUFFER_OVF_STAT_EN_BIT 5
#define I3C_TARG_INTR_STATUS_ENABLE_ASYNC_EVT_OVF_STAT_EN_BIT 6
#define I3C_TARG_INTR_STATUS_ENABLE_TX0_THLD_STAT_EN_BIT 8
#define I3C_TARG_INTR_STATUS_ENABLE_TX1_THLD_STAT_EN_BIT 9
#define I3C_TARG_INTR_STATUS_ENABLE_TX2_THLD_STAT_EN_BIT 10
#define I3C_TARG_INTR_STATUS_ENABLE_TX3_THLD_STAT_EN_BIT 11
#define I3C_TARG_INTR_STATUS_ENABLE_TX0_DESC_READY_STAT_EN_BIT 16
#define I3C_TARG_INTR_STATUS_ENABLE_TX1_DESC_READY_STAT_EN_BIT 17
#define I3C_TARG_INTR_STATUS_ENABLE_TX2_DESC_READY_STAT_EN_BIT 18
#define I3C_TARG_INTR_STATUS_ENABLE_TX3_DESC_READY_STAT_EN_BIT 19
#define I3C_TARG_INTR_STATUS_ENABLE_TE_STAT_EN_BIT 31
 
// Target Interrupt Signal Enable.
#define I3C_TARG_INTR_SIGNAL_ENABLE_REG_OFFSET 0x31c
#define I3C_TARG_INTR_SIGNAL_ENABLE_REG_RESVAL 0x0u
#define I3C_TARG_INTR_SIGNAL_ENABLE_RX_DESC_READY_SIGNAL_EN_BIT 0
#define I3C_TARG_INTR_SIGNAL_ENABLE_IBI_STATUS_THLD_SIGNAL_EN_BIT 1
#define I3C_TARG_INTR_SIGNAL_ENABLE_ASYNC_EVT_READY_SIGNAL_EN_BIT 2
#define I3C_TARG_INTR_SIGNAL_ENABLE_TRANSFER_ABORT_SIGNAL_EN_BIT 3
#define I3C_TARG_INTR_SIGNAL_ENABLE_TRANSFER_ERR_SIGNAL_EN_BIT 4
#define I3C_TARG_INTR_SIGNAL_ENABLE_RX_BUFFER_OVF_SIGNAL_EN_BIT 5
#define I3C_TARG_INTR_SIGNAL_ENABLE_ASYNC_EVT_OVF_SIGNAL_EN_BIT 6
#define I3C_TARG_INTR_SIGNAL_ENABLE_TX0_THLD_SIGNAL_EN_BIT 8
#define I3C_TARG_INTR_SIGNAL_ENABLE_TX1_THLD_SIGNAL_EN_BIT 9
#define I3C_TARG_INTR_SIGNAL_ENABLE_TX2_THLD_SIGNAL_EN_BIT 10
#define I3C_TARG_INTR_SIGNAL_ENABLE_TX3_THLD_SIGNAL_EN_BIT 11
#define I3C_TARG_INTR_SIGNAL_ENABLE_TX0_DESC_READY_SIGNAL_EN_BIT 16
#define I3C_TARG_INTR_SIGNAL_ENABLE_TX1_DESC_READY_SIGNAL_EN_BIT 17
#define I3C_TARG_INTR_SIGNAL_ENABLE_TX2_DESC_READY_SIGNAL_EN_BIT 18
#define I3C_TARG_INTR_SIGNAL_ENABLE_TX3_DESC_READY_SIGNAL_EN_BIT 19
#define I3C_TARG_INTR_SIGNAL_ENABLE_TE_SIGNAL_EN_BIT 31
 
// Target Interrupt Force.
#define I3C_TARG_INTR_FORCE_REG_OFFSET 0x320
#define I3C_TARG_INTR_FORCE_REG_RESVAL 0x0u
#define I3C_TARG_INTR_FORCE_RX_DESC_READY_FORCE_BIT 0
#define I3C_TARG_INTR_FORCE_IBI_THLD_FORCE_BIT 1
#define I3C_TARG_INTR_FORCE_ASYNC_EVT_READY_FORCE_BIT 2
#define I3C_TARG_INTR_FORCE_TRANSFER_ABORT_FORCE_BIT 3
#define I3C_TARG_INTR_FORCE_TRANSFER_ERR_FORCE_BIT 4
#define I3C_TARG_INTR_FORCE_RX_BUFFER_OVF_FORCE_BIT 5
#define I3C_TARG_INTR_FORCE_ASYNC_EVT_OVF_FORCE_BIT 6
#define I3C_TARG_INTR_FORCE_TX0_THLD_FORCE_BIT 8
#define I3C_TARG_INTR_FORCE_TX1_THLD_FORCE_BIT 9
#define I3C_TARG_INTR_FORCE_TX2_THLD_FORCE_BIT 10
#define I3C_TARG_INTR_FORCE_TX3_THLD_FORCE_BIT 11
#define I3C_TARG_INTR_FORCE_TX0_DESC_READY_FORCE_BIT 16
#define I3C_TARG_INTR_FORCE_TX1_DESC_READY_FORCE_BIT 17
#define I3C_TARG_INTR_FORCE_TX2_DESC_READY_FORCE_BIT 18
#define I3C_TARG_INTR_FORCE_TX3_DESC_READY_FORCE_BIT 19
#define I3C_TARG_INTR_FORCE_TE_FORCE_BIT 31
 
// Target PIO mode Control register.
#define I3C_TARG_PIO_CONTROL_REG_OFFSET 0x324
#define I3C_TARG_PIO_CONTROL_REG_RESVAL 0x0u
#define I3C_TARG_PIO_CONTROL_IBI_SUSPENDED_BIT 0
#define I3C_TARG_PIO_CONTROL_IBI_ABORT_BIT 1
#define I3C_TARG_PIO_CONTROL_SUSPENDED_MASK 0xfu
#define I3C_TARG_PIO_CONTROL_SUSPENDED_OFFSET 16
#define I3C_TARG_PIO_CONTROL_SUSPENDED_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_PIO_CONTROL_SUSPENDED_MASK, .index = I3C_TARG_PIO_CONTROL_SUSPENDED_OFFSET })
#define I3C_TARG_PIO_CONTROL_ABORT_MASK 0xfu
#define I3C_TARG_PIO_CONTROL_ABORT_OFFSET 24
#define I3C_TARG_PIO_CONTROL_ABORT_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_PIO_CONTROL_ABORT_MASK, .index = I3C_TARG_PIO_CONTROL_ABORT_OFFSET })
 
// Target Asynchronous Event Queue Control.
#define I3C_TARG_ASYNC_EVT_CONTROL_REG_OFFSET 0x328
#define I3C_TARG_ASYNC_EVT_CONTROL_REG_RESVAL 0x0u
#define I3C_TARG_ASYNC_EVT_CONTROL_BCST_CCC_BIT 0
#define I3C_TARG_ASYNC_EVT_CONTROL_DIR_SET_CCC_BIT 1
#define I3C_TARG_ASYNC_EVT_CONTROL_DIR_GET_CCC_BIT 2
#define I3C_TARG_ASYNC_EVT_CONTROL_TX_NOTIFY_BIT 3
#define I3C_TARG_ASYNC_EVT_CONTROL_IBI_NOTIFY_BIT 4
#define I3C_TARG_ASYNC_EVT_CONTROL_TX_SUSPEND_BIT 5
#define I3C_TARG_ASYNC_EVT_CONTROL_IBI_SUSPEND_BIT 6
#define I3C_TARG_ASYNC_EVT_CONTROL_BUS_EVENTS_BIT 7
#define I3C_TARG_ASYNC_EVT_CONTROL_QUEUE_RESET_BIT 31
 
// Target Error counts.
#define I3C_TARG_ERROR_REG_OFFSET 0x32c
#define I3C_TARG_ERROR_REG_RESVAL 0x0u
#define I3C_TARG_ERROR_TE0_MASK 0xfu
#define I3C_TARG_ERROR_TE0_OFFSET 0
#define I3C_TARG_ERROR_TE0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE0_MASK, .index = I3C_TARG_ERROR_TE0_OFFSET })
#define I3C_TARG_ERROR_TE1_MASK 0xfu
#define I3C_TARG_ERROR_TE1_OFFSET 4
#define I3C_TARG_ERROR_TE1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE1_MASK, .index = I3C_TARG_ERROR_TE1_OFFSET })
#define I3C_TARG_ERROR_TE2_MASK 0xfu
#define I3C_TARG_ERROR_TE2_OFFSET 8
#define I3C_TARG_ERROR_TE2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE2_MASK, .index = I3C_TARG_ERROR_TE2_OFFSET })
#define I3C_TARG_ERROR_TE3_MASK 0xfu
#define I3C_TARG_ERROR_TE3_OFFSET 12
#define I3C_TARG_ERROR_TE3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE3_MASK, .index = I3C_TARG_ERROR_TE3_OFFSET })
#define I3C_TARG_ERROR_TE4_MASK 0xfu
#define I3C_TARG_ERROR_TE4_OFFSET 16
#define I3C_TARG_ERROR_TE4_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE4_MASK, .index = I3C_TARG_ERROR_TE4_OFFSET })
#define I3C_TARG_ERROR_TE5_MASK 0xfu
#define I3C_TARG_ERROR_TE5_OFFSET 20
#define I3C_TARG_ERROR_TE5_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE5_MASK, .index = I3C_TARG_ERROR_TE5_OFFSET })
#define I3C_TARG_ERROR_TE6_MASK 0xfu
#define I3C_TARG_ERROR_TE6_OFFSET 24
#define I3C_TARG_ERROR_TE6_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_TE6_MASK, .index = I3C_TARG_ERROR_TE6_OFFSET })
#define I3C_TARG_ERROR_DBR_MASK 0xfu
#define I3C_TARG_ERROR_DBR_OFFSET 28
#define I3C_TARG_ERROR_DBR_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ERROR_DBR_MASK, .index = I3C_TARG_ERROR_DBR_OFFSET })
 
// Target-side control register for setting queue interrupt thresholds.
#define I3C_TARG_QUEUE_THLD_CTRL_REG_OFFSET 0x330
#define I3C_TARG_QUEUE_THLD_CTRL_REG_RESVAL 0x1000100u
#define I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_MASK 0xffu
#define I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_OFFSET 8
#define I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_MASK, .index = I3C_TARG_QUEUE_THLD_CTRL_RX_DESC_THLD_OFFSET })
#define I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK 0xffu
#define I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET 24
#define I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_MASK, .index = I3C_TARG_QUEUE_THLD_CTRL_IBI_STATUS_THLD_OFFSET })
 
// Target-side queue levels.
#define I3C_TARG_QUEUE_STATUS_LEVEL_REG_OFFSET 0x334
#define I3C_TARG_QUEUE_STATUS_LEVEL_REG_RESVAL 0x0u
#define I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_MASK 0xffu
#define I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_OFFSET 0
#define I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_MASK, .index = I3C_TARG_QUEUE_STATUS_LEVEL_RX_DESC_LVL_OFFSET })
#define I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_MASK 0xfffu
#define I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_OFFSET 16
#define I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_MASK, .index = I3C_TARG_QUEUE_STATUS_LEVEL_ASYNC_EVT_LVL_OFFSET })
 
// Target-side control register for setting buffer interrupt thresholds.
#define I3C_TARG_BUF_THLD_CTRL_REG_OFFSET 0x338
#define I3C_TARG_BUF_THLD_CTRL_REG_RESVAL 0x10000001u
#define I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_MASK 0xfffu
#define I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_OFFSET 0
#define I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_MASK, .index = I3C_TARG_BUF_THLD_CTRL_RX_SEGMENT_SIZE_OFFSET })
#define I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_MASK 0x7u
#define I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_OFFSET 28
#define I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_MASK, .index = I3C_TARG_BUF_THLD_CTRL_RX_START_THLD_OFFSET })
 
// Target-side data buffer levels.
#define I3C_TARG_BUF_STATUS_LEVEL_REG_OFFSET 0x33c
#define I3C_TARG_BUF_STATUS_LEVEL_REG_RESVAL 0x400000u
#define I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_MASK 0xfffu
#define I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_OFFSET 0
#define I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_MASK, .index = I3C_TARG_BUF_STATUS_LEVEL_RX_BUF_LVL_OFFSET })
#define I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_MASK 0xfffu
#define I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_OFFSET 16
#define I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_MASK, .index = I3C_TARG_BUF_STATUS_LEVEL_IBI_FREE_LVL_OFFSET })
 
// Target Read/Write Length. (common parameters)
#define I3C_TARG_RW_LEN_MRL_FIELD_WIDTH 16
#define I3C_TARG_RW_LEN_MWL_FIELD_WIDTH 16
#define I3C_TARG_RW_LEN_MULTIREG_COUNT 4
 
// Target Read/Write Length.
#define I3C_TARG_RW_LEN_0_REG_OFFSET 0x340
#define I3C_TARG_RW_LEN_0_REG_RESVAL 0xffffffffu
#define I3C_TARG_RW_LEN_0_MRL_0_MASK 0xffffu
#define I3C_TARG_RW_LEN_0_MRL_0_OFFSET 0
#define I3C_TARG_RW_LEN_0_MRL_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_0_MRL_0_MASK, .index = I3C_TARG_RW_LEN_0_MRL_0_OFFSET })
#define I3C_TARG_RW_LEN_0_MWL_0_MASK 0xffffu
#define I3C_TARG_RW_LEN_0_MWL_0_OFFSET 16
#define I3C_TARG_RW_LEN_0_MWL_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_0_MWL_0_MASK, .index = I3C_TARG_RW_LEN_0_MWL_0_OFFSET })
 
// Target Read/Write Length.
#define I3C_TARG_RW_LEN_1_REG_OFFSET 0x344
#define I3C_TARG_RW_LEN_1_REG_RESVAL 0xffffffffu
#define I3C_TARG_RW_LEN_1_MRL_1_MASK 0xffffu
#define I3C_TARG_RW_LEN_1_MRL_1_OFFSET 0
#define I3C_TARG_RW_LEN_1_MRL_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_1_MRL_1_MASK, .index = I3C_TARG_RW_LEN_1_MRL_1_OFFSET })
#define I3C_TARG_RW_LEN_1_MWL_1_MASK 0xffffu
#define I3C_TARG_RW_LEN_1_MWL_1_OFFSET 16
#define I3C_TARG_RW_LEN_1_MWL_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_1_MWL_1_MASK, .index = I3C_TARG_RW_LEN_1_MWL_1_OFFSET })
 
// Target Read/Write Length.
#define I3C_TARG_RW_LEN_2_REG_OFFSET 0x348
#define I3C_TARG_RW_LEN_2_REG_RESVAL 0xffffffffu
#define I3C_TARG_RW_LEN_2_MRL_2_MASK 0xffffu
#define I3C_TARG_RW_LEN_2_MRL_2_OFFSET 0
#define I3C_TARG_RW_LEN_2_MRL_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_2_MRL_2_MASK, .index = I3C_TARG_RW_LEN_2_MRL_2_OFFSET })
#define I3C_TARG_RW_LEN_2_MWL_2_MASK 0xffffu
#define I3C_TARG_RW_LEN_2_MWL_2_OFFSET 16
#define I3C_TARG_RW_LEN_2_MWL_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_2_MWL_2_MASK, .index = I3C_TARG_RW_LEN_2_MWL_2_OFFSET })
 
// Target Read/Write Length.
#define I3C_TARG_RW_LEN_3_REG_OFFSET 0x34c
#define I3C_TARG_RW_LEN_3_REG_RESVAL 0xffffffffu
#define I3C_TARG_RW_LEN_3_MRL_3_MASK 0xffffu
#define I3C_TARG_RW_LEN_3_MRL_3_OFFSET 0
#define I3C_TARG_RW_LEN_3_MRL_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_3_MRL_3_MASK, .index = I3C_TARG_RW_LEN_3_MRL_3_OFFSET })
#define I3C_TARG_RW_LEN_3_MWL_3_MASK 0xffffu
#define I3C_TARG_RW_LEN_3_MWL_3_OFFSET 16
#define I3C_TARG_RW_LEN_3_MWL_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_RW_LEN_3_MWL_3_MASK, .index = I3C_TARG_RW_LEN_3_MWL_3_OFFSET })
 
// Target IBI payload Length. (common parameters)
#define I3C_TARG_IBI_LEN_IBI_LEN_FIELD_WIDTH 8
#define I3C_TARG_IBI_LEN_MULTIREG_COUNT 1
 
// Target IBI payload Length.
#define I3C_TARG_IBI_LEN_REG_OFFSET 0x350
#define I3C_TARG_IBI_LEN_REG_RESVAL 0xffffffffu
#define I3C_TARG_IBI_LEN_IBI_LEN_0_MASK 0xffu
#define I3C_TARG_IBI_LEN_IBI_LEN_0_OFFSET 0
#define I3C_TARG_IBI_LEN_IBI_LEN_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_0_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_0_OFFSET })
#define I3C_TARG_IBI_LEN_IBI_LEN_1_MASK 0xffu
#define I3C_TARG_IBI_LEN_IBI_LEN_1_OFFSET 8
#define I3C_TARG_IBI_LEN_IBI_LEN_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_1_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_1_OFFSET })
#define I3C_TARG_IBI_LEN_IBI_LEN_2_MASK 0xffu
#define I3C_TARG_IBI_LEN_IBI_LEN_2_OFFSET 16
#define I3C_TARG_IBI_LEN_IBI_LEN_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_2_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_2_OFFSET })
#define I3C_TARG_IBI_LEN_IBI_LEN_3_MASK 0xffu
#define I3C_TARG_IBI_LEN_IBI_LEN_3_OFFSET 24
#define I3C_TARG_IBI_LEN_IBI_LEN_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_IBI_LEN_IBI_LEN_3_MASK, .index = I3C_TARG_IBI_LEN_IBI_LEN_3_OFFSET })
 
// Target Event enables. (common parameters)
#define I3C_TARG_EVENT_ENABLE_ENINT_FIELD_WIDTH 1
#define I3C_TARG_EVENT_ENABLE_ENCR_FIELD_WIDTH 1
#define I3C_TARG_EVENT_ENABLE_ENHJ_FIELD_WIDTH 1
#define I3C_TARG_EVENT_ENABLE_MULTIREG_COUNT 4
 
// Target Event enables.
#define I3C_TARG_EVENT_ENABLE_0_REG_OFFSET 0x354
#define I3C_TARG_EVENT_ENABLE_0_REG_RESVAL 0x7u
#define I3C_TARG_EVENT_ENABLE_0_ENINT_0_BIT 0
#define I3C_TARG_EVENT_ENABLE_0_ENCR_0_BIT 1
#define I3C_TARG_EVENT_ENABLE_0_ENHJ_0_BIT 2
 
// Target Event enables.
#define I3C_TARG_EVENT_ENABLE_1_REG_OFFSET 0x358
#define I3C_TARG_EVENT_ENABLE_1_REG_RESVAL 0x7u
#define I3C_TARG_EVENT_ENABLE_1_ENINT_1_BIT 0
#define I3C_TARG_EVENT_ENABLE_1_ENCR_1_BIT 1
#define I3C_TARG_EVENT_ENABLE_1_ENHJ_1_BIT 2
 
// Target Event enables.
#define I3C_TARG_EVENT_ENABLE_2_REG_OFFSET 0x35c
#define I3C_TARG_EVENT_ENABLE_2_REG_RESVAL 0x7u
#define I3C_TARG_EVENT_ENABLE_2_ENINT_2_BIT 0
#define I3C_TARG_EVENT_ENABLE_2_ENCR_2_BIT 1
#define I3C_TARG_EVENT_ENABLE_2_ENHJ_2_BIT 2
 
// Target Event enables.
#define I3C_TARG_EVENT_ENABLE_3_REG_OFFSET 0x360
#define I3C_TARG_EVENT_ENABLE_3_REG_RESVAL 0x7u
#define I3C_TARG_EVENT_ENABLE_3_ENINT_3_BIT 0
#define I3C_TARG_EVENT_ENABLE_3_ENCR_3_BIT 1
#define I3C_TARG_EVENT_ENABLE_3_ENHJ_3_BIT 2
 
// Target State Debug
#define I3C_TARG_STATE_DEBUG_REG_OFFSET 0x364
#define I3C_TARG_STATE_DEBUG_REG_RESVAL 0x3u
#define I3C_TARG_STATE_DEBUG_SCL_LINE_SIGNAL_LEVEL_BIT 0
#define I3C_TARG_STATE_DEBUG_SDA_LINE_SIGNAL_LEVEL_BIT 1
#define I3C_TARG_STATE_DEBUG_BUS_AVAIL_BIT 8
#define I3C_TARG_STATE_DEBUG_BUS_IDLE_BIT 9
#define I3C_TARG_STATE_DEBUG_BUS_MODE_MASK 0xfu
#define I3C_TARG_STATE_DEBUG_BUS_MODE_OFFSET 12
#define I3C_TARG_STATE_DEBUG_BUS_MODE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_STATE_DEBUG_BUS_MODE_MASK, .index = I3C_TARG_STATE_DEBUG_BUS_MODE_OFFSET })
#define I3C_TARG_STATE_DEBUG_FSM_STATE_MASK 0xffu
#define I3C_TARG_STATE_DEBUG_FSM_STATE_OFFSET 16
#define I3C_TARG_STATE_DEBUG_FSM_STATE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_STATE_DEBUG_FSM_STATE_MASK, .index = I3C_TARG_STATE_DEBUG_FSM_STATE_OFFSET })
#define I3C_TARG_STATE_DEBUG_TRX_STATE_MASK 0xffu
#define I3C_TARG_STATE_DEBUG_TRX_STATE_OFFSET 24
#define I3C_TARG_STATE_DEBUG_TRX_STATE_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_STATE_DEBUG_TRX_STATE_MASK, .index = I3C_TARG_STATE_DEBUG_TRX_STATE_OFFSET })
 
// Enable signals for individual virtual targets. (common parameters)
#define I3C_TARG_ENABLE_ENABLE_FIELD_WIDTH 1
#define I3C_TARG_ENABLE_MULTIREG_COUNT 1
 
// Enable signals for individual virtual targets.
#define I3C_TARG_ENABLE_REG_OFFSET 0x368
#define I3C_TARG_ENABLE_REG_RESVAL 0x0u
#define I3C_TARG_ENABLE_ENABLE_0_BIT 0
#define I3C_TARG_ENABLE_ENABLE_1_BIT 1
#define I3C_TARG_ENABLE_ENABLE_2_BIT 2
#define I3C_TARG_ENABLE_ENABLE_3_BIT 3
 
// Group addressing configuration. (common parameters)
#define I3C_TARG_GROUP_GROUP_ADDR_FIELD_WIDTH 7
#define I3C_TARG_GROUP_TARGETS_FIELD_WIDTH 4
#define I3C_TARG_GROUP_MULTIREG_COUNT 8
 
// Group addressing configuration.
#define I3C_TARG_GROUP_0_REG_OFFSET 0x36c
#define I3C_TARG_GROUP_0_REG_RESVAL 0x0u
#define I3C_TARG_GROUP_0_GROUP_ADDR_0_MASK 0x7fu
#define I3C_TARG_GROUP_0_GROUP_ADDR_0_OFFSET 0
#define I3C_TARG_GROUP_0_GROUP_ADDR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_0_GROUP_ADDR_0_MASK, .index = I3C_TARG_GROUP_0_GROUP_ADDR_0_OFFSET })
#define I3C_TARG_GROUP_0_TARGETS_0_MASK 0xfu
#define I3C_TARG_GROUP_0_TARGETS_0_OFFSET 8
#define I3C_TARG_GROUP_0_TARGETS_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_0_TARGETS_0_MASK, .index = I3C_TARG_GROUP_0_TARGETS_0_OFFSET })
 
// Group addressing configuration.
#define I3C_TARG_GROUP_1_REG_OFFSET 0x370
#define I3C_TARG_GROUP_1_REG_RESVAL 0x0u
#define I3C_TARG_GROUP_1_GROUP_ADDR_1_MASK 0x7fu
#define I3C_TARG_GROUP_1_GROUP_ADDR_1_OFFSET 0
#define I3C_TARG_GROUP_1_GROUP_ADDR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_1_GROUP_ADDR_1_MASK, .index = I3C_TARG_GROUP_1_GROUP_ADDR_1_OFFSET })
#define I3C_TARG_GROUP_1_TARGETS_1_MASK 0xfu
#define I3C_TARG_GROUP_1_TARGETS_1_OFFSET 8
#define I3C_TARG_GROUP_1_TARGETS_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_1_TARGETS_1_MASK, .index = I3C_TARG_GROUP_1_TARGETS_1_OFFSET })
 
// Group addressing configuration.
#define I3C_TARG_GROUP_2_REG_OFFSET 0x374
#define I3C_TARG_GROUP_2_REG_RESVAL 0x0u
#define I3C_TARG_GROUP_2_GROUP_ADDR_2_MASK 0x7fu
#define I3C_TARG_GROUP_2_GROUP_ADDR_2_OFFSET 0
#define I3C_TARG_GROUP_2_GROUP_ADDR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_2_GROUP_ADDR_2_MASK, .index = I3C_TARG_GROUP_2_GROUP_ADDR_2_OFFSET })
#define I3C_TARG_GROUP_2_TARGETS_2_MASK 0xfu
#define I3C_TARG_GROUP_2_TARGETS_2_OFFSET 8
#define I3C_TARG_GROUP_2_TARGETS_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_2_TARGETS_2_MASK, .index = I3C_TARG_GROUP_2_TARGETS_2_OFFSET })
 
// Group addressing configuration.
#define I3C_TARG_GROUP_3_REG_OFFSET 0x378
#define I3C_TARG_GROUP_3_REG_RESVAL 0x0u
#define I3C_TARG_GROUP_3_GROUP_ADDR_3_MASK 0x7fu
#define I3C_TARG_GROUP_3_GROUP_ADDR_3_OFFSET 0
#define I3C_TARG_GROUP_3_GROUP_ADDR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_3_GROUP_ADDR_3_MASK, .index = I3C_TARG_GROUP_3_GROUP_ADDR_3_OFFSET })
#define I3C_TARG_GROUP_3_TARGETS_3_MASK 0xfu
#define I3C_TARG_GROUP_3_TARGETS_3_OFFSET 8
#define I3C_TARG_GROUP_3_TARGETS_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_3_TARGETS_3_MASK, .index = I3C_TARG_GROUP_3_TARGETS_3_OFFSET })
 
// Group addressing configuration.
#define I3C_TARG_GROUP_4_REG_OFFSET 0x37c
#define I3C_TARG_GROUP_4_REG_RESVAL 0x0u
#define I3C_TARG_GROUP_4_GROUP_ADDR_4_MASK 0x7fu
#define I3C_TARG_GROUP_4_GROUP_ADDR_4_OFFSET 0
#define I3C_TARG_GROUP_4_GROUP_ADDR_4_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_4_GROUP_ADDR_4_MASK, .index = I3C_TARG_GROUP_4_GROUP_ADDR_4_OFFSET })
#define I3C_TARG_GROUP_4_TARGETS_4_MASK 0xfu
#define I3C_TARG_GROUP_4_TARGETS_4_OFFSET 8
#define I3C_TARG_GROUP_4_TARGETS_4_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_4_TARGETS_4_MASK, .index = I3C_TARG_GROUP_4_TARGETS_4_OFFSET })
 
// Group addressing configuration.
#define I3C_TARG_GROUP_5_REG_OFFSET 0x380
#define I3C_TARG_GROUP_5_REG_RESVAL 0x0u
#define I3C_TARG_GROUP_5_GROUP_ADDR_5_MASK 0x7fu
#define I3C_TARG_GROUP_5_GROUP_ADDR_5_OFFSET 0
#define I3C_TARG_GROUP_5_GROUP_ADDR_5_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_5_GROUP_ADDR_5_MASK, .index = I3C_TARG_GROUP_5_GROUP_ADDR_5_OFFSET })
#define I3C_TARG_GROUP_5_TARGETS_5_MASK 0xfu
#define I3C_TARG_GROUP_5_TARGETS_5_OFFSET 8
#define I3C_TARG_GROUP_5_TARGETS_5_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_5_TARGETS_5_MASK, .index = I3C_TARG_GROUP_5_TARGETS_5_OFFSET })
 
// Group addressing configuration.
#define I3C_TARG_GROUP_6_REG_OFFSET 0x384
#define I3C_TARG_GROUP_6_REG_RESVAL 0x0u
#define I3C_TARG_GROUP_6_GROUP_ADDR_6_MASK 0x7fu
#define I3C_TARG_GROUP_6_GROUP_ADDR_6_OFFSET 0
#define I3C_TARG_GROUP_6_GROUP_ADDR_6_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_6_GROUP_ADDR_6_MASK, .index = I3C_TARG_GROUP_6_GROUP_ADDR_6_OFFSET })
#define I3C_TARG_GROUP_6_TARGETS_6_MASK 0xfu
#define I3C_TARG_GROUP_6_TARGETS_6_OFFSET 8
#define I3C_TARG_GROUP_6_TARGETS_6_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_6_TARGETS_6_MASK, .index = I3C_TARG_GROUP_6_TARGETS_6_OFFSET })
 
// Group addressing configuration.
#define I3C_TARG_GROUP_7_REG_OFFSET 0x388
#define I3C_TARG_GROUP_7_REG_RESVAL 0x0u
#define I3C_TARG_GROUP_7_GROUP_ADDR_7_MASK 0x7fu
#define I3C_TARG_GROUP_7_GROUP_ADDR_7_OFFSET 0
#define I3C_TARG_GROUP_7_GROUP_ADDR_7_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_7_GROUP_ADDR_7_MASK, .index = I3C_TARG_GROUP_7_GROUP_ADDR_7_OFFSET })
#define I3C_TARG_GROUP_7_TARGETS_7_MASK 0xfu
#define I3C_TARG_GROUP_7_TARGETS_7_OFFSET 8
#define I3C_TARG_GROUP_7_TARGETS_7_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_GROUP_7_TARGETS_7_MASK, .index = I3C_TARG_GROUP_7_TARGETS_7_OFFSET })
 
// Target control register for setting Tx thresholds. (common parameters)
#define I3C_TARG_TX_THLD_CTRL_TX_BUF_FREE_THLD_FIELD_WIDTH 12
#define I3C_TARG_TX_THLD_CTRL_TX_DESC_EMPTY_THLD_FIELD_WIDTH 8
#define I3C_TARG_TX_THLD_CTRL_TX_START_THLD_FIELD_WIDTH 4
#define I3C_TARG_TX_THLD_CTRL_MULTIREG_COUNT 4
 
// Target control register for setting Tx thresholds.
#define I3C_TARG_TX_THLD_CTRL_0_REG_OFFSET 0x38c
#define I3C_TARG_TX_THLD_CTRL_0_REG_RESVAL 0x10010001u
#define I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_MASK 0xfffu
#define I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_OFFSET 0
#define I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_MASK, .index = I3C_TARG_TX_THLD_CTRL_0_TX_BUF_FREE_THLD_0_OFFSET })
#define I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_MASK 0xffu
#define I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_OFFSET 16
#define I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_MASK, .index = I3C_TARG_TX_THLD_CTRL_0_TX_DESC_EMPTY_THLD_0_OFFSET })
#define I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_MASK 0xfu
#define I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_OFFSET 28
#define I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_MASK, .index = I3C_TARG_TX_THLD_CTRL_0_TX_START_THLD_0_OFFSET })
 
// Target control register for setting Tx thresholds.
#define I3C_TARG_TX_THLD_CTRL_1_REG_OFFSET 0x390
#define I3C_TARG_TX_THLD_CTRL_1_REG_RESVAL 0x10010001u
#define I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_MASK 0xfffu
#define I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_OFFSET 0
#define I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_MASK, .index = I3C_TARG_TX_THLD_CTRL_1_TX_BUF_FREE_THLD_1_OFFSET })
#define I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_MASK 0xffu
#define I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_OFFSET 16
#define I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_MASK, .index = I3C_TARG_TX_THLD_CTRL_1_TX_DESC_EMPTY_THLD_1_OFFSET })
#define I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_MASK 0xfu
#define I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_OFFSET 28
#define I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_MASK, .index = I3C_TARG_TX_THLD_CTRL_1_TX_START_THLD_1_OFFSET })
 
// Target control register for setting Tx thresholds.
#define I3C_TARG_TX_THLD_CTRL_2_REG_OFFSET 0x394
#define I3C_TARG_TX_THLD_CTRL_2_REG_RESVAL 0x10010001u
#define I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_MASK 0xfffu
#define I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_OFFSET 0
#define I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_MASK, .index = I3C_TARG_TX_THLD_CTRL_2_TX_BUF_FREE_THLD_2_OFFSET })
#define I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_MASK 0xffu
#define I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_OFFSET 16
#define I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_MASK, .index = I3C_TARG_TX_THLD_CTRL_2_TX_DESC_EMPTY_THLD_2_OFFSET })
#define I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_MASK 0xfu
#define I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_OFFSET 28
#define I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_MASK, .index = I3C_TARG_TX_THLD_CTRL_2_TX_START_THLD_2_OFFSET })
 
// Target control register for setting Tx thresholds.
#define I3C_TARG_TX_THLD_CTRL_3_REG_OFFSET 0x398
#define I3C_TARG_TX_THLD_CTRL_3_REG_RESVAL 0x10010001u
#define I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_MASK 0xfffu
#define I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_OFFSET 0
#define I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_MASK, .index = I3C_TARG_TX_THLD_CTRL_3_TX_BUF_FREE_THLD_3_OFFSET })
#define I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_MASK 0xffu
#define I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_OFFSET 16
#define I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_MASK, .index = I3C_TARG_TX_THLD_CTRL_3_TX_DESC_EMPTY_THLD_3_OFFSET })
#define I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_MASK 0xfu
#define I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_OFFSET 28
#define I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_MASK, .index = I3C_TARG_TX_THLD_CTRL_3_TX_START_THLD_3_OFFSET })
 
// Target status register reporting transmit queue levels. (common
// parameters)
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_TX_BUF_FREE_LVL_FIELD_WIDTH 12
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_TX_DESC_FREE_LVL_FIELD_WIDTH 8
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_MULTIREG_COUNT 4
 
// Target status register reporting transmit queue levels.
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_REG_OFFSET 0x39c
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_REG_RESVAL 0x80040u
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_MASK 0xfffu
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_OFFSET 0
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_BUF_FREE_LVL_0_OFFSET })
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_MASK 0xffu
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_OFFSET 16
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_0_TX_DESC_FREE_LVL_0_OFFSET })
 
// Target status register reporting transmit queue levels.
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_REG_OFFSET 0x3a0
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_REG_RESVAL 0x80040u
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_MASK 0xfffu
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_OFFSET 0
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_BUF_FREE_LVL_1_OFFSET })
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_MASK 0xffu
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_OFFSET 16
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_1_TX_DESC_FREE_LVL_1_OFFSET })
 
// Target status register reporting transmit queue levels.
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_REG_OFFSET 0x3a4
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_REG_RESVAL 0x80040u
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_MASK 0xfffu
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_OFFSET 0
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_BUF_FREE_LVL_2_OFFSET })
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_MASK 0xffu
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_OFFSET 16
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_2_TX_DESC_FREE_LVL_2_OFFSET })
 
// Target status register reporting transmit queue levels.
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_REG_OFFSET 0x3a8
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_REG_RESVAL 0x80040u
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_MASK 0xfffu
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_OFFSET 0
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_BUF_FREE_LVL_3_OFFSET })
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_MASK 0xffu
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_OFFSET 16
#define I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_MASK, .index = I3C_TARG_TX_QUEUE_STATUS_LEVEL_3_TX_DESC_FREE_LVL_3_OFFSET })
 
// Target address on the I3C bus. (common parameters)
#define I3C_TARG_ADDR_STATIC_ADDR_FIELD_WIDTH 7
#define I3C_TARG_ADDR_STATIC_ADDR_VALID_FIELD_WIDTH 1
#define I3C_TARG_ADDR_DYNAMIC_ADDR_FIELD_WIDTH 7
#define I3C_TARG_ADDR_DYNAMIC_ADDR_VALID_FIELD_WIDTH 1
#define I3C_TARG_ADDR_MULTIREG_COUNT 4
 
// Target address on the I3C bus.
#define I3C_TARG_ADDR_0_REG_OFFSET 0x3ac
#define I3C_TARG_ADDR_0_REG_RESVAL 0x0u
#define I3C_TARG_ADDR_0_STATIC_ADDR_0_MASK 0x7fu
#define I3C_TARG_ADDR_0_STATIC_ADDR_0_OFFSET 0
#define I3C_TARG_ADDR_0_STATIC_ADDR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_0_STATIC_ADDR_0_MASK, .index = I3C_TARG_ADDR_0_STATIC_ADDR_0_OFFSET })
#define I3C_TARG_ADDR_0_STATIC_ADDR_VALID_0_BIT 15
#define I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_MASK 0x7fu
#define I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_OFFSET 16
#define I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_MASK, .index = I3C_TARG_ADDR_0_DYNAMIC_ADDR_0_OFFSET })
#define I3C_TARG_ADDR_0_DYNAMIC_ADDR_VALID_0_BIT 31
 
// Target address on the I3C bus.
#define I3C_TARG_ADDR_1_REG_OFFSET 0x3b0
#define I3C_TARG_ADDR_1_REG_RESVAL 0x0u
#define I3C_TARG_ADDR_1_STATIC_ADDR_1_MASK 0x7fu
#define I3C_TARG_ADDR_1_STATIC_ADDR_1_OFFSET 0
#define I3C_TARG_ADDR_1_STATIC_ADDR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_1_STATIC_ADDR_1_MASK, .index = I3C_TARG_ADDR_1_STATIC_ADDR_1_OFFSET })
#define I3C_TARG_ADDR_1_STATIC_ADDR_VALID_1_BIT 15
#define I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_MASK 0x7fu
#define I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_OFFSET 16
#define I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_MASK, .index = I3C_TARG_ADDR_1_DYNAMIC_ADDR_1_OFFSET })
#define I3C_TARG_ADDR_1_DYNAMIC_ADDR_VALID_1_BIT 31
 
// Target address on the I3C bus.
#define I3C_TARG_ADDR_2_REG_OFFSET 0x3b4
#define I3C_TARG_ADDR_2_REG_RESVAL 0x0u
#define I3C_TARG_ADDR_2_STATIC_ADDR_2_MASK 0x7fu
#define I3C_TARG_ADDR_2_STATIC_ADDR_2_OFFSET 0
#define I3C_TARG_ADDR_2_STATIC_ADDR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_2_STATIC_ADDR_2_MASK, .index = I3C_TARG_ADDR_2_STATIC_ADDR_2_OFFSET })
#define I3C_TARG_ADDR_2_STATIC_ADDR_VALID_2_BIT 15
#define I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_MASK 0x7fu
#define I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_OFFSET 16
#define I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_MASK, .index = I3C_TARG_ADDR_2_DYNAMIC_ADDR_2_OFFSET })
#define I3C_TARG_ADDR_2_DYNAMIC_ADDR_VALID_2_BIT 31
 
// Target address on the I3C bus.
#define I3C_TARG_ADDR_3_REG_OFFSET 0x3b8
#define I3C_TARG_ADDR_3_REG_RESVAL 0x0u
#define I3C_TARG_ADDR_3_STATIC_ADDR_3_MASK 0x7fu
#define I3C_TARG_ADDR_3_STATIC_ADDR_3_OFFSET 0
#define I3C_TARG_ADDR_3_STATIC_ADDR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_3_STATIC_ADDR_3_MASK, .index = I3C_TARG_ADDR_3_STATIC_ADDR_3_OFFSET })
#define I3C_TARG_ADDR_3_STATIC_ADDR_VALID_3_BIT 15
#define I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_MASK 0x7fu
#define I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_OFFSET 16
#define I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_MASK, .index = I3C_TARG_ADDR_3_DYNAMIC_ADDR_3_OFFSET })
#define I3C_TARG_ADDR_3_DYNAMIC_ADDR_VALID_3_BIT 31
 
// Target Characteristics. (common parameters)
#define I3C_TARG_CHAR_PID_HI_FIELD_WIDTH 16
#define I3C_TARG_CHAR_DCR_FIELD_WIDTH 8
#define I3C_TARG_CHAR_BCR_FIELD_WIDTH 8
#define I3C_TARG_CHAR_MULTIREG_COUNT 4
 
// Target Characteristics.
#define I3C_TARG_CHAR_0_REG_OFFSET 0x3bc
#define I3C_TARG_CHAR_0_REG_RESVAL 0x3e000000u
#define I3C_TARG_CHAR_0_PID_HI_0_MASK 0xffffu
#define I3C_TARG_CHAR_0_PID_HI_0_OFFSET 0
#define I3C_TARG_CHAR_0_PID_HI_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_0_PID_HI_0_MASK, .index = I3C_TARG_CHAR_0_PID_HI_0_OFFSET })
#define I3C_TARG_CHAR_0_DCR_0_MASK 0xffu
#define I3C_TARG_CHAR_0_DCR_0_OFFSET 16
#define I3C_TARG_CHAR_0_DCR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_0_DCR_0_MASK, .index = I3C_TARG_CHAR_0_DCR_0_OFFSET })
#define I3C_TARG_CHAR_0_BCR_0_MASK 0xffu
#define I3C_TARG_CHAR_0_BCR_0_OFFSET 24
#define I3C_TARG_CHAR_0_BCR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_0_BCR_0_MASK, .index = I3C_TARG_CHAR_0_BCR_0_OFFSET })
 
// Target Characteristics.
#define I3C_TARG_CHAR_1_REG_OFFSET 0x3c0
#define I3C_TARG_CHAR_1_REG_RESVAL 0x3e000000u
#define I3C_TARG_CHAR_1_PID_HI_1_MASK 0xffffu
#define I3C_TARG_CHAR_1_PID_HI_1_OFFSET 0
#define I3C_TARG_CHAR_1_PID_HI_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_1_PID_HI_1_MASK, .index = I3C_TARG_CHAR_1_PID_HI_1_OFFSET })
#define I3C_TARG_CHAR_1_DCR_1_MASK 0xffu
#define I3C_TARG_CHAR_1_DCR_1_OFFSET 16
#define I3C_TARG_CHAR_1_DCR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_1_DCR_1_MASK, .index = I3C_TARG_CHAR_1_DCR_1_OFFSET })
#define I3C_TARG_CHAR_1_BCR_1_MASK 0xffu
#define I3C_TARG_CHAR_1_BCR_1_OFFSET 24
#define I3C_TARG_CHAR_1_BCR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_1_BCR_1_MASK, .index = I3C_TARG_CHAR_1_BCR_1_OFFSET })
 
// Target Characteristics.
#define I3C_TARG_CHAR_2_REG_OFFSET 0x3c4
#define I3C_TARG_CHAR_2_REG_RESVAL 0x3e000000u
#define I3C_TARG_CHAR_2_PID_HI_2_MASK 0xffffu
#define I3C_TARG_CHAR_2_PID_HI_2_OFFSET 0
#define I3C_TARG_CHAR_2_PID_HI_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_2_PID_HI_2_MASK, .index = I3C_TARG_CHAR_2_PID_HI_2_OFFSET })
#define I3C_TARG_CHAR_2_DCR_2_MASK 0xffu
#define I3C_TARG_CHAR_2_DCR_2_OFFSET 16
#define I3C_TARG_CHAR_2_DCR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_2_DCR_2_MASK, .index = I3C_TARG_CHAR_2_DCR_2_OFFSET })
#define I3C_TARG_CHAR_2_BCR_2_MASK 0xffu
#define I3C_TARG_CHAR_2_BCR_2_OFFSET 24
#define I3C_TARG_CHAR_2_BCR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_2_BCR_2_MASK, .index = I3C_TARG_CHAR_2_BCR_2_OFFSET })
 
// Target Characteristics.
#define I3C_TARG_CHAR_3_REG_OFFSET 0x3c8
#define I3C_TARG_CHAR_3_REG_RESVAL 0x3e000000u
#define I3C_TARG_CHAR_3_PID_HI_3_MASK 0xffffu
#define I3C_TARG_CHAR_3_PID_HI_3_OFFSET 0
#define I3C_TARG_CHAR_3_PID_HI_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_3_PID_HI_3_MASK, .index = I3C_TARG_CHAR_3_PID_HI_3_OFFSET })
#define I3C_TARG_CHAR_3_DCR_3_MASK 0xffu
#define I3C_TARG_CHAR_3_DCR_3_OFFSET 16
#define I3C_TARG_CHAR_3_DCR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_3_DCR_3_MASK, .index = I3C_TARG_CHAR_3_DCR_3_OFFSET })
#define I3C_TARG_CHAR_3_BCR_3_MASK 0xffu
#define I3C_TARG_CHAR_3_BCR_3_OFFSET 24
#define I3C_TARG_CHAR_3_BCR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CHAR_3_BCR_3_MASK, .index = I3C_TARG_CHAR_3_BCR_3_OFFSET })
 
// Low part of Target Provisioned ID. (common parameters)
#define I3C_TARG_PID_LO_PID_LO_FIELD_WIDTH 32
#define I3C_TARG_PID_LO_MULTIREG_COUNT 4
 
// Low part of Target Provisioned ID.
#define I3C_TARG_PID_LO_0_REG_OFFSET 0x3cc
#define I3C_TARG_PID_LO_0_REG_RESVAL 0x0u
 
// Low part of Target Provisioned ID.
#define I3C_TARG_PID_LO_1_REG_OFFSET 0x3d0
#define I3C_TARG_PID_LO_1_REG_RESVAL 0x0u
 
// Low part of Target Provisioned ID.
#define I3C_TARG_PID_LO_2_REG_OFFSET 0x3d4
#define I3C_TARG_PID_LO_2_REG_RESVAL 0x0u
 
// Low part of Target Provisioned ID.
#define I3C_TARG_PID_LO_3_REG_OFFSET 0x3d8
#define I3C_TARG_PID_LO_3_REG_RESVAL 0x0u
 
// Target Capabilities. (common parameters)
#define I3C_TARG_CAPS_VTCAP1_TYPE_FIELD_WIDTH 3
#define I3C_TARG_CAPS_VTCAP1_SIDE_FX_FIELD_WIDTH 1
#define I3C_TARG_CAPS_VTCAP1_SHARED_DET_FIELD_WIDTH 1
#define I3C_TARG_CAPS_VTCAP2_IRQ_FIELD_WIDTH 2
#define I3C_TARG_CAPS_VTCAP2_ADDR_REMAP_FIELD_WIDTH 1
#define I3C_TARG_CAPS_VTCAP2_BUS_CTX_FIELD_WIDTH 2
#define I3C_TARG_CAPS_MULTIREG_COUNT 4
 
// Target Capabilities.
#define I3C_TARG_CAPS_0_REG_OFFSET 0x3dc
#define I3C_TARG_CAPS_0_REG_RESVAL 0x0u
#define I3C_TARG_CAPS_0_VTCAP1_TYPE_0_MASK 0x7u
#define I3C_TARG_CAPS_0_VTCAP1_TYPE_0_OFFSET 0
#define I3C_TARG_CAPS_0_VTCAP1_TYPE_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_0_VTCAP1_TYPE_0_MASK, .index = I3C_TARG_CAPS_0_VTCAP1_TYPE_0_OFFSET })
#define I3C_TARG_CAPS_0_VTCAP1_SIDE_FX_0_BIT 4
#define I3C_TARG_CAPS_0_VTCAP1_SHARED_DET_0_BIT 5
#define I3C_TARG_CAPS_0_VTCAP2_IRQ_0_MASK 0x3u
#define I3C_TARG_CAPS_0_VTCAP2_IRQ_0_OFFSET 8
#define I3C_TARG_CAPS_0_VTCAP2_IRQ_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_0_VTCAP2_IRQ_0_MASK, .index = I3C_TARG_CAPS_0_VTCAP2_IRQ_0_OFFSET })
#define I3C_TARG_CAPS_0_VTCAP2_ADDR_REMAP_0_BIT 10
#define I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_MASK 0x3u
#define I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_OFFSET 11
#define I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_MASK, .index = I3C_TARG_CAPS_0_VTCAP2_BUS_CTX_0_OFFSET })
 
// Target Capabilities.
#define I3C_TARG_CAPS_1_REG_OFFSET 0x3e0
#define I3C_TARG_CAPS_1_REG_RESVAL 0x0u
#define I3C_TARG_CAPS_1_VTCAP1_TYPE_1_MASK 0x7u
#define I3C_TARG_CAPS_1_VTCAP1_TYPE_1_OFFSET 0
#define I3C_TARG_CAPS_1_VTCAP1_TYPE_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_1_VTCAP1_TYPE_1_MASK, .index = I3C_TARG_CAPS_1_VTCAP1_TYPE_1_OFFSET })
#define I3C_TARG_CAPS_1_VTCAP1_SIDE_FX_1_BIT 4
#define I3C_TARG_CAPS_1_VTCAP1_SHARED_DET_1_BIT 5
#define I3C_TARG_CAPS_1_VTCAP2_IRQ_1_MASK 0x3u
#define I3C_TARG_CAPS_1_VTCAP2_IRQ_1_OFFSET 8
#define I3C_TARG_CAPS_1_VTCAP2_IRQ_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_1_VTCAP2_IRQ_1_MASK, .index = I3C_TARG_CAPS_1_VTCAP2_IRQ_1_OFFSET })
#define I3C_TARG_CAPS_1_VTCAP2_ADDR_REMAP_1_BIT 10
#define I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_MASK 0x3u
#define I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_OFFSET 11
#define I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_MASK, .index = I3C_TARG_CAPS_1_VTCAP2_BUS_CTX_1_OFFSET })
 
// Target Capabilities.
#define I3C_TARG_CAPS_2_REG_OFFSET 0x3e4
#define I3C_TARG_CAPS_2_REG_RESVAL 0x0u
#define I3C_TARG_CAPS_2_VTCAP1_TYPE_2_MASK 0x7u
#define I3C_TARG_CAPS_2_VTCAP1_TYPE_2_OFFSET 0
#define I3C_TARG_CAPS_2_VTCAP1_TYPE_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_2_VTCAP1_TYPE_2_MASK, .index = I3C_TARG_CAPS_2_VTCAP1_TYPE_2_OFFSET })
#define I3C_TARG_CAPS_2_VTCAP1_SIDE_FX_2_BIT 4
#define I3C_TARG_CAPS_2_VTCAP1_SHARED_DET_2_BIT 5
#define I3C_TARG_CAPS_2_VTCAP2_IRQ_2_MASK 0x3u
#define I3C_TARG_CAPS_2_VTCAP2_IRQ_2_OFFSET 8
#define I3C_TARG_CAPS_2_VTCAP2_IRQ_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_2_VTCAP2_IRQ_2_MASK, .index = I3C_TARG_CAPS_2_VTCAP2_IRQ_2_OFFSET })
#define I3C_TARG_CAPS_2_VTCAP2_ADDR_REMAP_2_BIT 10
#define I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_MASK 0x3u
#define I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_OFFSET 11
#define I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_MASK, .index = I3C_TARG_CAPS_2_VTCAP2_BUS_CTX_2_OFFSET })
 
// Target Capabilities.
#define I3C_TARG_CAPS_3_REG_OFFSET 0x3e8
#define I3C_TARG_CAPS_3_REG_RESVAL 0x0u
#define I3C_TARG_CAPS_3_VTCAP1_TYPE_3_MASK 0x7u
#define I3C_TARG_CAPS_3_VTCAP1_TYPE_3_OFFSET 0
#define I3C_TARG_CAPS_3_VTCAP1_TYPE_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_3_VTCAP1_TYPE_3_MASK, .index = I3C_TARG_CAPS_3_VTCAP1_TYPE_3_OFFSET })
#define I3C_TARG_CAPS_3_VTCAP1_SIDE_FX_3_BIT 4
#define I3C_TARG_CAPS_3_VTCAP1_SHARED_DET_3_BIT 5
#define I3C_TARG_CAPS_3_VTCAP2_IRQ_3_MASK 0x3u
#define I3C_TARG_CAPS_3_VTCAP2_IRQ_3_OFFSET 8
#define I3C_TARG_CAPS_3_VTCAP2_IRQ_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_3_VTCAP2_IRQ_3_MASK, .index = I3C_TARG_CAPS_3_VTCAP2_IRQ_3_OFFSET })
#define I3C_TARG_CAPS_3_VTCAP2_ADDR_REMAP_3_BIT 10
#define I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_MASK 0x3u
#define I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_OFFSET 11
#define I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_MASK, .index = I3C_TARG_CAPS_3_VTCAP2_BUS_CTX_3_OFFSET })
 
// Target information. (common parameters)
#define I3C_TARG_INFO_AS_FIELD_WIDTH 2
#define I3C_TARG_INFO_ENDXFER_WR_NACK_FIELD_WIDTH 1
#define I3C_TARG_INFO_ENDXFER_WR_EARLY_TERM_FIELD_WIDTH 1
#define I3C_TARG_INFO_ENDXFER_CRC_EARLY_FIELD_WIDTH 1
#define I3C_TARG_INFO_ENDXFER_CAND_WR_NACK_FIELD_WIDTH 1
#define I3C_TARG_INFO_ENDXFER_CAND_WR_EARLY_TERM_FIELD_WIDTH 1
#define I3C_TARG_INFO_ENDXFER_CAND_CRC_EARLY_FIELD_WIDTH 1
#define I3C_TARG_INFO_MULTIREG_COUNT 4
 
// Target information.
#define I3C_TARG_INFO_0_REG_OFFSET 0x3ec
#define I3C_TARG_INFO_0_REG_RESVAL 0x2020u
#define I3C_TARG_INFO_0_AS_0_MASK 0x3u
#define I3C_TARG_INFO_0_AS_0_OFFSET 0
#define I3C_TARG_INFO_0_AS_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_INFO_0_AS_0_MASK, .index = I3C_TARG_INFO_0_AS_0_OFFSET })
#define I3C_TARG_INFO_0_ENDXFER_WR_NACK_0_BIT 3
#define I3C_TARG_INFO_0_ENDXFER_WR_EARLY_TERM_0_BIT 4
#define I3C_TARG_INFO_0_ENDXFER_CRC_EARLY_0_BIT 5
#define I3C_TARG_INFO_0_ENDXFER_CAND_WR_NACK_0_BIT 11
#define I3C_TARG_INFO_0_ENDXFER_CAND_WR_EARLY_TERM_0_BIT 12
#define I3C_TARG_INFO_0_ENDXFER_CAND_CRC_EARLY_0_BIT 13
 
// Target information.
#define I3C_TARG_INFO_1_REG_OFFSET 0x3f0
#define I3C_TARG_INFO_1_REG_RESVAL 0x2020u
#define I3C_TARG_INFO_1_AS_1_MASK 0x3u
#define I3C_TARG_INFO_1_AS_1_OFFSET 0
#define I3C_TARG_INFO_1_AS_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_INFO_1_AS_1_MASK, .index = I3C_TARG_INFO_1_AS_1_OFFSET })
#define I3C_TARG_INFO_1_ENDXFER_WR_NACK_1_BIT 3
#define I3C_TARG_INFO_1_ENDXFER_WR_EARLY_TERM_1_BIT 4
#define I3C_TARG_INFO_1_ENDXFER_CRC_EARLY_1_BIT 5
#define I3C_TARG_INFO_1_ENDXFER_CAND_WR_NACK_1_BIT 11
#define I3C_TARG_INFO_1_ENDXFER_CAND_WR_EARLY_TERM_1_BIT 12
#define I3C_TARG_INFO_1_ENDXFER_CAND_CRC_EARLY_1_BIT 13
 
// Target information.
#define I3C_TARG_INFO_2_REG_OFFSET 0x3f4
#define I3C_TARG_INFO_2_REG_RESVAL 0x2020u
#define I3C_TARG_INFO_2_AS_2_MASK 0x3u
#define I3C_TARG_INFO_2_AS_2_OFFSET 0
#define I3C_TARG_INFO_2_AS_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_INFO_2_AS_2_MASK, .index = I3C_TARG_INFO_2_AS_2_OFFSET })
#define I3C_TARG_INFO_2_ENDXFER_WR_NACK_2_BIT 3
#define I3C_TARG_INFO_2_ENDXFER_WR_EARLY_TERM_2_BIT 4
#define I3C_TARG_INFO_2_ENDXFER_CRC_EARLY_2_BIT 5
#define I3C_TARG_INFO_2_ENDXFER_CAND_WR_NACK_2_BIT 11
#define I3C_TARG_INFO_2_ENDXFER_CAND_WR_EARLY_TERM_2_BIT 12
#define I3C_TARG_INFO_2_ENDXFER_CAND_CRC_EARLY_2_BIT 13
 
// Target information.
#define I3C_TARG_INFO_3_REG_OFFSET 0x3f8
#define I3C_TARG_INFO_3_REG_RESVAL 0x2020u
#define I3C_TARG_INFO_3_AS_3_MASK 0x3u
#define I3C_TARG_INFO_3_AS_3_OFFSET 0
#define I3C_TARG_INFO_3_AS_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_INFO_3_AS_3_MASK, .index = I3C_TARG_INFO_3_AS_3_OFFSET })
#define I3C_TARG_INFO_3_ENDXFER_WR_NACK_3_BIT 3
#define I3C_TARG_INFO_3_ENDXFER_WR_EARLY_TERM_3_BIT 4
#define I3C_TARG_INFO_3_ENDXFER_CRC_EARLY_3_BIT 5
#define I3C_TARG_INFO_3_ENDXFER_CAND_WR_NACK_3_BIT 11
#define I3C_TARG_INFO_3_ENDXFER_CAND_WR_EARLY_TERM_3_BIT 12
#define I3C_TARG_INFO_3_ENDXFER_CAND_CRC_EARLY_3_BIT 13
 
// Target Maximum Read/Write Rate and Turnaround. (common parameters)
#define I3C_TARG_MAX_RDWR_MAXRD_FIELD_WIDTH 7
#define I3C_TARG_MAX_RDWR_MAXWR_FIELD_WIDTH 8
#define I3C_TARG_MAX_RDWR_RDTURN_VAL_FIELD_WIDTH 12
#define I3C_TARG_MAX_RDWR_RDTURN_SCALE_FIELD_WIDTH 4
#define I3C_TARG_MAX_RDWR_MULTIREG_COUNT 4
 
// Target Maximum Read/Write Rate and Turnaround.
#define I3C_TARG_MAX_RDWR_0_REG_OFFSET 0x3fc
#define I3C_TARG_MAX_RDWR_0_REG_RESVAL 0x10000u
#define I3C_TARG_MAX_RDWR_0_MAXRD_0_MASK 0x7fu
#define I3C_TARG_MAX_RDWR_0_MAXRD_0_OFFSET 0
#define I3C_TARG_MAX_RDWR_0_MAXRD_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_MAXRD_0_MASK, .index = I3C_TARG_MAX_RDWR_0_MAXRD_0_OFFSET })
#define I3C_TARG_MAX_RDWR_0_MAXWR_0_MASK 0xffu
#define I3C_TARG_MAX_RDWR_0_MAXWR_0_OFFSET 8
#define I3C_TARG_MAX_RDWR_0_MAXWR_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_MAXWR_0_MASK, .index = I3C_TARG_MAX_RDWR_0_MAXWR_0_OFFSET })
#define I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_MASK 0xfffu
#define I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_OFFSET 16
#define I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_MASK, .index = I3C_TARG_MAX_RDWR_0_RDTURN_VAL_0_OFFSET })
#define I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_MASK 0xfu
#define I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_OFFSET 28
#define I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_MASK, .index = I3C_TARG_MAX_RDWR_0_RDTURN_SCALE_0_OFFSET })
 
// Target Maximum Read/Write Rate and Turnaround.
#define I3C_TARG_MAX_RDWR_1_REG_OFFSET 0x400
#define I3C_TARG_MAX_RDWR_1_REG_RESVAL 0x10000u
#define I3C_TARG_MAX_RDWR_1_MAXRD_1_MASK 0x7fu
#define I3C_TARG_MAX_RDWR_1_MAXRD_1_OFFSET 0
#define I3C_TARG_MAX_RDWR_1_MAXRD_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_MAXRD_1_MASK, .index = I3C_TARG_MAX_RDWR_1_MAXRD_1_OFFSET })
#define I3C_TARG_MAX_RDWR_1_MAXWR_1_MASK 0xffu
#define I3C_TARG_MAX_RDWR_1_MAXWR_1_OFFSET 8
#define I3C_TARG_MAX_RDWR_1_MAXWR_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_MAXWR_1_MASK, .index = I3C_TARG_MAX_RDWR_1_MAXWR_1_OFFSET })
#define I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_MASK 0xfffu
#define I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_OFFSET 16
#define I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_MASK, .index = I3C_TARG_MAX_RDWR_1_RDTURN_VAL_1_OFFSET })
#define I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_MASK 0xfu
#define I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_OFFSET 28
#define I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_MASK, .index = I3C_TARG_MAX_RDWR_1_RDTURN_SCALE_1_OFFSET })
 
// Target Maximum Read/Write Rate and Turnaround.
#define I3C_TARG_MAX_RDWR_2_REG_OFFSET 0x404
#define I3C_TARG_MAX_RDWR_2_REG_RESVAL 0x10000u
#define I3C_TARG_MAX_RDWR_2_MAXRD_2_MASK 0x7fu
#define I3C_TARG_MAX_RDWR_2_MAXRD_2_OFFSET 0
#define I3C_TARG_MAX_RDWR_2_MAXRD_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_MAXRD_2_MASK, .index = I3C_TARG_MAX_RDWR_2_MAXRD_2_OFFSET })
#define I3C_TARG_MAX_RDWR_2_MAXWR_2_MASK 0xffu
#define I3C_TARG_MAX_RDWR_2_MAXWR_2_OFFSET 8
#define I3C_TARG_MAX_RDWR_2_MAXWR_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_MAXWR_2_MASK, .index = I3C_TARG_MAX_RDWR_2_MAXWR_2_OFFSET })
#define I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_MASK 0xfffu
#define I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_OFFSET 16
#define I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_MASK, .index = I3C_TARG_MAX_RDWR_2_RDTURN_VAL_2_OFFSET })
#define I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_MASK 0xfu
#define I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_OFFSET 28
#define I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_MASK, .index = I3C_TARG_MAX_RDWR_2_RDTURN_SCALE_2_OFFSET })
 
// Target Maximum Read/Write Rate and Turnaround.
#define I3C_TARG_MAX_RDWR_3_REG_OFFSET 0x408
#define I3C_TARG_MAX_RDWR_3_REG_RESVAL 0x10000u
#define I3C_TARG_MAX_RDWR_3_MAXRD_3_MASK 0x7fu
#define I3C_TARG_MAX_RDWR_3_MAXRD_3_OFFSET 0
#define I3C_TARG_MAX_RDWR_3_MAXRD_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_MAXRD_3_MASK, .index = I3C_TARG_MAX_RDWR_3_MAXRD_3_OFFSET })
#define I3C_TARG_MAX_RDWR_3_MAXWR_3_MASK 0xffu
#define I3C_TARG_MAX_RDWR_3_MAXWR_3_OFFSET 8
#define I3C_TARG_MAX_RDWR_3_MAXWR_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_MAXWR_3_MASK, .index = I3C_TARG_MAX_RDWR_3_MAXWR_3_OFFSET })
#define I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_MASK 0xfffu
#define I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_OFFSET 16
#define I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_MASK, .index = I3C_TARG_MAX_RDWR_3_RDTURN_VAL_3_OFFSET })
#define I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_MASK 0xfu
#define I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_OFFSET 28
#define I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_MASK, .index = I3C_TARG_MAX_RDWR_3_RDTURN_SCALE_3_OFFSET })
 
// Memory area: TTI ports, occupying successive word addresses:
#define I3C_TTI_PORTS_REG_OFFSET 0x440
#define I3C_TTI_PORTS_SIZE_WORDS 13
#define I3C_TTI_PORTS_SIZE_BYTES 52
// Target Extension Extended Capability Header
#define I3C_TARGEXT_EXTCAP_HEADER_REG_OFFSET 0x474
#define I3C_TARGEXT_EXTCAP_HEADER_REG_RESVAL 0x1c0u
#define I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_MASK 0xffu
#define I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_OFFSET 0
#define I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_TARGEXT_EXTCAP_HEADER_CAP_ID_OFFSET })
#define I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_MASK 0xffffu
#define I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_OFFSET 8
#define I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_TARGEXT_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
 
// Terminating Extended Capability Header
#define I3C_TERM_EXTCAP_HEADER_REG_OFFSET 0x478
#define I3C_TERM_EXTCAP_HEADER_REG_RESVAL 0x100u
#define I3C_TERM_EXTCAP_HEADER_CAP_ID_MASK 0xffu
#define I3C_TERM_EXTCAP_HEADER_CAP_ID_OFFSET 0
#define I3C_TERM_EXTCAP_HEADER_CAP_ID_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TERM_EXTCAP_HEADER_CAP_ID_MASK, .index = I3C_TERM_EXTCAP_HEADER_CAP_ID_OFFSET })
#define I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_MASK 0xffffu
#define I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_OFFSET 8
#define I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_FIELD \
  ((bitfield_field32_t) { .mask = I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_MASK, .index = I3C_TERM_EXTCAP_HEADER_CAP_LENGTH_OFFSET })
 
// Memory area: Device Address Table.
#define I3C_DAT_REG_OFFSET 0xa00
#define I3C_DAT_SIZE_WORDS 64
#define I3C_DAT_SIZE_BYTES 256
// Memory area: Device Characteristics Table.
#define I3C_DCT_REG_OFFSET 0xc00
#define I3C_DCT_SIZE_WORDS 128
#define I3C_DCT_SIZE_BYTES 512
// Memory area: Software-managed 4 KiB message buffer used for transmitting
// and receiving messages.
#define I3C_BUFFER_REG_OFFSET 0x1000
#define I3C_BUFFER_SIZE_WORDS 1024
#define I3C_BUFFER_SIZE_BYTES 4096
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _I3C_REG_DEFS_
// End generated register defines for i3c