Software APIs
dif_dma_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_dma_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "dma_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_dma_init(mmio_region_t base_addr, dif_dma_t *dma) {
18  if (dma == NULL) {
19  return kDifBadArg;
20  }
21 
22  dma->base_addr = base_addr;
23 
24  return kDifOk;
25 }
26 
27 dif_result_t dif_dma_alert_force(const dif_dma_t *dma, dif_dma_alert_t alert) {
28  if (dma == NULL) {
29  return kDifBadArg;
30  }
31 
32  bitfield_bit32_index_t alert_idx;
33  switch (alert) {
34  case kDifDmaAlertFatalFault:
35  alert_idx = DMA_ALERT_TEST_FATAL_FAULT_BIT;
36  break;
37  default:
38  return kDifBadArg;
39  }
40 
41  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
42  mmio_region_write32(dma->base_addr, (ptrdiff_t)DMA_ALERT_TEST_REG_OFFSET,
43  alert_test_reg);
44 
45  return kDifOk;
46 }
47 
48 /**
49  * Get the corresponding interrupt register bit offset of the IRQ.
50  */
51 static bool dma_get_irq_bit_index(dif_dma_irq_t irq,
52  bitfield_bit32_index_t *index_out) {
53  switch (irq) {
54  case kDifDmaIrqDmaDone:
55  *index_out = DMA_INTR_COMMON_DMA_DONE_BIT;
56  break;
57  case kDifDmaIrqDmaChunkDone:
58  *index_out = DMA_INTR_COMMON_DMA_CHUNK_DONE_BIT;
59  break;
60  case kDifDmaIrqDmaError:
61  *index_out = DMA_INTR_COMMON_DMA_ERROR_BIT;
62  break;
63  default:
64  return false;
65  }
66 
67  return true;
68 }
69 
70 static dif_irq_type_t irq_types[] = {
71  kDifIrqTypeStatus,
72  kDifIrqTypeStatus,
73  kDifIrqTypeStatus,
74 };
75 
76 OT_WARN_UNUSED_RESULT
77 dif_result_t dif_dma_irq_get_type(const dif_dma_t *dma, dif_dma_irq_t irq,
78  dif_irq_type_t *type) {
79  if (dma == NULL || type == NULL || irq < 0 || irq > kDifDmaIrqDmaError) {
80  return kDifBadArg;
81  }
82 
83  *type = irq_types[irq];
84 
85  return kDifOk;
86 }
87 
88 OT_WARN_UNUSED_RESULT
89 dif_result_t dif_dma_irq_get_state(const dif_dma_t *dma,
90  dif_dma_irq_state_snapshot_t *snapshot) {
91  if (dma == NULL || snapshot == NULL) {
92  return kDifBadArg;
93  }
94 
95  *snapshot =
96  mmio_region_read32(dma->base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET);
97 
98  return kDifOk;
99 }
100 
101 OT_WARN_UNUSED_RESULT
102 dif_result_t dif_dma_irq_acknowledge_state(
103  const dif_dma_t *dma, dif_dma_irq_state_snapshot_t snapshot) {
104  if (dma == NULL) {
105  return kDifBadArg;
106  }
107 
108  mmio_region_write32(dma->base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
109  snapshot);
110 
111  return kDifOk;
112 }
113 
114 OT_WARN_UNUSED_RESULT
115 dif_result_t dif_dma_irq_is_pending(const dif_dma_t *dma, dif_dma_irq_t irq,
116  bool *is_pending) {
117  if (dma == NULL || is_pending == NULL) {
118  return kDifBadArg;
119  }
120 
121  bitfield_bit32_index_t index;
122  if (!dma_get_irq_bit_index(irq, &index)) {
123  return kDifBadArg;
124  }
125 
126  uint32_t intr_state_reg =
127  mmio_region_read32(dma->base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET);
128 
129  *is_pending = bitfield_bit32_read(intr_state_reg, index);
130 
131  return kDifOk;
132 }
133 
134 OT_WARN_UNUSED_RESULT
135 dif_result_t dif_dma_irq_acknowledge_all(const dif_dma_t *dma) {
136  if (dma == NULL) {
137  return kDifBadArg;
138  }
139 
140  // Writing to the register clears the corresponding bits (Write-one clear).
141  mmio_region_write32(dma->base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
142  UINT32_MAX);
143 
144  return kDifOk;
145 }
146 
147 OT_WARN_UNUSED_RESULT
148 dif_result_t dif_dma_irq_acknowledge(const dif_dma_t *dma, dif_dma_irq_t irq) {
149  if (dma == NULL) {
150  return kDifBadArg;
151  }
152 
153  bitfield_bit32_index_t index;
154  if (!dma_get_irq_bit_index(irq, &index)) {
155  return kDifBadArg;
156  }
157 
158  // Writing to the register clears the corresponding bits (Write-one clear).
159  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
160  mmio_region_write32(dma->base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
161  intr_state_reg);
162 
163  return kDifOk;
164 }
165 
166 OT_WARN_UNUSED_RESULT
167 dif_result_t dif_dma_irq_force(const dif_dma_t *dma, dif_dma_irq_t irq,
168  const bool val) {
169  if (dma == NULL) {
170  return kDifBadArg;
171  }
172 
173  bitfield_bit32_index_t index;
174  if (!dma_get_irq_bit_index(irq, &index)) {
175  return kDifBadArg;
176  }
177 
178  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
179  mmio_region_write32(dma->base_addr, (ptrdiff_t)DMA_INTR_TEST_REG_OFFSET,
180  intr_test_reg);
181 
182  return kDifOk;
183 }
184 
185 OT_WARN_UNUSED_RESULT
186 dif_result_t dif_dma_irq_get_enabled(const dif_dma_t *dma, dif_dma_irq_t irq,
187  dif_toggle_t *state) {
188  if (dma == NULL || state == NULL) {
189  return kDifBadArg;
190  }
191 
192  bitfield_bit32_index_t index;
193  if (!dma_get_irq_bit_index(irq, &index)) {
194  return kDifBadArg;
195  }
196 
197  uint32_t intr_enable_reg =
198  mmio_region_read32(dma->base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
199 
200  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
201  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
202 
203  return kDifOk;
204 }
205 
206 OT_WARN_UNUSED_RESULT
207 dif_result_t dif_dma_irq_set_enabled(const dif_dma_t *dma, dif_dma_irq_t irq,
208  dif_toggle_t state) {
209  if (dma == NULL) {
210  return kDifBadArg;
211  }
212 
213  bitfield_bit32_index_t index;
214  if (!dma_get_irq_bit_index(irq, &index)) {
215  return kDifBadArg;
216  }
217 
218  uint32_t intr_enable_reg =
219  mmio_region_read32(dma->base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
220 
221  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
222  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
223  mmio_region_write32(dma->base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
224  intr_enable_reg);
225 
226  return kDifOk;
227 }
228 
229 OT_WARN_UNUSED_RESULT
230 dif_result_t dif_dma_irq_disable_all(const dif_dma_t *dma,
231  dif_dma_irq_enable_snapshot_t *snapshot) {
232  if (dma == NULL) {
233  return kDifBadArg;
234  }
235 
236  // Pass the current interrupt state to the caller, if requested.
237  if (snapshot != NULL) {
238  *snapshot = mmio_region_read32(dma->base_addr,
239  (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
240  }
241 
242  // Disable all interrupts.
243  mmio_region_write32(dma->base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
244  0u);
245 
246  return kDifOk;
247 }
248 
249 OT_WARN_UNUSED_RESULT
250 dif_result_t dif_dma_irq_restore_all(
251  const dif_dma_t *dma, const dif_dma_irq_enable_snapshot_t *snapshot) {
252  if (dma == NULL || snapshot == NULL) {
253  return kDifBadArg;
254  }
255 
256  mmio_region_write32(dma->base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
257  *snapshot);
258 
259  return kDifOk;
260 }
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