35 alert_idx = DMA_ALERT_TEST_FATAL_FAULT_BIT;
42 mmio_region_write32(dma->
base_addr, (ptrdiff_t)DMA_ALERT_TEST_REG_OFFSET,
55 *index_out = DMA_INTR_COMMON_DMA_DONE_BIT;
58 *index_out = DMA_INTR_COMMON_DMA_ERROR_BIT;
79 *type = irq_types[irq];
87 if (dma == NULL || snapshot == NULL) {
92 mmio_region_read32(dma->
base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET);
104 mmio_region_write32(dma->
base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
113 if (dma == NULL || is_pending == NULL) {
118 if (!dma_get_irq_bit_index(irq, &index)) {
122 uint32_t intr_state_reg =
123 mmio_region_read32(dma->
base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET);
137 mmio_region_write32(dma->
base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
150 if (!dma_get_irq_bit_index(irq, &index)) {
156 mmio_region_write32(dma->
base_addr, (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
170 if (!dma_get_irq_bit_index(irq, &index)) {
175 mmio_region_write32(dma->
base_addr, (ptrdiff_t)DMA_INTR_TEST_REG_OFFSET,
184 if (dma == NULL || state == NULL) {
189 if (!dma_get_irq_bit_index(irq, &index)) {
193 uint32_t intr_enable_reg =
194 mmio_region_read32(dma->
base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
210 if (!dma_get_irq_bit_index(irq, &index)) {
214 uint32_t intr_enable_reg =
215 mmio_region_read32(dma->
base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
219 mmio_region_write32(dma->
base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
233 if (snapshot != NULL) {
234 *snapshot = mmio_region_read32(dma->
base_addr,
235 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
239 mmio_region_write32(dma->
base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
248 if (dma == NULL || snapshot == NULL) {
252 mmio_region_write32(dma->
base_addr, (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,