Software APIs
dif_dma_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
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11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i hw/ip/dma/data/dma.hjson -o
13// bazel-out/k8-fastbuild-ST-24cc6a2908d2/bin/sw/device/lib/dif/autogen
14
15
16#include <stdint.h>
17
18#include "sw/device/lib/dif/dif_base.h"
19#include "sw/device/lib/dif/autogen/dif_dma_autogen.h"
20
21#include "dma_regs.h" // Generated.
22
23
24OT_WARN_UNUSED_RESULT
25dif_result_t dif_dma_init(
26 mmio_region_t base_addr,
27 dif_dma_t *dma) {
28 if (dma == NULL) {
29 return kDifBadArg;
30 }
31
32 dma->dt = kDtDmaCount;
33 dma->base_addr = base_addr;
34
35 return kDifOk;
36}
37
38OT_WARN_UNUSED_RESULT
39dif_result_t dif_dma_init_from_dt(
40 dt_dma_t dt,
41 dif_dma_t *dma) {
42 if (dma == NULL) {
43 return kDifBadArg;
44 }
45
46 dma->dt = dt;
47 dma->base_addr = mmio_region_from_addr(dt_dma_primary_reg_block(dt));
48
49 return kDifOk;
50}
51
52dif_result_t dif_dma_get_dt(
53 const dif_dma_t *dma,
54 dt_dma_t *dt) {
55 if (dma->dt == kDtDmaCount || dt == NULL) {
56 return kDifBadArg;
57 }
58 *dt = dma->dt;
59 return kDifOk;
60}
61
62 dif_result_t dif_dma_alert_force(
63 const dif_dma_t *dma,
64 dif_dma_alert_t alert) {
65 if (dma == NULL) {
66 return kDifBadArg;
67 }
68
69 bitfield_bit32_index_t alert_idx;
70 switch (alert) {
71 case kDifDmaAlertFatalFault:
72 alert_idx = DMA_ALERT_TEST_FATAL_FAULT_BIT;
73 break;
74 default:
75 return kDifBadArg;
76 }
77
78 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
79 mmio_region_write32(
80 dma->base_addr,
81 (ptrdiff_t)DMA_ALERT_TEST_REG_OFFSET,
82 alert_test_reg);
83
84
85 return kDifOk;
86}
87
88
89 /**
90 * Get the corresponding interrupt register bit offset of the IRQ.
91 */
92 static bool dma_get_irq_bit_index(
93 dif_dma_irq_t irq,
94 bitfield_bit32_index_t *index_out) {
95
96 switch (irq) {
97 case kDtDmaIrqDmaDone:
98 *index_out = DMA_INTR_COMMON_DMA_DONE_BIT;
99 break;
100 case kDtDmaIrqDmaChunkDone:
101 *index_out = DMA_INTR_COMMON_DMA_CHUNK_DONE_BIT;
102 break;
103 case kDtDmaIrqDmaError:
104 *index_out = DMA_INTR_COMMON_DMA_ERROR_BIT;
105 break;
106 default:
107 return false;
108 }
109
110 return true;
111 }
112
113 static dif_irq_type_t irq_types[] = {
114 kDifIrqTypeStatus,
115 kDifIrqTypeStatus,
116 kDifIrqTypeStatus,
117 };
118
119 OT_WARN_UNUSED_RESULT
120 dif_result_t dif_dma_irq_get_type(
121 const dif_dma_t *dma,
122 dif_dma_irq_t irq,
123 dif_irq_type_t *type) {
124
125
126 if (dma == NULL ||
127 type == NULL ||
128 irq < kDifDmaIrqDmaDone ||
129 irq > kDifDmaIrqDmaError) {
130 return kDifBadArg;
131 }
132
133 *type = irq_types[irq];
134
135 return kDifOk;
136 }
137
138 OT_WARN_UNUSED_RESULT
139 dif_result_t dif_dma_irq_get_state(
140 const dif_dma_t *dma,
141 dif_dma_irq_state_snapshot_t *snapshot) {
142
143 if (dma == NULL || snapshot == NULL) {
144 return kDifBadArg;
145 }
146
147 *snapshot = mmio_region_read32(
148 dma->base_addr,
149 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET);
150
151
152 return kDifOk;
153 }
154
155 OT_WARN_UNUSED_RESULT
156 dif_result_t dif_dma_irq_acknowledge_state(
157 const dif_dma_t *dma,
158 dif_dma_irq_state_snapshot_t snapshot) {
159 if (dma == NULL) {
160 return kDifBadArg;
161 }
162
163 mmio_region_write32(
164 dma->base_addr,
165 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
166 snapshot);
167
168
169 return kDifOk;
170 }
171
172 OT_WARN_UNUSED_RESULT
173 dif_result_t dif_dma_irq_is_pending(
174 const dif_dma_t *dma,
175 dif_dma_irq_t irq,
176 bool *is_pending) {
177
178 if (dma == NULL || is_pending == NULL) {
179 return kDifBadArg;
180 }
181
182 bitfield_bit32_index_t index;
183 if (!dma_get_irq_bit_index(irq, &index)) {
184 return kDifBadArg;
185 }
186
187 uint32_t intr_state_reg = mmio_region_read32(
188 dma->base_addr,
189 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET);
190
191
192 *is_pending = bitfield_bit32_read(intr_state_reg, index);
193
194 return kDifOk;
195 }
196
197 OT_WARN_UNUSED_RESULT
198 dif_result_t dif_dma_irq_acknowledge_all(
199 const dif_dma_t *dma
200 ) {
201
202 if (dma == NULL) {
203 return kDifBadArg;
204 }
205
206 // Writing to the register clears the corresponding bits (Write-one clear).
207 mmio_region_write32(
208 dma->base_addr,
209 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
210 UINT32_MAX);
211
212
213 return kDifOk;
214 }
215
216 OT_WARN_UNUSED_RESULT
217 dif_result_t dif_dma_irq_acknowledge(
218 const dif_dma_t *dma,
219 dif_dma_irq_t irq) {
220
221 if (dma == NULL) {
222 return kDifBadArg;
223 }
224
225 bitfield_bit32_index_t index;
226 if (!dma_get_irq_bit_index(irq, &index)) {
227 return kDifBadArg;
228 }
229
230 // Writing to the register clears the corresponding bits (Write-one clear).
231 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
232 mmio_region_write32(
233 dma->base_addr,
234 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
235 intr_state_reg);
236
237
238 return kDifOk;
239 }
240
241 OT_WARN_UNUSED_RESULT
242 dif_result_t dif_dma_irq_force(
243 const dif_dma_t *dma,
244 dif_dma_irq_t irq,
245 const bool val) {
246
247 if (dma == NULL) {
248 return kDifBadArg;
249 }
250
251 bitfield_bit32_index_t index;
252 if (!dma_get_irq_bit_index(irq, &index)) {
253 return kDifBadArg;
254 }
255
256 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
257 mmio_region_write32(
258 dma->base_addr,
259 (ptrdiff_t)DMA_INTR_TEST_REG_OFFSET,
260 intr_test_reg);
261
262
263 return kDifOk;
264 }
265
266 OT_WARN_UNUSED_RESULT
267 dif_result_t dif_dma_irq_get_enabled(
268 const dif_dma_t *dma,
269 dif_dma_irq_t irq,
270 dif_toggle_t *state) {
271
272 if (dma == NULL || state == NULL) {
273 return kDifBadArg;
274 }
275
276 bitfield_bit32_index_t index;
277 if (!dma_get_irq_bit_index(irq, &index)) {
278 return kDifBadArg;
279 }
280
281 uint32_t intr_enable_reg = mmio_region_read32(
282 dma->base_addr,
283 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
284
285
286 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
287 *state = is_enabled ?
288 kDifToggleEnabled : kDifToggleDisabled;
289
290 return kDifOk;
291 }
292
293 OT_WARN_UNUSED_RESULT
294 dif_result_t dif_dma_irq_set_enabled(
295 const dif_dma_t *dma,
296 dif_dma_irq_t irq,
297 dif_toggle_t state) {
298
299 if (dma == NULL) {
300 return kDifBadArg;
301 }
302
303 bitfield_bit32_index_t index;
304 if (!dma_get_irq_bit_index(irq, &index)) {
305 return kDifBadArg;
306 }
307
308 uint32_t intr_enable_reg = mmio_region_read32(
309 dma->base_addr,
310 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
311
312
313 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
314 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
315 mmio_region_write32(
316 dma->base_addr,
317 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
318 intr_enable_reg);
319
320
321 return kDifOk;
322 }
323
324 OT_WARN_UNUSED_RESULT
325 dif_result_t dif_dma_irq_disable_all(
326 const dif_dma_t *dma,
327 dif_dma_irq_enable_snapshot_t *snapshot) {
328
329 if (dma == NULL) {
330 return kDifBadArg;
331 }
332
333 // Pass the current interrupt state to the caller, if requested.
334 if (snapshot != NULL) {
335 *snapshot = mmio_region_read32(
336 dma->base_addr,
337 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
338
339 }
340
341 // Disable all interrupts.
342 mmio_region_write32(
343 dma->base_addr,
344 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
345 0u);
346
347
348 return kDifOk;
349 }
350
351 OT_WARN_UNUSED_RESULT
352 dif_result_t dif_dma_irq_restore_all(
353 const dif_dma_t *dma,
354 const dif_dma_irq_enable_snapshot_t *snapshot) {
355
356 if (dma == NULL || snapshot == NULL) {
357 return kDifBadArg;
358 }
359
360 mmio_region_write32(
361 dma->base_addr,
362 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
363 *snapshot);
364
365
366 return kDifOk;
367 }
368