Software APIs
dif_dma_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
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11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i hw/ip/dma/data/dma.hjson -o
13// bazel-out/k8-fastbuild-ST-24cc6a2908d2/bin/sw/device/lib/dif/autogen
14
15
16#include <stdint.h>
17
18#include "sw/device/lib/dif/dif_base.h"
19#include "sw/device/lib/dif/autogen/dif_dma_autogen.h"
20
21#include "hw/top/dma_regs.h" // Generated.
22
23
24OT_WARN_UNUSED_RESULT
25dif_result_t dif_dma_init(
26 mmio_region_t base_addr,
27 dif_dma_t *dma) {
28 if (dma == NULL) {
29 return kDifBadArg;
30 }
31
32 dma->dt = kDtDmaCount;
33 dma->base_addr = base_addr;
34
35 return kDifOk;
36}
37
38OT_WARN_UNUSED_RESULT
39dif_result_t dif_dma_init_from_dt(
40 dt_dma_t dt,
41 dif_dma_t *dma) {
42 if (dma == NULL) {
43 return kDifBadArg;
44 }
45
46 dma->dt = dt;
47 dma->base_addr = mmio_region_from_addr(dt_dma_primary_reg_block(dt));
48
49 return kDifOk;
50}
51
52dif_result_t dif_dma_get_dt(
53 const dif_dma_t *dma,
54 dt_dma_t *dt) {
55 if ((int)dma->dt == kDtDmaCount || dt == NULL) {
56 return kDifBadArg;
57 }
58 *dt = dma->dt;
59 return kDifOk;
60}
61
62 dif_result_t dif_dma_alert_force(
63 const dif_dma_t *dma,
64 dif_dma_alert_t alert) {
65 if (dma == NULL) {
66 return kDifBadArg;
67 }
68
69 bitfield_bit32_index_t alert_idx;
70 switch (alert) {
71 case kDifDmaAlertFatalFault:
72 alert_idx = DMA_ALERT_TEST_FATAL_FAULT_BIT;
73 break;
74 default:
75 return kDifBadArg;
76 }
77
78 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
79 // Keep the alert test enabled: writing 0 to the regwen bit locks the register.
80 alert_test_reg = bitfield_bit32_write(
81 alert_test_reg, DMA_ALERT_TEST_REGWEN_BIT, true);
82 mmio_region_write32(
83 dma->base_addr,
84 (ptrdiff_t)DMA_ALERT_TEST_REG_OFFSET,
85 alert_test_reg);
86
87
88 return kDifOk;
89}
90
91
92 /**
93 * Get the corresponding interrupt register bit offset of the IRQ.
94 */
95 static bool dma_get_irq_bit_index(
96 dif_dma_irq_t irq,
97 bitfield_bit32_index_t *index_out) {
98
99 switch (irq) {
100 case kDtDmaIrqDmaDone:
101 *index_out = DMA_INTR_COMMON_DMA_DONE_BIT;
102 break;
103 case kDtDmaIrqDmaChunkDone:
104 *index_out = DMA_INTR_COMMON_DMA_CHUNK_DONE_BIT;
105 break;
106 case kDtDmaIrqDmaError:
107 *index_out = DMA_INTR_COMMON_DMA_ERROR_BIT;
108 break;
109 default:
110 return false;
111 }
112
113 return true;
114 }
115
116 static dif_irq_type_t irq_types[] = {
117 kDifIrqTypeStatus,
118 kDifIrqTypeStatus,
119 kDifIrqTypeStatus,
120 };
121
122 OT_WARN_UNUSED_RESULT
123 dif_result_t dif_dma_irq_get_type(
124 const dif_dma_t *dma,
125 dif_dma_irq_t irq,
126 dif_irq_type_t *type) {
127
128
129 if (dma == NULL ||
130 type == NULL ||
131 irq < kDifDmaIrqDmaDone ||
132 irq > kDifDmaIrqDmaError) {
133 return kDifBadArg;
134 }
135
136 *type = irq_types[irq];
137
138 return kDifOk;
139 }
140
141 OT_WARN_UNUSED_RESULT
142 dif_result_t dif_dma_irq_get_state(
143 const dif_dma_t *dma,
144 dif_dma_irq_state_snapshot_t *snapshot) {
145
146 if (dma == NULL || snapshot == NULL) {
147 return kDifBadArg;
148 }
149
150 *snapshot = mmio_region_read32(
151 dma->base_addr,
152 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET);
153
154
155 return kDifOk;
156 }
157
158 OT_WARN_UNUSED_RESULT
159 dif_result_t dif_dma_irq_acknowledge_state(
160 const dif_dma_t *dma,
161 dif_dma_irq_state_snapshot_t snapshot) {
162 if (dma == NULL) {
163 return kDifBadArg;
164 }
165
166 mmio_region_write32(
167 dma->base_addr,
168 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
169 snapshot);
170
171
172 return kDifOk;
173 }
174
175 OT_WARN_UNUSED_RESULT
176 dif_result_t dif_dma_irq_is_pending(
177 const dif_dma_t *dma,
178 dif_dma_irq_t irq,
179 bool *is_pending) {
180
181 if (dma == NULL || is_pending == NULL) {
182 return kDifBadArg;
183 }
184
185 bitfield_bit32_index_t index;
186 if (!dma_get_irq_bit_index(irq, &index)) {
187 return kDifBadArg;
188 }
189
190 uint32_t intr_state_reg = mmio_region_read32(
191 dma->base_addr,
192 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET);
193
194
195 *is_pending = bitfield_bit32_read(intr_state_reg, index);
196
197 return kDifOk;
198 }
199
200 OT_WARN_UNUSED_RESULT
201 dif_result_t dif_dma_irq_acknowledge_all(
202 const dif_dma_t *dma
203 ) {
204
205 if (dma == NULL) {
206 return kDifBadArg;
207 }
208
209 // Writing to the register clears the corresponding bits (Write-one clear).
210 mmio_region_write32(
211 dma->base_addr,
212 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
213 UINT32_MAX);
214
215
216 return kDifOk;
217 }
218
219 OT_WARN_UNUSED_RESULT
220 dif_result_t dif_dma_irq_acknowledge(
221 const dif_dma_t *dma,
222 dif_dma_irq_t irq) {
223
224 if (dma == NULL) {
225 return kDifBadArg;
226 }
227
228 bitfield_bit32_index_t index;
229 if (!dma_get_irq_bit_index(irq, &index)) {
230 return kDifBadArg;
231 }
232
233 // Writing to the register clears the corresponding bits (Write-one clear).
234 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
235 mmio_region_write32(
236 dma->base_addr,
237 (ptrdiff_t)DMA_INTR_STATE_REG_OFFSET,
238 intr_state_reg);
239
240
241 return kDifOk;
242 }
243
244 OT_WARN_UNUSED_RESULT
245 dif_result_t dif_dma_irq_force(
246 const dif_dma_t *dma,
247 dif_dma_irq_t irq,
248 const bool val) {
249
250 if (dma == NULL) {
251 return kDifBadArg;
252 }
253
254 bitfield_bit32_index_t index;
255 if (!dma_get_irq_bit_index(irq, &index)) {
256 return kDifBadArg;
257 }
258
259 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
260 mmio_region_write32(
261 dma->base_addr,
262 (ptrdiff_t)DMA_INTR_TEST_REG_OFFSET,
263 intr_test_reg);
264
265
266 return kDifOk;
267 }
268
269 OT_WARN_UNUSED_RESULT
270 dif_result_t dif_dma_irq_get_enabled(
271 const dif_dma_t *dma,
272 dif_dma_irq_t irq,
273 dif_toggle_t *state) {
274
275 if (dma == NULL || state == NULL) {
276 return kDifBadArg;
277 }
278
279 bitfield_bit32_index_t index;
280 if (!dma_get_irq_bit_index(irq, &index)) {
281 return kDifBadArg;
282 }
283
284 uint32_t intr_enable_reg = mmio_region_read32(
285 dma->base_addr,
286 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
287
288
289 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
290 *state = is_enabled ?
291 kDifToggleEnabled : kDifToggleDisabled;
292
293 return kDifOk;
294 }
295
296 OT_WARN_UNUSED_RESULT
297 dif_result_t dif_dma_irq_set_enabled(
298 const dif_dma_t *dma,
299 dif_dma_irq_t irq,
300 dif_toggle_t state) {
301
302 if (dma == NULL) {
303 return kDifBadArg;
304 }
305
306 bitfield_bit32_index_t index;
307 if (!dma_get_irq_bit_index(irq, &index)) {
308 return kDifBadArg;
309 }
310
311 uint32_t intr_enable_reg = mmio_region_read32(
312 dma->base_addr,
313 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
314
315
316 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
317 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
318 mmio_region_write32(
319 dma->base_addr,
320 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
321 intr_enable_reg);
322
323
324 return kDifOk;
325 }
326
327 OT_WARN_UNUSED_RESULT
328 dif_result_t dif_dma_irq_disable_all(
329 const dif_dma_t *dma,
330 dif_dma_irq_enable_snapshot_t *snapshot) {
331
332 if (dma == NULL) {
333 return kDifBadArg;
334 }
335
336 // Pass the current interrupt state to the caller, if requested.
337 if (snapshot != NULL) {
338 *snapshot = mmio_region_read32(
339 dma->base_addr,
340 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET);
341
342 }
343
344 // Disable all interrupts.
345 mmio_region_write32(
346 dma->base_addr,
347 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
348 0u);
349
350
351 return kDifOk;
352 }
353
354 OT_WARN_UNUSED_RESULT
355 dif_result_t dif_dma_irq_restore_all(
356 const dif_dma_t *dma,
357 const dif_dma_irq_enable_snapshot_t *snapshot) {
358
359 if (dma == NULL || snapshot == NULL) {
360 return kDifBadArg;
361 }
362
363 mmio_region_write32(
364 dma->base_addr,
365 (ptrdiff_t)DMA_INTR_ENABLE_REG_OFFSET,
366 *snapshot);
367
368
369 return kDifOk;
370 }
371