Software APIs
Macros
cheriot_mem_sys_regs.h File Reference

Generated register defines for cheriot_mem_sys. More...

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Macros

#define CHERIOT_MEM_SYS_PARAM_TBRE_NUM_CAPS_W   31
 
#define CHERIOT_MEM_SYS_PARAM_TBRE_EPOCH_W   31
 
#define CHERIOT_MEM_SYS_PARAM_NUM_ALERTS   1
 
#define CHERIOT_MEM_SYS_PARAM_REG_WIDTH   32
 
#define CHERIOT_MEM_SYS_INTR_COMMON_TBRE_DONE_BIT   0
 
#define CHERIOT_MEM_SYS_INTR_STATE_REG_OFFSET   0x0
 
#define CHERIOT_MEM_SYS_INTR_STATE_REG_RESVAL   0x0u
 
#define CHERIOT_MEM_SYS_INTR_STATE_TBRE_DONE_BIT   0
 
#define CHERIOT_MEM_SYS_INTR_ENABLE_REG_OFFSET   0x4
 
#define CHERIOT_MEM_SYS_INTR_ENABLE_REG_RESVAL   0x0u
 
#define CHERIOT_MEM_SYS_INTR_ENABLE_TBRE_DONE_BIT   0
 
#define CHERIOT_MEM_SYS_INTR_TEST_REG_OFFSET   0x8
 
#define CHERIOT_MEM_SYS_INTR_TEST_REG_RESVAL   0x0u
 
#define CHERIOT_MEM_SYS_INTR_TEST_TBRE_DONE_BIT   0
 
#define CHERIOT_MEM_SYS_ALERT_TEST_REG_OFFSET   0xc
 
#define CHERIOT_MEM_SYS_ALERT_TEST_REG_RESVAL   0x80000000u
 
#define CHERIOT_MEM_SYS_ALERT_TEST_FATAL_FAULT_BIT   0
 
#define CHERIOT_MEM_SYS_ALERT_TEST_REGWEN_BIT   31
 
#define CHERIOT_MEM_SYS_TBRE_REGWEN_REG_OFFSET   0x10
 
#define CHERIOT_MEM_SYS_TBRE_REGWEN_REG_RESVAL   0x1u
 
#define CHERIOT_MEM_SYS_TBRE_REGWEN_EN_BIT   0
 
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_REG_OFFSET   0x14
 
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_REG_RESVAL   0x0u
 
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_MASK   0x1fffffffu
 
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_OFFSET   3
 
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_FIELD    ((bitfield_field32_t) { .mask = CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_MASK, .index = CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_OFFSET })
 
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_REG_OFFSET   0x18
 
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_REG_RESVAL   0x0u
 
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_MASK   0x7fffffffu
 
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_OFFSET   0
 
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_FIELD    ((bitfield_field32_t) { .mask = CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_MASK, .index = CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_OFFSET })
 
#define CHERIOT_MEM_SYS_TBRE_START_REG_OFFSET   0x1c
 
#define CHERIOT_MEM_SYS_TBRE_START_REG_RESVAL   0x0u
 
#define CHERIOT_MEM_SYS_TBRE_START_START_BIT   0
 
#define CHERIOT_MEM_SYS_TBRE_STATUS_REG_OFFSET   0x20
 
#define CHERIOT_MEM_SYS_TBRE_STATUS_REG_RESVAL   0x0u
 
#define CHERIOT_MEM_SYS_TBRE_STATUS_BUSY_BIT   0
 
#define CHERIOT_MEM_SYS_TBRE_STATUS_START_ERR_BIT   8
 
#define CHERIOT_MEM_SYS_TBRE_STATUS_SWEEP_ERR_BIT   9
 
#define CHERIOT_MEM_SYS_TBRE_EPOCH_REG_OFFSET   0x24
 
#define CHERIOT_MEM_SYS_TBRE_EPOCH_REG_RESVAL   0x0u
 
#define CHERIOT_MEM_SYS_TBRE_EPOCH_ACTIVE_BIT   0
 
#define CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_MASK   0x7fffffffu
 
#define CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_OFFSET   1
 
#define CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_FIELD    ((bitfield_field32_t) { .mask = CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_MASK, .index = CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_OFFSET })
 

Detailed Description

Generated register defines for cheriot_mem_sys.

Definition in file cheriot_mem_sys_regs.h.

Macro Definition Documentation

◆ CHERIOT_MEM_SYS_ALERT_TEST_FATAL_FAULT_BIT

#define CHERIOT_MEM_SYS_ALERT_TEST_FATAL_FAULT_BIT   0

Definition at line 53 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_ALERT_TEST_REG_OFFSET

#define CHERIOT_MEM_SYS_ALERT_TEST_REG_OFFSET   0xc

Definition at line 51 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_ALERT_TEST_REG_RESVAL

#define CHERIOT_MEM_SYS_ALERT_TEST_REG_RESVAL   0x80000000u

Definition at line 52 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_ALERT_TEST_REGWEN_BIT

#define CHERIOT_MEM_SYS_ALERT_TEST_REGWEN_BIT   31

Definition at line 54 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_COMMON_TBRE_DONE_BIT

#define CHERIOT_MEM_SYS_INTR_COMMON_TBRE_DONE_BIT   0

Definition at line 33 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_ENABLE_REG_OFFSET

#define CHERIOT_MEM_SYS_INTR_ENABLE_REG_OFFSET   0x4

Definition at line 41 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_ENABLE_REG_RESVAL

#define CHERIOT_MEM_SYS_INTR_ENABLE_REG_RESVAL   0x0u

Definition at line 42 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_ENABLE_TBRE_DONE_BIT

#define CHERIOT_MEM_SYS_INTR_ENABLE_TBRE_DONE_BIT   0

Definition at line 43 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_STATE_REG_OFFSET

#define CHERIOT_MEM_SYS_INTR_STATE_REG_OFFSET   0x0

Definition at line 36 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_STATE_REG_RESVAL

#define CHERIOT_MEM_SYS_INTR_STATE_REG_RESVAL   0x0u

Definition at line 37 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_STATE_TBRE_DONE_BIT

#define CHERIOT_MEM_SYS_INTR_STATE_TBRE_DONE_BIT   0

Definition at line 38 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_TEST_REG_OFFSET

#define CHERIOT_MEM_SYS_INTR_TEST_REG_OFFSET   0x8

Definition at line 46 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_TEST_REG_RESVAL

#define CHERIOT_MEM_SYS_INTR_TEST_REG_RESVAL   0x0u

Definition at line 47 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_INTR_TEST_TBRE_DONE_BIT

#define CHERIOT_MEM_SYS_INTR_TEST_TBRE_DONE_BIT   0

Definition at line 48 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_PARAM_NUM_ALERTS

#define CHERIOT_MEM_SYS_PARAM_NUM_ALERTS   1

Definition at line 27 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_PARAM_REG_WIDTH

#define CHERIOT_MEM_SYS_PARAM_REG_WIDTH   32

Definition at line 30 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_PARAM_TBRE_EPOCH_W

#define CHERIOT_MEM_SYS_PARAM_TBRE_EPOCH_W   31

Definition at line 24 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_PARAM_TBRE_NUM_CAPS_W

#define CHERIOT_MEM_SYS_PARAM_TBRE_NUM_CAPS_W   31

Definition at line 21 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_FIELD

#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_FIELD    ((bitfield_field32_t) { .mask = CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_MASK, .index = CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_OFFSET })

Definition at line 66 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_MASK

#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_MASK   0x1fffffffu

Definition at line 64 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_OFFSET

#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_OFFSET   3

Definition at line 65 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_BASE_ADDR_REG_OFFSET

#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_REG_OFFSET   0x14

Definition at line 62 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_BASE_ADDR_REG_RESVAL

#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_REG_RESVAL   0x0u

Definition at line 63 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_EPOCH_ACTIVE_BIT

#define CHERIOT_MEM_SYS_TBRE_EPOCH_ACTIVE_BIT   0

Definition at line 95 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_FIELD

#define CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_FIELD    ((bitfield_field32_t) { .mask = CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_MASK, .index = CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_OFFSET })

Definition at line 98 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_MASK

#define CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_MASK   0x7fffffffu

Definition at line 96 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_OFFSET

#define CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_OFFSET   1

Definition at line 97 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_EPOCH_REG_OFFSET

#define CHERIOT_MEM_SYS_TBRE_EPOCH_REG_OFFSET   0x24

Definition at line 93 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_EPOCH_REG_RESVAL

#define CHERIOT_MEM_SYS_TBRE_EPOCH_REG_RESVAL   0x0u

Definition at line 94 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_FIELD

#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_FIELD    ((bitfield_field32_t) { .mask = CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_MASK, .index = CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_OFFSET })

Definition at line 75 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_MASK

#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_MASK   0x7fffffffu

Definition at line 73 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_OFFSET

#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_OFFSET   0

Definition at line 74 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_NUM_CAPS_REG_OFFSET

#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_REG_OFFSET   0x18

Definition at line 71 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_NUM_CAPS_REG_RESVAL

#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_REG_RESVAL   0x0u

Definition at line 72 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_REGWEN_EN_BIT

#define CHERIOT_MEM_SYS_TBRE_REGWEN_EN_BIT   0

Definition at line 59 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_REGWEN_REG_OFFSET

#define CHERIOT_MEM_SYS_TBRE_REGWEN_REG_OFFSET   0x10

Definition at line 57 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_REGWEN_REG_RESVAL

#define CHERIOT_MEM_SYS_TBRE_REGWEN_REG_RESVAL   0x1u

Definition at line 58 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_START_REG_OFFSET

#define CHERIOT_MEM_SYS_TBRE_START_REG_OFFSET   0x1c

Definition at line 80 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_START_REG_RESVAL

#define CHERIOT_MEM_SYS_TBRE_START_REG_RESVAL   0x0u

Definition at line 81 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_START_START_BIT

#define CHERIOT_MEM_SYS_TBRE_START_START_BIT   0

Definition at line 82 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_STATUS_BUSY_BIT

#define CHERIOT_MEM_SYS_TBRE_STATUS_BUSY_BIT   0

Definition at line 87 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_STATUS_REG_OFFSET

#define CHERIOT_MEM_SYS_TBRE_STATUS_REG_OFFSET   0x20

Definition at line 85 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_STATUS_REG_RESVAL

#define CHERIOT_MEM_SYS_TBRE_STATUS_REG_RESVAL   0x0u

Definition at line 86 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_STATUS_START_ERR_BIT

#define CHERIOT_MEM_SYS_TBRE_STATUS_START_ERR_BIT   8

Definition at line 88 of file cheriot_mem_sys_regs.h.

◆ CHERIOT_MEM_SYS_TBRE_STATUS_SWEEP_ERR_BIT

#define CHERIOT_MEM_SYS_TBRE_STATUS_SWEEP_ERR_BIT   9

Definition at line 89 of file cheriot_mem_sys_regs.h.