cheriot_mem_sys_regs.h

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/**
 * @file
 * @brief Generated register defines for cheriot_mem_sys
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _CHERIOT_MEM_SYS_REG_DEFS_
#define _CHERIOT_MEM_SYS_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Width of TBRE_NUM_CAPS. A sweep reads two words per capability, and that
// word count
#define CHERIOT_MEM_SYS_PARAM_TBRE_NUM_CAPS_W 31
 
// Width of TBRE_EPOCH.count, the sweep count above the active bit.
#define CHERIOT_MEM_SYS_PARAM_TBRE_EPOCH_W 31
 
// Number of alerts
#define CHERIOT_MEM_SYS_PARAM_NUM_ALERTS 1
 
// Register width
#define CHERIOT_MEM_SYS_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define CHERIOT_MEM_SYS_INTR_COMMON_TBRE_DONE_BIT 0
 
// Interrupt State Register
#define CHERIOT_MEM_SYS_INTR_STATE_REG_OFFSET 0x0
#define CHERIOT_MEM_SYS_INTR_STATE_REG_RESVAL 0x0u
#define CHERIOT_MEM_SYS_INTR_STATE_TBRE_DONE_BIT 0
 
// Interrupt Enable Register
#define CHERIOT_MEM_SYS_INTR_ENABLE_REG_OFFSET 0x4
#define CHERIOT_MEM_SYS_INTR_ENABLE_REG_RESVAL 0x0u
#define CHERIOT_MEM_SYS_INTR_ENABLE_TBRE_DONE_BIT 0
 
// Interrupt Test Register
#define CHERIOT_MEM_SYS_INTR_TEST_REG_OFFSET 0x8
#define CHERIOT_MEM_SYS_INTR_TEST_REG_RESVAL 0x0u
#define CHERIOT_MEM_SYS_INTR_TEST_TBRE_DONE_BIT 0
 
// Alert Test Register
#define CHERIOT_MEM_SYS_ALERT_TEST_REG_OFFSET 0xc
#define CHERIOT_MEM_SYS_ALERT_TEST_REG_RESVAL 0x80000000u
#define CHERIOT_MEM_SYS_ALERT_TEST_FATAL_FAULT_BIT 0
#define CHERIOT_MEM_SYS_ALERT_TEST_REGWEN_BIT 31
 
// Write enable for the revocation engine registers.
#define CHERIOT_MEM_SYS_TBRE_REGWEN_REG_OFFSET 0x10
#define CHERIOT_MEM_SYS_TBRE_REGWEN_REG_RESVAL 0x1u
#define CHERIOT_MEM_SYS_TBRE_REGWEN_EN_BIT 0
 
// Address of the first capability the revocation engine sweeps.
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_REG_OFFSET 0x14
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_REG_RESVAL 0x0u
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_MASK 0x1fffffffu
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_OFFSET 3
#define CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_MASK, .index = CHERIOT_MEM_SYS_TBRE_BASE_ADDR_ADDR_OFFSET })
 
// Number of capabilities the revocation engine sweeps, each of them two
// 32-bit words.
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_REG_OFFSET 0x18
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_REG_RESVAL 0x0u
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_MASK 0x7fffffffu
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_OFFSET 0
#define CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_FIELD \
  ((bitfield_field32_t) { .mask = CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_MASK, .index = CHERIOT_MEM_SYS_TBRE_NUM_CAPS_NUM_OFFSET })
 
// Starts a sweep over the capabilities !!TBRE_BASE_ADDR and !!TBRE_NUM_CAPS
// describe.
#define CHERIOT_MEM_SYS_TBRE_START_REG_OFFSET 0x1c
#define CHERIOT_MEM_SYS_TBRE_START_REG_RESVAL 0x0u
#define CHERIOT_MEM_SYS_TBRE_START_START_BIT 0
 
// Status of the revocation engine.
#define CHERIOT_MEM_SYS_TBRE_STATUS_REG_OFFSET 0x20
#define CHERIOT_MEM_SYS_TBRE_STATUS_REG_RESVAL 0x0u
#define CHERIOT_MEM_SYS_TBRE_STATUS_BUSY_BIT 0
#define CHERIOT_MEM_SYS_TBRE_STATUS_START_ERR_BIT 8
#define CHERIOT_MEM_SYS_TBRE_STATUS_SWEEP_ERR_BIT 9
 
// Sweep epoch, twice the number of sweeps that ended without an error, plus
// one while the
#define CHERIOT_MEM_SYS_TBRE_EPOCH_REG_OFFSET 0x24
#define CHERIOT_MEM_SYS_TBRE_EPOCH_REG_RESVAL 0x0u
#define CHERIOT_MEM_SYS_TBRE_EPOCH_ACTIVE_BIT 0
#define CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_MASK 0x7fffffffu
#define CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_OFFSET 1
#define CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_MASK, .index = CHERIOT_MEM_SYS_TBRE_EPOCH_COUNT_OFFSET })
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _CHERIOT_MEM_SYS_REG_DEFS_
// End generated register defines for cheriot_mem_sys