Generated register defines for adc_ctrl. More...

Macros
#define	ADC_CTRL_PARAM_NUM_ADC_FILTER 8

#define	ADC_CTRL_PARAM_NUM_ADC_CHANNEL 2

#define	ADC_CTRL_PARAM_NUM_ALERTS 1

#define	ADC_CTRL_PARAM_REG_WIDTH 32

#define	ADC_CTRL_INTR_COMMON_MATCH_PENDING_BIT 0

#define	ADC_CTRL_INTR_STATE_REG_OFFSET 0x0

#define	ADC_CTRL_INTR_STATE_REG_RESVAL 0x0u

#define	ADC_CTRL_INTR_STATE_MATCH_PENDING_BIT 0

#define	ADC_CTRL_INTR_ENABLE_REG_OFFSET 0x4

#define	ADC_CTRL_INTR_ENABLE_REG_RESVAL 0x0u

#define	ADC_CTRL_INTR_ENABLE_MATCH_PENDING_BIT 0

#define	ADC_CTRL_INTR_TEST_REG_OFFSET 0x8

#define	ADC_CTRL_INTR_TEST_REG_RESVAL 0x0u

#define	ADC_CTRL_INTR_TEST_MATCH_PENDING_BIT 0

#define	ADC_CTRL_ALERT_TEST_REG_OFFSET 0xc

#define	ADC_CTRL_ALERT_TEST_REG_RESVAL 0x0u

#define	ADC_CTRL_ALERT_TEST_FATAL_FAULT_BIT 0

#define	ADC_CTRL_ADC_EN_CTL_REG_OFFSET 0x10

#define	ADC_CTRL_ADC_EN_CTL_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_EN_CTL_ADC_ENABLE_BIT 0

#define	ADC_CTRL_ADC_EN_CTL_ONESHOT_MODE_BIT 1

#define	ADC_CTRL_ADC_PD_CTL_REG_OFFSET 0x14

#define	ADC_CTRL_ADC_PD_CTL_REG_RESVAL 0x64070u

#define	ADC_CTRL_ADC_PD_CTL_LP_MODE_BIT 0

#define	ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_MASK 0xfu

#define	ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET 4

#define	ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_MASK, .index = ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET })

#define	ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_MASK 0xffffffu

#define	ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET 8

#define	ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_MASK, .index = ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET })

#define	ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_OFFSET 0x18

#define	ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_RESVAL 0x4u

#define	ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_MASK 0xffu

#define	ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_OFFSET 0

#define	ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_MASK, .index = ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_OFFSET })

#define	ADC_CTRL_ADC_SAMPLE_CTL_REG_OFFSET 0x1c

#define	ADC_CTRL_ADC_SAMPLE_CTL_REG_RESVAL 0x9bu

#define	ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_MASK 0xffffu

#define	ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_OFFSET 0

#define	ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_MASK, .index = ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_OFFSET })

#define	ADC_CTRL_ADC_FSM_RST_REG_OFFSET 0x20

#define	ADC_CTRL_ADC_FSM_RST_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_FSM_RST_RST_EN_BIT 0

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_MIN_V_FIELD_WIDTH 10

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_COND_FIELD_WIDTH 1

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_MAX_V_FIELD_WIDTH 10

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_EN_FIELD_WIDTH 1

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_MULTIREG_COUNT 8

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_REG_OFFSET 0x24

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_OFFSET 2

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_COND_0_BIT 12

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_OFFSET 18

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_0_EN_0_BIT 31

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_REG_OFFSET 0x28

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_OFFSET 2

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_COND_1_BIT 12

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_OFFSET 18

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_1_EN_1_BIT 31

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_REG_OFFSET 0x2c

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_OFFSET 2

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_COND_2_BIT 12

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_OFFSET 18

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_2_EN_2_BIT 31

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_REG_OFFSET 0x30

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_OFFSET 2

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_COND_3_BIT 12

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_OFFSET 18

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_3_EN_3_BIT 31

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_REG_OFFSET 0x34

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_OFFSET 2

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_COND_4_BIT 12

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_OFFSET 18

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_4_EN_4_BIT 31

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_REG_OFFSET 0x38

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_OFFSET 2

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_COND_5_BIT 12

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_OFFSET 18

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_5_EN_5_BIT 31

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_REG_OFFSET 0x3c

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_OFFSET 2

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_COND_6_BIT 12

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_OFFSET 18

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_6_EN_6_BIT 31

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_OFFSET 0x40

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_OFFSET 2

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_COND_7_BIT 12

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_OFFSET 18

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_OFFSET })

#define	ADC_CTRL_ADC_CHN0_FILTER_CTL_7_EN_7_BIT 31

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_MIN_V_FIELD_WIDTH 10

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_COND_FIELD_WIDTH 1

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_MAX_V_FIELD_WIDTH 10

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_EN_FIELD_WIDTH 1

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_MULTIREG_COUNT 8

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_REG_OFFSET 0x44

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_OFFSET 2

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_COND_0_BIT 12

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_OFFSET 18

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_0_EN_0_BIT 31

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_REG_OFFSET 0x48

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_OFFSET 2

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_COND_1_BIT 12

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_OFFSET 18

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_1_EN_1_BIT 31

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_OFFSET 0x4c

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET 2

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_COND_2_BIT 12

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET 18

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_2_EN_2_BIT 31

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_REG_OFFSET 0x50

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_OFFSET 2

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_COND_3_BIT 12

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_OFFSET 18

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_3_EN_3_BIT 31

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_REG_OFFSET 0x54

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_OFFSET 2

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_COND_4_BIT 12

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_OFFSET 18

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_4_EN_4_BIT 31

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_REG_OFFSET 0x58

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_OFFSET 2

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_COND_5_BIT 12

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_OFFSET 18

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_5_EN_5_BIT 31

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_REG_OFFSET 0x5c

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_OFFSET 2

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_COND_6_BIT 12

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_OFFSET 18

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_6_EN_6_BIT 31

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_REG_OFFSET 0x60

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_OFFSET 2

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_COND_7_BIT 12

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_OFFSET 18

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_OFFSET })

#define	ADC_CTRL_ADC_CHN1_FILTER_CTL_7_EN_7_BIT 31

#define	ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_EXT_FIELD_WIDTH 2

#define	ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_FIELD_WIDTH 10

#define	ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_INTR_EXT_FIELD_WIDTH 2

#define	ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_INTR_FIELD_WIDTH 10

#define	ADC_CTRL_ADC_CHN_VAL_MULTIREG_COUNT 2

#define	ADC_CTRL_ADC_CHN_VAL_0_REG_OFFSET 0x64

#define	ADC_CTRL_ADC_CHN_VAL_0_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_MASK 0x3u

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_OFFSET 0

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_OFFSET })

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_OFFSET 2

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_OFFSET })

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_MASK 0x3u

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_OFFSET 16

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_OFFSET })

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_OFFSET 18

#define	ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_OFFSET })

#define	ADC_CTRL_ADC_CHN_VAL_1_REG_OFFSET 0x68

#define	ADC_CTRL_ADC_CHN_VAL_1_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_MASK 0x3u

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_OFFSET 0

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_OFFSET })

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_OFFSET 2

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_OFFSET })

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_MASK 0x3u

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_OFFSET 16

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_OFFSET })

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_MASK 0x3ffu

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_OFFSET 18

#define	ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_OFFSET })

#define	ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET 0x6c

#define	ADC_CTRL_ADC_WAKEUP_CTL_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_MASK 0xffu

#define	ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_OFFSET 0

#define	ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_MASK, .index = ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_OFFSET })

#define	ADC_CTRL_ADC_WAKEUP_CTL_TRANS_EN_BIT 8

#define	ADC_CTRL_FILTER_STATUS_REG_OFFSET 0x70

#define	ADC_CTRL_FILTER_STATUS_REG_RESVAL 0x0u

#define	ADC_CTRL_FILTER_STATUS_MATCH_MASK 0xffu

#define	ADC_CTRL_FILTER_STATUS_MATCH_OFFSET 0

#define	ADC_CTRL_FILTER_STATUS_MATCH_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_FILTER_STATUS_MATCH_MASK, .index = ADC_CTRL_FILTER_STATUS_MATCH_OFFSET })

#define	ADC_CTRL_FILTER_STATUS_TRANS_BIT 8

#define	ADC_CTRL_ADC_INTR_CTL_REG_OFFSET 0x74

#define	ADC_CTRL_ADC_INTR_CTL_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_INTR_CTL_MATCH_EN_MASK 0xffu

#define	ADC_CTRL_ADC_INTR_CTL_MATCH_EN_OFFSET 0

#define	ADC_CTRL_ADC_INTR_CTL_MATCH_EN_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_INTR_CTL_MATCH_EN_MASK, .index = ADC_CTRL_ADC_INTR_CTL_MATCH_EN_OFFSET })

#define	ADC_CTRL_ADC_INTR_CTL_TRANS_EN_BIT 8

#define	ADC_CTRL_ADC_INTR_CTL_ONESHOT_EN_BIT 9

#define	ADC_CTRL_ADC_INTR_STATUS_REG_OFFSET 0x78

#define	ADC_CTRL_ADC_INTR_STATUS_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_INTR_STATUS_MATCH_MASK 0xffu

#define	ADC_CTRL_ADC_INTR_STATUS_MATCH_OFFSET 0

#define	ADC_CTRL_ADC_INTR_STATUS_MATCH_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_INTR_STATUS_MATCH_MASK, .index = ADC_CTRL_ADC_INTR_STATUS_MATCH_OFFSET })

#define	ADC_CTRL_ADC_INTR_STATUS_TRANS_BIT 8

#define	ADC_CTRL_ADC_INTR_STATUS_ONESHOT_BIT 9

#define	ADC_CTRL_ADC_FSM_STATE_REG_OFFSET 0x7c

#define	ADC_CTRL_ADC_FSM_STATE_REG_RESVAL 0x0u

#define	ADC_CTRL_ADC_FSM_STATE_STATE_MASK 0x1fu

#define	ADC_CTRL_ADC_FSM_STATE_STATE_OFFSET 0

#define	ADC_CTRL_ADC_FSM_STATE_STATE_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_FSM_STATE_STATE_MASK, .index = ADC_CTRL_ADC_FSM_STATE_STATE_OFFSET })

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_PWRDN 0x0

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_PWRUP 0x1

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_0 0x2

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_021 0x3

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_1 0x4

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_DONE 0x5

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_0 0x6

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_021 0x7

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_1 0x8

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_EVAL 0x9

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_SLP 0xa

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_PWRUP 0xb

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_0 0xc

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_021 0xd

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_1 0xe

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_EVAL 0xf

#define	ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_DONE 0x10

Detailed Description

Generated register defines for adc_ctrl.

Definition in file adc_ctrl_regs.h.

Macro Definition Documentation

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_COND_0_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_COND_0_BIT 12

Definition at line 108 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_EN_0_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_EN_0_BIT 31

Definition at line 113 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_OFFSET })

Definition at line 111 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_MASK 0x3ffu

Definition at line 109 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_OFFSET 18

Definition at line 110 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_OFFSET })

Definition at line 106 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_MASK 0x3ffu

Definition at line 104 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_OFFSET 2

Definition at line 105 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_REG_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_REG_OFFSET 0x24

Definition at line 102 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_0_REG_RESVAL

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_REG_RESVAL 0x0u

Definition at line 103 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_COND_1_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_COND_1_BIT 12

Definition at line 122 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_EN_1_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_EN_1_BIT 31

Definition at line 127 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_OFFSET })

Definition at line 125 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_MASK 0x3ffu

Definition at line 123 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_OFFSET 18

Definition at line 124 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_OFFSET })

Definition at line 120 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_MASK 0x3ffu

Definition at line 118 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_OFFSET 2

Definition at line 119 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_REG_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_REG_OFFSET 0x28

Definition at line 116 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_1_REG_RESVAL

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_REG_RESVAL 0x0u

Definition at line 117 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_COND_2_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_COND_2_BIT 12

Definition at line 136 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_EN_2_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_EN_2_BIT 31

Definition at line 141 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_OFFSET })

Definition at line 139 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_MASK 0x3ffu

Definition at line 137 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_OFFSET 18

Definition at line 138 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_OFFSET })

Definition at line 134 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_MASK 0x3ffu

Definition at line 132 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_OFFSET 2

Definition at line 133 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_REG_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_REG_OFFSET 0x2c

Definition at line 130 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_2_REG_RESVAL

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_REG_RESVAL 0x0u

Definition at line 131 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_COND_3_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_COND_3_BIT 12

Definition at line 150 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_EN_3_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_EN_3_BIT 31

Definition at line 155 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_OFFSET })

Definition at line 153 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_MASK 0x3ffu

Definition at line 151 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_OFFSET 18

Definition at line 152 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_OFFSET })

Definition at line 148 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_MASK 0x3ffu

Definition at line 146 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_OFFSET 2

Definition at line 147 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_REG_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_REG_OFFSET 0x30

Definition at line 144 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_3_REG_RESVAL

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_REG_RESVAL 0x0u

Definition at line 145 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_COND_4_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_COND_4_BIT 12

Definition at line 164 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_EN_4_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_EN_4_BIT 31

Definition at line 169 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_OFFSET })

Definition at line 167 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_MASK 0x3ffu

Definition at line 165 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_OFFSET 18

Definition at line 166 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_OFFSET })

Definition at line 162 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_MASK 0x3ffu

Definition at line 160 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_OFFSET 2

Definition at line 161 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_REG_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_REG_OFFSET 0x34

Definition at line 158 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_4_REG_RESVAL

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_REG_RESVAL 0x0u

Definition at line 159 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_COND_5_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_COND_5_BIT 12

Definition at line 178 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_EN_5_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_EN_5_BIT 31

Definition at line 183 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_OFFSET })

Definition at line 181 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_MASK 0x3ffu

Definition at line 179 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_OFFSET 18

Definition at line 180 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_OFFSET })

Definition at line 176 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_MASK 0x3ffu

Definition at line 174 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_OFFSET 2

Definition at line 175 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_REG_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_REG_OFFSET 0x38

Definition at line 172 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_5_REG_RESVAL

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_REG_RESVAL 0x0u

Definition at line 173 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_COND_6_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_COND_6_BIT 12

Definition at line 192 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_EN_6_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_EN_6_BIT 31

Definition at line 197 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_OFFSET })

Definition at line 195 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_MASK 0x3ffu

Definition at line 193 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_OFFSET 18

Definition at line 194 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_OFFSET })

Definition at line 190 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_MASK 0x3ffu

Definition at line 188 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_OFFSET 2

Definition at line 189 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_REG_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_REG_OFFSET 0x3c

Definition at line 186 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_6_REG_RESVAL

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_REG_RESVAL 0x0u

Definition at line 187 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_COND_7_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_COND_7_BIT 12

Definition at line 206 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_EN_7_BIT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_EN_7_BIT 31

Definition at line 211 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_OFFSET })

Definition at line 209 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_MASK 0x3ffu

Definition at line 207 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_OFFSET 18

Definition at line 208 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_FIELD

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_OFFSET })

Definition at line 204 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_MASK

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_MASK 0x3ffu

Definition at line 202 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_OFFSET 2

Definition at line 203 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_OFFSET

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_OFFSET 0x40

Definition at line 200 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_RESVAL

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_RESVAL 0x0u

Definition at line 201 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_COND_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_COND_FIELD_WIDTH 1

Definition at line 96 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_EN_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_EN_FIELD_WIDTH 1

Definition at line 98 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_MAX_V_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_MAX_V_FIELD_WIDTH 10

Definition at line 97 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_MIN_V_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_MIN_V_FIELD_WIDTH 10

Definition at line 95 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN0_FILTER_CTL_MULTIREG_COUNT

#define ADC_CTRL_ADC_CHN0_FILTER_CTL_MULTIREG_COUNT 8

Definition at line 99 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_COND_0_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_COND_0_BIT 12

Definition at line 227 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_EN_0_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_EN_0_BIT 31

Definition at line 232 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_OFFSET })

Definition at line 230 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_MASK 0x3ffu

Definition at line 228 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_OFFSET 18

Definition at line 229 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_OFFSET })

Definition at line 225 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_MASK 0x3ffu

Definition at line 223 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_OFFSET 2

Definition at line 224 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_REG_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_REG_OFFSET 0x44

Definition at line 221 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_0_REG_RESVAL

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_REG_RESVAL 0x0u

Definition at line 222 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_COND_1_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_COND_1_BIT 12

Definition at line 241 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_EN_1_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_EN_1_BIT 31

Definition at line 246 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_OFFSET })

Definition at line 244 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_MASK 0x3ffu

Definition at line 242 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_OFFSET 18

Definition at line 243 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_OFFSET })

Definition at line 239 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_MASK 0x3ffu

Definition at line 237 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_OFFSET 2

Definition at line 238 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_REG_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_REG_OFFSET 0x48

Definition at line 235 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_1_REG_RESVAL

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_REG_RESVAL 0x0u

Definition at line 236 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_COND_2_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_COND_2_BIT 12

Definition at line 255 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_EN_2_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_EN_2_BIT 31

Definition at line 260 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET })

Definition at line 258 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_MASK 0x3ffu

Definition at line 256 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET 18

Definition at line 257 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET })

Definition at line 253 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_MASK 0x3ffu

Definition at line 251 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET 2

Definition at line 252 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_OFFSET 0x4c

Definition at line 249 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_RESVAL

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_RESVAL 0x0u

Definition at line 250 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_COND_3_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_COND_3_BIT 12

Definition at line 269 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_EN_3_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_EN_3_BIT 31

Definition at line 274 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_OFFSET })

Definition at line 272 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_MASK 0x3ffu

Definition at line 270 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_OFFSET 18

Definition at line 271 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_OFFSET })

Definition at line 267 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_MASK 0x3ffu

Definition at line 265 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_OFFSET 2

Definition at line 266 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_REG_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_REG_OFFSET 0x50

Definition at line 263 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_3_REG_RESVAL

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_REG_RESVAL 0x0u

Definition at line 264 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_COND_4_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_COND_4_BIT 12

Definition at line 283 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_EN_4_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_EN_4_BIT 31

Definition at line 288 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_OFFSET })

Definition at line 286 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_MASK 0x3ffu

Definition at line 284 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_OFFSET 18

Definition at line 285 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_OFFSET })

Definition at line 281 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_MASK 0x3ffu

Definition at line 279 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_OFFSET 2

Definition at line 280 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_REG_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_REG_OFFSET 0x54

Definition at line 277 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_4_REG_RESVAL

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_REG_RESVAL 0x0u

Definition at line 278 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_COND_5_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_COND_5_BIT 12

Definition at line 297 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_EN_5_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_EN_5_BIT 31

Definition at line 302 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_OFFSET })

Definition at line 300 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_MASK 0x3ffu

Definition at line 298 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_OFFSET 18

Definition at line 299 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_OFFSET })

Definition at line 295 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_MASK 0x3ffu

Definition at line 293 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_OFFSET 2

Definition at line 294 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_REG_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_REG_OFFSET 0x58

Definition at line 291 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_5_REG_RESVAL

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_REG_RESVAL 0x0u

Definition at line 292 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_COND_6_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_COND_6_BIT 12

Definition at line 311 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_EN_6_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_EN_6_BIT 31

Definition at line 316 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_OFFSET })

Definition at line 314 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_MASK 0x3ffu

Definition at line 312 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_OFFSET 18

Definition at line 313 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_OFFSET })

Definition at line 309 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_MASK 0x3ffu

Definition at line 307 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_OFFSET 2

Definition at line 308 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_REG_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_REG_OFFSET 0x5c

Definition at line 305 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_6_REG_RESVAL

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_REG_RESVAL 0x0u

Definition at line 306 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_COND_7_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_COND_7_BIT 12

Definition at line 325 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_EN_7_BIT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_EN_7_BIT 31

Definition at line 330 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_OFFSET })

Definition at line 328 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_MASK 0x3ffu

Definition at line 326 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_OFFSET 18

Definition at line 327 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_FIELD

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_OFFSET })

Definition at line 323 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_MASK

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_MASK 0x3ffu

Definition at line 321 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_OFFSET 2

Definition at line 322 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_REG_OFFSET

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_REG_OFFSET 0x60

Definition at line 319 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_7_REG_RESVAL

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_REG_RESVAL 0x0u

Definition at line 320 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_COND_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_COND_FIELD_WIDTH 1

Definition at line 215 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_EN_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_EN_FIELD_WIDTH 1

Definition at line 217 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_MAX_V_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_MAX_V_FIELD_WIDTH 10

Definition at line 216 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_MIN_V_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_MIN_V_FIELD_WIDTH 10

Definition at line 214 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN1_FILTER_CTL_MULTIREG_COUNT

#define ADC_CTRL_ADC_CHN1_FILTER_CTL_MULTIREG_COUNT 8

Definition at line 218 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_FIELD

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_OFFSET })

Definition at line 348 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_MASK

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_MASK 0x3ffu

Definition at line 346 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_OFFSET 2

Definition at line 347 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_FIELD

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_OFFSET })

Definition at line 344 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_MASK

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_MASK 0x3u

Definition at line 342 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_OFFSET 0

Definition at line 343 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_FIELD

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_OFFSET })

Definition at line 356 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_MASK

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_MASK 0x3ffu

Definition at line 354 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_OFFSET 18

Definition at line 355 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_FIELD

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_OFFSET })

Definition at line 352 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_MASK

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_MASK 0x3u

Definition at line 350 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_OFFSET 16

Definition at line 351 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_REG_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_0_REG_OFFSET 0x64

Definition at line 340 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_0_REG_RESVAL

#define ADC_CTRL_ADC_CHN_VAL_0_REG_RESVAL 0x0u

Definition at line 341 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_FIELD

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_OFFSET })

Definition at line 368 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_MASK

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_MASK 0x3ffu

Definition at line 366 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_OFFSET 2

Definition at line 367 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_FIELD

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_OFFSET })

Definition at line 364 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_MASK

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_MASK 0x3u

Definition at line 362 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_OFFSET 0

Definition at line 363 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_FIELD

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_OFFSET })

Definition at line 376 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_MASK

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_MASK 0x3ffu

Definition at line 374 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_OFFSET 18

Definition at line 375 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_FIELD

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_OFFSET })

Definition at line 372 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_MASK

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_MASK 0x3u

Definition at line 370 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_OFFSET 16

Definition at line 371 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_REG_OFFSET

#define ADC_CTRL_ADC_CHN_VAL_1_REG_OFFSET 0x68

Definition at line 360 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_1_REG_RESVAL

#define ADC_CTRL_ADC_CHN_VAL_1_REG_RESVAL 0x0u

Definition at line 361 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_EXT_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_EXT_FIELD_WIDTH 2

Definition at line 333 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_FIELD_WIDTH 10

Definition at line 334 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_INTR_EXT_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_INTR_EXT_FIELD_WIDTH 2

Definition at line 335 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_INTR_FIELD_WIDTH

#define ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_INTR_FIELD_WIDTH 10

Definition at line 336 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_CHN_VAL_MULTIREG_COUNT

#define ADC_CTRL_ADC_CHN_VAL_MULTIREG_COUNT 2

Definition at line 337 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_EN_CTL_ADC_ENABLE_BIT

#define ADC_CTRL_ADC_EN_CTL_ADC_ENABLE_BIT 0

Definition at line 57 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_EN_CTL_ONESHOT_MODE_BIT

#define ADC_CTRL_ADC_EN_CTL_ONESHOT_MODE_BIT 1

Definition at line 58 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_EN_CTL_REG_OFFSET

#define ADC_CTRL_ADC_EN_CTL_REG_OFFSET 0x10

Definition at line 55 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_EN_CTL_REG_RESVAL

#define ADC_CTRL_ADC_EN_CTL_REG_RESVAL 0x0u

Definition at line 56 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_RST_REG_OFFSET

#define ADC_CTRL_ADC_FSM_RST_REG_OFFSET 0x20

Definition at line 90 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_RST_REG_RESVAL

#define ADC_CTRL_ADC_FSM_RST_REG_RESVAL 0x0u

Definition at line 91 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_RST_RST_EN_BIT

#define ADC_CTRL_ADC_FSM_RST_RST_EN_BIT 0

Definition at line 92 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_REG_OFFSET

#define ADC_CTRL_ADC_FSM_STATE_REG_OFFSET 0x7c

Definition at line 418 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_REG_RESVAL

#define ADC_CTRL_ADC_FSM_STATE_REG_RESVAL 0x0u

Definition at line 419 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_FIELD

#define ADC_CTRL_ADC_FSM_STATE_STATE_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_FSM_STATE_STATE_MASK, .index = ADC_CTRL_ADC_FSM_STATE_STATE_OFFSET })

Definition at line 422 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_MASK

#define ADC_CTRL_ADC_FSM_STATE_STATE_MASK 0x1fu

Definition at line 420 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_OFFSET

#define ADC_CTRL_ADC_FSM_STATE_STATE_OFFSET 0

Definition at line 421 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_0

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_0 0x6

Definition at line 430 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_021

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_021 0x7

Definition at line 431 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_1

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_1 0x8

Definition at line 432 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_EVAL

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_EVAL 0x9

Definition at line 433 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_PWRUP

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_PWRUP 0xb

Definition at line 435 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_SLP

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_SLP 0xa

Definition at line 434 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_0

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_0 0xc

Definition at line 436 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_021

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_021 0xd

Definition at line 437 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_1

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_1 0xe

Definition at line 438 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_DONE

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_DONE 0x10

Definition at line 440 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_EVAL

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_EVAL 0xf

Definition at line 439 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_0

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_0 0x2

Definition at line 426 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_021

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_021 0x3

Definition at line 427 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_1

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_1 0x4

Definition at line 428 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_DONE

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_DONE 0x5

Definition at line 429 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_PWRDN

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_PWRDN 0x0

Definition at line 424 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_PWRUP

#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_PWRUP 0x1

Definition at line 425 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_CTL_MATCH_EN_FIELD

#define ADC_CTRL_ADC_INTR_CTL_MATCH_EN_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_INTR_CTL_MATCH_EN_MASK, .index = ADC_CTRL_ADC_INTR_CTL_MATCH_EN_OFFSET })

Definition at line 402 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_CTL_MATCH_EN_MASK

#define ADC_CTRL_ADC_INTR_CTL_MATCH_EN_MASK 0xffu

Definition at line 400 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_CTL_MATCH_EN_OFFSET

#define ADC_CTRL_ADC_INTR_CTL_MATCH_EN_OFFSET 0

Definition at line 401 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_CTL_ONESHOT_EN_BIT

#define ADC_CTRL_ADC_INTR_CTL_ONESHOT_EN_BIT 9

Definition at line 405 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_CTL_REG_OFFSET

#define ADC_CTRL_ADC_INTR_CTL_REG_OFFSET 0x74

Definition at line 398 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_CTL_REG_RESVAL

#define ADC_CTRL_ADC_INTR_CTL_REG_RESVAL 0x0u

Definition at line 399 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_CTL_TRANS_EN_BIT

#define ADC_CTRL_ADC_INTR_CTL_TRANS_EN_BIT 8

Definition at line 404 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_STATUS_MATCH_FIELD

#define ADC_CTRL_ADC_INTR_STATUS_MATCH_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_INTR_STATUS_MATCH_MASK, .index = ADC_CTRL_ADC_INTR_STATUS_MATCH_OFFSET })

Definition at line 412 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_STATUS_MATCH_MASK

#define ADC_CTRL_ADC_INTR_STATUS_MATCH_MASK 0xffu

Definition at line 410 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_STATUS_MATCH_OFFSET

#define ADC_CTRL_ADC_INTR_STATUS_MATCH_OFFSET 0

Definition at line 411 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_STATUS_ONESHOT_BIT

#define ADC_CTRL_ADC_INTR_STATUS_ONESHOT_BIT 9

Definition at line 415 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_STATUS_REG_OFFSET

#define ADC_CTRL_ADC_INTR_STATUS_REG_OFFSET 0x78

Definition at line 408 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_STATUS_REG_RESVAL

#define ADC_CTRL_ADC_INTR_STATUS_REG_RESVAL 0x0u

Definition at line 409 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_INTR_STATUS_TRANS_BIT

#define ADC_CTRL_ADC_INTR_STATUS_TRANS_BIT 8

Definition at line 414 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_FIELD

#define ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_MASK, .index = ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_OFFSET })

Definition at line 78 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_MASK

#define ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_MASK 0xffu

Definition at line 76 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_OFFSET

#define ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_OFFSET 0

Definition at line 77 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_OFFSET

#define ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_OFFSET 0x18

Definition at line 74 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_RESVAL

#define ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_RESVAL 0x4u

Definition at line 75 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_PD_CTL_LP_MODE_BIT

#define ADC_CTRL_ADC_PD_CTL_LP_MODE_BIT 0

Definition at line 63 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_FIELD

#define ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_MASK, .index = ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET })

Definition at line 66 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_MASK

#define ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_MASK 0xfu

Definition at line 64 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET

#define ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET 4

Definition at line 65 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_PD_CTL_REG_OFFSET

#define ADC_CTRL_ADC_PD_CTL_REG_OFFSET 0x14

Definition at line 61 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_PD_CTL_REG_RESVAL

#define ADC_CTRL_ADC_PD_CTL_REG_RESVAL 0x64070u

Definition at line 62 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_FIELD

#define ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_MASK, .index = ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET })

Definition at line 70 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_MASK

#define ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_MASK 0xffffffu

Definition at line 68 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET

#define ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET 8

Definition at line 69 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_FIELD

#define ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_MASK, .index = ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_OFFSET })

Definition at line 86 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_MASK

#define ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_MASK 0xffffu

Definition at line 84 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_OFFSET

#define ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_OFFSET 0

Definition at line 85 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_SAMPLE_CTL_REG_OFFSET

#define ADC_CTRL_ADC_SAMPLE_CTL_REG_OFFSET 0x1c

Definition at line 82 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_SAMPLE_CTL_REG_RESVAL

#define ADC_CTRL_ADC_SAMPLE_CTL_REG_RESVAL 0x9bu

Definition at line 83 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_FIELD

#define ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_MASK, .index = ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_OFFSET })

Definition at line 384 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_MASK

#define ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_MASK 0xffu

Definition at line 382 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_OFFSET

#define ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_OFFSET 0

Definition at line 383 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET

#define ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET 0x6c

Definition at line 380 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_WAKEUP_CTL_REG_RESVAL

#define ADC_CTRL_ADC_WAKEUP_CTL_REG_RESVAL 0x0u

Definition at line 381 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ADC_WAKEUP_CTL_TRANS_EN_BIT

#define ADC_CTRL_ADC_WAKEUP_CTL_TRANS_EN_BIT 8

Definition at line 386 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ALERT_TEST_FATAL_FAULT_BIT

#define ADC_CTRL_ALERT_TEST_FATAL_FAULT_BIT 0

Definition at line 52 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ALERT_TEST_REG_OFFSET

#define ADC_CTRL_ALERT_TEST_REG_OFFSET 0xc

Definition at line 50 of file adc_ctrl_regs.h.

◆ ADC_CTRL_ALERT_TEST_REG_RESVAL

#define ADC_CTRL_ALERT_TEST_REG_RESVAL 0x0u

Definition at line 51 of file adc_ctrl_regs.h.

◆ ADC_CTRL_FILTER_STATUS_MATCH_FIELD

#define ADC_CTRL_FILTER_STATUS_MATCH_FIELD ((bitfield_field32_t) { .mask = ADC_CTRL_FILTER_STATUS_MATCH_MASK, .index = ADC_CTRL_FILTER_STATUS_MATCH_OFFSET })

Definition at line 393 of file adc_ctrl_regs.h.

◆ ADC_CTRL_FILTER_STATUS_MATCH_MASK

#define ADC_CTRL_FILTER_STATUS_MATCH_MASK 0xffu

Definition at line 391 of file adc_ctrl_regs.h.

◆ ADC_CTRL_FILTER_STATUS_MATCH_OFFSET

#define ADC_CTRL_FILTER_STATUS_MATCH_OFFSET 0

Definition at line 392 of file adc_ctrl_regs.h.

◆ ADC_CTRL_FILTER_STATUS_REG_OFFSET

#define ADC_CTRL_FILTER_STATUS_REG_OFFSET 0x70

Definition at line 389 of file adc_ctrl_regs.h.

◆ ADC_CTRL_FILTER_STATUS_REG_RESVAL

#define ADC_CTRL_FILTER_STATUS_REG_RESVAL 0x0u

Definition at line 390 of file adc_ctrl_regs.h.

◆ ADC_CTRL_FILTER_STATUS_TRANS_BIT

#define ADC_CTRL_FILTER_STATUS_TRANS_BIT 8

Definition at line 395 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_COMMON_MATCH_PENDING_BIT

#define ADC_CTRL_INTR_COMMON_MATCH_PENDING_BIT 0

Definition at line 32 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_ENABLE_MATCH_PENDING_BIT

#define ADC_CTRL_INTR_ENABLE_MATCH_PENDING_BIT 0

Definition at line 42 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_ENABLE_REG_OFFSET

#define ADC_CTRL_INTR_ENABLE_REG_OFFSET 0x4

Definition at line 40 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_ENABLE_REG_RESVAL

#define ADC_CTRL_INTR_ENABLE_REG_RESVAL 0x0u

Definition at line 41 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_STATE_MATCH_PENDING_BIT

#define ADC_CTRL_INTR_STATE_MATCH_PENDING_BIT 0

Definition at line 37 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_STATE_REG_OFFSET

#define ADC_CTRL_INTR_STATE_REG_OFFSET 0x0

Definition at line 35 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_STATE_REG_RESVAL

#define ADC_CTRL_INTR_STATE_REG_RESVAL 0x0u

Definition at line 36 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_TEST_MATCH_PENDING_BIT

#define ADC_CTRL_INTR_TEST_MATCH_PENDING_BIT 0

Definition at line 47 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_TEST_REG_OFFSET

#define ADC_CTRL_INTR_TEST_REG_OFFSET 0x8

Definition at line 45 of file adc_ctrl_regs.h.

◆ ADC_CTRL_INTR_TEST_REG_RESVAL

#define ADC_CTRL_INTR_TEST_REG_RESVAL 0x0u

Definition at line 46 of file adc_ctrl_regs.h.

◆ ADC_CTRL_PARAM_NUM_ADC_CHANNEL

#define ADC_CTRL_PARAM_NUM_ADC_CHANNEL 2

Definition at line 23 of file adc_ctrl_regs.h.

◆ ADC_CTRL_PARAM_NUM_ADC_FILTER

#define ADC_CTRL_PARAM_NUM_ADC_FILTER 8

Definition at line 20 of file adc_ctrl_regs.h.

◆ ADC_CTRL_PARAM_NUM_ALERTS

#define ADC_CTRL_PARAM_NUM_ALERTS 1

Definition at line 26 of file adc_ctrl_regs.h.

◆ ADC_CTRL_PARAM_REG_WIDTH

#define ADC_CTRL_PARAM_REG_WIDTH 32

Definition at line 29 of file adc_ctrl_regs.h.

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