adc_ctrl_regs.h

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/**
 * @file
 * @brief Generated register defines for adc_ctrl
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _ADC_CTRL_REG_DEFS_
#define _ADC_CTRL_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number for ADC filters
#define ADC_CTRL_PARAM_NUM_ADC_FILTER 8
 
// Number for ADC channels
#define ADC_CTRL_PARAM_NUM_ADC_CHANNEL 2
 
// Number of alerts
#define ADC_CTRL_PARAM_NUM_ALERTS 1
 
// Register width
#define ADC_CTRL_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define ADC_CTRL_INTR_COMMON_MATCH_PENDING_BIT 0
 
// Interrupt State Register
#define ADC_CTRL_INTR_STATE_REG_OFFSET 0x0
#define ADC_CTRL_INTR_STATE_REG_RESVAL 0x0u
#define ADC_CTRL_INTR_STATE_MATCH_PENDING_BIT 0
 
// Interrupt Enable Register
#define ADC_CTRL_INTR_ENABLE_REG_OFFSET 0x4
#define ADC_CTRL_INTR_ENABLE_REG_RESVAL 0x0u
#define ADC_CTRL_INTR_ENABLE_MATCH_PENDING_BIT 0
 
// Interrupt Test Register
#define ADC_CTRL_INTR_TEST_REG_OFFSET 0x8
#define ADC_CTRL_INTR_TEST_REG_RESVAL 0x0u
#define ADC_CTRL_INTR_TEST_MATCH_PENDING_BIT 0
 
// Alert Test Register
#define ADC_CTRL_ALERT_TEST_REG_OFFSET 0xc
#define ADC_CTRL_ALERT_TEST_REG_RESVAL 0x80000000u
#define ADC_CTRL_ALERT_TEST_FATAL_FAULT_BIT 0
#define ADC_CTRL_ALERT_TEST_REGWEN_BIT 31
 
// ADC enable control register
#define ADC_CTRL_ADC_EN_CTL_REG_OFFSET 0x10
#define ADC_CTRL_ADC_EN_CTL_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_EN_CTL_ADC_ENABLE_BIT 0
#define ADC_CTRL_ADC_EN_CTL_ONESHOT_MODE_BIT 1
 
// ADC PowerDown(PD) control register
#define ADC_CTRL_ADC_PD_CTL_REG_OFFSET 0x14
#define ADC_CTRL_ADC_PD_CTL_REG_RESVAL 0x64070u
#define ADC_CTRL_ADC_PD_CTL_LP_MODE_BIT 0
#define ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_MASK 0xfu
#define ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET 4
#define ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_MASK, .index = ADC_CTRL_ADC_PD_CTL_PWRUP_TIME_OFFSET })
#define ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_MASK 0xffffffu
#define ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET 8
#define ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_MASK, .index = ADC_CTRL_ADC_PD_CTL_WAKEUP_TIME_OFFSET })
 
// ADC Low-Power(LP) sample control register
#define ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_OFFSET 0x18
#define ADC_CTRL_ADC_LP_SAMPLE_CTL_REG_RESVAL 0x4u
#define ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_MASK 0xffu
#define ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_OFFSET 0
#define ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_MASK, .index = ADC_CTRL_ADC_LP_SAMPLE_CTL_LP_SAMPLE_CNT_OFFSET })
 
// ADC sample control register
#define ADC_CTRL_ADC_SAMPLE_CTL_REG_OFFSET 0x1c
#define ADC_CTRL_ADC_SAMPLE_CTL_REG_RESVAL 0x9bu
#define ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_MASK 0xffffu
#define ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_OFFSET 0
#define ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_MASK, .index = ADC_CTRL_ADC_SAMPLE_CTL_NP_SAMPLE_CNT_OFFSET })
 
// ADC FSM reset control
#define ADC_CTRL_ADC_FSM_RST_REG_OFFSET 0x20
#define ADC_CTRL_ADC_FSM_RST_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_FSM_RST_RST_EN_BIT 0
 
// ADC channel0 filter range
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_MIN_V_FIELD_WIDTH 10
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_COND_FIELD_WIDTH 1
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_MAX_V_FIELD_WIDTH 10
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_EN_FIELD_WIDTH 1
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_MULTIREG_COUNT 8
 
// ADC channel0 filter range
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_REG_OFFSET 0x24
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_OFFSET 2
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MIN_V_0_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_COND_0_BIT 12
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_OFFSET 18
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_0_MAX_V_0_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_0_EN_0_BIT 31
 
// ADC channel0 filter range
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_REG_OFFSET 0x28
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_OFFSET 2
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MIN_V_1_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_COND_1_BIT 12
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_OFFSET 18
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_1_MAX_V_1_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_1_EN_1_BIT 31
 
// ADC channel0 filter range
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_REG_OFFSET 0x2c
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_OFFSET 2
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MIN_V_2_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_COND_2_BIT 12
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_OFFSET 18
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_2_MAX_V_2_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_2_EN_2_BIT 31
 
// ADC channel0 filter range
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_REG_OFFSET 0x30
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_OFFSET 2
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MIN_V_3_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_COND_3_BIT 12
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_OFFSET 18
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_3_MAX_V_3_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_3_EN_3_BIT 31
 
// ADC channel0 filter range
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_REG_OFFSET 0x34
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_OFFSET 2
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MIN_V_4_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_COND_4_BIT 12
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_OFFSET 18
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_4_MAX_V_4_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_4_EN_4_BIT 31
 
// ADC channel0 filter range
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_REG_OFFSET 0x38
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_OFFSET 2
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MIN_V_5_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_COND_5_BIT 12
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_OFFSET 18
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_5_MAX_V_5_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_5_EN_5_BIT 31
 
// ADC channel0 filter range
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_REG_OFFSET 0x3c
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_OFFSET 2
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MIN_V_6_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_COND_6_BIT 12
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_OFFSET 18
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_6_MAX_V_6_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_6_EN_6_BIT 31
 
// ADC channel0 filter range
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_OFFSET 0x40
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_OFFSET 2
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MIN_V_7_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_COND_7_BIT 12
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_OFFSET 18
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_MASK, .index = ADC_CTRL_ADC_CHN0_FILTER_CTL_7_MAX_V_7_OFFSET })
#define ADC_CTRL_ADC_CHN0_FILTER_CTL_7_EN_7_BIT 31
 
// ADC channel1 filter range
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_MIN_V_FIELD_WIDTH 10
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_COND_FIELD_WIDTH 1
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_MAX_V_FIELD_WIDTH 10
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_EN_FIELD_WIDTH 1
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_MULTIREG_COUNT 8
 
// ADC channel1 filter range
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_REG_OFFSET 0x44
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_OFFSET 2
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MIN_V_0_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_COND_0_BIT 12
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_OFFSET 18
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_0_MAX_V_0_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_0_EN_0_BIT 31
 
// ADC channel1 filter range
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_REG_OFFSET 0x48
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_OFFSET 2
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MIN_V_1_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_COND_1_BIT 12
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_OFFSET 18
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_1_MAX_V_1_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_1_EN_1_BIT 31
 
// ADC channel1 filter range
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_OFFSET 0x4c
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET 2
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MIN_V_2_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_COND_2_BIT 12
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET 18
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_2_MAX_V_2_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_2_EN_2_BIT 31
 
// ADC channel1 filter range
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_REG_OFFSET 0x50
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_OFFSET 2
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MIN_V_3_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_COND_3_BIT 12
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_OFFSET 18
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_3_MAX_V_3_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_3_EN_3_BIT 31
 
// ADC channel1 filter range
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_REG_OFFSET 0x54
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_OFFSET 2
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MIN_V_4_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_COND_4_BIT 12
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_OFFSET 18
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_4_MAX_V_4_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_4_EN_4_BIT 31
 
// ADC channel1 filter range
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_REG_OFFSET 0x58
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_OFFSET 2
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MIN_V_5_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_COND_5_BIT 12
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_OFFSET 18
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_5_MAX_V_5_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_5_EN_5_BIT 31
 
// ADC channel1 filter range
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_REG_OFFSET 0x5c
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_OFFSET 2
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MIN_V_6_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_COND_6_BIT 12
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_OFFSET 18
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_6_MAX_V_6_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_6_EN_6_BIT 31
 
// ADC channel1 filter range
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_REG_OFFSET 0x60
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_OFFSET 2
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MIN_V_7_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_COND_7_BIT 12
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_OFFSET 18
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_MASK, .index = ADC_CTRL_ADC_CHN1_FILTER_CTL_7_MAX_V_7_OFFSET })
#define ADC_CTRL_ADC_CHN1_FILTER_CTL_7_EN_7_BIT 31
 
// ADC value sampled on channel (common parameters)
#define ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_EXT_FIELD_WIDTH 2
#define ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_FIELD_WIDTH 10
#define ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_INTR_EXT_FIELD_WIDTH 2
#define ADC_CTRL_ADC_CHN_VAL_ADC_CHN_VALUE_INTR_FIELD_WIDTH 10
#define ADC_CTRL_ADC_CHN_VAL_MULTIREG_COUNT 2
 
// ADC value sampled on channel
#define ADC_CTRL_ADC_CHN_VAL_0_REG_OFFSET 0x64
#define ADC_CTRL_ADC_CHN_VAL_0_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_MASK 0x3u
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_OFFSET 0
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_EXT_0_OFFSET })
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_OFFSET 2
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_0_OFFSET })
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_MASK 0x3u
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_OFFSET 16
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_EXT_0_OFFSET })
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_OFFSET 18
#define ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_MASK, .index = ADC_CTRL_ADC_CHN_VAL_0_ADC_CHN_VALUE_INTR_0_OFFSET })
 
// ADC value sampled on channel
#define ADC_CTRL_ADC_CHN_VAL_1_REG_OFFSET 0x68
#define ADC_CTRL_ADC_CHN_VAL_1_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_MASK 0x3u
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_OFFSET 0
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_EXT_1_OFFSET })
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_OFFSET 2
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_1_OFFSET })
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_MASK 0x3u
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_OFFSET 16
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_EXT_1_OFFSET })
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_MASK 0x3ffu
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_OFFSET 18
#define ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_MASK, .index = ADC_CTRL_ADC_CHN_VAL_1_ADC_CHN_VALUE_INTR_1_OFFSET })
 
// Enable filter matches as wakeups
#define ADC_CTRL_ADC_WAKEUP_CTL_REG_OFFSET 0x6c
#define ADC_CTRL_ADC_WAKEUP_CTL_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_MASK 0xffu
#define ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_OFFSET 0
#define ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_MASK, .index = ADC_CTRL_ADC_WAKEUP_CTL_MATCH_EN_OFFSET })
#define ADC_CTRL_ADC_WAKEUP_CTL_TRANS_EN_BIT 8
 
// Adc filter match status
#define ADC_CTRL_FILTER_STATUS_REG_OFFSET 0x70
#define ADC_CTRL_FILTER_STATUS_REG_RESVAL 0x0u
#define ADC_CTRL_FILTER_STATUS_MATCH_MASK 0xffu
#define ADC_CTRL_FILTER_STATUS_MATCH_OFFSET 0
#define ADC_CTRL_FILTER_STATUS_MATCH_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_FILTER_STATUS_MATCH_MASK, .index = ADC_CTRL_FILTER_STATUS_MATCH_OFFSET })
#define ADC_CTRL_FILTER_STATUS_TRANS_BIT 8
 
// Interrupt enable controls.
#define ADC_CTRL_ADC_INTR_CTL_REG_OFFSET 0x74
#define ADC_CTRL_ADC_INTR_CTL_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_INTR_CTL_MATCH_EN_MASK 0xffu
#define ADC_CTRL_ADC_INTR_CTL_MATCH_EN_OFFSET 0
#define ADC_CTRL_ADC_INTR_CTL_MATCH_EN_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_INTR_CTL_MATCH_EN_MASK, .index = ADC_CTRL_ADC_INTR_CTL_MATCH_EN_OFFSET })
#define ADC_CTRL_ADC_INTR_CTL_TRANS_EN_BIT 8
#define ADC_CTRL_ADC_INTR_CTL_ONESHOT_EN_BIT 9
 
// Debug cable internal status
#define ADC_CTRL_ADC_INTR_STATUS_REG_OFFSET 0x78
#define ADC_CTRL_ADC_INTR_STATUS_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_INTR_STATUS_MATCH_MASK 0xffu
#define ADC_CTRL_ADC_INTR_STATUS_MATCH_OFFSET 0
#define ADC_CTRL_ADC_INTR_STATUS_MATCH_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_INTR_STATUS_MATCH_MASK, .index = ADC_CTRL_ADC_INTR_STATUS_MATCH_OFFSET })
#define ADC_CTRL_ADC_INTR_STATUS_TRANS_BIT 8
#define ADC_CTRL_ADC_INTR_STATUS_ONESHOT_BIT 9
 
// State of the internal state machine
#define ADC_CTRL_ADC_FSM_STATE_REG_OFFSET 0x7c
#define ADC_CTRL_ADC_FSM_STATE_REG_RESVAL 0x0u
#define ADC_CTRL_ADC_FSM_STATE_STATE_MASK 0x1fu
#define ADC_CTRL_ADC_FSM_STATE_STATE_OFFSET 0
#define ADC_CTRL_ADC_FSM_STATE_STATE_FIELD \
  ((bitfield_field32_t) { .mask = ADC_CTRL_ADC_FSM_STATE_STATE_MASK, .index = ADC_CTRL_ADC_FSM_STATE_STATE_OFFSET })
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_PWRDN 0x0
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_PWRUP 0x1
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_0 0x2
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_021 0x3
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_1 0x4
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_ONEST_DONE 0x5
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_0 0x6
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_021 0x7
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_1 0x8
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_EVAL 0x9
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_SLP 0xa
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_LP_PWRUP 0xb
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_0 0xc
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_021 0xd
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_1 0xe
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_EVAL 0xf
#define ADC_CTRL_ADC_FSM_STATE_STATE_VALUE_NP_DONE 0x10
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _ADC_CTRL_REG_DEFS_
// End generated register defines for adc_ctrl