Software APIs
dt_rv_timer.c
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// Copyright lowRISC contributors (OpenTitan project).
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Device table API auto-generated by `dtgen`
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/**
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* @file
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* @brief Device Tables (DT) for IP rv_timer and top englishbreakfast.
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*/
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#include "hw/top/dt/dt_rv_timer.h"
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/**
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* Description of instances.
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*/
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typedef
struct
dt_desc_rv_timer
{
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dt_instance_id_t
inst_id
;
/**< Instance ID */
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uint32_t
reg_addr
[kDtRvTimerRegBlockCount];
/**< Base address of each register block */
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uint32_t
mem_addr
[kDtRvTimerMemoryCount];
/**< Base address of each memory */
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uint32_t
mem_size
[kDtRvTimerMemoryCount];
/**< Size in bytes of each memory */
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/**
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* PLIC ID of the first IRQ of this instance
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*
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* This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
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*/
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top_englishbreakfast_plic_irq_id_t
first_irq
;
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dt_clock_t
clock
[kDtRvTimerClockCount];
/**< Clock signal connected to each clock port */
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dt_reset_t
reset
[kDtRvTimerResetCount];
/**< Reset signal connected to each reset port */
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}
dt_desc_rv_timer_t
;
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static
const
dt_desc_rv_timer_t
rv_timer_desc[kDtRvTimerCount] = {
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[
kDtRvTimer
] = {
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.inst_id =
kDtInstanceIdRvTimer
,
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.reg_addr = {
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[kDtRvTimerRegBlockCore] = 0x40100000,
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},
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.mem_addr = {
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},
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.mem_size = {
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},
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.first_irq =
kTopEnglishbreakfastPlicIrqIdNone
,
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.clock = {
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[
kDtRvTimerClockClk
] =
kDtClockIoDiv4
,
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},
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.reset = {
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[
kDtRvTimerResetRst
] =
kDtResetSysIoDiv4
,
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},
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},
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};
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/**
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* Return a pointer to the `dt_rv_timer_desc_t` structure of the requested
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* `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
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* the function) with the provided default value.
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*/
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#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_rv_timer_t)0 || (dt) >= kDtRvTimerCount) return (default); &rv_timer_desc[dt]; })
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dt_rv_timer_t
dt_rv_timer_from_instance_id
(
dt_instance_id_t
inst_id) {
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if
(inst_id >=
kDtInstanceIdRvTimer
&& inst_id <=
kDtInstanceIdRvTimer
) {
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return
(
dt_rv_timer_t
)(inst_id -
kDtInstanceIdRvTimer
);
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}
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return
(
dt_rv_timer_t
)0;
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}
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dt_instance_id_t
dt_rv_timer_instance_id
(
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dt_rv_timer_t
dt) {
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return
TRY_GET_DT
(dt,
kDtInstanceIdUnknown
)->inst_id;
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}
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uint32_t
dt_rv_timer_reg_block
(
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dt_rv_timer_t
dt,
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dt_rv_timer_reg_block_t
reg_block) {
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// Return a recognizable address in case of wrong argument.
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return
TRY_GET_DT
(dt, 0xdeadbeef)->reg_addr[reg_block];
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}
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uint32_t
dt_rv_timer_memory_base
(
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dt_rv_timer_t
dt,
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dt_rv_timer_memory_t
mem) {
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// Return a recognizable address in case of wrong argument.
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return
TRY_GET_DT
(dt, 0xdeadbeef)->mem_addr[mem];
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}
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uint32_t
dt_rv_timer_memory_size
(
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dt_rv_timer_t
dt,
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dt_rv_timer_memory_t
mem) {
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// Return an empty size in case of wrong argument.
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return
TRY_GET_DT
(dt, 0)->mem_size[mem];
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}
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dt_plic_irq_id_t
dt_rv_timer_irq_to_plic_id
(
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dt_rv_timer_t
dt,
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dt_rv_timer_irq_t
irq) {
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dt_plic_irq_id_t
first_irq =
TRY_GET_DT
(dt, kDtPlicIrqIdNone)->first_irq;
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if
(first_irq == kDtPlicIrqIdNone) {
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return
kDtPlicIrqIdNone;
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}
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return
(
dt_plic_irq_id_t
)((uint32_t)first_irq + (uint32_t)irq);
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}
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dt_rv_timer_irq_t
dt_rv_timer_irq_from_plic_id
(
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dt_rv_timer_t
dt,
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dt_plic_irq_id_t
irq) {
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dt_rv_timer_irq_t
count = kDtRvTimerIrqCount;
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dt_plic_irq_id_t
first_irq =
TRY_GET_DT
(dt, count)->first_irq;
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if
(first_irq == kDtPlicIrqIdNone) {
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return
count;
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}
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if
(irq < first_irq || irq >= first_irq + (
dt_plic_irq_id_t
)count) {
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return
count;
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}
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return
(
dt_rv_timer_irq_t
)(irq - first_irq);
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}
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dt_clock_t
dt_rv_timer_clock
(
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dt_rv_timer_t
dt,
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dt_rv_timer_clock_t
clk) {
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// Return the first clock in case of invalid argument.
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return
TRY_GET_DT
(dt, (
dt_clock_t
)0)->clock[clk];
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}
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dt_reset_t
dt_rv_timer_reset
(
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dt_rv_timer_t
dt,
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dt_rv_timer_reset_t
rst) {
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const
dt_rv_timer_reset_t
count = kDtRvTimerResetCount;
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if
(rst >= count) {
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return
kDtResetUnknown
;
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}
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return
TRY_GET_DT
(dt,
kDtResetUnknown
)->reset[rst];
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}
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(englishbreakfast)
hw
top
dt
dt_rv_timer.c
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