15void isr_testutils_adc_ctrl_isr(
18 dif_adc_ctrl_irq_t *irq_serviced) {
23 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
27 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
30 dif_adc_ctrl_irq_t irq =
31 (dif_adc_ctrl_irq_t)(plic_irq_id -
38 CHECK_DIF_OK(dif_adc_ctrl_irq_get_state(adc_ctrl_ctx.
adc_ctrl, &snapshot));
40 "Only adc_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
47 CHECK_DIF_OK(dif_adc_ctrl_irq_clear_causes(adc_ctrl_ctx.
adc_ctrl,
52 CHECK_DIF_OK(dif_adc_ctrl_irq_get_type(adc_ctrl_ctx.
adc_ctrl, irq, &type));
54 CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge(adc_ctrl_ctx.
adc_ctrl, irq));
55 }
else if (mute_status_irq) {
56 CHECK_DIF_OK(dif_adc_ctrl_irq_set_enabled(adc_ctrl_ctx.
adc_ctrl, irq,
61 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
65void isr_testutils_alert_handler_isr(
68 dif_alert_handler_irq_t *irq_serviced) {
73 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
77 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
80 dif_alert_handler_irq_t irq =
81 (dif_alert_handler_irq_t)(plic_irq_id -
83 .plic_alert_handler_start_irq_id);
89 CHECK_DIF_OK(dif_alert_handler_irq_get_state(
92 "Only alert_handler IRQ %d expected to fire. Actual IRQ state = %x",
98 CHECK_DIF_OK(dif_alert_handler_irq_get_type(alert_handler_ctx.
alert_handler,
101 CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(
106 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
110void isr_testutils_aon_timer_isr(
113 dif_aon_timer_irq_t *irq_serviced) {
118 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
122 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
125 dif_aon_timer_irq_t irq =
126 (dif_aon_timer_irq_t)(plic_irq_id -
134 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
136 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
142 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
144 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
148 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
152void isr_testutils_csrng_isr(
155 dif_csrng_irq_t *irq_serviced) {
160 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
164 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
167 dif_csrng_irq_t irq =
174 CHECK_DIF_OK(dif_csrng_irq_get_state(csrng_ctx.
csrng, &snapshot));
176 "Only csrng IRQ %d expected to fire. Actual IRQ state = %x", irq,
182 CHECK_DIF_OK(dif_csrng_irq_get_type(csrng_ctx.
csrng, irq, &type));
184 CHECK_DIF_OK(dif_csrng_irq_acknowledge(csrng_ctx.
csrng, irq));
188 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
194 dif_edn_irq_t *irq_serviced) {
199 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
203 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
213 CHECK_DIF_OK(dif_edn_irq_get_state(edn_ctx.
edn, &snapshot));
215 "Only edn IRQ %d expected to fire. Actual IRQ state = %x", irq,
221 CHECK_DIF_OK(dif_edn_irq_get_type(edn_ctx.
edn, irq, &type));
223 CHECK_DIF_OK(dif_edn_irq_acknowledge(edn_ctx.
edn, irq));
227 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
231void isr_testutils_entropy_src_isr(
234 dif_entropy_src_irq_t *irq_serviced) {
239 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
243 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
246 dif_entropy_src_irq_t irq =
247 (dif_entropy_src_irq_t)(plic_irq_id -
255 dif_entropy_src_irq_get_state(entropy_src_ctx.
entropy_src, &snapshot));
257 "Only entropy_src IRQ %d expected to fire. Actual IRQ state = %x",
264 dif_entropy_src_irq_get_type(entropy_src_ctx.
entropy_src, irq, &type));
267 dif_entropy_src_irq_acknowledge(entropy_src_ctx.
entropy_src, irq));
271 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
277 dif_gpio_irq_t *irq_serviced) {
282 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
286 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
296 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
298 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
304 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
306 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
310 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
315 bool mute_status_irq,
317 dif_hmac_irq_t *irq_serviced) {
322 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
326 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
336 CHECK_DIF_OK(dif_hmac_irq_get_state(hmac_ctx.
hmac, &snapshot));
338 "Only hmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
344 CHECK_DIF_OK(dif_hmac_irq_get_type(hmac_ctx.
hmac, irq, &type));
346 CHECK_DIF_OK(dif_hmac_irq_acknowledge(hmac_ctx.
hmac, irq));
347 }
else if (mute_status_irq) {
353 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
358 bool mute_status_irq,
360 dif_i2c_irq_t *irq_serviced) {
365 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
369 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
379 CHECK_DIF_OK(dif_i2c_irq_get_state(i2c_ctx.
i2c, &snapshot));
381 "Only i2c IRQ %d expected to fire. Actual IRQ state = %x", irq,
387 CHECK_DIF_OK(dif_i2c_irq_get_type(i2c_ctx.
i2c, irq, &type));
389 CHECK_DIF_OK(dif_i2c_irq_acknowledge(i2c_ctx.
i2c, irq));
390 }
else if (mute_status_irq) {
395 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
399void isr_testutils_keymgr_dpe_isr(
402 dif_keymgr_dpe_irq_t *irq_serviced) {
407 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
411 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
414 dif_keymgr_dpe_irq_t irq =
415 (dif_keymgr_dpe_irq_t)(plic_irq_id -
423 dif_keymgr_dpe_irq_get_state(keymgr_dpe_ctx.
keymgr_dpe, &snapshot));
425 "Only keymgr_dpe IRQ %d expected to fire. Actual IRQ state = %x", irq,
432 dif_keymgr_dpe_irq_get_type(keymgr_dpe_ctx.
keymgr_dpe, irq, &type));
435 dif_keymgr_dpe_irq_acknowledge(keymgr_dpe_ctx.
keymgr_dpe, irq));
439 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
444 bool mute_status_irq,
446 dif_kmac_irq_t *irq_serviced) {
451 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
455 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
465 CHECK_DIF_OK(dif_kmac_irq_get_state(kmac_ctx.
kmac, &snapshot));
467 "Only kmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
473 CHECK_DIF_OK(dif_kmac_irq_get_type(kmac_ctx.
kmac, irq, &type));
475 CHECK_DIF_OK(dif_kmac_irq_acknowledge(kmac_ctx.
kmac, irq));
476 }
else if (mute_status_irq) {
482 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
488 dif_otbn_irq_t *irq_serviced) {
493 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
497 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
507 CHECK_DIF_OK(dif_otbn_irq_get_state(otbn_ctx.
otbn, &snapshot));
509 "Only otbn IRQ %d expected to fire. Actual IRQ state = %x", irq,
515 CHECK_DIF_OK(dif_otbn_irq_get_type(otbn_ctx.
otbn, irq, &type));
517 CHECK_DIF_OK(dif_otbn_irq_acknowledge(otbn_ctx.
otbn, irq));
521 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
525void isr_testutils_otp_ctrl_isr(
528 dif_otp_ctrl_irq_t *irq_serviced) {
533 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
537 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
540 dif_otp_ctrl_irq_t irq =
541 (dif_otp_ctrl_irq_t)(plic_irq_id -
548 CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(otp_ctrl_ctx.
otp_ctrl, &snapshot));
550 "Only otp_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
556 CHECK_DIF_OK(dif_otp_ctrl_irq_get_type(otp_ctrl_ctx.
otp_ctrl, irq, &type));
558 CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(otp_ctrl_ctx.
otp_ctrl, irq));
562 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
566void isr_testutils_pwrmgr_isr(
569 dif_pwrmgr_irq_t *irq_serviced) {
574 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
578 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
581 dif_pwrmgr_irq_t irq =
588 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
590 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
596 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
598 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
602 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
606void isr_testutils_rram_ctrl_isr(
609 dif_rram_ctrl_irq_t *irq_serviced) {
614 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
618 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
621 dif_rram_ctrl_irq_t irq =
622 (dif_rram_ctrl_irq_t)(plic_irq_id -
630 dif_rram_ctrl_irq_get_state(rram_ctrl_ctx.
rram_ctrl, &snapshot));
632 "Only rram_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
638 CHECK_DIF_OK(dif_rram_ctrl_irq_get_type(rram_ctrl_ctx.
rram_ctrl, irq, &type));
640 CHECK_DIF_OK(dif_rram_ctrl_irq_acknowledge(rram_ctrl_ctx.
rram_ctrl, irq));
641 }
else if (mute_status_irq) {
642 CHECK_DIF_OK(dif_rram_ctrl_irq_set_enabled(rram_ctrl_ctx.
rram_ctrl, irq,
647 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
651void isr_testutils_rv_timer_isr(
654 dif_rv_timer_irq_t *irq_serviced) {
659 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
663 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
666 dif_rv_timer_irq_t irq =
667 (dif_rv_timer_irq_t)(plic_irq_id -
674 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
677 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
683 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
685 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
689 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
693void isr_testutils_sensor_ctrl_isr(
696 dif_sensor_ctrl_irq_t *irq_serviced) {
701 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
705 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
708 dif_sensor_ctrl_irq_t irq =
709 (dif_sensor_ctrl_irq_t)(plic_irq_id -
717 dif_sensor_ctrl_irq_get_state(sensor_ctrl_ctx.
sensor_ctrl, &snapshot));
719 "Only sensor_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
726 dif_sensor_ctrl_irq_get_type(sensor_ctrl_ctx.
sensor_ctrl, irq, &type));
729 dif_sensor_ctrl_irq_acknowledge(sensor_ctrl_ctx.
sensor_ctrl, irq));
733 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
737void isr_testutils_spi_device_isr(
740 dif_spi_device_irq_t *irq_serviced) {
745 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
749 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
752 dif_spi_device_irq_t irq =
753 (dif_spi_device_irq_t)(plic_irq_id -
761 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
763 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
770 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
773 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
774 }
else if (mute_status_irq) {
775 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
780 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
784void isr_testutils_spi_host_isr(
787 dif_spi_host_irq_t *irq_serviced) {
792 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
796 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
799 dif_spi_host_irq_t irq =
800 (dif_spi_host_irq_t)(plic_irq_id -
807 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
809 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
815 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
817 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
818 }
else if (mute_status_irq) {
819 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
824 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
828void isr_testutils_sysrst_ctrl_isr(
831 dif_sysrst_ctrl_irq_t *irq_serviced) {
836 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
840 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
843 dif_sysrst_ctrl_irq_t irq =
844 (dif_sysrst_ctrl_irq_t)(plic_irq_id -
852 dif_sysrst_ctrl_irq_get_state(sysrst_ctrl_ctx.
sysrst_ctrl, &snapshot));
854 "Only sysrst_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
861 dif_sysrst_ctrl_irq_get_type(sysrst_ctrl_ctx.
sysrst_ctrl, irq, &type));
864 dif_sysrst_ctrl_irq_acknowledge(sysrst_ctrl_ctx.
sysrst_ctrl, irq));
865 }
else if (mute_status_irq) {
866 CHECK_DIF_OK(dif_sysrst_ctrl_irq_set_enabled(sysrst_ctrl_ctx.
sysrst_ctrl,
871 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
876 bool mute_status_irq,
878 dif_uart_irq_t *irq_serviced) {
883 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
887 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
897 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
899 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
905 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
907 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
908 }
else if (mute_status_irq) {
914 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
918void isr_testutils_usbdev_isr(
921 dif_usbdev_irq_t *irq_serviced) {
926 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
930 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
933 dif_usbdev_irq_t irq =
940 CHECK_DIF_OK(dif_usbdev_irq_get_state(usbdev_ctx.
usbdev, &snapshot));
942 "Only usbdev IRQ %d expected to fire. Actual IRQ state = %x", irq,
948 CHECK_DIF_OK(dif_usbdev_irq_get_type(usbdev_ctx.
usbdev, irq, &type));
950 CHECK_DIF_OK(dif_usbdev_irq_acknowledge(usbdev_ctx.
usbdev, irq));
951 }
else if (mute_status_irq) {
957 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,