15void isr_testutils_adc_ctrl_isr(
18 dif_adc_ctrl_irq_t *irq_serviced) {
23 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
27 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
30 dif_adc_ctrl_irq_t irq =
31 (dif_adc_ctrl_irq_t)(plic_irq_id -
38 CHECK_DIF_OK(dif_adc_ctrl_irq_get_state(adc_ctrl_ctx.
adc_ctrl, &snapshot));
40 "Only adc_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
47 CHECK_DIF_OK(dif_adc_ctrl_irq_clear_causes(adc_ctrl_ctx.
adc_ctrl,
52 CHECK_DIF_OK(dif_adc_ctrl_irq_get_type(adc_ctrl_ctx.
adc_ctrl, irq, &type));
54 CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge(adc_ctrl_ctx.
adc_ctrl, irq));
55 }
else if (mute_status_irq) {
56 CHECK_DIF_OK(dif_adc_ctrl_irq_set_enabled(adc_ctrl_ctx.
adc_ctrl, irq,
61 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
65void isr_testutils_alert_handler_isr(
68 dif_alert_handler_irq_t *irq_serviced) {
73 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
77 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
80 dif_alert_handler_irq_t irq =
81 (dif_alert_handler_irq_t)(plic_irq_id -
83 .plic_alert_handler_start_irq_id);
89 CHECK_DIF_OK(dif_alert_handler_irq_get_state(
92 "Only alert_handler IRQ %d expected to fire. Actual IRQ state = %x",
98 CHECK_DIF_OK(dif_alert_handler_irq_get_type(alert_handler_ctx.
alert_handler,
101 CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(
106 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
110void isr_testutils_aon_timer_isr(
113 dif_aon_timer_irq_t *irq_serviced) {
118 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
122 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
125 dif_aon_timer_irq_t irq =
126 (dif_aon_timer_irq_t)(plic_irq_id -
134 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
136 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
142 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
144 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
148 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
152void isr_testutils_cheriot_mem_sys_isr(
155 dif_cheriot_mem_sys_irq_t *irq_serviced) {
160 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
164 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
167 dif_cheriot_mem_sys_irq_t irq =
168 (dif_cheriot_mem_sys_irq_t)(plic_irq_id -
170 .plic_cheriot_mem_sys_start_irq_id);
176 CHECK_DIF_OK(dif_cheriot_mem_sys_irq_get_state(
179 "Only cheriot_mem_sys IRQ %d expected to fire. Actual IRQ state = %x",
185 CHECK_DIF_OK(dif_cheriot_mem_sys_irq_get_type(
188 CHECK_DIF_OK(dif_cheriot_mem_sys_irq_acknowledge(
193 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
197void isr_testutils_csrng_isr(
200 dif_csrng_irq_t *irq_serviced) {
205 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
209 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
212 dif_csrng_irq_t irq =
219 CHECK_DIF_OK(dif_csrng_irq_get_state(csrng_ctx.
csrng, &snapshot));
221 "Only csrng IRQ %d expected to fire. Actual IRQ state = %x", irq,
227 CHECK_DIF_OK(dif_csrng_irq_get_type(csrng_ctx.
csrng, irq, &type));
229 CHECK_DIF_OK(dif_csrng_irq_acknowledge(csrng_ctx.
csrng, irq));
233 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
239 dif_edn_irq_t *irq_serviced) {
244 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
248 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
258 CHECK_DIF_OK(dif_edn_irq_get_state(edn_ctx.
edn, &snapshot));
260 "Only edn IRQ %d expected to fire. Actual IRQ state = %x", irq,
266 CHECK_DIF_OK(dif_edn_irq_get_type(edn_ctx.
edn, irq, &type));
268 CHECK_DIF_OK(dif_edn_irq_acknowledge(edn_ctx.
edn, irq));
272 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
276void isr_testutils_entropy_src_isr(
279 dif_entropy_src_irq_t *irq_serviced) {
284 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
288 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
291 dif_entropy_src_irq_t irq =
292 (dif_entropy_src_irq_t)(plic_irq_id -
300 dif_entropy_src_irq_get_state(entropy_src_ctx.
entropy_src, &snapshot));
302 "Only entropy_src IRQ %d expected to fire. Actual IRQ state = %x",
309 dif_entropy_src_irq_get_type(entropy_src_ctx.
entropy_src, irq, &type));
312 dif_entropy_src_irq_acknowledge(entropy_src_ctx.
entropy_src, irq));
316 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
322 dif_gpio_irq_t *irq_serviced) {
327 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
331 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
341 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
343 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
349 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
351 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
355 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
360 bool mute_status_irq,
362 dif_hmac_irq_t *irq_serviced) {
367 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
371 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
381 CHECK_DIF_OK(dif_hmac_irq_get_state(hmac_ctx.
hmac, &snapshot));
383 "Only hmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
389 CHECK_DIF_OK(dif_hmac_irq_get_type(hmac_ctx.
hmac, irq, &type));
391 CHECK_DIF_OK(dif_hmac_irq_acknowledge(hmac_ctx.
hmac, irq));
392 }
else if (mute_status_irq) {
398 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
403 bool mute_status_irq,
405 dif_i2c_irq_t *irq_serviced) {
410 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
414 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
424 CHECK_DIF_OK(dif_i2c_irq_get_state(i2c_ctx.
i2c, &snapshot));
426 "Only i2c IRQ %d expected to fire. Actual IRQ state = %x", irq,
432 CHECK_DIF_OK(dif_i2c_irq_get_type(i2c_ctx.
i2c, irq, &type));
434 CHECK_DIF_OK(dif_i2c_irq_acknowledge(i2c_ctx.
i2c, irq));
435 }
else if (mute_status_irq) {
440 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
444void isr_testutils_keymgr_dpe_isr(
447 dif_keymgr_dpe_irq_t *irq_serviced) {
452 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
456 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
459 dif_keymgr_dpe_irq_t irq =
460 (dif_keymgr_dpe_irq_t)(plic_irq_id -
468 dif_keymgr_dpe_irq_get_state(keymgr_dpe_ctx.
keymgr_dpe, &snapshot));
470 "Only keymgr_dpe IRQ %d expected to fire. Actual IRQ state = %x", irq,
477 dif_keymgr_dpe_irq_get_type(keymgr_dpe_ctx.
keymgr_dpe, irq, &type));
480 dif_keymgr_dpe_irq_acknowledge(keymgr_dpe_ctx.
keymgr_dpe, irq));
484 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
489 bool mute_status_irq,
491 dif_kmac_irq_t *irq_serviced) {
496 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
500 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
510 CHECK_DIF_OK(dif_kmac_irq_get_state(kmac_ctx.
kmac, &snapshot));
512 "Only kmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
518 CHECK_DIF_OK(dif_kmac_irq_get_type(kmac_ctx.
kmac, irq, &type));
520 CHECK_DIF_OK(dif_kmac_irq_acknowledge(kmac_ctx.
kmac, irq));
521 }
else if (mute_status_irq) {
527 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
533 dif_otbn_irq_t *irq_serviced) {
538 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
542 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
552 CHECK_DIF_OK(dif_otbn_irq_get_state(otbn_ctx.
otbn, &snapshot));
554 "Only otbn IRQ %d expected to fire. Actual IRQ state = %x", irq,
560 CHECK_DIF_OK(dif_otbn_irq_get_type(otbn_ctx.
otbn, irq, &type));
562 CHECK_DIF_OK(dif_otbn_irq_acknowledge(otbn_ctx.
otbn, irq));
566 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
570void isr_testutils_otp_ctrl_isr(
573 dif_otp_ctrl_irq_t *irq_serviced) {
578 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
582 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
585 dif_otp_ctrl_irq_t irq =
586 (dif_otp_ctrl_irq_t)(plic_irq_id -
593 CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(otp_ctrl_ctx.
otp_ctrl, &snapshot));
595 "Only otp_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
601 CHECK_DIF_OK(dif_otp_ctrl_irq_get_type(otp_ctrl_ctx.
otp_ctrl, irq, &type));
603 CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(otp_ctrl_ctx.
otp_ctrl, irq));
607 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
611void isr_testutils_pwrmgr_isr(
614 dif_pwrmgr_irq_t *irq_serviced) {
619 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
623 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
626 dif_pwrmgr_irq_t irq =
633 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
635 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
641 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
643 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
647 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
651void isr_testutils_rram_ctrl_isr(
654 dif_rram_ctrl_irq_t *irq_serviced) {
659 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
663 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
666 dif_rram_ctrl_irq_t irq =
667 (dif_rram_ctrl_irq_t)(plic_irq_id -
675 dif_rram_ctrl_irq_get_state(rram_ctrl_ctx.
rram_ctrl, &snapshot));
677 "Only rram_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
683 CHECK_DIF_OK(dif_rram_ctrl_irq_get_type(rram_ctrl_ctx.
rram_ctrl, irq, &type));
685 CHECK_DIF_OK(dif_rram_ctrl_irq_acknowledge(rram_ctrl_ctx.
rram_ctrl, irq));
686 }
else if (mute_status_irq) {
687 CHECK_DIF_OK(dif_rram_ctrl_irq_set_enabled(rram_ctrl_ctx.
rram_ctrl, irq,
692 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
696void isr_testutils_rv_timer_isr(
699 dif_rv_timer_irq_t *irq_serviced) {
704 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
708 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
711 dif_rv_timer_irq_t irq =
712 (dif_rv_timer_irq_t)(plic_irq_id -
719 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
722 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
728 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
730 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
734 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
738void isr_testutils_sensor_ctrl_isr(
741 dif_sensor_ctrl_irq_t *irq_serviced) {
746 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
750 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
753 dif_sensor_ctrl_irq_t irq =
754 (dif_sensor_ctrl_irq_t)(plic_irq_id -
762 dif_sensor_ctrl_irq_get_state(sensor_ctrl_ctx.
sensor_ctrl, &snapshot));
764 "Only sensor_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
771 dif_sensor_ctrl_irq_get_type(sensor_ctrl_ctx.
sensor_ctrl, irq, &type));
774 dif_sensor_ctrl_irq_acknowledge(sensor_ctrl_ctx.
sensor_ctrl, irq));
778 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
782void isr_testutils_spi_device_isr(
785 dif_spi_device_irq_t *irq_serviced) {
790 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
794 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
797 dif_spi_device_irq_t irq =
798 (dif_spi_device_irq_t)(plic_irq_id -
806 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
808 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
815 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
818 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
819 }
else if (mute_status_irq) {
820 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
825 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
829void isr_testutils_spi_host_isr(
832 dif_spi_host_irq_t *irq_serviced) {
837 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
841 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
844 dif_spi_host_irq_t irq =
845 (dif_spi_host_irq_t)(plic_irq_id -
852 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
854 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
860 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
862 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
863 }
else if (mute_status_irq) {
864 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
869 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
873void isr_testutils_sysrst_ctrl_isr(
876 dif_sysrst_ctrl_irq_t *irq_serviced) {
881 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
885 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
888 dif_sysrst_ctrl_irq_t irq =
889 (dif_sysrst_ctrl_irq_t)(plic_irq_id -
897 dif_sysrst_ctrl_irq_get_state(sysrst_ctrl_ctx.
sysrst_ctrl, &snapshot));
899 "Only sysrst_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
906 dif_sysrst_ctrl_irq_get_type(sysrst_ctrl_ctx.
sysrst_ctrl, irq, &type));
909 dif_sysrst_ctrl_irq_acknowledge(sysrst_ctrl_ctx.
sysrst_ctrl, irq));
910 }
else if (mute_status_irq) {
911 CHECK_DIF_OK(dif_sysrst_ctrl_irq_set_enabled(sysrst_ctrl_ctx.
sysrst_ctrl,
916 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
921 bool mute_status_irq,
923 dif_uart_irq_t *irq_serviced) {
928 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
932 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
942 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
944 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
950 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
952 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
953 }
else if (mute_status_irq) {
959 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
963void isr_testutils_usbdev_isr(
966 dif_usbdev_irq_t *irq_serviced) {
971 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
975 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
978 dif_usbdev_irq_t irq =
985 CHECK_DIF_OK(dif_usbdev_irq_get_state(usbdev_ctx.
usbdev, &snapshot));
987 "Only usbdev IRQ %d expected to fire. Actual IRQ state = %x", irq,
993 CHECK_DIF_OK(dif_usbdev_irq_get_type(usbdev_ctx.
usbdev, irq, &type));
995 CHECK_DIF_OK(dif_usbdev_irq_acknowledge(usbdev_ctx.
usbdev, irq));
996 }
else if (mute_status_irq) {
1002 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,