15void isr_testutils_adc_ctrl_isr(
18 dif_adc_ctrl_irq_t *irq_serviced) {
23 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
27 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
30 dif_adc_ctrl_irq_t irq =
31 (dif_adc_ctrl_irq_t)(plic_irq_id -
38 CHECK_DIF_OK(dif_adc_ctrl_irq_get_state(adc_ctrl_ctx.
adc_ctrl, &snapshot));
40 "Only adc_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
47 CHECK_DIF_OK(dif_adc_ctrl_irq_clear_causes(adc_ctrl_ctx.
adc_ctrl,
52 CHECK_DIF_OK(dif_adc_ctrl_irq_get_type(adc_ctrl_ctx.
adc_ctrl, irq, &type));
54 CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge(adc_ctrl_ctx.
adc_ctrl, irq));
55 }
else if (mute_status_irq) {
56 CHECK_DIF_OK(dif_adc_ctrl_irq_set_enabled(adc_ctrl_ctx.
adc_ctrl, irq,
61 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
65void isr_testutils_alert_handler_isr(
68 dif_alert_handler_irq_t *irq_serviced) {
73 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
77 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
80 dif_alert_handler_irq_t irq =
81 (dif_alert_handler_irq_t)(plic_irq_id -
83 .plic_alert_handler_start_irq_id);
89 CHECK_DIF_OK(dif_alert_handler_irq_get_state(
92 "Only alert_handler IRQ %d expected to fire. Actual IRQ state = %x",
98 CHECK_DIF_OK(dif_alert_handler_irq_get_type(alert_handler_ctx.
alert_handler,
101 CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(
106 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
110void isr_testutils_aon_timer_isr(
113 dif_aon_timer_irq_t *irq_serviced) {
118 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
122 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
125 dif_aon_timer_irq_t irq =
126 (dif_aon_timer_irq_t)(plic_irq_id -
134 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
136 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
142 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
144 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
148 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
152void isr_testutils_csrng_isr(
155 dif_csrng_irq_t *irq_serviced) {
160 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
164 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
167 dif_csrng_irq_t irq =
174 CHECK_DIF_OK(dif_csrng_irq_get_state(csrng_ctx.
csrng, &snapshot));
176 "Only csrng IRQ %d expected to fire. Actual IRQ state = %x", irq,
182 CHECK_DIF_OK(dif_csrng_irq_get_type(csrng_ctx.
csrng, irq, &type));
184 CHECK_DIF_OK(dif_csrng_irq_acknowledge(csrng_ctx.
csrng, irq));
188 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
194 dif_edn_irq_t *irq_serviced) {
199 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
203 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
213 CHECK_DIF_OK(dif_edn_irq_get_state(edn_ctx.
edn, &snapshot));
215 "Only edn IRQ %d expected to fire. Actual IRQ state = %x", irq,
221 CHECK_DIF_OK(dif_edn_irq_get_type(edn_ctx.
edn, irq, &type));
223 CHECK_DIF_OK(dif_edn_irq_acknowledge(edn_ctx.
edn, irq));
227 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
231void isr_testutils_entropy_src_isr(
234 dif_entropy_src_irq_t *irq_serviced) {
239 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
243 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
246 dif_entropy_src_irq_t irq =
247 (dif_entropy_src_irq_t)(plic_irq_id -
255 dif_entropy_src_irq_get_state(entropy_src_ctx.
entropy_src, &snapshot));
257 "Only entropy_src IRQ %d expected to fire. Actual IRQ state = %x",
264 dif_entropy_src_irq_get_type(entropy_src_ctx.
entropy_src, irq, &type));
267 dif_entropy_src_irq_acknowledge(entropy_src_ctx.
entropy_src, irq));
271 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
275void isr_testutils_flash_ctrl_isr(
278 dif_flash_ctrl_irq_t *irq_serviced) {
283 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
287 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
290 dif_flash_ctrl_irq_t irq =
291 (dif_flash_ctrl_irq_t)(plic_irq_id -
299 dif_flash_ctrl_irq_get_state(flash_ctrl_ctx.
flash_ctrl, &snapshot));
301 "Only flash_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
308 dif_flash_ctrl_irq_get_type(flash_ctrl_ctx.
flash_ctrl, irq, &type));
311 dif_flash_ctrl_irq_acknowledge(flash_ctrl_ctx.
flash_ctrl, irq));
312 }
else if (mute_status_irq) {
313 CHECK_DIF_OK(dif_flash_ctrl_irq_set_enabled(flash_ctrl_ctx.
flash_ctrl, irq,
318 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
324 dif_gpio_irq_t *irq_serviced) {
329 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
333 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
343 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
345 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
351 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
353 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
357 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
362 bool mute_status_irq,
364 dif_hmac_irq_t *irq_serviced) {
369 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
373 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
383 CHECK_DIF_OK(dif_hmac_irq_get_state(hmac_ctx.
hmac, &snapshot));
385 "Only hmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
391 CHECK_DIF_OK(dif_hmac_irq_get_type(hmac_ctx.
hmac, irq, &type));
393 CHECK_DIF_OK(dif_hmac_irq_acknowledge(hmac_ctx.
hmac, irq));
394 }
else if (mute_status_irq) {
400 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
405 bool mute_status_irq,
407 dif_i2c_irq_t *irq_serviced) {
412 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
416 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
426 CHECK_DIF_OK(dif_i2c_irq_get_state(i2c_ctx.
i2c, &snapshot));
428 "Only i2c IRQ %d expected to fire. Actual IRQ state = %x", irq,
434 CHECK_DIF_OK(dif_i2c_irq_get_type(i2c_ctx.
i2c, irq, &type));
436 CHECK_DIF_OK(dif_i2c_irq_acknowledge(i2c_ctx.
i2c, irq));
437 }
else if (mute_status_irq) {
442 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
446void isr_testutils_keymgr_isr(
449 dif_keymgr_irq_t *irq_serviced) {
454 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
458 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
461 dif_keymgr_irq_t irq =
468 CHECK_DIF_OK(dif_keymgr_irq_get_state(keymgr_ctx.
keymgr, &snapshot));
470 "Only keymgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
476 CHECK_DIF_OK(dif_keymgr_irq_get_type(keymgr_ctx.
keymgr, irq, &type));
478 CHECK_DIF_OK(dif_keymgr_irq_acknowledge(keymgr_ctx.
keymgr, irq));
482 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
487 bool mute_status_irq,
489 dif_kmac_irq_t *irq_serviced) {
494 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
498 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
508 CHECK_DIF_OK(dif_kmac_irq_get_state(kmac_ctx.
kmac, &snapshot));
510 "Only kmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
516 CHECK_DIF_OK(dif_kmac_irq_get_type(kmac_ctx.
kmac, irq, &type));
518 CHECK_DIF_OK(dif_kmac_irq_acknowledge(kmac_ctx.
kmac, irq));
519 }
else if (mute_status_irq) {
525 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
531 dif_otbn_irq_t *irq_serviced) {
536 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
540 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
550 CHECK_DIF_OK(dif_otbn_irq_get_state(otbn_ctx.
otbn, &snapshot));
552 "Only otbn IRQ %d expected to fire. Actual IRQ state = %x", irq,
558 CHECK_DIF_OK(dif_otbn_irq_get_type(otbn_ctx.
otbn, irq, &type));
560 CHECK_DIF_OK(dif_otbn_irq_acknowledge(otbn_ctx.
otbn, irq));
564 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
568void isr_testutils_otp_ctrl_isr(
571 dif_otp_ctrl_irq_t *irq_serviced) {
576 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
580 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
583 dif_otp_ctrl_irq_t irq =
584 (dif_otp_ctrl_irq_t)(plic_irq_id -
591 CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(otp_ctrl_ctx.
otp_ctrl, &snapshot));
593 "Only otp_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
599 CHECK_DIF_OK(dif_otp_ctrl_irq_get_type(otp_ctrl_ctx.
otp_ctrl, irq, &type));
601 CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(otp_ctrl_ctx.
otp_ctrl, irq));
605 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
609void isr_testutils_pattgen_isr(
612 dif_pattgen_irq_t *irq_serviced) {
617 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
621 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
624 dif_pattgen_irq_t irq =
631 CHECK_DIF_OK(dif_pattgen_irq_get_state(pattgen_ctx.
pattgen, &snapshot));
633 "Only pattgen IRQ %d expected to fire. Actual IRQ state = %x", irq,
639 CHECK_DIF_OK(dif_pattgen_irq_get_type(pattgen_ctx.
pattgen, irq, &type));
641 CHECK_DIF_OK(dif_pattgen_irq_acknowledge(pattgen_ctx.
pattgen, irq));
645 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
649void isr_testutils_pwrmgr_isr(
652 dif_pwrmgr_irq_t *irq_serviced) {
657 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
661 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
664 dif_pwrmgr_irq_t irq =
671 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
673 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
679 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
681 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
685 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
689void isr_testutils_rv_timer_isr(
692 dif_rv_timer_irq_t *irq_serviced) {
697 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
701 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
704 dif_rv_timer_irq_t irq =
705 (dif_rv_timer_irq_t)(plic_irq_id -
712 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
715 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
721 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
723 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
727 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
731void isr_testutils_sensor_ctrl_isr(
734 dif_sensor_ctrl_irq_t *irq_serviced) {
739 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
743 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
746 dif_sensor_ctrl_irq_t irq =
747 (dif_sensor_ctrl_irq_t)(plic_irq_id -
755 dif_sensor_ctrl_irq_get_state(sensor_ctrl_ctx.
sensor_ctrl, &snapshot));
757 "Only sensor_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
764 dif_sensor_ctrl_irq_get_type(sensor_ctrl_ctx.
sensor_ctrl, irq, &type));
767 dif_sensor_ctrl_irq_acknowledge(sensor_ctrl_ctx.
sensor_ctrl, irq));
771 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
775void isr_testutils_spi_device_isr(
778 dif_spi_device_irq_t *irq_serviced) {
783 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
787 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
790 dif_spi_device_irq_t irq =
791 (dif_spi_device_irq_t)(plic_irq_id -
799 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
801 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
808 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
811 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
812 }
else if (mute_status_irq) {
813 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
818 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
822void isr_testutils_spi_host_isr(
825 dif_spi_host_irq_t *irq_serviced) {
830 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
834 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
837 dif_spi_host_irq_t irq =
838 (dif_spi_host_irq_t)(plic_irq_id -
845 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
847 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
853 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
855 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
856 }
else if (mute_status_irq) {
857 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
862 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
866void isr_testutils_sysrst_ctrl_isr(
869 dif_sysrst_ctrl_irq_t *irq_serviced) {
874 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
878 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
881 dif_sysrst_ctrl_irq_t irq =
882 (dif_sysrst_ctrl_irq_t)(plic_irq_id -
890 dif_sysrst_ctrl_irq_get_state(sysrst_ctrl_ctx.
sysrst_ctrl, &snapshot));
892 "Only sysrst_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
899 dif_sysrst_ctrl_irq_get_type(sysrst_ctrl_ctx.
sysrst_ctrl, irq, &type));
902 dif_sysrst_ctrl_irq_acknowledge(sysrst_ctrl_ctx.
sysrst_ctrl, irq));
903 }
else if (mute_status_irq) {
904 CHECK_DIF_OK(dif_sysrst_ctrl_irq_set_enabled(sysrst_ctrl_ctx.
sysrst_ctrl,
909 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
914 bool mute_status_irq,
916 dif_uart_irq_t *irq_serviced) {
921 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
925 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
935 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
937 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
943 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
945 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
946 }
else if (mute_status_irq) {
952 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
956void isr_testutils_usbdev_isr(
959 dif_usbdev_irq_t *irq_serviced) {
964 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
968 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
971 dif_usbdev_irq_t irq =
978 CHECK_DIF_OK(dif_usbdev_irq_get_state(usbdev_ctx.
usbdev, &snapshot));
980 "Only usbdev IRQ %d expected to fire. Actual IRQ state = %x", irq,
986 CHECK_DIF_OK(dif_usbdev_irq_get_type(usbdev_ctx.
usbdev, irq, &type));
988 CHECK_DIF_OK(dif_usbdev_irq_acknowledge(usbdev_ctx.
usbdev, irq));
989 }
else if (mute_status_irq) {
995 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,