15void isr_testutils_adc_ctrl_isr(
18 dif_adc_ctrl_irq_t *irq_serviced) {
23 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
27 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
30 dif_adc_ctrl_irq_t irq =
31 (dif_adc_ctrl_irq_t)(plic_irq_id -
38 CHECK_DIF_OK(dif_adc_ctrl_irq_get_state(adc_ctrl_ctx.
adc_ctrl, &snapshot));
40 "Only adc_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
47 CHECK_DIF_OK(dif_adc_ctrl_irq_clear_causes(adc_ctrl_ctx.
adc_ctrl,
52 CHECK_DIF_OK(dif_adc_ctrl_irq_get_type(adc_ctrl_ctx.
adc_ctrl, irq, &type));
54 CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge(adc_ctrl_ctx.
adc_ctrl, irq));
55 }
else if (mute_status_irq) {
56 CHECK_DIF_OK(dif_adc_ctrl_irq_set_enabled(adc_ctrl_ctx.
adc_ctrl, irq,
61 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
65void isr_testutils_alert_handler_isr(
68 dif_alert_handler_irq_t *irq_serviced) {
73 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
77 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
80 dif_alert_handler_irq_t irq =
81 (dif_alert_handler_irq_t)(plic_irq_id -
83 .plic_alert_handler_start_irq_id);
89 CHECK_DIF_OK(dif_alert_handler_irq_get_state(
92 "Only alert_handler IRQ %d expected to fire. Actual IRQ state = %x",
98 CHECK_DIF_OK(dif_alert_handler_irq_get_type(alert_handler_ctx.
alert_handler,
101 CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(
106 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
110void isr_testutils_aon_timer_isr(
113 dif_aon_timer_irq_t *irq_serviced) {
118 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
122 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
125 dif_aon_timer_irq_t irq =
126 (dif_aon_timer_irq_t)(plic_irq_id -
134 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
136 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
142 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
144 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
148 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
152void isr_testutils_cheriot_mem_sys_isr(
155 dif_cheriot_mem_sys_irq_t *irq_serviced) {
160 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
164 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
167 dif_cheriot_mem_sys_irq_t irq =
168 (dif_cheriot_mem_sys_irq_t)(plic_irq_id -
170 .plic_cheriot_mem_sys_start_irq_id);
176 CHECK_DIF_OK(dif_cheriot_mem_sys_irq_get_state(
179 "Only cheriot_mem_sys IRQ %d expected to fire. Actual IRQ state = %x",
185 CHECK_DIF_OK(dif_cheriot_mem_sys_irq_get_type(
188 CHECK_DIF_OK(dif_cheriot_mem_sys_irq_acknowledge(
193 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
197void isr_testutils_csrng_isr(
200 dif_csrng_irq_t *irq_serviced) {
205 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
209 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
212 dif_csrng_irq_t irq =
219 CHECK_DIF_OK(dif_csrng_irq_get_state(csrng_ctx.
csrng, &snapshot));
221 "Only csrng IRQ %d expected to fire. Actual IRQ state = %x", irq,
227 CHECK_DIF_OK(dif_csrng_irq_get_type(csrng_ctx.
csrng, irq, &type));
229 CHECK_DIF_OK(dif_csrng_irq_acknowledge(csrng_ctx.
csrng, irq));
233 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
239 dif_edn_irq_t *irq_serviced) {
244 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
248 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
258 CHECK_DIF_OK(dif_edn_irq_get_state(edn_ctx.
edn, &snapshot));
260 "Only edn IRQ %d expected to fire. Actual IRQ state = %x", irq,
266 CHECK_DIF_OK(dif_edn_irq_get_type(edn_ctx.
edn, irq, &type));
268 CHECK_DIF_OK(dif_edn_irq_acknowledge(edn_ctx.
edn, irq));
272 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
276void isr_testutils_entropy_src_isr(
279 dif_entropy_src_irq_t *irq_serviced) {
284 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
288 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
291 dif_entropy_src_irq_t irq =
292 (dif_entropy_src_irq_t)(plic_irq_id -
300 dif_entropy_src_irq_get_state(entropy_src_ctx.
entropy_src, &snapshot));
302 "Only entropy_src IRQ %d expected to fire. Actual IRQ state = %x",
309 dif_entropy_src_irq_get_type(entropy_src_ctx.
entropy_src, irq, &type));
312 dif_entropy_src_irq_acknowledge(entropy_src_ctx.
entropy_src, irq));
316 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
322 dif_gpio_irq_t *irq_serviced) {
327 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
331 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
341 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
343 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
349 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
351 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
355 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
360 bool mute_status_irq,
362 dif_hmac_irq_t *irq_serviced) {
367 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
371 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
381 CHECK_DIF_OK(dif_hmac_irq_get_state(hmac_ctx.
hmac, &snapshot));
383 "Only hmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
389 CHECK_DIF_OK(dif_hmac_irq_get_type(hmac_ctx.
hmac, irq, &type));
391 CHECK_DIF_OK(dif_hmac_irq_acknowledge(hmac_ctx.
hmac, irq));
392 }
else if (mute_status_irq) {
398 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
403 bool mute_status_irq,
405 dif_i2c_irq_t *irq_serviced) {
410 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
414 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
424 CHECK_DIF_OK(dif_i2c_irq_get_state(i2c_ctx.
i2c, &snapshot));
426 "Only i2c IRQ %d expected to fire. Actual IRQ state = %x", irq,
432 CHECK_DIF_OK(dif_i2c_irq_get_type(i2c_ctx.
i2c, irq, &type));
434 CHECK_DIF_OK(dif_i2c_irq_acknowledge(i2c_ctx.
i2c, irq));
435 }
else if (mute_status_irq) {
440 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
445 bool mute_status_irq,
447 dif_i3c_irq_t *irq_serviced) {
452 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
456 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
466 CHECK_DIF_OK(dif_i3c_irq_get_state(i3c_ctx.
i3c, &snapshot));
468 "Only i3c IRQ %d expected to fire. Actual IRQ state = %x", irq,
474 CHECK_DIF_OK(dif_i3c_irq_get_type(i3c_ctx.
i3c, irq, &type));
476 CHECK_DIF_OK(dif_i3c_irq_acknowledge(i3c_ctx.
i3c, irq));
477 }
else if (mute_status_irq) {
482 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
486void isr_testutils_keymgr_dpe_isr(
489 dif_keymgr_dpe_irq_t *irq_serviced) {
494 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
498 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
501 dif_keymgr_dpe_irq_t irq =
502 (dif_keymgr_dpe_irq_t)(plic_irq_id -
510 dif_keymgr_dpe_irq_get_state(keymgr_dpe_ctx.
keymgr_dpe, &snapshot));
512 "Only keymgr_dpe IRQ %d expected to fire. Actual IRQ state = %x", irq,
519 dif_keymgr_dpe_irq_get_type(keymgr_dpe_ctx.
keymgr_dpe, irq, &type));
522 dif_keymgr_dpe_irq_acknowledge(keymgr_dpe_ctx.
keymgr_dpe, irq));
526 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
531 bool mute_status_irq,
533 dif_kmac_irq_t *irq_serviced) {
538 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
542 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
552 CHECK_DIF_OK(dif_kmac_irq_get_state(kmac_ctx.
kmac, &snapshot));
554 "Only kmac IRQ %d expected to fire. Actual IRQ state = %x", irq,
560 CHECK_DIF_OK(dif_kmac_irq_get_type(kmac_ctx.
kmac, irq, &type));
562 CHECK_DIF_OK(dif_kmac_irq_acknowledge(kmac_ctx.
kmac, irq));
563 }
else if (mute_status_irq) {
569 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
575 dif_otbn_irq_t *irq_serviced) {
580 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
584 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
594 CHECK_DIF_OK(dif_otbn_irq_get_state(otbn_ctx.
otbn, &snapshot));
596 "Only otbn IRQ %d expected to fire. Actual IRQ state = %x", irq,
602 CHECK_DIF_OK(dif_otbn_irq_get_type(otbn_ctx.
otbn, irq, &type));
604 CHECK_DIF_OK(dif_otbn_irq_acknowledge(otbn_ctx.
otbn, irq));
608 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
612void isr_testutils_otp_ctrl_isr(
615 dif_otp_ctrl_irq_t *irq_serviced) {
620 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
624 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
627 dif_otp_ctrl_irq_t irq =
628 (dif_otp_ctrl_irq_t)(plic_irq_id -
635 CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(otp_ctrl_ctx.
otp_ctrl, &snapshot));
637 "Only otp_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
643 CHECK_DIF_OK(dif_otp_ctrl_irq_get_type(otp_ctrl_ctx.
otp_ctrl, irq, &type));
645 CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(otp_ctrl_ctx.
otp_ctrl, irq));
649 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
653void isr_testutils_pwrmgr_isr(
656 dif_pwrmgr_irq_t *irq_serviced) {
661 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
665 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
668 dif_pwrmgr_irq_t irq =
675 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
677 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
683 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
685 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
689 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
693void isr_testutils_rram_ctrl_isr(
696 dif_rram_ctrl_irq_t *irq_serviced) {
701 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
705 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
708 dif_rram_ctrl_irq_t irq =
709 (dif_rram_ctrl_irq_t)(plic_irq_id -
717 dif_rram_ctrl_irq_get_state(rram_ctrl_ctx.
rram_ctrl, &snapshot));
719 "Only rram_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
725 CHECK_DIF_OK(dif_rram_ctrl_irq_get_type(rram_ctrl_ctx.
rram_ctrl, irq, &type));
727 CHECK_DIF_OK(dif_rram_ctrl_irq_acknowledge(rram_ctrl_ctx.
rram_ctrl, irq));
728 }
else if (mute_status_irq) {
729 CHECK_DIF_OK(dif_rram_ctrl_irq_set_enabled(rram_ctrl_ctx.
rram_ctrl, irq,
734 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
738void isr_testutils_rv_timer_isr(
741 dif_rv_timer_irq_t *irq_serviced) {
746 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
750 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
753 dif_rv_timer_irq_t irq =
754 (dif_rv_timer_irq_t)(plic_irq_id -
761 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
764 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
770 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
772 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
776 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
780void isr_testutils_sensor_ctrl_isr(
783 dif_sensor_ctrl_irq_t *irq_serviced) {
788 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
792 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
795 dif_sensor_ctrl_irq_t irq =
796 (dif_sensor_ctrl_irq_t)(plic_irq_id -
804 dif_sensor_ctrl_irq_get_state(sensor_ctrl_ctx.
sensor_ctrl, &snapshot));
806 "Only sensor_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
813 dif_sensor_ctrl_irq_get_type(sensor_ctrl_ctx.
sensor_ctrl, irq, &type));
816 dif_sensor_ctrl_irq_acknowledge(sensor_ctrl_ctx.
sensor_ctrl, irq));
820 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
824void isr_testutils_spi_device_isr(
827 dif_spi_device_irq_t *irq_serviced) {
832 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
836 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
839 dif_spi_device_irq_t irq =
840 (dif_spi_device_irq_t)(plic_irq_id -
848 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
850 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
857 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
860 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
861 }
else if (mute_status_irq) {
862 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
867 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
871void isr_testutils_spi_host_isr(
874 dif_spi_host_irq_t *irq_serviced) {
879 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
883 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
886 dif_spi_host_irq_t irq =
887 (dif_spi_host_irq_t)(plic_irq_id -
894 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
896 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
902 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
904 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
905 }
else if (mute_status_irq) {
906 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
911 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
915void isr_testutils_sysrst_ctrl_isr(
918 dif_sysrst_ctrl_irq_t *irq_serviced) {
923 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
927 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
930 dif_sysrst_ctrl_irq_t irq =
931 (dif_sysrst_ctrl_irq_t)(plic_irq_id -
939 dif_sysrst_ctrl_irq_get_state(sysrst_ctrl_ctx.
sysrst_ctrl, &snapshot));
941 "Only sysrst_ctrl IRQ %d expected to fire. Actual IRQ state = %x",
948 dif_sysrst_ctrl_irq_get_type(sysrst_ctrl_ctx.
sysrst_ctrl, irq, &type));
951 dif_sysrst_ctrl_irq_acknowledge(sysrst_ctrl_ctx.
sysrst_ctrl, irq));
952 }
else if (mute_status_irq) {
953 CHECK_DIF_OK(dif_sysrst_ctrl_irq_set_enabled(sysrst_ctrl_ctx.
sysrst_ctrl,
958 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
963 bool mute_status_irq,
965 dif_uart_irq_t *irq_serviced) {
970 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
974 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
984 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
986 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
992 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
994 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
995 }
else if (mute_status_irq) {
1001 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
1005void isr_testutils_usbdev_isr(
1008 dif_usbdev_irq_t *irq_serviced) {
1013 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
1017 top_earlgrey_plic_interrupt_for_peripheral[plic_irq_id];
1020 dif_usbdev_irq_t irq =
1022 *irq_serviced = irq;
1027 CHECK_DIF_OK(dif_usbdev_irq_get_state(usbdev_ctx.
usbdev, &snapshot));
1029 "Only usbdev IRQ %d expected to fire. Actual IRQ state = %x", irq,
1035 CHECK_DIF_OK(dif_usbdev_irq_get_type(usbdev_ctx.
usbdev, irq, &type));
1037 CHECK_DIF_OK(dif_usbdev_irq_acknowledge(usbdev_ctx.
usbdev, irq));
1038 }
else if (mute_status_irq) {
1044 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,