spi_device_regs.h File Reference

Generated register defines for spi_device. More...

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Macros
#define	SPI_DEVICE_PARAM_SRAM_DEPTH   1024
#define	SPI_DEVICE_PARAM_SRAM_EGRESS_DEPTH   848
#define	SPI_DEVICE_PARAM_SRAM_INGRESS_DEPTH   112
#define	SPI_DEVICE_PARAM_SRAM_READ_BUFFER_OFFSET   0
#define	SPI_DEVICE_PARAM_SRAM_READ_BUFFER_DEPTH   512
#define	SPI_DEVICE_PARAM_SRAM_MAILBOX_OFFSET   512
#define	SPI_DEVICE_PARAM_SRAM_MAILBOX_DEPTH   256
#define	SPI_DEVICE_PARAM_SRAM_SFDP_OFFSET   768
#define	SPI_DEVICE_PARAM_SRAM_SFDP_DEPTH   64
#define	SPI_DEVICE_PARAM_SRAM_TPM_RD_FIFO_OFFSET   832
#define	SPI_DEVICE_PARAM_SRAM_TPM_RD_FIFO_DEPTH   16
#define	SPI_DEVICE_PARAM_SRAM_PAYLOAD_OFFSET   0
#define	SPI_DEVICE_PARAM_SRAM_PAYLOAD_DEPTH   64
#define	SPI_DEVICE_PARAM_SRAM_CMD_FIFO_OFFSET   64
#define	SPI_DEVICE_PARAM_SRAM_CMD_FIFO_DEPTH   16
#define	SPI_DEVICE_PARAM_SRAM_ADDR_FIFO_OFFSET   80
#define	SPI_DEVICE_PARAM_SRAM_ADDR_FIFO_DEPTH   16
#define	SPI_DEVICE_PARAM_SRAM_TPM_WR_FIFO_OFFSET   96
#define	SPI_DEVICE_PARAM_SRAM_TPM_WR_FIFO_DEPTH   16
#define	SPI_DEVICE_PARAM_NUM_CMD_INFO   24
#define	SPI_DEVICE_PARAM_NUM_LOCALITY   5
#define	SPI_DEVICE_PARAM_TPM_RD_FIFO_PTR_W   5
#define	SPI_DEVICE_PARAM_TPM_RD_FIFO_WIDTH   32
#define	SPI_DEVICE_PARAM_NUM_ALERTS   1
#define	SPI_DEVICE_PARAM_REG_WIDTH   32
#define	SPI_DEVICE_INTR_COMMON_UPLOAD_CMDFIFO_NOT_EMPTY_BIT   0
#define	SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_NOT_EMPTY_BIT   1
#define	SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_OVERFLOW_BIT   2
#define	SPI_DEVICE_INTR_COMMON_READBUF_WATERMARK_BIT   3
#define	SPI_DEVICE_INTR_COMMON_READBUF_FLIP_BIT   4
#define	SPI_DEVICE_INTR_COMMON_TPM_HEADER_NOT_EMPTY_BIT   5
#define	SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_CMD_END_BIT   6
#define	SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_DROP_BIT   7
#define	SPI_DEVICE_INTR_STATE_REG_OFFSET   0x0
#define	SPI_DEVICE_INTR_STATE_REG_RESVAL   0x0u
#define	SPI_DEVICE_INTR_STATE_UPLOAD_CMDFIFO_NOT_EMPTY_BIT   0
#define	SPI_DEVICE_INTR_STATE_UPLOAD_PAYLOAD_NOT_EMPTY_BIT   1
#define	SPI_DEVICE_INTR_STATE_UPLOAD_PAYLOAD_OVERFLOW_BIT   2
#define	SPI_DEVICE_INTR_STATE_READBUF_WATERMARK_BIT   3
#define	SPI_DEVICE_INTR_STATE_READBUF_FLIP_BIT   4
#define	SPI_DEVICE_INTR_STATE_TPM_HEADER_NOT_EMPTY_BIT   5
#define	SPI_DEVICE_INTR_STATE_TPM_RDFIFO_CMD_END_BIT   6
#define	SPI_DEVICE_INTR_STATE_TPM_RDFIFO_DROP_BIT   7
#define	SPI_DEVICE_INTR_ENABLE_REG_OFFSET   0x4
#define	SPI_DEVICE_INTR_ENABLE_REG_RESVAL   0x0u
#define	SPI_DEVICE_INTR_ENABLE_UPLOAD_CMDFIFO_NOT_EMPTY_BIT   0
#define	SPI_DEVICE_INTR_ENABLE_UPLOAD_PAYLOAD_NOT_EMPTY_BIT   1
#define	SPI_DEVICE_INTR_ENABLE_UPLOAD_PAYLOAD_OVERFLOW_BIT   2
#define	SPI_DEVICE_INTR_ENABLE_READBUF_WATERMARK_BIT   3
#define	SPI_DEVICE_INTR_ENABLE_READBUF_FLIP_BIT   4
#define	SPI_DEVICE_INTR_ENABLE_TPM_HEADER_NOT_EMPTY_BIT   5
#define	SPI_DEVICE_INTR_ENABLE_TPM_RDFIFO_CMD_END_BIT   6
#define	SPI_DEVICE_INTR_ENABLE_TPM_RDFIFO_DROP_BIT   7
#define	SPI_DEVICE_INTR_TEST_REG_OFFSET   0x8
#define	SPI_DEVICE_INTR_TEST_REG_RESVAL   0x0u
#define	SPI_DEVICE_INTR_TEST_UPLOAD_CMDFIFO_NOT_EMPTY_BIT   0
#define	SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_NOT_EMPTY_BIT   1
#define	SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_OVERFLOW_BIT   2
#define	SPI_DEVICE_INTR_TEST_READBUF_WATERMARK_BIT   3
#define	SPI_DEVICE_INTR_TEST_READBUF_FLIP_BIT   4
#define	SPI_DEVICE_INTR_TEST_TPM_HEADER_NOT_EMPTY_BIT   5
#define	SPI_DEVICE_INTR_TEST_TPM_RDFIFO_CMD_END_BIT   6
#define	SPI_DEVICE_INTR_TEST_TPM_RDFIFO_DROP_BIT   7
#define	SPI_DEVICE_ALERT_TEST_REG_OFFSET   0xc
#define	SPI_DEVICE_ALERT_TEST_REG_RESVAL   0x0u
#define	SPI_DEVICE_ALERT_TEST_FATAL_FAULT_BIT   0
#define	SPI_DEVICE_CONTROL_REG_OFFSET   0x10
#define	SPI_DEVICE_CONTROL_REG_RESVAL   0x10u
#define	SPI_DEVICE_CONTROL_FLASH_STATUS_FIFO_CLR_BIT   0
#define	SPI_DEVICE_CONTROL_FLASH_READ_BUFFER_CLR_BIT   1
#define	SPI_DEVICE_CONTROL_MODE_MASK   0x3u
#define	SPI_DEVICE_CONTROL_MODE_OFFSET   4
#define	SPI_DEVICE_CONTROL_MODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CONTROL_MODE_MASK, .index = SPI_DEVICE_CONTROL_MODE_OFFSET })
#define	SPI_DEVICE_CONTROL_MODE_VALUE_DISABLED   0x0
#define	SPI_DEVICE_CONTROL_MODE_VALUE_FLASHMODE   0x1
#define	SPI_DEVICE_CONTROL_MODE_VALUE_PASSTHROUGH   0x2
#define	SPI_DEVICE_CFG_REG_OFFSET   0x14
#define	SPI_DEVICE_CFG_REG_RESVAL   0x0u
#define	SPI_DEVICE_CFG_TX_ORDER_BIT   2
#define	SPI_DEVICE_CFG_RX_ORDER_BIT   3
#define	SPI_DEVICE_CFG_MAILBOX_EN_BIT   24
#define	SPI_DEVICE_STATUS_REG_OFFSET   0x18
#define	SPI_DEVICE_STATUS_REG_RESVAL   0x60u
#define	SPI_DEVICE_STATUS_CSB_BIT   5
#define	SPI_DEVICE_STATUS_TPM_CSB_BIT   6
#define	SPI_DEVICE_INTERCEPT_EN_REG_OFFSET   0x1c
#define	SPI_DEVICE_INTERCEPT_EN_REG_RESVAL   0x0u
#define	SPI_DEVICE_INTERCEPT_EN_STATUS_BIT   0
#define	SPI_DEVICE_INTERCEPT_EN_JEDEC_BIT   1
#define	SPI_DEVICE_INTERCEPT_EN_SFDP_BIT   2
#define	SPI_DEVICE_INTERCEPT_EN_MBX_BIT   3
#define	SPI_DEVICE_ADDR_MODE_REG_OFFSET   0x20
#define	SPI_DEVICE_ADDR_MODE_REG_RESVAL   0x0u
#define	SPI_DEVICE_ADDR_MODE_ADDR_4B_EN_BIT   0
#define	SPI_DEVICE_ADDR_MODE_PENDING_BIT   31
#define	SPI_DEVICE_LAST_READ_ADDR_REG_OFFSET   0x24
#define	SPI_DEVICE_LAST_READ_ADDR_REG_RESVAL   0x0u
#define	SPI_DEVICE_FLASH_STATUS_REG_OFFSET   0x28
#define	SPI_DEVICE_FLASH_STATUS_REG_RESVAL   0x0u
#define	SPI_DEVICE_FLASH_STATUS_BUSY_BIT   0
#define	SPI_DEVICE_FLASH_STATUS_WEL_BIT   1
#define	SPI_DEVICE_FLASH_STATUS_STATUS_MASK   0x3fffffu
#define	SPI_DEVICE_FLASH_STATUS_STATUS_OFFSET   2
#define	SPI_DEVICE_FLASH_STATUS_STATUS_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_FLASH_STATUS_STATUS_MASK, .index = SPI_DEVICE_FLASH_STATUS_STATUS_OFFSET })
#define	SPI_DEVICE_JEDEC_CC_REG_OFFSET   0x2c
#define	SPI_DEVICE_JEDEC_CC_REG_RESVAL   0x7fu
#define	SPI_DEVICE_JEDEC_CC_CC_MASK   0xffu
#define	SPI_DEVICE_JEDEC_CC_CC_OFFSET   0
#define	SPI_DEVICE_JEDEC_CC_CC_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_CC_CC_MASK, .index = SPI_DEVICE_JEDEC_CC_CC_OFFSET })
#define	SPI_DEVICE_JEDEC_CC_NUM_CC_MASK   0xffu
#define	SPI_DEVICE_JEDEC_CC_NUM_CC_OFFSET   8
#define	SPI_DEVICE_JEDEC_CC_NUM_CC_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_CC_NUM_CC_MASK, .index = SPI_DEVICE_JEDEC_CC_NUM_CC_OFFSET })
#define	SPI_DEVICE_JEDEC_ID_REG_OFFSET   0x30
#define	SPI_DEVICE_JEDEC_ID_REG_RESVAL   0x0u
#define	SPI_DEVICE_JEDEC_ID_ID_MASK   0xffffu
#define	SPI_DEVICE_JEDEC_ID_ID_OFFSET   0
#define	SPI_DEVICE_JEDEC_ID_ID_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_ID_ID_MASK, .index = SPI_DEVICE_JEDEC_ID_ID_OFFSET })
#define	SPI_DEVICE_JEDEC_ID_MF_MASK   0xffu
#define	SPI_DEVICE_JEDEC_ID_MF_OFFSET   16
#define	SPI_DEVICE_JEDEC_ID_MF_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_ID_MF_MASK, .index = SPI_DEVICE_JEDEC_ID_MF_OFFSET })
#define	SPI_DEVICE_READ_THRESHOLD_REG_OFFSET   0x34
#define	SPI_DEVICE_READ_THRESHOLD_REG_RESVAL   0x0u
#define	SPI_DEVICE_READ_THRESHOLD_THRESHOLD_MASK   0x3ffu
#define	SPI_DEVICE_READ_THRESHOLD_THRESHOLD_OFFSET   0
#define	SPI_DEVICE_READ_THRESHOLD_THRESHOLD_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_READ_THRESHOLD_THRESHOLD_MASK, .index = SPI_DEVICE_READ_THRESHOLD_THRESHOLD_OFFSET })
#define	SPI_DEVICE_MAILBOX_ADDR_REG_OFFSET   0x38
#define	SPI_DEVICE_MAILBOX_ADDR_REG_RESVAL   0x0u
#define	SPI_DEVICE_UPLOAD_STATUS_REG_OFFSET   0x3c
#define	SPI_DEVICE_UPLOAD_STATUS_REG_RESVAL   0x0u
#define	SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_MASK   0x1fu
#define	SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_OFFSET   0
#define	SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_MASK, .index = SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_OFFSET })
#define	SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_NOTEMPTY_BIT   7
#define	SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_MASK   0x1fu
#define	SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_OFFSET   8
#define	SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_MASK, .index = SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_OFFSET })
#define	SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_NOTEMPTY_BIT   15
#define	SPI_DEVICE_UPLOAD_STATUS2_REG_OFFSET   0x40
#define	SPI_DEVICE_UPLOAD_STATUS2_REG_RESVAL   0x0u
#define	SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_MASK   0x1ffu
#define	SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_OFFSET   0
#define	SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_MASK, .index = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_OFFSET })
#define	SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_MASK   0xffu
#define	SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_OFFSET   16
#define	SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_MASK, .index = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_OFFSET })
#define	SPI_DEVICE_UPLOAD_CMDFIFO_REG_OFFSET   0x44
#define	SPI_DEVICE_UPLOAD_CMDFIFO_REG_RESVAL   0x0u
#define	SPI_DEVICE_UPLOAD_CMDFIFO_DATA_MASK   0xffu
#define	SPI_DEVICE_UPLOAD_CMDFIFO_DATA_OFFSET   0
#define	SPI_DEVICE_UPLOAD_CMDFIFO_DATA_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_CMDFIFO_DATA_MASK, .index = SPI_DEVICE_UPLOAD_CMDFIFO_DATA_OFFSET })
#define	SPI_DEVICE_UPLOAD_CMDFIFO_BUSY_BIT   13
#define	SPI_DEVICE_UPLOAD_CMDFIFO_WEL_BIT   14
#define	SPI_DEVICE_UPLOAD_CMDFIFO_ADDR4B_MODE_BIT   15
#define	SPI_DEVICE_UPLOAD_ADDRFIFO_REG_OFFSET   0x48
#define	SPI_DEVICE_UPLOAD_ADDRFIFO_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_FILTER_FILTER_FIELD_WIDTH   1
#define	SPI_DEVICE_CMD_FILTER_MULTIREG_COUNT   8
#define	SPI_DEVICE_CMD_FILTER_0_REG_OFFSET   0x4c
#define	SPI_DEVICE_CMD_FILTER_0_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_0_BIT   0
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_1_BIT   1
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_2_BIT   2
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_3_BIT   3
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_4_BIT   4
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_5_BIT   5
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_6_BIT   6
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_7_BIT   7
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_8_BIT   8
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_9_BIT   9
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_10_BIT   10
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_11_BIT   11
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_12_BIT   12
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_13_BIT   13
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_14_BIT   14
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_15_BIT   15
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_16_BIT   16
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_17_BIT   17
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_18_BIT   18
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_19_BIT   19
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_20_BIT   20
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_21_BIT   21
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_22_BIT   22
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_23_BIT   23
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_24_BIT   24
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_25_BIT   25
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_26_BIT   26
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_27_BIT   27
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_28_BIT   28
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_29_BIT   29
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_30_BIT   30
#define	SPI_DEVICE_CMD_FILTER_0_FILTER_31_BIT   31
#define	SPI_DEVICE_CMD_FILTER_1_REG_OFFSET   0x50
#define	SPI_DEVICE_CMD_FILTER_1_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_32_BIT   0
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_33_BIT   1
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_34_BIT   2
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_35_BIT   3
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_36_BIT   4
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_37_BIT   5
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_38_BIT   6
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_39_BIT   7
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_40_BIT   8
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_41_BIT   9
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_42_BIT   10
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_43_BIT   11
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_44_BIT   12
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_45_BIT   13
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_46_BIT   14
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_47_BIT   15
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_48_BIT   16
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_49_BIT   17
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_50_BIT   18
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_51_BIT   19
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_52_BIT   20
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_53_BIT   21
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_54_BIT   22
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_55_BIT   23
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_56_BIT   24
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_57_BIT   25
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_58_BIT   26
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_59_BIT   27
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_60_BIT   28
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_61_BIT   29
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_62_BIT   30
#define	SPI_DEVICE_CMD_FILTER_1_FILTER_63_BIT   31
#define	SPI_DEVICE_CMD_FILTER_2_REG_OFFSET   0x54
#define	SPI_DEVICE_CMD_FILTER_2_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_64_BIT   0
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_65_BIT   1
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_66_BIT   2
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_67_BIT   3
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_68_BIT   4
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_69_BIT   5
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_70_BIT   6
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_71_BIT   7
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_72_BIT   8
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_73_BIT   9
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_74_BIT   10
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_75_BIT   11
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_76_BIT   12
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_77_BIT   13
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_78_BIT   14
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_79_BIT   15
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_80_BIT   16
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_81_BIT   17
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_82_BIT   18
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_83_BIT   19
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_84_BIT   20
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_85_BIT   21
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_86_BIT   22
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_87_BIT   23
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_88_BIT   24
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_89_BIT   25
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_90_BIT   26
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_91_BIT   27
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_92_BIT   28
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_93_BIT   29
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_94_BIT   30
#define	SPI_DEVICE_CMD_FILTER_2_FILTER_95_BIT   31
#define	SPI_DEVICE_CMD_FILTER_3_REG_OFFSET   0x58
#define	SPI_DEVICE_CMD_FILTER_3_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_96_BIT   0
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_97_BIT   1
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_98_BIT   2
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_99_BIT   3
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_100_BIT   4
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_101_BIT   5
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_102_BIT   6
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_103_BIT   7
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_104_BIT   8
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_105_BIT   9
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_106_BIT   10
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_107_BIT   11
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_108_BIT   12
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_109_BIT   13
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_110_BIT   14
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_111_BIT   15
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_112_BIT   16
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_113_BIT   17
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_114_BIT   18
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_115_BIT   19
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_116_BIT   20
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_117_BIT   21
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_118_BIT   22
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_119_BIT   23
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_120_BIT   24
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_121_BIT   25
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_122_BIT   26
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_123_BIT   27
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_124_BIT   28
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_125_BIT   29
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_126_BIT   30
#define	SPI_DEVICE_CMD_FILTER_3_FILTER_127_BIT   31
#define	SPI_DEVICE_CMD_FILTER_4_REG_OFFSET   0x5c
#define	SPI_DEVICE_CMD_FILTER_4_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_128_BIT   0
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_129_BIT   1
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_130_BIT   2
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_131_BIT   3
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_132_BIT   4
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_133_BIT   5
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_134_BIT   6
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_135_BIT   7
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_136_BIT   8
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_137_BIT   9
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_138_BIT   10
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_139_BIT   11
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_140_BIT   12
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_141_BIT   13
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_142_BIT   14
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_143_BIT   15
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_144_BIT   16
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_145_BIT   17
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_146_BIT   18
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_147_BIT   19
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_148_BIT   20
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_149_BIT   21
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_150_BIT   22
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_151_BIT   23
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_152_BIT   24
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_153_BIT   25
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_154_BIT   26
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_155_BIT   27
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_156_BIT   28
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_157_BIT   29
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_158_BIT   30
#define	SPI_DEVICE_CMD_FILTER_4_FILTER_159_BIT   31
#define	SPI_DEVICE_CMD_FILTER_5_REG_OFFSET   0x60
#define	SPI_DEVICE_CMD_FILTER_5_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_160_BIT   0
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_161_BIT   1
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_162_BIT   2
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_163_BIT   3
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_164_BIT   4
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_165_BIT   5
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_166_BIT   6
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_167_BIT   7
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_168_BIT   8
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_169_BIT   9
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_170_BIT   10
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_171_BIT   11
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_172_BIT   12
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_173_BIT   13
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_174_BIT   14
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_175_BIT   15
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_176_BIT   16
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_177_BIT   17
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_178_BIT   18
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_179_BIT   19
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_180_BIT   20
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_181_BIT   21
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_182_BIT   22
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_183_BIT   23
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_184_BIT   24
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_185_BIT   25
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_186_BIT   26
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_187_BIT   27
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_188_BIT   28
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_189_BIT   29
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_190_BIT   30
#define	SPI_DEVICE_CMD_FILTER_5_FILTER_191_BIT   31
#define	SPI_DEVICE_CMD_FILTER_6_REG_OFFSET   0x64
#define	SPI_DEVICE_CMD_FILTER_6_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_192_BIT   0
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_193_BIT   1
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_194_BIT   2
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_195_BIT   3
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_196_BIT   4
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_197_BIT   5
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_198_BIT   6
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_199_BIT   7
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_200_BIT   8
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_201_BIT   9
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_202_BIT   10
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_203_BIT   11
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_204_BIT   12
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_205_BIT   13
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_206_BIT   14
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_207_BIT   15
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_208_BIT   16
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_209_BIT   17
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_210_BIT   18
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_211_BIT   19
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_212_BIT   20
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_213_BIT   21
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_214_BIT   22
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_215_BIT   23
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_216_BIT   24
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_217_BIT   25
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_218_BIT   26
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_219_BIT   27
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_220_BIT   28
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_221_BIT   29
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_222_BIT   30
#define	SPI_DEVICE_CMD_FILTER_6_FILTER_223_BIT   31
#define	SPI_DEVICE_CMD_FILTER_7_REG_OFFSET   0x68
#define	SPI_DEVICE_CMD_FILTER_7_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_224_BIT   0
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_225_BIT   1
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_226_BIT   2
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_227_BIT   3
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_228_BIT   4
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_229_BIT   5
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_230_BIT   6
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_231_BIT   7
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_232_BIT   8
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_233_BIT   9
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_234_BIT   10
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_235_BIT   11
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_236_BIT   12
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_237_BIT   13
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_238_BIT   14
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_239_BIT   15
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_240_BIT   16
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_241_BIT   17
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_242_BIT   18
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_243_BIT   19
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_244_BIT   20
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_245_BIT   21
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_246_BIT   22
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_247_BIT   23
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_248_BIT   24
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_249_BIT   25
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_250_BIT   26
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_251_BIT   27
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_252_BIT   28
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_253_BIT   29
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_254_BIT   30
#define	SPI_DEVICE_CMD_FILTER_7_FILTER_255_BIT   31
#define	SPI_DEVICE_ADDR_SWAP_MASK_REG_OFFSET   0x6c
#define	SPI_DEVICE_ADDR_SWAP_MASK_REG_RESVAL   0x0u
#define	SPI_DEVICE_ADDR_SWAP_DATA_REG_OFFSET   0x70
#define	SPI_DEVICE_ADDR_SWAP_DATA_REG_RESVAL   0x0u
#define	SPI_DEVICE_PAYLOAD_SWAP_MASK_REG_OFFSET   0x74
#define	SPI_DEVICE_PAYLOAD_SWAP_MASK_REG_RESVAL   0x0u
#define	SPI_DEVICE_PAYLOAD_SWAP_DATA_REG_OFFSET   0x78
#define	SPI_DEVICE_PAYLOAD_SWAP_DATA_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_INFO_OPCODE_FIELD_WIDTH   8
#define	SPI_DEVICE_CMD_INFO_ADDR_MODE_FIELD_WIDTH   2
#define	SPI_DEVICE_CMD_INFO_ADDR_SWAP_EN_FIELD_WIDTH   1
#define	SPI_DEVICE_CMD_INFO_MBYTE_EN_FIELD_WIDTH   1
#define	SPI_DEVICE_CMD_INFO_DUMMY_SIZE_FIELD_WIDTH   3
#define	SPI_DEVICE_CMD_INFO_DUMMY_EN_FIELD_WIDTH   1
#define	SPI_DEVICE_CMD_INFO_PAYLOAD_EN_FIELD_WIDTH   4
#define	SPI_DEVICE_CMD_INFO_PAYLOAD_DIR_FIELD_WIDTH   1
#define	SPI_DEVICE_CMD_INFO_PAYLOAD_SWAP_EN_FIELD_WIDTH   1
#define	SPI_DEVICE_CMD_INFO_READ_PIPELINE_MODE_FIELD_WIDTH   2
#define	SPI_DEVICE_CMD_INFO_UPLOAD_FIELD_WIDTH   1
#define	SPI_DEVICE_CMD_INFO_BUSY_FIELD_WIDTH   1
#define	SPI_DEVICE_CMD_INFO_VALID_FIELD_WIDTH   1
#define	SPI_DEVICE_CMD_INFO_MULTIREG_COUNT   24
#define	SPI_DEVICE_CMD_INFO_0_REG_OFFSET   0x7c
#define	SPI_DEVICE_CMD_INFO_0_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_0_OPCODE_0_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_0_OPCODE_0_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_0_OPCODE_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_OPCODE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_OPCODE_0_OFFSET })
#define	SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_OFFSET })
#define	SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDRDISABLED   0x0
#define	SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDRCFG   0x1
#define	SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDR3B   0x2
#define	SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDR4B   0x3
#define	SPI_DEVICE_CMD_INFO_0_ADDR_SWAP_EN_0_BIT   10
#define	SPI_DEVICE_CMD_INFO_0_MBYTE_EN_0_BIT   11
#define	SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_OFFSET })
#define	SPI_DEVICE_CMD_INFO_0_DUMMY_EN_0_BIT   15
#define	SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_OFFSET })
#define	SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_BIT   20
#define	SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_VALUE_PAYLOADIN   0x0
#define	SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_VALUE_PAYLOADOUT   0x1
#define	SPI_DEVICE_CMD_INFO_0_PAYLOAD_SWAP_EN_0_BIT   21
#define	SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_OFFSET })
#define	SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_ZERO_STAGES   0x0
#define	SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_TWO_STAGES_HALF_CYCLE    0x1
#define	SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_TWO_STAGES_FULL_CYCLE    0x2
#define	SPI_DEVICE_CMD_INFO_0_UPLOAD_0_BIT   24
#define	SPI_DEVICE_CMD_INFO_0_BUSY_0_BIT   25
#define	SPI_DEVICE_CMD_INFO_0_VALID_0_BIT   31
#define	SPI_DEVICE_CMD_INFO_1_REG_OFFSET   0x80
#define	SPI_DEVICE_CMD_INFO_1_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_1_OPCODE_1_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_1_OPCODE_1_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_1_OPCODE_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_OPCODE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_OPCODE_1_OFFSET })
#define	SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_OFFSET })
#define	SPI_DEVICE_CMD_INFO_1_ADDR_SWAP_EN_1_BIT   10
#define	SPI_DEVICE_CMD_INFO_1_MBYTE_EN_1_BIT   11
#define	SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_OFFSET })
#define	SPI_DEVICE_CMD_INFO_1_DUMMY_EN_1_BIT   15
#define	SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_OFFSET })
#define	SPI_DEVICE_CMD_INFO_1_PAYLOAD_DIR_1_BIT   20
#define	SPI_DEVICE_CMD_INFO_1_PAYLOAD_SWAP_EN_1_BIT   21
#define	SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_OFFSET })
#define	SPI_DEVICE_CMD_INFO_1_UPLOAD_1_BIT   24
#define	SPI_DEVICE_CMD_INFO_1_BUSY_1_BIT   25
#define	SPI_DEVICE_CMD_INFO_1_VALID_1_BIT   31
#define	SPI_DEVICE_CMD_INFO_2_REG_OFFSET   0x84
#define	SPI_DEVICE_CMD_INFO_2_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_2_OPCODE_2_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_2_OPCODE_2_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_2_OPCODE_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_OPCODE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_OPCODE_2_OFFSET })
#define	SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_OFFSET })
#define	SPI_DEVICE_CMD_INFO_2_ADDR_SWAP_EN_2_BIT   10
#define	SPI_DEVICE_CMD_INFO_2_MBYTE_EN_2_BIT   11
#define	SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_OFFSET })
#define	SPI_DEVICE_CMD_INFO_2_DUMMY_EN_2_BIT   15
#define	SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_OFFSET })
#define	SPI_DEVICE_CMD_INFO_2_PAYLOAD_DIR_2_BIT   20
#define	SPI_DEVICE_CMD_INFO_2_PAYLOAD_SWAP_EN_2_BIT   21
#define	SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_OFFSET })
#define	SPI_DEVICE_CMD_INFO_2_UPLOAD_2_BIT   24
#define	SPI_DEVICE_CMD_INFO_2_BUSY_2_BIT   25
#define	SPI_DEVICE_CMD_INFO_2_VALID_2_BIT   31
#define	SPI_DEVICE_CMD_INFO_3_REG_OFFSET   0x88
#define	SPI_DEVICE_CMD_INFO_3_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_3_OPCODE_3_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_3_OPCODE_3_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_3_OPCODE_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_OPCODE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_OPCODE_3_OFFSET })
#define	SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_OFFSET })
#define	SPI_DEVICE_CMD_INFO_3_ADDR_SWAP_EN_3_BIT   10
#define	SPI_DEVICE_CMD_INFO_3_MBYTE_EN_3_BIT   11
#define	SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_OFFSET })
#define	SPI_DEVICE_CMD_INFO_3_DUMMY_EN_3_BIT   15
#define	SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_OFFSET })
#define	SPI_DEVICE_CMD_INFO_3_PAYLOAD_DIR_3_BIT   20
#define	SPI_DEVICE_CMD_INFO_3_PAYLOAD_SWAP_EN_3_BIT   21
#define	SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_OFFSET })
#define	SPI_DEVICE_CMD_INFO_3_UPLOAD_3_BIT   24
#define	SPI_DEVICE_CMD_INFO_3_BUSY_3_BIT   25
#define	SPI_DEVICE_CMD_INFO_3_VALID_3_BIT   31
#define	SPI_DEVICE_CMD_INFO_4_REG_OFFSET   0x8c
#define	SPI_DEVICE_CMD_INFO_4_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_4_OPCODE_4_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_4_OPCODE_4_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_4_OPCODE_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_OPCODE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_OPCODE_4_OFFSET })
#define	SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_OFFSET })
#define	SPI_DEVICE_CMD_INFO_4_ADDR_SWAP_EN_4_BIT   10
#define	SPI_DEVICE_CMD_INFO_4_MBYTE_EN_4_BIT   11
#define	SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_OFFSET })
#define	SPI_DEVICE_CMD_INFO_4_DUMMY_EN_4_BIT   15
#define	SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_OFFSET })
#define	SPI_DEVICE_CMD_INFO_4_PAYLOAD_DIR_4_BIT   20
#define	SPI_DEVICE_CMD_INFO_4_PAYLOAD_SWAP_EN_4_BIT   21
#define	SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_OFFSET })
#define	SPI_DEVICE_CMD_INFO_4_UPLOAD_4_BIT   24
#define	SPI_DEVICE_CMD_INFO_4_BUSY_4_BIT   25
#define	SPI_DEVICE_CMD_INFO_4_VALID_4_BIT   31
#define	SPI_DEVICE_CMD_INFO_5_REG_OFFSET   0x90
#define	SPI_DEVICE_CMD_INFO_5_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_5_OPCODE_5_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_5_OPCODE_5_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_5_OPCODE_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_OPCODE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_OPCODE_5_OFFSET })
#define	SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_OFFSET })
#define	SPI_DEVICE_CMD_INFO_5_ADDR_SWAP_EN_5_BIT   10
#define	SPI_DEVICE_CMD_INFO_5_MBYTE_EN_5_BIT   11
#define	SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_OFFSET })
#define	SPI_DEVICE_CMD_INFO_5_DUMMY_EN_5_BIT   15
#define	SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_OFFSET })
#define	SPI_DEVICE_CMD_INFO_5_PAYLOAD_DIR_5_BIT   20
#define	SPI_DEVICE_CMD_INFO_5_PAYLOAD_SWAP_EN_5_BIT   21
#define	SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_OFFSET })
#define	SPI_DEVICE_CMD_INFO_5_UPLOAD_5_BIT   24
#define	SPI_DEVICE_CMD_INFO_5_BUSY_5_BIT   25
#define	SPI_DEVICE_CMD_INFO_5_VALID_5_BIT   31
#define	SPI_DEVICE_CMD_INFO_6_REG_OFFSET   0x94
#define	SPI_DEVICE_CMD_INFO_6_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_6_OPCODE_6_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_6_OPCODE_6_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_6_OPCODE_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_OPCODE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_OPCODE_6_OFFSET })
#define	SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_OFFSET })
#define	SPI_DEVICE_CMD_INFO_6_ADDR_SWAP_EN_6_BIT   10
#define	SPI_DEVICE_CMD_INFO_6_MBYTE_EN_6_BIT   11
#define	SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_OFFSET })
#define	SPI_DEVICE_CMD_INFO_6_DUMMY_EN_6_BIT   15
#define	SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_OFFSET })
#define	SPI_DEVICE_CMD_INFO_6_PAYLOAD_DIR_6_BIT   20
#define	SPI_DEVICE_CMD_INFO_6_PAYLOAD_SWAP_EN_6_BIT   21
#define	SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_OFFSET })
#define	SPI_DEVICE_CMD_INFO_6_UPLOAD_6_BIT   24
#define	SPI_DEVICE_CMD_INFO_6_BUSY_6_BIT   25
#define	SPI_DEVICE_CMD_INFO_6_VALID_6_BIT   31
#define	SPI_DEVICE_CMD_INFO_7_REG_OFFSET   0x98
#define	SPI_DEVICE_CMD_INFO_7_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_7_OPCODE_7_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_7_OPCODE_7_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_7_OPCODE_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_OPCODE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_OPCODE_7_OFFSET })
#define	SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_OFFSET })
#define	SPI_DEVICE_CMD_INFO_7_ADDR_SWAP_EN_7_BIT   10
#define	SPI_DEVICE_CMD_INFO_7_MBYTE_EN_7_BIT   11
#define	SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_OFFSET })
#define	SPI_DEVICE_CMD_INFO_7_DUMMY_EN_7_BIT   15
#define	SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_OFFSET })
#define	SPI_DEVICE_CMD_INFO_7_PAYLOAD_DIR_7_BIT   20
#define	SPI_DEVICE_CMD_INFO_7_PAYLOAD_SWAP_EN_7_BIT   21
#define	SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_OFFSET })
#define	SPI_DEVICE_CMD_INFO_7_UPLOAD_7_BIT   24
#define	SPI_DEVICE_CMD_INFO_7_BUSY_7_BIT   25
#define	SPI_DEVICE_CMD_INFO_7_VALID_7_BIT   31
#define	SPI_DEVICE_CMD_INFO_8_REG_OFFSET   0x9c
#define	SPI_DEVICE_CMD_INFO_8_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_8_OPCODE_8_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_8_OPCODE_8_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_8_OPCODE_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_OPCODE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_OPCODE_8_OFFSET })
#define	SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_OFFSET })
#define	SPI_DEVICE_CMD_INFO_8_ADDR_SWAP_EN_8_BIT   10
#define	SPI_DEVICE_CMD_INFO_8_MBYTE_EN_8_BIT   11
#define	SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_OFFSET })
#define	SPI_DEVICE_CMD_INFO_8_DUMMY_EN_8_BIT   15
#define	SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_OFFSET })
#define	SPI_DEVICE_CMD_INFO_8_PAYLOAD_DIR_8_BIT   20
#define	SPI_DEVICE_CMD_INFO_8_PAYLOAD_SWAP_EN_8_BIT   21
#define	SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_OFFSET })
#define	SPI_DEVICE_CMD_INFO_8_UPLOAD_8_BIT   24
#define	SPI_DEVICE_CMD_INFO_8_BUSY_8_BIT   25
#define	SPI_DEVICE_CMD_INFO_8_VALID_8_BIT   31
#define	SPI_DEVICE_CMD_INFO_9_REG_OFFSET   0xa0
#define	SPI_DEVICE_CMD_INFO_9_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_9_OPCODE_9_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_9_OPCODE_9_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_9_OPCODE_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_OPCODE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_OPCODE_9_OFFSET })
#define	SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_OFFSET })
#define	SPI_DEVICE_CMD_INFO_9_ADDR_SWAP_EN_9_BIT   10
#define	SPI_DEVICE_CMD_INFO_9_MBYTE_EN_9_BIT   11
#define	SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_OFFSET })
#define	SPI_DEVICE_CMD_INFO_9_DUMMY_EN_9_BIT   15
#define	SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_OFFSET })
#define	SPI_DEVICE_CMD_INFO_9_PAYLOAD_DIR_9_BIT   20
#define	SPI_DEVICE_CMD_INFO_9_PAYLOAD_SWAP_EN_9_BIT   21
#define	SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_OFFSET })
#define	SPI_DEVICE_CMD_INFO_9_UPLOAD_9_BIT   24
#define	SPI_DEVICE_CMD_INFO_9_BUSY_9_BIT   25
#define	SPI_DEVICE_CMD_INFO_9_VALID_9_BIT   31
#define	SPI_DEVICE_CMD_INFO_10_REG_OFFSET   0xa4
#define	SPI_DEVICE_CMD_INFO_10_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_10_OPCODE_10_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_10_OPCODE_10_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_10_OPCODE_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_OPCODE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_OPCODE_10_OFFSET })
#define	SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_OFFSET })
#define	SPI_DEVICE_CMD_INFO_10_ADDR_SWAP_EN_10_BIT   10
#define	SPI_DEVICE_CMD_INFO_10_MBYTE_EN_10_BIT   11
#define	SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_OFFSET })
#define	SPI_DEVICE_CMD_INFO_10_DUMMY_EN_10_BIT   15
#define	SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_OFFSET })
#define	SPI_DEVICE_CMD_INFO_10_PAYLOAD_DIR_10_BIT   20
#define	SPI_DEVICE_CMD_INFO_10_PAYLOAD_SWAP_EN_10_BIT   21
#define	SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_OFFSET })
#define	SPI_DEVICE_CMD_INFO_10_UPLOAD_10_BIT   24
#define	SPI_DEVICE_CMD_INFO_10_BUSY_10_BIT   25
#define	SPI_DEVICE_CMD_INFO_10_VALID_10_BIT   31
#define	SPI_DEVICE_CMD_INFO_11_REG_OFFSET   0xa8
#define	SPI_DEVICE_CMD_INFO_11_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_11_OPCODE_11_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_11_OPCODE_11_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_11_OPCODE_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_OPCODE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_OPCODE_11_OFFSET })
#define	SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_OFFSET })
#define	SPI_DEVICE_CMD_INFO_11_ADDR_SWAP_EN_11_BIT   10
#define	SPI_DEVICE_CMD_INFO_11_MBYTE_EN_11_BIT   11
#define	SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_OFFSET })
#define	SPI_DEVICE_CMD_INFO_11_DUMMY_EN_11_BIT   15
#define	SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_OFFSET })
#define	SPI_DEVICE_CMD_INFO_11_PAYLOAD_DIR_11_BIT   20
#define	SPI_DEVICE_CMD_INFO_11_PAYLOAD_SWAP_EN_11_BIT   21
#define	SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_OFFSET })
#define	SPI_DEVICE_CMD_INFO_11_UPLOAD_11_BIT   24
#define	SPI_DEVICE_CMD_INFO_11_BUSY_11_BIT   25
#define	SPI_DEVICE_CMD_INFO_11_VALID_11_BIT   31
#define	SPI_DEVICE_CMD_INFO_12_REG_OFFSET   0xac
#define	SPI_DEVICE_CMD_INFO_12_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_12_OPCODE_12_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_12_OPCODE_12_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_12_OPCODE_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_OPCODE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_OPCODE_12_OFFSET })
#define	SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_OFFSET })
#define	SPI_DEVICE_CMD_INFO_12_ADDR_SWAP_EN_12_BIT   10
#define	SPI_DEVICE_CMD_INFO_12_MBYTE_EN_12_BIT   11
#define	SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_OFFSET })
#define	SPI_DEVICE_CMD_INFO_12_DUMMY_EN_12_BIT   15
#define	SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_OFFSET })
#define	SPI_DEVICE_CMD_INFO_12_PAYLOAD_DIR_12_BIT   20
#define	SPI_DEVICE_CMD_INFO_12_PAYLOAD_SWAP_EN_12_BIT   21
#define	SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_OFFSET })
#define	SPI_DEVICE_CMD_INFO_12_UPLOAD_12_BIT   24
#define	SPI_DEVICE_CMD_INFO_12_BUSY_12_BIT   25
#define	SPI_DEVICE_CMD_INFO_12_VALID_12_BIT   31
#define	SPI_DEVICE_CMD_INFO_13_REG_OFFSET   0xb0
#define	SPI_DEVICE_CMD_INFO_13_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_13_OPCODE_13_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_13_OPCODE_13_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_13_OPCODE_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_OPCODE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_OPCODE_13_OFFSET })
#define	SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_OFFSET })
#define	SPI_DEVICE_CMD_INFO_13_ADDR_SWAP_EN_13_BIT   10
#define	SPI_DEVICE_CMD_INFO_13_MBYTE_EN_13_BIT   11
#define	SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_OFFSET })
#define	SPI_DEVICE_CMD_INFO_13_DUMMY_EN_13_BIT   15
#define	SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_OFFSET })
#define	SPI_DEVICE_CMD_INFO_13_PAYLOAD_DIR_13_BIT   20
#define	SPI_DEVICE_CMD_INFO_13_PAYLOAD_SWAP_EN_13_BIT   21
#define	SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_OFFSET })
#define	SPI_DEVICE_CMD_INFO_13_UPLOAD_13_BIT   24
#define	SPI_DEVICE_CMD_INFO_13_BUSY_13_BIT   25
#define	SPI_DEVICE_CMD_INFO_13_VALID_13_BIT   31
#define	SPI_DEVICE_CMD_INFO_14_REG_OFFSET   0xb4
#define	SPI_DEVICE_CMD_INFO_14_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_14_OPCODE_14_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_14_OPCODE_14_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_14_OPCODE_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_OPCODE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_OPCODE_14_OFFSET })
#define	SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_OFFSET })
#define	SPI_DEVICE_CMD_INFO_14_ADDR_SWAP_EN_14_BIT   10
#define	SPI_DEVICE_CMD_INFO_14_MBYTE_EN_14_BIT   11
#define	SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_OFFSET })
#define	SPI_DEVICE_CMD_INFO_14_DUMMY_EN_14_BIT   15
#define	SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_OFFSET })
#define	SPI_DEVICE_CMD_INFO_14_PAYLOAD_DIR_14_BIT   20
#define	SPI_DEVICE_CMD_INFO_14_PAYLOAD_SWAP_EN_14_BIT   21
#define	SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_OFFSET })
#define	SPI_DEVICE_CMD_INFO_14_UPLOAD_14_BIT   24
#define	SPI_DEVICE_CMD_INFO_14_BUSY_14_BIT   25
#define	SPI_DEVICE_CMD_INFO_14_VALID_14_BIT   31
#define	SPI_DEVICE_CMD_INFO_15_REG_OFFSET   0xb8
#define	SPI_DEVICE_CMD_INFO_15_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_15_OPCODE_15_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_15_OPCODE_15_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_15_OPCODE_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_OPCODE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_OPCODE_15_OFFSET })
#define	SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_OFFSET })
#define	SPI_DEVICE_CMD_INFO_15_ADDR_SWAP_EN_15_BIT   10
#define	SPI_DEVICE_CMD_INFO_15_MBYTE_EN_15_BIT   11
#define	SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_OFFSET })
#define	SPI_DEVICE_CMD_INFO_15_DUMMY_EN_15_BIT   15
#define	SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_OFFSET })
#define	SPI_DEVICE_CMD_INFO_15_PAYLOAD_DIR_15_BIT   20
#define	SPI_DEVICE_CMD_INFO_15_PAYLOAD_SWAP_EN_15_BIT   21
#define	SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_OFFSET })
#define	SPI_DEVICE_CMD_INFO_15_UPLOAD_15_BIT   24
#define	SPI_DEVICE_CMD_INFO_15_BUSY_15_BIT   25
#define	SPI_DEVICE_CMD_INFO_15_VALID_15_BIT   31
#define	SPI_DEVICE_CMD_INFO_16_REG_OFFSET   0xbc
#define	SPI_DEVICE_CMD_INFO_16_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_16_OPCODE_16_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_16_OPCODE_16_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_16_OPCODE_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_OPCODE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_OPCODE_16_OFFSET })
#define	SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_OFFSET })
#define	SPI_DEVICE_CMD_INFO_16_ADDR_SWAP_EN_16_BIT   10
#define	SPI_DEVICE_CMD_INFO_16_MBYTE_EN_16_BIT   11
#define	SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_OFFSET })
#define	SPI_DEVICE_CMD_INFO_16_DUMMY_EN_16_BIT   15
#define	SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_OFFSET })
#define	SPI_DEVICE_CMD_INFO_16_PAYLOAD_DIR_16_BIT   20
#define	SPI_DEVICE_CMD_INFO_16_PAYLOAD_SWAP_EN_16_BIT   21
#define	SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_OFFSET })
#define	SPI_DEVICE_CMD_INFO_16_UPLOAD_16_BIT   24
#define	SPI_DEVICE_CMD_INFO_16_BUSY_16_BIT   25
#define	SPI_DEVICE_CMD_INFO_16_VALID_16_BIT   31
#define	SPI_DEVICE_CMD_INFO_17_REG_OFFSET   0xc0
#define	SPI_DEVICE_CMD_INFO_17_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_17_OPCODE_17_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_17_OPCODE_17_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_17_OPCODE_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_OPCODE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_OPCODE_17_OFFSET })
#define	SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_OFFSET })
#define	SPI_DEVICE_CMD_INFO_17_ADDR_SWAP_EN_17_BIT   10
#define	SPI_DEVICE_CMD_INFO_17_MBYTE_EN_17_BIT   11
#define	SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_OFFSET })
#define	SPI_DEVICE_CMD_INFO_17_DUMMY_EN_17_BIT   15
#define	SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_OFFSET })
#define	SPI_DEVICE_CMD_INFO_17_PAYLOAD_DIR_17_BIT   20
#define	SPI_DEVICE_CMD_INFO_17_PAYLOAD_SWAP_EN_17_BIT   21
#define	SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_OFFSET })
#define	SPI_DEVICE_CMD_INFO_17_UPLOAD_17_BIT   24
#define	SPI_DEVICE_CMD_INFO_17_BUSY_17_BIT   25
#define	SPI_DEVICE_CMD_INFO_17_VALID_17_BIT   31
#define	SPI_DEVICE_CMD_INFO_18_REG_OFFSET   0xc4
#define	SPI_DEVICE_CMD_INFO_18_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_18_OPCODE_18_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_18_OPCODE_18_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_18_OPCODE_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_OPCODE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_OPCODE_18_OFFSET })
#define	SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_OFFSET })
#define	SPI_DEVICE_CMD_INFO_18_ADDR_SWAP_EN_18_BIT   10
#define	SPI_DEVICE_CMD_INFO_18_MBYTE_EN_18_BIT   11
#define	SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_OFFSET })
#define	SPI_DEVICE_CMD_INFO_18_DUMMY_EN_18_BIT   15
#define	SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_OFFSET })
#define	SPI_DEVICE_CMD_INFO_18_PAYLOAD_DIR_18_BIT   20
#define	SPI_DEVICE_CMD_INFO_18_PAYLOAD_SWAP_EN_18_BIT   21
#define	SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_OFFSET })
#define	SPI_DEVICE_CMD_INFO_18_UPLOAD_18_BIT   24
#define	SPI_DEVICE_CMD_INFO_18_BUSY_18_BIT   25
#define	SPI_DEVICE_CMD_INFO_18_VALID_18_BIT   31
#define	SPI_DEVICE_CMD_INFO_19_REG_OFFSET   0xc8
#define	SPI_DEVICE_CMD_INFO_19_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_19_OPCODE_19_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_19_OPCODE_19_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_19_OPCODE_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_OPCODE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_OPCODE_19_OFFSET })
#define	SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_OFFSET })
#define	SPI_DEVICE_CMD_INFO_19_ADDR_SWAP_EN_19_BIT   10
#define	SPI_DEVICE_CMD_INFO_19_MBYTE_EN_19_BIT   11
#define	SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_OFFSET })
#define	SPI_DEVICE_CMD_INFO_19_DUMMY_EN_19_BIT   15
#define	SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_OFFSET })
#define	SPI_DEVICE_CMD_INFO_19_PAYLOAD_DIR_19_BIT   20
#define	SPI_DEVICE_CMD_INFO_19_PAYLOAD_SWAP_EN_19_BIT   21
#define	SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_OFFSET })
#define	SPI_DEVICE_CMD_INFO_19_UPLOAD_19_BIT   24
#define	SPI_DEVICE_CMD_INFO_19_BUSY_19_BIT   25
#define	SPI_DEVICE_CMD_INFO_19_VALID_19_BIT   31
#define	SPI_DEVICE_CMD_INFO_20_REG_OFFSET   0xcc
#define	SPI_DEVICE_CMD_INFO_20_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_20_OPCODE_20_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_20_OPCODE_20_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_20_OPCODE_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_OPCODE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_OPCODE_20_OFFSET })
#define	SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_OFFSET })
#define	SPI_DEVICE_CMD_INFO_20_ADDR_SWAP_EN_20_BIT   10
#define	SPI_DEVICE_CMD_INFO_20_MBYTE_EN_20_BIT   11
#define	SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_OFFSET })
#define	SPI_DEVICE_CMD_INFO_20_DUMMY_EN_20_BIT   15
#define	SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_OFFSET })
#define	SPI_DEVICE_CMD_INFO_20_PAYLOAD_DIR_20_BIT   20
#define	SPI_DEVICE_CMD_INFO_20_PAYLOAD_SWAP_EN_20_BIT   21
#define	SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_OFFSET })
#define	SPI_DEVICE_CMD_INFO_20_UPLOAD_20_BIT   24
#define	SPI_DEVICE_CMD_INFO_20_BUSY_20_BIT   25
#define	SPI_DEVICE_CMD_INFO_20_VALID_20_BIT   31
#define	SPI_DEVICE_CMD_INFO_21_REG_OFFSET   0xd0
#define	SPI_DEVICE_CMD_INFO_21_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_21_OPCODE_21_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_21_OPCODE_21_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_21_OPCODE_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_OPCODE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_OPCODE_21_OFFSET })
#define	SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_OFFSET })
#define	SPI_DEVICE_CMD_INFO_21_ADDR_SWAP_EN_21_BIT   10
#define	SPI_DEVICE_CMD_INFO_21_MBYTE_EN_21_BIT   11
#define	SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_OFFSET })
#define	SPI_DEVICE_CMD_INFO_21_DUMMY_EN_21_BIT   15
#define	SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_OFFSET })
#define	SPI_DEVICE_CMD_INFO_21_PAYLOAD_DIR_21_BIT   20
#define	SPI_DEVICE_CMD_INFO_21_PAYLOAD_SWAP_EN_21_BIT   21
#define	SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_OFFSET })
#define	SPI_DEVICE_CMD_INFO_21_UPLOAD_21_BIT   24
#define	SPI_DEVICE_CMD_INFO_21_BUSY_21_BIT   25
#define	SPI_DEVICE_CMD_INFO_21_VALID_21_BIT   31
#define	SPI_DEVICE_CMD_INFO_22_REG_OFFSET   0xd4
#define	SPI_DEVICE_CMD_INFO_22_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_22_OPCODE_22_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_22_OPCODE_22_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_22_OPCODE_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_OPCODE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_OPCODE_22_OFFSET })
#define	SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_OFFSET })
#define	SPI_DEVICE_CMD_INFO_22_ADDR_SWAP_EN_22_BIT   10
#define	SPI_DEVICE_CMD_INFO_22_MBYTE_EN_22_BIT   11
#define	SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_OFFSET })
#define	SPI_DEVICE_CMD_INFO_22_DUMMY_EN_22_BIT   15
#define	SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_OFFSET })
#define	SPI_DEVICE_CMD_INFO_22_PAYLOAD_DIR_22_BIT   20
#define	SPI_DEVICE_CMD_INFO_22_PAYLOAD_SWAP_EN_22_BIT   21
#define	SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_OFFSET })
#define	SPI_DEVICE_CMD_INFO_22_UPLOAD_22_BIT   24
#define	SPI_DEVICE_CMD_INFO_22_BUSY_22_BIT   25
#define	SPI_DEVICE_CMD_INFO_22_VALID_22_BIT   31
#define	SPI_DEVICE_CMD_INFO_23_REG_OFFSET   0xd8
#define	SPI_DEVICE_CMD_INFO_23_REG_RESVAL   0x7000u
#define	SPI_DEVICE_CMD_INFO_23_OPCODE_23_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_23_OPCODE_23_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_23_OPCODE_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_OPCODE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_OPCODE_23_OFFSET })
#define	SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_OFFSET   8
#define	SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_OFFSET })
#define	SPI_DEVICE_CMD_INFO_23_ADDR_SWAP_EN_23_BIT   10
#define	SPI_DEVICE_CMD_INFO_23_MBYTE_EN_23_BIT   11
#define	SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_MASK   0x7u
#define	SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_OFFSET   12
#define	SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_OFFSET })
#define	SPI_DEVICE_CMD_INFO_23_DUMMY_EN_23_BIT   15
#define	SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_MASK   0xfu
#define	SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_OFFSET   16
#define	SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_OFFSET })
#define	SPI_DEVICE_CMD_INFO_23_PAYLOAD_DIR_23_BIT   20
#define	SPI_DEVICE_CMD_INFO_23_PAYLOAD_SWAP_EN_23_BIT   21
#define	SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_MASK   0x3u
#define	SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_OFFSET   22
#define	SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_OFFSET })
#define	SPI_DEVICE_CMD_INFO_23_UPLOAD_23_BIT   24
#define	SPI_DEVICE_CMD_INFO_23_BUSY_23_BIT   25
#define	SPI_DEVICE_CMD_INFO_23_VALID_23_BIT   31
#define	SPI_DEVICE_CMD_INFO_EN4B_REG_OFFSET   0xdc
#define	SPI_DEVICE_CMD_INFO_EN4B_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_INFO_EN4B_OPCODE_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_EN4B_OPCODE_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_EN4B_OPCODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_EN4B_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_EN4B_OPCODE_OFFSET })
#define	SPI_DEVICE_CMD_INFO_EN4B_VALID_BIT   31
#define	SPI_DEVICE_CMD_INFO_EX4B_REG_OFFSET   0xe0
#define	SPI_DEVICE_CMD_INFO_EX4B_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_INFO_EX4B_OPCODE_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_EX4B_OPCODE_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_EX4B_OPCODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_EX4B_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_EX4B_OPCODE_OFFSET })
#define	SPI_DEVICE_CMD_INFO_EX4B_VALID_BIT   31
#define	SPI_DEVICE_CMD_INFO_WREN_REG_OFFSET   0xe4
#define	SPI_DEVICE_CMD_INFO_WREN_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_INFO_WREN_OPCODE_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_WREN_OPCODE_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_WREN_OPCODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_WREN_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_WREN_OPCODE_OFFSET })
#define	SPI_DEVICE_CMD_INFO_WREN_VALID_BIT   31
#define	SPI_DEVICE_CMD_INFO_WRDI_REG_OFFSET   0xe8
#define	SPI_DEVICE_CMD_INFO_WRDI_REG_RESVAL   0x0u
#define	SPI_DEVICE_CMD_INFO_WRDI_OPCODE_MASK   0xffu
#define	SPI_DEVICE_CMD_INFO_WRDI_OPCODE_OFFSET   0
#define	SPI_DEVICE_CMD_INFO_WRDI_OPCODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_WRDI_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_WRDI_OPCODE_OFFSET })
#define	SPI_DEVICE_CMD_INFO_WRDI_VALID_BIT   31
#define	SPI_DEVICE_TPM_CAP_REG_OFFSET   0x800
#define	SPI_DEVICE_TPM_CAP_REG_RESVAL   0x660100u
#define	SPI_DEVICE_TPM_CAP_REV_MASK   0xffu
#define	SPI_DEVICE_TPM_CAP_REV_OFFSET   0
#define	SPI_DEVICE_TPM_CAP_REV_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CAP_REV_MASK, .index = SPI_DEVICE_TPM_CAP_REV_OFFSET })
#define	SPI_DEVICE_TPM_CAP_LOCALITY_BIT   8
#define	SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_MASK   0x7u
#define	SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_OFFSET   16
#define	SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_MASK, .index = SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_OFFSET })
#define	SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_MASK   0x7u
#define	SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_OFFSET   20
#define	SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_MASK, .index = SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_OFFSET })
#define	SPI_DEVICE_TPM_CFG_REG_OFFSET   0x804
#define	SPI_DEVICE_TPM_CFG_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_CFG_EN_BIT   0
#define	SPI_DEVICE_TPM_CFG_TPM_MODE_BIT   1
#define	SPI_DEVICE_TPM_CFG_HW_REG_DIS_BIT   2
#define	SPI_DEVICE_TPM_CFG_TPM_REG_CHK_DIS_BIT   3
#define	SPI_DEVICE_TPM_CFG_INVALID_LOCALITY_BIT   4
#define	SPI_DEVICE_TPM_STATUS_REG_OFFSET   0x808
#define	SPI_DEVICE_TPM_STATUS_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_STATUS_CMDADDR_NOTEMPTY_BIT   0
#define	SPI_DEVICE_TPM_STATUS_WRFIFO_PENDING_BIT   1
#define	SPI_DEVICE_TPM_STATUS_RDFIFO_ABORTED_BIT   2
#define	SPI_DEVICE_TPM_ACCESS_ACCESS_FIELD_WIDTH   8
#define	SPI_DEVICE_TPM_ACCESS_MULTIREG_COUNT   2
#define	SPI_DEVICE_TPM_ACCESS_0_REG_OFFSET   0x80c
#define	SPI_DEVICE_TPM_ACCESS_0_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_MASK   0xffu
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_OFFSET   0
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_OFFSET })
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_MASK   0xffu
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_OFFSET   8
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_OFFSET })
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_MASK   0xffu
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_OFFSET   16
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_OFFSET })
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_MASK   0xffu
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_OFFSET   24
#define	SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_OFFSET })
#define	SPI_DEVICE_TPM_ACCESS_1_REG_OFFSET   0x810
#define	SPI_DEVICE_TPM_ACCESS_1_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_MASK   0xffu
#define	SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_OFFSET   0
#define	SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_MASK, .index = SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_OFFSET })
#define	SPI_DEVICE_TPM_STS_REG_OFFSET   0x814
#define	SPI_DEVICE_TPM_STS_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_INTF_CAPABILITY_REG_OFFSET   0x818
#define	SPI_DEVICE_TPM_INTF_CAPABILITY_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_INT_ENABLE_REG_OFFSET   0x81c
#define	SPI_DEVICE_TPM_INT_ENABLE_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_INT_VECTOR_REG_OFFSET   0x820
#define	SPI_DEVICE_TPM_INT_VECTOR_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_MASK   0xffu
#define	SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_OFFSET   0
#define	SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_MASK, .index = SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_OFFSET })
#define	SPI_DEVICE_TPM_INT_STATUS_REG_OFFSET   0x824
#define	SPI_DEVICE_TPM_INT_STATUS_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_DID_VID_REG_OFFSET   0x828
#define	SPI_DEVICE_TPM_DID_VID_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_DID_VID_VID_MASK   0xffffu
#define	SPI_DEVICE_TPM_DID_VID_VID_OFFSET   0
#define	SPI_DEVICE_TPM_DID_VID_VID_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_DID_VID_VID_MASK, .index = SPI_DEVICE_TPM_DID_VID_VID_OFFSET })
#define	SPI_DEVICE_TPM_DID_VID_DID_MASK   0xffffu
#define	SPI_DEVICE_TPM_DID_VID_DID_OFFSET   16
#define	SPI_DEVICE_TPM_DID_VID_DID_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_DID_VID_DID_MASK, .index = SPI_DEVICE_TPM_DID_VID_DID_OFFSET })
#define	SPI_DEVICE_TPM_RID_REG_OFFSET   0x82c
#define	SPI_DEVICE_TPM_RID_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_RID_RID_MASK   0xffu
#define	SPI_DEVICE_TPM_RID_RID_OFFSET   0
#define	SPI_DEVICE_TPM_RID_RID_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_RID_RID_MASK, .index = SPI_DEVICE_TPM_RID_RID_OFFSET })
#define	SPI_DEVICE_TPM_CMD_ADDR_REG_OFFSET   0x830
#define	SPI_DEVICE_TPM_CMD_ADDR_REG_RESVAL   0x0u
#define	SPI_DEVICE_TPM_CMD_ADDR_ADDR_MASK   0xffffffu
#define	SPI_DEVICE_TPM_CMD_ADDR_ADDR_OFFSET   0
#define	SPI_DEVICE_TPM_CMD_ADDR_ADDR_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CMD_ADDR_ADDR_MASK, .index = SPI_DEVICE_TPM_CMD_ADDR_ADDR_OFFSET })
#define	SPI_DEVICE_TPM_CMD_ADDR_CMD_MASK   0xffu
#define	SPI_DEVICE_TPM_CMD_ADDR_CMD_OFFSET   24
#define	SPI_DEVICE_TPM_CMD_ADDR_CMD_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CMD_ADDR_CMD_MASK, .index = SPI_DEVICE_TPM_CMD_ADDR_CMD_OFFSET })
#define	SPI_DEVICE_TPM_READ_FIFO_REG_OFFSET   0x834
#define	SPI_DEVICE_TPM_READ_FIFO_REG_RESVAL   0x0u
#define	SPI_DEVICE_EGRESS_BUFFER_REG_OFFSET   0x1000
#define	SPI_DEVICE_EGRESS_BUFFER_SIZE_WORDS   848
#define	SPI_DEVICE_EGRESS_BUFFER_SIZE_BYTES   3392
#define	SPI_DEVICE_INGRESS_BUFFER_REG_OFFSET   0x1e00
#define	SPI_DEVICE_INGRESS_BUFFER_SIZE_WORDS   112
#define	SPI_DEVICE_INGRESS_BUFFER_SIZE_BYTES   448

Detailed Description

Generated register defines for spi_device.

Definition in file spi_device_regs.h.

Macro Definition Documentation

SPI_DEVICE_ADDR_MODE_ADDR_4B_EN_BIT

#define SPI_DEVICE_ADDR_MODE_ADDR_4B_EN_BIT   0

Definition at line 190 of file spi_device_regs.h.

SPI_DEVICE_ADDR_MODE_PENDING_BIT

#define SPI_DEVICE_ADDR_MODE_PENDING_BIT   31

Definition at line 191 of file spi_device_regs.h.

SPI_DEVICE_ADDR_MODE_REG_OFFSET

#define SPI_DEVICE_ADDR_MODE_REG_OFFSET   0x20

Definition at line 188 of file spi_device_regs.h.

SPI_DEVICE_ADDR_MODE_REG_RESVAL

#define SPI_DEVICE_ADDR_MODE_REG_RESVAL   0x0u

Definition at line 189 of file spi_device_regs.h.

SPI_DEVICE_ADDR_SWAP_DATA_REG_OFFSET

#define SPI_DEVICE_ADDR_SWAP_DATA_REG_OFFSET   0x70

Definition at line 581 of file spi_device_regs.h.

SPI_DEVICE_ADDR_SWAP_DATA_REG_RESVAL

#define SPI_DEVICE_ADDR_SWAP_DATA_REG_RESVAL   0x0u

Definition at line 582 of file spi_device_regs.h.

SPI_DEVICE_ADDR_SWAP_MASK_REG_OFFSET

#define SPI_DEVICE_ADDR_SWAP_MASK_REG_OFFSET   0x6c

Definition at line 577 of file spi_device_regs.h.

SPI_DEVICE_ADDR_SWAP_MASK_REG_RESVAL

#define SPI_DEVICE_ADDR_SWAP_MASK_REG_RESVAL   0x0u

Definition at line 578 of file spi_device_regs.h.

SPI_DEVICE_ALERT_TEST_FATAL_FAULT_BIT

#define SPI_DEVICE_ALERT_TEST_FATAL_FAULT_BIT   0

Definition at line 151 of file spi_device_regs.h.

SPI_DEVICE_ALERT_TEST_REG_OFFSET

#define SPI_DEVICE_ALERT_TEST_REG_OFFSET   0xc

Definition at line 149 of file spi_device_regs.h.

SPI_DEVICE_ALERT_TEST_REG_RESVAL

#define SPI_DEVICE_ALERT_TEST_REG_RESVAL   0x0u

Definition at line 150 of file spi_device_regs.h.

SPI_DEVICE_CFG_MAILBOX_EN_BIT

#define SPI_DEVICE_CFG_MAILBOX_EN_BIT   24

Definition at line 171 of file spi_device_regs.h.

SPI_DEVICE_CFG_REG_OFFSET

#define SPI_DEVICE_CFG_REG_OFFSET   0x14

Definition at line 167 of file spi_device_regs.h.

SPI_DEVICE_CFG_REG_RESVAL

#define SPI_DEVICE_CFG_REG_RESVAL   0x0u

Definition at line 168 of file spi_device_regs.h.

SPI_DEVICE_CFG_RX_ORDER_BIT

#define SPI_DEVICE_CFG_RX_ORDER_BIT   3

Definition at line 170 of file spi_device_regs.h.

SPI_DEVICE_CFG_TX_ORDER_BIT

#define SPI_DEVICE_CFG_TX_ORDER_BIT   2

Definition at line 169 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_0_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_0_BIT   0

Definition at line 291 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_10_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_10_BIT   10

Definition at line 301 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_11_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_11_BIT   11

Definition at line 302 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_12_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_12_BIT   12

Definition at line 303 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_13_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_13_BIT   13

Definition at line 304 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_14_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_14_BIT   14

Definition at line 305 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_15_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_15_BIT   15

Definition at line 306 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_16_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_16_BIT   16

Definition at line 307 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_17_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_17_BIT   17

Definition at line 308 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_18_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_18_BIT   18

Definition at line 309 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_19_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_19_BIT   19

Definition at line 310 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_1_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_1_BIT   1

Definition at line 292 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_20_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_20_BIT   20

Definition at line 311 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_21_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_21_BIT   21

Definition at line 312 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_22_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_22_BIT   22

Definition at line 313 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_23_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_23_BIT   23

Definition at line 314 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_24_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_24_BIT   24

Definition at line 315 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_25_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_25_BIT   25

Definition at line 316 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_26_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_26_BIT   26

Definition at line 317 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_27_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_27_BIT   27

Definition at line 318 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_28_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_28_BIT   28

Definition at line 319 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_29_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_29_BIT   29

Definition at line 320 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_2_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_2_BIT   2

Definition at line 293 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_30_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_30_BIT   30

Definition at line 321 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_31_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_31_BIT   31

Definition at line 322 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_3_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_3_BIT   3

Definition at line 294 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_4_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_4_BIT   4

Definition at line 295 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_5_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_5_BIT   5

Definition at line 296 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_6_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_6_BIT   6

Definition at line 297 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_7_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_7_BIT   7

Definition at line 298 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_8_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_8_BIT   8

Definition at line 299 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_FILTER_9_BIT

#define SPI_DEVICE_CMD_FILTER_0_FILTER_9_BIT   9

Definition at line 300 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_REG_OFFSET

#define SPI_DEVICE_CMD_FILTER_0_REG_OFFSET   0x4c

Definition at line 289 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_0_REG_RESVAL

#define SPI_DEVICE_CMD_FILTER_0_REG_RESVAL   0x0u

Definition at line 290 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_32_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_32_BIT   0

Definition at line 327 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_33_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_33_BIT   1

Definition at line 328 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_34_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_34_BIT   2

Definition at line 329 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_35_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_35_BIT   3

Definition at line 330 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_36_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_36_BIT   4

Definition at line 331 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_37_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_37_BIT   5

Definition at line 332 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_38_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_38_BIT   6

Definition at line 333 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_39_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_39_BIT   7

Definition at line 334 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_40_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_40_BIT   8

Definition at line 335 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_41_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_41_BIT   9

Definition at line 336 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_42_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_42_BIT   10

Definition at line 337 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_43_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_43_BIT   11

Definition at line 338 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_44_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_44_BIT   12

Definition at line 339 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_45_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_45_BIT   13

Definition at line 340 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_46_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_46_BIT   14

Definition at line 341 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_47_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_47_BIT   15

Definition at line 342 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_48_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_48_BIT   16

Definition at line 343 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_49_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_49_BIT   17

Definition at line 344 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_50_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_50_BIT   18

Definition at line 345 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_51_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_51_BIT   19

Definition at line 346 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_52_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_52_BIT   20

Definition at line 347 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_53_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_53_BIT   21

Definition at line 348 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_54_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_54_BIT   22

Definition at line 349 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_55_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_55_BIT   23

Definition at line 350 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_56_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_56_BIT   24

Definition at line 351 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_57_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_57_BIT   25

Definition at line 352 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_58_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_58_BIT   26

Definition at line 353 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_59_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_59_BIT   27

Definition at line 354 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_60_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_60_BIT   28

Definition at line 355 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_61_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_61_BIT   29

Definition at line 356 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_62_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_62_BIT   30

Definition at line 357 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_FILTER_63_BIT

#define SPI_DEVICE_CMD_FILTER_1_FILTER_63_BIT   31

Definition at line 358 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_REG_OFFSET

#define SPI_DEVICE_CMD_FILTER_1_REG_OFFSET   0x50

Definition at line 325 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_1_REG_RESVAL

#define SPI_DEVICE_CMD_FILTER_1_REG_RESVAL   0x0u

Definition at line 326 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_64_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_64_BIT   0

Definition at line 363 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_65_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_65_BIT   1

Definition at line 364 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_66_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_66_BIT   2

Definition at line 365 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_67_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_67_BIT   3

Definition at line 366 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_68_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_68_BIT   4

Definition at line 367 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_69_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_69_BIT   5

Definition at line 368 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_70_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_70_BIT   6

Definition at line 369 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_71_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_71_BIT   7

Definition at line 370 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_72_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_72_BIT   8

Definition at line 371 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_73_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_73_BIT   9

Definition at line 372 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_74_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_74_BIT   10

Definition at line 373 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_75_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_75_BIT   11

Definition at line 374 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_76_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_76_BIT   12

Definition at line 375 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_77_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_77_BIT   13

Definition at line 376 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_78_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_78_BIT   14

Definition at line 377 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_79_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_79_BIT   15

Definition at line 378 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_80_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_80_BIT   16

Definition at line 379 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_81_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_81_BIT   17

Definition at line 380 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_82_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_82_BIT   18

Definition at line 381 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_83_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_83_BIT   19

Definition at line 382 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_84_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_84_BIT   20

Definition at line 383 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_85_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_85_BIT   21

Definition at line 384 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_86_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_86_BIT   22

Definition at line 385 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_87_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_87_BIT   23

Definition at line 386 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_88_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_88_BIT   24

Definition at line 387 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_89_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_89_BIT   25

Definition at line 388 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_90_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_90_BIT   26

Definition at line 389 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_91_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_91_BIT   27

Definition at line 390 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_92_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_92_BIT   28

Definition at line 391 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_93_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_93_BIT   29

Definition at line 392 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_94_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_94_BIT   30

Definition at line 393 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_FILTER_95_BIT

#define SPI_DEVICE_CMD_FILTER_2_FILTER_95_BIT   31

Definition at line 394 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_REG_OFFSET

#define SPI_DEVICE_CMD_FILTER_2_REG_OFFSET   0x54

Definition at line 361 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_2_REG_RESVAL

#define SPI_DEVICE_CMD_FILTER_2_REG_RESVAL   0x0u

Definition at line 362 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_100_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_100_BIT   4

Definition at line 403 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_101_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_101_BIT   5

Definition at line 404 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_102_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_102_BIT   6

Definition at line 405 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_103_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_103_BIT   7

Definition at line 406 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_104_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_104_BIT   8

Definition at line 407 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_105_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_105_BIT   9

Definition at line 408 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_106_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_106_BIT   10

Definition at line 409 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_107_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_107_BIT   11

Definition at line 410 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_108_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_108_BIT   12

Definition at line 411 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_109_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_109_BIT   13

Definition at line 412 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_110_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_110_BIT   14

Definition at line 413 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_111_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_111_BIT   15

Definition at line 414 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_112_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_112_BIT   16

Definition at line 415 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_113_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_113_BIT   17

Definition at line 416 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_114_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_114_BIT   18

Definition at line 417 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_115_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_115_BIT   19

Definition at line 418 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_116_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_116_BIT   20

Definition at line 419 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_117_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_117_BIT   21

Definition at line 420 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_118_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_118_BIT   22

Definition at line 421 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_119_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_119_BIT   23

Definition at line 422 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_120_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_120_BIT   24

Definition at line 423 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_121_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_121_BIT   25

Definition at line 424 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_122_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_122_BIT   26

Definition at line 425 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_123_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_123_BIT   27

Definition at line 426 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_124_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_124_BIT   28

Definition at line 427 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_125_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_125_BIT   29

Definition at line 428 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_126_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_126_BIT   30

Definition at line 429 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_127_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_127_BIT   31

Definition at line 430 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_96_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_96_BIT   0

Definition at line 399 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_97_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_97_BIT   1

Definition at line 400 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_98_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_98_BIT   2

Definition at line 401 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_FILTER_99_BIT

#define SPI_DEVICE_CMD_FILTER_3_FILTER_99_BIT   3

Definition at line 402 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_REG_OFFSET

#define SPI_DEVICE_CMD_FILTER_3_REG_OFFSET   0x58

Definition at line 397 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_3_REG_RESVAL

#define SPI_DEVICE_CMD_FILTER_3_REG_RESVAL   0x0u

Definition at line 398 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_128_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_128_BIT   0

Definition at line 435 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_129_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_129_BIT   1

Definition at line 436 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_130_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_130_BIT   2

Definition at line 437 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_131_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_131_BIT   3

Definition at line 438 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_132_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_132_BIT   4

Definition at line 439 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_133_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_133_BIT   5

Definition at line 440 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_134_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_134_BIT   6

Definition at line 441 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_135_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_135_BIT   7

Definition at line 442 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_136_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_136_BIT   8

Definition at line 443 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_137_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_137_BIT   9

Definition at line 444 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_138_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_138_BIT   10

Definition at line 445 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_139_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_139_BIT   11

Definition at line 446 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_140_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_140_BIT   12

Definition at line 447 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_141_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_141_BIT   13

Definition at line 448 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_142_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_142_BIT   14

Definition at line 449 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_143_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_143_BIT   15

Definition at line 450 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_144_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_144_BIT   16

Definition at line 451 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_145_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_145_BIT   17

Definition at line 452 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_146_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_146_BIT   18

Definition at line 453 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_147_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_147_BIT   19

Definition at line 454 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_148_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_148_BIT   20

Definition at line 455 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_149_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_149_BIT   21

Definition at line 456 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_150_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_150_BIT   22

Definition at line 457 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_151_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_151_BIT   23

Definition at line 458 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_152_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_152_BIT   24

Definition at line 459 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_153_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_153_BIT   25

Definition at line 460 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_154_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_154_BIT   26

Definition at line 461 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_155_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_155_BIT   27

Definition at line 462 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_156_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_156_BIT   28

Definition at line 463 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_157_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_157_BIT   29

Definition at line 464 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_158_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_158_BIT   30

Definition at line 465 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_FILTER_159_BIT

#define SPI_DEVICE_CMD_FILTER_4_FILTER_159_BIT   31

Definition at line 466 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_REG_OFFSET

#define SPI_DEVICE_CMD_FILTER_4_REG_OFFSET   0x5c

Definition at line 433 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_4_REG_RESVAL

#define SPI_DEVICE_CMD_FILTER_4_REG_RESVAL   0x0u

Definition at line 434 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_160_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_160_BIT   0

Definition at line 471 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_161_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_161_BIT   1

Definition at line 472 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_162_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_162_BIT   2

Definition at line 473 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_163_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_163_BIT   3

Definition at line 474 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_164_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_164_BIT   4

Definition at line 475 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_165_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_165_BIT   5

Definition at line 476 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_166_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_166_BIT   6

Definition at line 477 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_167_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_167_BIT   7

Definition at line 478 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_168_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_168_BIT   8

Definition at line 479 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_169_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_169_BIT   9

Definition at line 480 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_170_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_170_BIT   10

Definition at line 481 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_171_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_171_BIT   11

Definition at line 482 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_172_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_172_BIT   12

Definition at line 483 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_173_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_173_BIT   13

Definition at line 484 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_174_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_174_BIT   14

Definition at line 485 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_175_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_175_BIT   15

Definition at line 486 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_176_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_176_BIT   16

Definition at line 487 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_177_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_177_BIT   17

Definition at line 488 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_178_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_178_BIT   18

Definition at line 489 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_179_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_179_BIT   19

Definition at line 490 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_180_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_180_BIT   20

Definition at line 491 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_181_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_181_BIT   21

Definition at line 492 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_182_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_182_BIT   22

Definition at line 493 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_183_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_183_BIT   23

Definition at line 494 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_184_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_184_BIT   24

Definition at line 495 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_185_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_185_BIT   25

Definition at line 496 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_186_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_186_BIT   26

Definition at line 497 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_187_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_187_BIT   27

Definition at line 498 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_188_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_188_BIT   28

Definition at line 499 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_189_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_189_BIT   29

Definition at line 500 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_190_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_190_BIT   30

Definition at line 501 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_FILTER_191_BIT

#define SPI_DEVICE_CMD_FILTER_5_FILTER_191_BIT   31

Definition at line 502 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_REG_OFFSET

#define SPI_DEVICE_CMD_FILTER_5_REG_OFFSET   0x60

Definition at line 469 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_5_REG_RESVAL

#define SPI_DEVICE_CMD_FILTER_5_REG_RESVAL   0x0u

Definition at line 470 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_192_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_192_BIT   0

Definition at line 507 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_193_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_193_BIT   1

Definition at line 508 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_194_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_194_BIT   2

Definition at line 509 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_195_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_195_BIT   3

Definition at line 510 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_196_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_196_BIT   4

Definition at line 511 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_197_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_197_BIT   5

Definition at line 512 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_198_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_198_BIT   6

Definition at line 513 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_199_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_199_BIT   7

Definition at line 514 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_200_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_200_BIT   8

Definition at line 515 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_201_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_201_BIT   9

Definition at line 516 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_202_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_202_BIT   10

Definition at line 517 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_203_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_203_BIT   11

Definition at line 518 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_204_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_204_BIT   12

Definition at line 519 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_205_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_205_BIT   13

Definition at line 520 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_206_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_206_BIT   14

Definition at line 521 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_207_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_207_BIT   15

Definition at line 522 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_208_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_208_BIT   16

Definition at line 523 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_209_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_209_BIT   17

Definition at line 524 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_210_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_210_BIT   18

Definition at line 525 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_211_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_211_BIT   19

Definition at line 526 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_212_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_212_BIT   20

Definition at line 527 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_213_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_213_BIT   21

Definition at line 528 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_214_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_214_BIT   22

Definition at line 529 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_215_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_215_BIT   23

Definition at line 530 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_216_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_216_BIT   24

Definition at line 531 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_217_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_217_BIT   25

Definition at line 532 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_218_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_218_BIT   26

Definition at line 533 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_219_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_219_BIT   27

Definition at line 534 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_220_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_220_BIT   28

Definition at line 535 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_221_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_221_BIT   29

Definition at line 536 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_222_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_222_BIT   30

Definition at line 537 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_FILTER_223_BIT

#define SPI_DEVICE_CMD_FILTER_6_FILTER_223_BIT   31

Definition at line 538 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_REG_OFFSET

#define SPI_DEVICE_CMD_FILTER_6_REG_OFFSET   0x64

Definition at line 505 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_6_REG_RESVAL

#define SPI_DEVICE_CMD_FILTER_6_REG_RESVAL   0x0u

Definition at line 506 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_224_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_224_BIT   0

Definition at line 543 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_225_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_225_BIT   1

Definition at line 544 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_226_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_226_BIT   2

Definition at line 545 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_227_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_227_BIT   3

Definition at line 546 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_228_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_228_BIT   4

Definition at line 547 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_229_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_229_BIT   5

Definition at line 548 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_230_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_230_BIT   6

Definition at line 549 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_231_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_231_BIT   7

Definition at line 550 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_232_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_232_BIT   8

Definition at line 551 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_233_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_233_BIT   9

Definition at line 552 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_234_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_234_BIT   10

Definition at line 553 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_235_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_235_BIT   11

Definition at line 554 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_236_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_236_BIT   12

Definition at line 555 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_237_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_237_BIT   13

Definition at line 556 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_238_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_238_BIT   14

Definition at line 557 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_239_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_239_BIT   15

Definition at line 558 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_240_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_240_BIT   16

Definition at line 559 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_241_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_241_BIT   17

Definition at line 560 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_242_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_242_BIT   18

Definition at line 561 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_243_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_243_BIT   19

Definition at line 562 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_244_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_244_BIT   20

Definition at line 563 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_245_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_245_BIT   21

Definition at line 564 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_246_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_246_BIT   22

Definition at line 565 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_247_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_247_BIT   23

Definition at line 566 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_248_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_248_BIT   24

Definition at line 567 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_249_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_249_BIT   25

Definition at line 568 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_250_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_250_BIT   26

Definition at line 569 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_251_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_251_BIT   27

Definition at line 570 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_252_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_252_BIT   28

Definition at line 571 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_253_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_253_BIT   29

Definition at line 572 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_254_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_254_BIT   30

Definition at line 573 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_FILTER_255_BIT

#define SPI_DEVICE_CMD_FILTER_7_FILTER_255_BIT   31

Definition at line 574 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_REG_OFFSET

#define SPI_DEVICE_CMD_FILTER_7_REG_OFFSET   0x68

Definition at line 541 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_7_REG_RESVAL

#define SPI_DEVICE_CMD_FILTER_7_REG_RESVAL   0x0u

Definition at line 542 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_FILTER_FIELD_WIDTH

#define SPI_DEVICE_CMD_FILTER_FILTER_FIELD_WIDTH   1

Definition at line 285 of file spi_device_regs.h.

SPI_DEVICE_CMD_FILTER_MULTIREG_COUNT

#define SPI_DEVICE_CMD_FILTER_MULTIREG_COUNT   8

Definition at line 286 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_FIELD

#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_OFFSET })

Definition at line 617 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_MASK

#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_MASK   0x3u

Definition at line 615 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_OFFSET

#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_OFFSET   8

Definition at line 616 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDR3B

#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDR3B   0x2

Definition at line 621 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDR4B

#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDR4B   0x3

Definition at line 622 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDRCFG

#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDRCFG   0x1

Definition at line 620 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDRDISABLED

#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDRDISABLED   0x0

Definition at line 619 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_ADDR_SWAP_EN_0_BIT

#define SPI_DEVICE_CMD_INFO_0_ADDR_SWAP_EN_0_BIT   10

Definition at line 623 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_BUSY_0_BIT

#define SPI_DEVICE_CMD_INFO_0_BUSY_0_BIT   25

Definition at line 648 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_DUMMY_EN_0_BIT

#define SPI_DEVICE_CMD_INFO_0_DUMMY_EN_0_BIT   15

Definition at line 629 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_FIELD

#define SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_OFFSET })

Definition at line 627 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_MASK

#define SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_MASK   0x7u

Definition at line 625 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_OFFSET

#define SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_OFFSET   12

Definition at line 626 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_MBYTE_EN_0_BIT

#define SPI_DEVICE_CMD_INFO_0_MBYTE_EN_0_BIT   11

Definition at line 624 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_OPCODE_0_FIELD

#define SPI_DEVICE_CMD_INFO_0_OPCODE_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_OPCODE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_OPCODE_0_OFFSET })

Definition at line 613 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_OPCODE_0_MASK

#define SPI_DEVICE_CMD_INFO_0_OPCODE_0_MASK   0xffu

Definition at line 611 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_OPCODE_0_OFFSET

#define SPI_DEVICE_CMD_INFO_0_OPCODE_0_OFFSET   0

Definition at line 612 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_BIT

#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_BIT   20

Definition at line 634 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_VALUE_PAYLOADIN

#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_VALUE_PAYLOADIN   0x0

Definition at line 635 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_VALUE_PAYLOADOUT

#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_VALUE_PAYLOADOUT   0x1

Definition at line 636 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_FIELD

#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_OFFSET })

Definition at line 632 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_MASK

#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_MASK   0xfu

Definition at line 630 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_OFFSET

#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_OFFSET   16

Definition at line 631 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_PAYLOAD_SWAP_EN_0_BIT

#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_SWAP_EN_0_BIT   21

Definition at line 637 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_FIELD

#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_OFFSET })

Definition at line 640 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_MASK

#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_MASK   0x3u

Definition at line 638 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_OFFSET

#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_OFFSET   22

Definition at line 639 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_TWO_STAGES_FULL_CYCLE

#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_TWO_STAGES_FULL_CYCLE    0x2

Definition at line 645 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_TWO_STAGES_HALF_CYCLE

#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_TWO_STAGES_HALF_CYCLE    0x1

Definition at line 643 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_ZERO_STAGES

#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_ZERO_STAGES   0x0

Definition at line 642 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_0_REG_OFFSET   0x7c

Definition at line 609 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_0_REG_RESVAL   0x7000u

Definition at line 610 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_UPLOAD_0_BIT

#define SPI_DEVICE_CMD_INFO_0_UPLOAD_0_BIT   24

Definition at line 647 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_0_VALID_0_BIT

#define SPI_DEVICE_CMD_INFO_0_VALID_0_BIT   31

Definition at line 649 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_FIELD

#define SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_OFFSET })

Definition at line 948 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_MASK

#define SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_MASK   0x3u

Definition at line 946 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_OFFSET

#define SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_OFFSET   8

Definition at line 947 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_ADDR_SWAP_EN_10_BIT

#define SPI_DEVICE_CMD_INFO_10_ADDR_SWAP_EN_10_BIT   10

Definition at line 950 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_BUSY_10_BIT

#define SPI_DEVICE_CMD_INFO_10_BUSY_10_BIT   25

Definition at line 968 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_DUMMY_EN_10_BIT

#define SPI_DEVICE_CMD_INFO_10_DUMMY_EN_10_BIT   15

Definition at line 956 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_FIELD

#define SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_OFFSET })

Definition at line 954 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_MASK

#define SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_MASK   0x7u

Definition at line 952 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_OFFSET

#define SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_OFFSET   12

Definition at line 953 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_MBYTE_EN_10_BIT

#define SPI_DEVICE_CMD_INFO_10_MBYTE_EN_10_BIT   11

Definition at line 951 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_OPCODE_10_FIELD

#define SPI_DEVICE_CMD_INFO_10_OPCODE_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_OPCODE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_OPCODE_10_OFFSET })

Definition at line 944 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_OPCODE_10_MASK

#define SPI_DEVICE_CMD_INFO_10_OPCODE_10_MASK   0xffu

Definition at line 942 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_OPCODE_10_OFFSET

#define SPI_DEVICE_CMD_INFO_10_OPCODE_10_OFFSET   0

Definition at line 943 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_PAYLOAD_DIR_10_BIT

#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_DIR_10_BIT   20

Definition at line 961 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_FIELD

#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_OFFSET })

Definition at line 959 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_MASK

#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_MASK   0xfu

Definition at line 957 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_OFFSET

#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_OFFSET   16

Definition at line 958 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_PAYLOAD_SWAP_EN_10_BIT

#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_SWAP_EN_10_BIT   21

Definition at line 962 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_FIELD

#define SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_OFFSET })

Definition at line 965 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_MASK

#define SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_MASK   0x3u

Definition at line 963 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_OFFSET

#define SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_OFFSET   22

Definition at line 964 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_10_REG_OFFSET   0xa4

Definition at line 940 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_10_REG_RESVAL   0x7000u

Definition at line 941 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_UPLOAD_10_BIT

#define SPI_DEVICE_CMD_INFO_10_UPLOAD_10_BIT   24

Definition at line 967 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_10_VALID_10_BIT

#define SPI_DEVICE_CMD_INFO_10_VALID_10_BIT   31

Definition at line 969 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_FIELD

#define SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_OFFSET })

Definition at line 980 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_MASK

#define SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_MASK   0x3u

Definition at line 978 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_OFFSET

#define SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_OFFSET   8

Definition at line 979 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_ADDR_SWAP_EN_11_BIT

#define SPI_DEVICE_CMD_INFO_11_ADDR_SWAP_EN_11_BIT   10

Definition at line 982 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_BUSY_11_BIT

#define SPI_DEVICE_CMD_INFO_11_BUSY_11_BIT   25

Definition at line 1000 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_DUMMY_EN_11_BIT

#define SPI_DEVICE_CMD_INFO_11_DUMMY_EN_11_BIT   15

Definition at line 988 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_FIELD

#define SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_OFFSET })

Definition at line 986 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_MASK

#define SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_MASK   0x7u

Definition at line 984 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_OFFSET

#define SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_OFFSET   12

Definition at line 985 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_MBYTE_EN_11_BIT

#define SPI_DEVICE_CMD_INFO_11_MBYTE_EN_11_BIT   11

Definition at line 983 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_OPCODE_11_FIELD

#define SPI_DEVICE_CMD_INFO_11_OPCODE_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_OPCODE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_OPCODE_11_OFFSET })

Definition at line 976 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_OPCODE_11_MASK

#define SPI_DEVICE_CMD_INFO_11_OPCODE_11_MASK   0xffu

Definition at line 974 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_OPCODE_11_OFFSET

#define SPI_DEVICE_CMD_INFO_11_OPCODE_11_OFFSET   0

Definition at line 975 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_PAYLOAD_DIR_11_BIT

#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_DIR_11_BIT   20

Definition at line 993 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_FIELD

#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_OFFSET })

Definition at line 991 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_MASK

#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_MASK   0xfu

Definition at line 989 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_OFFSET

#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_OFFSET   16

Definition at line 990 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_PAYLOAD_SWAP_EN_11_BIT

#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_SWAP_EN_11_BIT   21

Definition at line 994 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_FIELD

#define SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_OFFSET })

Definition at line 997 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_MASK

#define SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_MASK   0x3u

Definition at line 995 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_OFFSET

#define SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_OFFSET   22

Definition at line 996 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_11_REG_OFFSET   0xa8

Definition at line 972 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_11_REG_RESVAL   0x7000u

Definition at line 973 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_UPLOAD_11_BIT

#define SPI_DEVICE_CMD_INFO_11_UPLOAD_11_BIT   24

Definition at line 999 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_11_VALID_11_BIT

#define SPI_DEVICE_CMD_INFO_11_VALID_11_BIT   31

Definition at line 1001 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_FIELD

#define SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_OFFSET })

Definition at line 1012 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_MASK

#define SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_MASK   0x3u

Definition at line 1010 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_OFFSET

#define SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_OFFSET   8

Definition at line 1011 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_ADDR_SWAP_EN_12_BIT

#define SPI_DEVICE_CMD_INFO_12_ADDR_SWAP_EN_12_BIT   10

Definition at line 1014 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_BUSY_12_BIT

#define SPI_DEVICE_CMD_INFO_12_BUSY_12_BIT   25

Definition at line 1032 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_DUMMY_EN_12_BIT

#define SPI_DEVICE_CMD_INFO_12_DUMMY_EN_12_BIT   15

Definition at line 1020 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_FIELD

#define SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_OFFSET })

Definition at line 1018 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_MASK

#define SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_MASK   0x7u

Definition at line 1016 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_OFFSET

#define SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_OFFSET   12

Definition at line 1017 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_MBYTE_EN_12_BIT

#define SPI_DEVICE_CMD_INFO_12_MBYTE_EN_12_BIT   11

Definition at line 1015 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_OPCODE_12_FIELD

#define SPI_DEVICE_CMD_INFO_12_OPCODE_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_OPCODE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_OPCODE_12_OFFSET })

Definition at line 1008 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_OPCODE_12_MASK

#define SPI_DEVICE_CMD_INFO_12_OPCODE_12_MASK   0xffu

Definition at line 1006 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_OPCODE_12_OFFSET

#define SPI_DEVICE_CMD_INFO_12_OPCODE_12_OFFSET   0

Definition at line 1007 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_PAYLOAD_DIR_12_BIT

#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_DIR_12_BIT   20

Definition at line 1025 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_FIELD

#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_OFFSET })

Definition at line 1023 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_MASK

#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_MASK   0xfu

Definition at line 1021 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_OFFSET

#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_OFFSET   16

Definition at line 1022 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_PAYLOAD_SWAP_EN_12_BIT

#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_SWAP_EN_12_BIT   21

Definition at line 1026 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_FIELD

#define SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_OFFSET })

Definition at line 1029 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_MASK

#define SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_MASK   0x3u

Definition at line 1027 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_OFFSET

#define SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_OFFSET   22

Definition at line 1028 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_12_REG_OFFSET   0xac

Definition at line 1004 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_12_REG_RESVAL   0x7000u

Definition at line 1005 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_UPLOAD_12_BIT

#define SPI_DEVICE_CMD_INFO_12_UPLOAD_12_BIT   24

Definition at line 1031 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_12_VALID_12_BIT

#define SPI_DEVICE_CMD_INFO_12_VALID_12_BIT   31

Definition at line 1033 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_FIELD

#define SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_OFFSET })

Definition at line 1044 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_MASK

#define SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_MASK   0x3u

Definition at line 1042 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_OFFSET

#define SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_OFFSET   8

Definition at line 1043 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_ADDR_SWAP_EN_13_BIT

#define SPI_DEVICE_CMD_INFO_13_ADDR_SWAP_EN_13_BIT   10

Definition at line 1046 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_BUSY_13_BIT

#define SPI_DEVICE_CMD_INFO_13_BUSY_13_BIT   25

Definition at line 1064 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_DUMMY_EN_13_BIT

#define SPI_DEVICE_CMD_INFO_13_DUMMY_EN_13_BIT   15

Definition at line 1052 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_FIELD

#define SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_OFFSET })

Definition at line 1050 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_MASK

#define SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_MASK   0x7u

Definition at line 1048 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_OFFSET

#define SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_OFFSET   12

Definition at line 1049 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_MBYTE_EN_13_BIT

#define SPI_DEVICE_CMD_INFO_13_MBYTE_EN_13_BIT   11

Definition at line 1047 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_OPCODE_13_FIELD

#define SPI_DEVICE_CMD_INFO_13_OPCODE_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_OPCODE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_OPCODE_13_OFFSET })

Definition at line 1040 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_OPCODE_13_MASK

#define SPI_DEVICE_CMD_INFO_13_OPCODE_13_MASK   0xffu

Definition at line 1038 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_OPCODE_13_OFFSET

#define SPI_DEVICE_CMD_INFO_13_OPCODE_13_OFFSET   0

Definition at line 1039 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_PAYLOAD_DIR_13_BIT

#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_DIR_13_BIT   20

Definition at line 1057 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_FIELD

#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_OFFSET })

Definition at line 1055 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_MASK

#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_MASK   0xfu

Definition at line 1053 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_OFFSET

#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_OFFSET   16

Definition at line 1054 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_PAYLOAD_SWAP_EN_13_BIT

#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_SWAP_EN_13_BIT   21

Definition at line 1058 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_FIELD

#define SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_OFFSET })

Definition at line 1061 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_MASK

#define SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_MASK   0x3u

Definition at line 1059 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_OFFSET

#define SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_OFFSET   22

Definition at line 1060 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_13_REG_OFFSET   0xb0

Definition at line 1036 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_13_REG_RESVAL   0x7000u

Definition at line 1037 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_UPLOAD_13_BIT

#define SPI_DEVICE_CMD_INFO_13_UPLOAD_13_BIT   24

Definition at line 1063 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_13_VALID_13_BIT

#define SPI_DEVICE_CMD_INFO_13_VALID_13_BIT   31

Definition at line 1065 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_FIELD

#define SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_OFFSET })

Definition at line 1076 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_MASK

#define SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_MASK   0x3u

Definition at line 1074 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_OFFSET

#define SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_OFFSET   8

Definition at line 1075 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_ADDR_SWAP_EN_14_BIT

#define SPI_DEVICE_CMD_INFO_14_ADDR_SWAP_EN_14_BIT   10

Definition at line 1078 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_BUSY_14_BIT

#define SPI_DEVICE_CMD_INFO_14_BUSY_14_BIT   25

Definition at line 1096 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_DUMMY_EN_14_BIT

#define SPI_DEVICE_CMD_INFO_14_DUMMY_EN_14_BIT   15

Definition at line 1084 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_FIELD

#define SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_OFFSET })

Definition at line 1082 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_MASK

#define SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_MASK   0x7u

Definition at line 1080 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_OFFSET

#define SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_OFFSET   12

Definition at line 1081 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_MBYTE_EN_14_BIT

#define SPI_DEVICE_CMD_INFO_14_MBYTE_EN_14_BIT   11

Definition at line 1079 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_OPCODE_14_FIELD

#define SPI_DEVICE_CMD_INFO_14_OPCODE_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_OPCODE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_OPCODE_14_OFFSET })

Definition at line 1072 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_OPCODE_14_MASK

#define SPI_DEVICE_CMD_INFO_14_OPCODE_14_MASK   0xffu

Definition at line 1070 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_OPCODE_14_OFFSET

#define SPI_DEVICE_CMD_INFO_14_OPCODE_14_OFFSET   0

Definition at line 1071 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_PAYLOAD_DIR_14_BIT

#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_DIR_14_BIT   20

Definition at line 1089 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_FIELD

#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_OFFSET })

Definition at line 1087 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_MASK

#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_MASK   0xfu

Definition at line 1085 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_OFFSET

#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_OFFSET   16

Definition at line 1086 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_PAYLOAD_SWAP_EN_14_BIT

#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_SWAP_EN_14_BIT   21

Definition at line 1090 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_FIELD

#define SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_OFFSET })

Definition at line 1093 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_MASK

#define SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_MASK   0x3u

Definition at line 1091 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_OFFSET

#define SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_OFFSET   22

Definition at line 1092 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_14_REG_OFFSET   0xb4

Definition at line 1068 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_14_REG_RESVAL   0x7000u

Definition at line 1069 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_UPLOAD_14_BIT

#define SPI_DEVICE_CMD_INFO_14_UPLOAD_14_BIT   24

Definition at line 1095 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_14_VALID_14_BIT

#define SPI_DEVICE_CMD_INFO_14_VALID_14_BIT   31

Definition at line 1097 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_FIELD

#define SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_OFFSET })

Definition at line 1108 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_MASK

#define SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_MASK   0x3u

Definition at line 1106 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_OFFSET

#define SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_OFFSET   8

Definition at line 1107 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_ADDR_SWAP_EN_15_BIT

#define SPI_DEVICE_CMD_INFO_15_ADDR_SWAP_EN_15_BIT   10

Definition at line 1110 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_BUSY_15_BIT

#define SPI_DEVICE_CMD_INFO_15_BUSY_15_BIT   25

Definition at line 1128 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_DUMMY_EN_15_BIT

#define SPI_DEVICE_CMD_INFO_15_DUMMY_EN_15_BIT   15

Definition at line 1116 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_FIELD

#define SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_OFFSET })

Definition at line 1114 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_MASK

#define SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_MASK   0x7u

Definition at line 1112 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_OFFSET

#define SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_OFFSET   12

Definition at line 1113 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_MBYTE_EN_15_BIT

#define SPI_DEVICE_CMD_INFO_15_MBYTE_EN_15_BIT   11

Definition at line 1111 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_OPCODE_15_FIELD

#define SPI_DEVICE_CMD_INFO_15_OPCODE_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_OPCODE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_OPCODE_15_OFFSET })

Definition at line 1104 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_OPCODE_15_MASK

#define SPI_DEVICE_CMD_INFO_15_OPCODE_15_MASK   0xffu

Definition at line 1102 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_OPCODE_15_OFFSET

#define SPI_DEVICE_CMD_INFO_15_OPCODE_15_OFFSET   0

Definition at line 1103 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_PAYLOAD_DIR_15_BIT

#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_DIR_15_BIT   20

Definition at line 1121 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_FIELD

#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_OFFSET })

Definition at line 1119 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_MASK

#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_MASK   0xfu

Definition at line 1117 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_OFFSET

#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_OFFSET   16

Definition at line 1118 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_PAYLOAD_SWAP_EN_15_BIT

#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_SWAP_EN_15_BIT   21

Definition at line 1122 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_FIELD

#define SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_OFFSET })

Definition at line 1125 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_MASK

#define SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_MASK   0x3u

Definition at line 1123 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_OFFSET

#define SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_OFFSET   22

Definition at line 1124 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_15_REG_OFFSET   0xb8

Definition at line 1100 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_15_REG_RESVAL   0x7000u

Definition at line 1101 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_UPLOAD_15_BIT

#define SPI_DEVICE_CMD_INFO_15_UPLOAD_15_BIT   24

Definition at line 1127 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_15_VALID_15_BIT

#define SPI_DEVICE_CMD_INFO_15_VALID_15_BIT   31

Definition at line 1129 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_FIELD

#define SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_OFFSET })

Definition at line 1140 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_MASK

#define SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_MASK   0x3u

Definition at line 1138 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_OFFSET

#define SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_OFFSET   8

Definition at line 1139 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_ADDR_SWAP_EN_16_BIT

#define SPI_DEVICE_CMD_INFO_16_ADDR_SWAP_EN_16_BIT   10

Definition at line 1142 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_BUSY_16_BIT

#define SPI_DEVICE_CMD_INFO_16_BUSY_16_BIT   25

Definition at line 1160 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_DUMMY_EN_16_BIT

#define SPI_DEVICE_CMD_INFO_16_DUMMY_EN_16_BIT   15

Definition at line 1148 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_FIELD

#define SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_OFFSET })

Definition at line 1146 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_MASK

#define SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_MASK   0x7u

Definition at line 1144 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_OFFSET

#define SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_OFFSET   12

Definition at line 1145 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_MBYTE_EN_16_BIT

#define SPI_DEVICE_CMD_INFO_16_MBYTE_EN_16_BIT   11

Definition at line 1143 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_OPCODE_16_FIELD

#define SPI_DEVICE_CMD_INFO_16_OPCODE_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_OPCODE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_OPCODE_16_OFFSET })

Definition at line 1136 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_OPCODE_16_MASK

#define SPI_DEVICE_CMD_INFO_16_OPCODE_16_MASK   0xffu

Definition at line 1134 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_OPCODE_16_OFFSET

#define SPI_DEVICE_CMD_INFO_16_OPCODE_16_OFFSET   0

Definition at line 1135 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_PAYLOAD_DIR_16_BIT

#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_DIR_16_BIT   20

Definition at line 1153 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_FIELD

#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_OFFSET })

Definition at line 1151 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_MASK

#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_MASK   0xfu

Definition at line 1149 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_OFFSET

#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_OFFSET   16

Definition at line 1150 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_PAYLOAD_SWAP_EN_16_BIT

#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_SWAP_EN_16_BIT   21

Definition at line 1154 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_FIELD

#define SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_OFFSET })

Definition at line 1157 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_MASK

#define SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_MASK   0x3u

Definition at line 1155 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_OFFSET

#define SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_OFFSET   22

Definition at line 1156 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_16_REG_OFFSET   0xbc

Definition at line 1132 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_16_REG_RESVAL   0x7000u

Definition at line 1133 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_UPLOAD_16_BIT

#define SPI_DEVICE_CMD_INFO_16_UPLOAD_16_BIT   24

Definition at line 1159 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_16_VALID_16_BIT

#define SPI_DEVICE_CMD_INFO_16_VALID_16_BIT   31

Definition at line 1161 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_FIELD

#define SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_OFFSET })

Definition at line 1172 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_MASK

#define SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_MASK   0x3u

Definition at line 1170 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_OFFSET

#define SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_OFFSET   8

Definition at line 1171 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_ADDR_SWAP_EN_17_BIT

#define SPI_DEVICE_CMD_INFO_17_ADDR_SWAP_EN_17_BIT   10

Definition at line 1174 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_BUSY_17_BIT

#define SPI_DEVICE_CMD_INFO_17_BUSY_17_BIT   25

Definition at line 1192 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_DUMMY_EN_17_BIT

#define SPI_DEVICE_CMD_INFO_17_DUMMY_EN_17_BIT   15

Definition at line 1180 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_FIELD

#define SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_OFFSET })

Definition at line 1178 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_MASK

#define SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_MASK   0x7u

Definition at line 1176 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_OFFSET

#define SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_OFFSET   12

Definition at line 1177 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_MBYTE_EN_17_BIT

#define SPI_DEVICE_CMD_INFO_17_MBYTE_EN_17_BIT   11

Definition at line 1175 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_OPCODE_17_FIELD

#define SPI_DEVICE_CMD_INFO_17_OPCODE_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_OPCODE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_OPCODE_17_OFFSET })

Definition at line 1168 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_OPCODE_17_MASK

#define SPI_DEVICE_CMD_INFO_17_OPCODE_17_MASK   0xffu

Definition at line 1166 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_OPCODE_17_OFFSET

#define SPI_DEVICE_CMD_INFO_17_OPCODE_17_OFFSET   0

Definition at line 1167 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_PAYLOAD_DIR_17_BIT

#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_DIR_17_BIT   20

Definition at line 1185 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_FIELD

#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_OFFSET })

Definition at line 1183 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_MASK

#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_MASK   0xfu

Definition at line 1181 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_OFFSET

#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_OFFSET   16

Definition at line 1182 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_PAYLOAD_SWAP_EN_17_BIT

#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_SWAP_EN_17_BIT   21

Definition at line 1186 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_FIELD

#define SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_OFFSET })

Definition at line 1189 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_MASK

#define SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_MASK   0x3u

Definition at line 1187 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_OFFSET

#define SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_OFFSET   22

Definition at line 1188 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_17_REG_OFFSET   0xc0

Definition at line 1164 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_17_REG_RESVAL   0x7000u

Definition at line 1165 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_UPLOAD_17_BIT

#define SPI_DEVICE_CMD_INFO_17_UPLOAD_17_BIT   24

Definition at line 1191 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_17_VALID_17_BIT

#define SPI_DEVICE_CMD_INFO_17_VALID_17_BIT   31

Definition at line 1193 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_FIELD

#define SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_OFFSET })

Definition at line 1204 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_MASK

#define SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_MASK   0x3u

Definition at line 1202 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_OFFSET

#define SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_OFFSET   8

Definition at line 1203 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_ADDR_SWAP_EN_18_BIT

#define SPI_DEVICE_CMD_INFO_18_ADDR_SWAP_EN_18_BIT   10

Definition at line 1206 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_BUSY_18_BIT

#define SPI_DEVICE_CMD_INFO_18_BUSY_18_BIT   25

Definition at line 1224 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_DUMMY_EN_18_BIT

#define SPI_DEVICE_CMD_INFO_18_DUMMY_EN_18_BIT   15

Definition at line 1212 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_FIELD

#define SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_OFFSET })

Definition at line 1210 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_MASK

#define SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_MASK   0x7u

Definition at line 1208 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_OFFSET

#define SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_OFFSET   12

Definition at line 1209 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_MBYTE_EN_18_BIT

#define SPI_DEVICE_CMD_INFO_18_MBYTE_EN_18_BIT   11

Definition at line 1207 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_OPCODE_18_FIELD

#define SPI_DEVICE_CMD_INFO_18_OPCODE_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_OPCODE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_OPCODE_18_OFFSET })

Definition at line 1200 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_OPCODE_18_MASK

#define SPI_DEVICE_CMD_INFO_18_OPCODE_18_MASK   0xffu

Definition at line 1198 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_OPCODE_18_OFFSET

#define SPI_DEVICE_CMD_INFO_18_OPCODE_18_OFFSET   0

Definition at line 1199 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_PAYLOAD_DIR_18_BIT

#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_DIR_18_BIT   20

Definition at line 1217 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_FIELD

#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_OFFSET })

Definition at line 1215 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_MASK

#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_MASK   0xfu

Definition at line 1213 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_OFFSET

#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_OFFSET   16

Definition at line 1214 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_PAYLOAD_SWAP_EN_18_BIT

#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_SWAP_EN_18_BIT   21

Definition at line 1218 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_FIELD

#define SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_OFFSET })

Definition at line 1221 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_MASK

#define SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_MASK   0x3u

Definition at line 1219 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_OFFSET

#define SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_OFFSET   22

Definition at line 1220 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_18_REG_OFFSET   0xc4

Definition at line 1196 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_18_REG_RESVAL   0x7000u

Definition at line 1197 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_UPLOAD_18_BIT

#define SPI_DEVICE_CMD_INFO_18_UPLOAD_18_BIT   24

Definition at line 1223 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_18_VALID_18_BIT

#define SPI_DEVICE_CMD_INFO_18_VALID_18_BIT   31

Definition at line 1225 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_FIELD

#define SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_OFFSET })

Definition at line 1236 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_MASK

#define SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_MASK   0x3u

Definition at line 1234 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_OFFSET

#define SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_OFFSET   8

Definition at line 1235 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_ADDR_SWAP_EN_19_BIT

#define SPI_DEVICE_CMD_INFO_19_ADDR_SWAP_EN_19_BIT   10

Definition at line 1238 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_BUSY_19_BIT

#define SPI_DEVICE_CMD_INFO_19_BUSY_19_BIT   25

Definition at line 1256 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_DUMMY_EN_19_BIT

#define SPI_DEVICE_CMD_INFO_19_DUMMY_EN_19_BIT   15

Definition at line 1244 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_FIELD

#define SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_OFFSET })

Definition at line 1242 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_MASK

#define SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_MASK   0x7u

Definition at line 1240 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_OFFSET

#define SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_OFFSET   12

Definition at line 1241 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_MBYTE_EN_19_BIT

#define SPI_DEVICE_CMD_INFO_19_MBYTE_EN_19_BIT   11

Definition at line 1239 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_OPCODE_19_FIELD

#define SPI_DEVICE_CMD_INFO_19_OPCODE_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_OPCODE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_OPCODE_19_OFFSET })

Definition at line 1232 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_OPCODE_19_MASK

#define SPI_DEVICE_CMD_INFO_19_OPCODE_19_MASK   0xffu

Definition at line 1230 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_OPCODE_19_OFFSET

#define SPI_DEVICE_CMD_INFO_19_OPCODE_19_OFFSET   0

Definition at line 1231 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_PAYLOAD_DIR_19_BIT

#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_DIR_19_BIT   20

Definition at line 1249 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_FIELD

#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_OFFSET })

Definition at line 1247 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_MASK

#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_MASK   0xfu

Definition at line 1245 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_OFFSET

#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_OFFSET   16

Definition at line 1246 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_PAYLOAD_SWAP_EN_19_BIT

#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_SWAP_EN_19_BIT   21

Definition at line 1250 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_FIELD

#define SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_OFFSET })

Definition at line 1253 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_MASK

#define SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_MASK   0x3u

Definition at line 1251 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_OFFSET

#define SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_OFFSET   22

Definition at line 1252 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_19_REG_OFFSET   0xc8

Definition at line 1228 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_19_REG_RESVAL   0x7000u

Definition at line 1229 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_UPLOAD_19_BIT

#define SPI_DEVICE_CMD_INFO_19_UPLOAD_19_BIT   24

Definition at line 1255 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_19_VALID_19_BIT

#define SPI_DEVICE_CMD_INFO_19_VALID_19_BIT   31

Definition at line 1257 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_FIELD

#define SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_OFFSET })

Definition at line 660 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_MASK

#define SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_MASK   0x3u

Definition at line 658 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_OFFSET

#define SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_OFFSET   8

Definition at line 659 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_ADDR_SWAP_EN_1_BIT

#define SPI_DEVICE_CMD_INFO_1_ADDR_SWAP_EN_1_BIT   10

Definition at line 662 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_BUSY_1_BIT

#define SPI_DEVICE_CMD_INFO_1_BUSY_1_BIT   25

Definition at line 680 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_DUMMY_EN_1_BIT

#define SPI_DEVICE_CMD_INFO_1_DUMMY_EN_1_BIT   15

Definition at line 668 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_FIELD

#define SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_OFFSET })

Definition at line 666 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_MASK

#define SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_MASK   0x7u

Definition at line 664 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_OFFSET

#define SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_OFFSET   12

Definition at line 665 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_MBYTE_EN_1_BIT

#define SPI_DEVICE_CMD_INFO_1_MBYTE_EN_1_BIT   11

Definition at line 663 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_OPCODE_1_FIELD

#define SPI_DEVICE_CMD_INFO_1_OPCODE_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_OPCODE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_OPCODE_1_OFFSET })

Definition at line 656 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_OPCODE_1_MASK

#define SPI_DEVICE_CMD_INFO_1_OPCODE_1_MASK   0xffu

Definition at line 654 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_OPCODE_1_OFFSET

#define SPI_DEVICE_CMD_INFO_1_OPCODE_1_OFFSET   0

Definition at line 655 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_PAYLOAD_DIR_1_BIT

#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_DIR_1_BIT   20

Definition at line 673 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_FIELD

#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_OFFSET })

Definition at line 671 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_MASK

#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_MASK   0xfu

Definition at line 669 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_OFFSET

#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_OFFSET   16

Definition at line 670 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_PAYLOAD_SWAP_EN_1_BIT

#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_SWAP_EN_1_BIT   21

Definition at line 674 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_FIELD

#define SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_OFFSET })

Definition at line 677 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_MASK

#define SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_MASK   0x3u

Definition at line 675 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_OFFSET

#define SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_OFFSET   22

Definition at line 676 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_1_REG_OFFSET   0x80

Definition at line 652 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_1_REG_RESVAL   0x7000u

Definition at line 653 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_UPLOAD_1_BIT

#define SPI_DEVICE_CMD_INFO_1_UPLOAD_1_BIT   24

Definition at line 679 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_1_VALID_1_BIT

#define SPI_DEVICE_CMD_INFO_1_VALID_1_BIT   31

Definition at line 681 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_FIELD

#define SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_OFFSET })

Definition at line 1268 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_MASK

#define SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_MASK   0x3u

Definition at line 1266 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_OFFSET

#define SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_OFFSET   8

Definition at line 1267 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_ADDR_SWAP_EN_20_BIT

#define SPI_DEVICE_CMD_INFO_20_ADDR_SWAP_EN_20_BIT   10

Definition at line 1270 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_BUSY_20_BIT

#define SPI_DEVICE_CMD_INFO_20_BUSY_20_BIT   25

Definition at line 1288 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_DUMMY_EN_20_BIT

#define SPI_DEVICE_CMD_INFO_20_DUMMY_EN_20_BIT   15

Definition at line 1276 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_FIELD

#define SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_OFFSET })

Definition at line 1274 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_MASK

#define SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_MASK   0x7u

Definition at line 1272 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_OFFSET

#define SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_OFFSET   12

Definition at line 1273 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_MBYTE_EN_20_BIT

#define SPI_DEVICE_CMD_INFO_20_MBYTE_EN_20_BIT   11

Definition at line 1271 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_OPCODE_20_FIELD

#define SPI_DEVICE_CMD_INFO_20_OPCODE_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_OPCODE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_OPCODE_20_OFFSET })

Definition at line 1264 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_OPCODE_20_MASK

#define SPI_DEVICE_CMD_INFO_20_OPCODE_20_MASK   0xffu

Definition at line 1262 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_OPCODE_20_OFFSET

#define SPI_DEVICE_CMD_INFO_20_OPCODE_20_OFFSET   0

Definition at line 1263 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_PAYLOAD_DIR_20_BIT

#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_DIR_20_BIT   20

Definition at line 1281 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_FIELD

#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_OFFSET })

Definition at line 1279 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_MASK

#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_MASK   0xfu

Definition at line 1277 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_OFFSET

#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_OFFSET   16

Definition at line 1278 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_PAYLOAD_SWAP_EN_20_BIT

#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_SWAP_EN_20_BIT   21

Definition at line 1282 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_FIELD

#define SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_OFFSET })

Definition at line 1285 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_MASK

#define SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_MASK   0x3u

Definition at line 1283 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_OFFSET

#define SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_OFFSET   22

Definition at line 1284 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_20_REG_OFFSET   0xcc

Definition at line 1260 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_20_REG_RESVAL   0x7000u

Definition at line 1261 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_UPLOAD_20_BIT

#define SPI_DEVICE_CMD_INFO_20_UPLOAD_20_BIT   24

Definition at line 1287 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_20_VALID_20_BIT

#define SPI_DEVICE_CMD_INFO_20_VALID_20_BIT   31

Definition at line 1289 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_FIELD

#define SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_OFFSET })

Definition at line 1300 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_MASK

#define SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_MASK   0x3u

Definition at line 1298 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_OFFSET

#define SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_OFFSET   8

Definition at line 1299 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_ADDR_SWAP_EN_21_BIT

#define SPI_DEVICE_CMD_INFO_21_ADDR_SWAP_EN_21_BIT   10

Definition at line 1302 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_BUSY_21_BIT

#define SPI_DEVICE_CMD_INFO_21_BUSY_21_BIT   25

Definition at line 1320 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_DUMMY_EN_21_BIT

#define SPI_DEVICE_CMD_INFO_21_DUMMY_EN_21_BIT   15

Definition at line 1308 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_FIELD

#define SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_OFFSET })

Definition at line 1306 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_MASK

#define SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_MASK   0x7u

Definition at line 1304 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_OFFSET

#define SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_OFFSET   12

Definition at line 1305 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_MBYTE_EN_21_BIT

#define SPI_DEVICE_CMD_INFO_21_MBYTE_EN_21_BIT   11

Definition at line 1303 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_OPCODE_21_FIELD

#define SPI_DEVICE_CMD_INFO_21_OPCODE_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_OPCODE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_OPCODE_21_OFFSET })

Definition at line 1296 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_OPCODE_21_MASK

#define SPI_DEVICE_CMD_INFO_21_OPCODE_21_MASK   0xffu

Definition at line 1294 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_OPCODE_21_OFFSET

#define SPI_DEVICE_CMD_INFO_21_OPCODE_21_OFFSET   0

Definition at line 1295 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_PAYLOAD_DIR_21_BIT

#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_DIR_21_BIT   20

Definition at line 1313 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_FIELD

#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_OFFSET })

Definition at line 1311 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_MASK

#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_MASK   0xfu

Definition at line 1309 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_OFFSET

#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_OFFSET   16

Definition at line 1310 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_PAYLOAD_SWAP_EN_21_BIT

#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_SWAP_EN_21_BIT   21

Definition at line 1314 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_FIELD

#define SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_OFFSET })

Definition at line 1317 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_MASK

#define SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_MASK   0x3u

Definition at line 1315 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_OFFSET

#define SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_OFFSET   22

Definition at line 1316 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_21_REG_OFFSET   0xd0

Definition at line 1292 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_21_REG_RESVAL   0x7000u

Definition at line 1293 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_UPLOAD_21_BIT

#define SPI_DEVICE_CMD_INFO_21_UPLOAD_21_BIT   24

Definition at line 1319 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_21_VALID_21_BIT

#define SPI_DEVICE_CMD_INFO_21_VALID_21_BIT   31

Definition at line 1321 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_FIELD

#define SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_OFFSET })

Definition at line 1332 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_MASK

#define SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_MASK   0x3u

Definition at line 1330 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_OFFSET

#define SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_OFFSET   8

Definition at line 1331 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_ADDR_SWAP_EN_22_BIT

#define SPI_DEVICE_CMD_INFO_22_ADDR_SWAP_EN_22_BIT   10

Definition at line 1334 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_BUSY_22_BIT

#define SPI_DEVICE_CMD_INFO_22_BUSY_22_BIT   25

Definition at line 1352 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_DUMMY_EN_22_BIT

#define SPI_DEVICE_CMD_INFO_22_DUMMY_EN_22_BIT   15

Definition at line 1340 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_FIELD

#define SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_OFFSET })

Definition at line 1338 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_MASK

#define SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_MASK   0x7u

Definition at line 1336 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_OFFSET

#define SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_OFFSET   12

Definition at line 1337 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_MBYTE_EN_22_BIT

#define SPI_DEVICE_CMD_INFO_22_MBYTE_EN_22_BIT   11

Definition at line 1335 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_OPCODE_22_FIELD

#define SPI_DEVICE_CMD_INFO_22_OPCODE_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_OPCODE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_OPCODE_22_OFFSET })

Definition at line 1328 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_OPCODE_22_MASK

#define SPI_DEVICE_CMD_INFO_22_OPCODE_22_MASK   0xffu

Definition at line 1326 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_OPCODE_22_OFFSET

#define SPI_DEVICE_CMD_INFO_22_OPCODE_22_OFFSET   0

Definition at line 1327 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_PAYLOAD_DIR_22_BIT

#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_DIR_22_BIT   20

Definition at line 1345 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_FIELD

#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_OFFSET })

Definition at line 1343 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_MASK

#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_MASK   0xfu

Definition at line 1341 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_OFFSET

#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_OFFSET   16

Definition at line 1342 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_PAYLOAD_SWAP_EN_22_BIT

#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_SWAP_EN_22_BIT   21

Definition at line 1346 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_FIELD

#define SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_OFFSET })

Definition at line 1349 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_MASK

#define SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_MASK   0x3u

Definition at line 1347 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_OFFSET

#define SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_OFFSET   22

Definition at line 1348 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_22_REG_OFFSET   0xd4

Definition at line 1324 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_22_REG_RESVAL   0x7000u

Definition at line 1325 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_UPLOAD_22_BIT

#define SPI_DEVICE_CMD_INFO_22_UPLOAD_22_BIT   24

Definition at line 1351 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_22_VALID_22_BIT

#define SPI_DEVICE_CMD_INFO_22_VALID_22_BIT   31

Definition at line 1353 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_FIELD

#define SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_OFFSET })

Definition at line 1364 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_MASK

#define SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_MASK   0x3u

Definition at line 1362 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_OFFSET

#define SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_OFFSET   8

Definition at line 1363 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_ADDR_SWAP_EN_23_BIT

#define SPI_DEVICE_CMD_INFO_23_ADDR_SWAP_EN_23_BIT   10

Definition at line 1366 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_BUSY_23_BIT

#define SPI_DEVICE_CMD_INFO_23_BUSY_23_BIT   25

Definition at line 1384 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_DUMMY_EN_23_BIT

#define SPI_DEVICE_CMD_INFO_23_DUMMY_EN_23_BIT   15

Definition at line 1372 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_FIELD

#define SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_OFFSET })

Definition at line 1370 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_MASK

#define SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_MASK   0x7u

Definition at line 1368 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_OFFSET

#define SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_OFFSET   12

Definition at line 1369 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_MBYTE_EN_23_BIT

#define SPI_DEVICE_CMD_INFO_23_MBYTE_EN_23_BIT   11

Definition at line 1367 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_OPCODE_23_FIELD

#define SPI_DEVICE_CMD_INFO_23_OPCODE_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_OPCODE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_OPCODE_23_OFFSET })

Definition at line 1360 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_OPCODE_23_MASK

#define SPI_DEVICE_CMD_INFO_23_OPCODE_23_MASK   0xffu

Definition at line 1358 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_OPCODE_23_OFFSET

#define SPI_DEVICE_CMD_INFO_23_OPCODE_23_OFFSET   0

Definition at line 1359 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_PAYLOAD_DIR_23_BIT

#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_DIR_23_BIT   20

Definition at line 1377 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_FIELD

#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_OFFSET })

Definition at line 1375 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_MASK

#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_MASK   0xfu

Definition at line 1373 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_OFFSET

#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_OFFSET   16

Definition at line 1374 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_PAYLOAD_SWAP_EN_23_BIT

#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_SWAP_EN_23_BIT   21

Definition at line 1378 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_FIELD

#define SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_OFFSET })

Definition at line 1381 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_MASK

#define SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_MASK   0x3u

Definition at line 1379 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_OFFSET

#define SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_OFFSET   22

Definition at line 1380 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_23_REG_OFFSET   0xd8

Definition at line 1356 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_23_REG_RESVAL   0x7000u

Definition at line 1357 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_UPLOAD_23_BIT

#define SPI_DEVICE_CMD_INFO_23_UPLOAD_23_BIT   24

Definition at line 1383 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_23_VALID_23_BIT

#define SPI_DEVICE_CMD_INFO_23_VALID_23_BIT   31

Definition at line 1385 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_FIELD

#define SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_OFFSET })

Definition at line 692 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_MASK

#define SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_MASK   0x3u

Definition at line 690 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_OFFSET

#define SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_OFFSET   8

Definition at line 691 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_ADDR_SWAP_EN_2_BIT

#define SPI_DEVICE_CMD_INFO_2_ADDR_SWAP_EN_2_BIT   10

Definition at line 694 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_BUSY_2_BIT

#define SPI_DEVICE_CMD_INFO_2_BUSY_2_BIT   25

Definition at line 712 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_DUMMY_EN_2_BIT

#define SPI_DEVICE_CMD_INFO_2_DUMMY_EN_2_BIT   15

Definition at line 700 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_FIELD

#define SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_OFFSET })

Definition at line 698 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_MASK

#define SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_MASK   0x7u

Definition at line 696 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_OFFSET

#define SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_OFFSET   12

Definition at line 697 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_MBYTE_EN_2_BIT

#define SPI_DEVICE_CMD_INFO_2_MBYTE_EN_2_BIT   11

Definition at line 695 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_OPCODE_2_FIELD

#define SPI_DEVICE_CMD_INFO_2_OPCODE_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_OPCODE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_OPCODE_2_OFFSET })

Definition at line 688 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_OPCODE_2_MASK

#define SPI_DEVICE_CMD_INFO_2_OPCODE_2_MASK   0xffu

Definition at line 686 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_OPCODE_2_OFFSET

#define SPI_DEVICE_CMD_INFO_2_OPCODE_2_OFFSET   0

Definition at line 687 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_PAYLOAD_DIR_2_BIT

#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_DIR_2_BIT   20

Definition at line 705 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_FIELD

#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_OFFSET })

Definition at line 703 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_MASK

#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_MASK   0xfu

Definition at line 701 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_OFFSET

#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_OFFSET   16

Definition at line 702 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_PAYLOAD_SWAP_EN_2_BIT

#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_SWAP_EN_2_BIT   21

Definition at line 706 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_FIELD

#define SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_OFFSET })

Definition at line 709 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_MASK

#define SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_MASK   0x3u

Definition at line 707 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_OFFSET

#define SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_OFFSET   22

Definition at line 708 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_2_REG_OFFSET   0x84

Definition at line 684 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_2_REG_RESVAL   0x7000u

Definition at line 685 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_UPLOAD_2_BIT

#define SPI_DEVICE_CMD_INFO_2_UPLOAD_2_BIT   24

Definition at line 711 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_2_VALID_2_BIT

#define SPI_DEVICE_CMD_INFO_2_VALID_2_BIT   31

Definition at line 713 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_FIELD

#define SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_OFFSET })

Definition at line 724 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_MASK

#define SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_MASK   0x3u

Definition at line 722 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_OFFSET

#define SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_OFFSET   8

Definition at line 723 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_ADDR_SWAP_EN_3_BIT

#define SPI_DEVICE_CMD_INFO_3_ADDR_SWAP_EN_3_BIT   10

Definition at line 726 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_BUSY_3_BIT

#define SPI_DEVICE_CMD_INFO_3_BUSY_3_BIT   25

Definition at line 744 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_DUMMY_EN_3_BIT

#define SPI_DEVICE_CMD_INFO_3_DUMMY_EN_3_BIT   15

Definition at line 732 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_FIELD

#define SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_OFFSET })

Definition at line 730 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_MASK

#define SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_MASK   0x7u

Definition at line 728 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_OFFSET

#define SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_OFFSET   12

Definition at line 729 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_MBYTE_EN_3_BIT

#define SPI_DEVICE_CMD_INFO_3_MBYTE_EN_3_BIT   11

Definition at line 727 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_OPCODE_3_FIELD

#define SPI_DEVICE_CMD_INFO_3_OPCODE_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_OPCODE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_OPCODE_3_OFFSET })

Definition at line 720 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_OPCODE_3_MASK

#define SPI_DEVICE_CMD_INFO_3_OPCODE_3_MASK   0xffu

Definition at line 718 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_OPCODE_3_OFFSET

#define SPI_DEVICE_CMD_INFO_3_OPCODE_3_OFFSET   0

Definition at line 719 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_PAYLOAD_DIR_3_BIT

#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_DIR_3_BIT   20

Definition at line 737 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_FIELD

#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_OFFSET })

Definition at line 735 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_MASK

#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_MASK   0xfu

Definition at line 733 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_OFFSET

#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_OFFSET   16

Definition at line 734 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_PAYLOAD_SWAP_EN_3_BIT

#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_SWAP_EN_3_BIT   21

Definition at line 738 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_FIELD

#define SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_OFFSET })

Definition at line 741 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_MASK

#define SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_MASK   0x3u

Definition at line 739 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_OFFSET

#define SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_OFFSET   22

Definition at line 740 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_3_REG_OFFSET   0x88

Definition at line 716 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_3_REG_RESVAL   0x7000u

Definition at line 717 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_UPLOAD_3_BIT

#define SPI_DEVICE_CMD_INFO_3_UPLOAD_3_BIT   24

Definition at line 743 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_3_VALID_3_BIT

#define SPI_DEVICE_CMD_INFO_3_VALID_3_BIT   31

Definition at line 745 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_FIELD

#define SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_OFFSET })

Definition at line 756 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_MASK

#define SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_MASK   0x3u

Definition at line 754 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_OFFSET

#define SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_OFFSET   8

Definition at line 755 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_ADDR_SWAP_EN_4_BIT

#define SPI_DEVICE_CMD_INFO_4_ADDR_SWAP_EN_4_BIT   10

Definition at line 758 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_BUSY_4_BIT

#define SPI_DEVICE_CMD_INFO_4_BUSY_4_BIT   25

Definition at line 776 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_DUMMY_EN_4_BIT

#define SPI_DEVICE_CMD_INFO_4_DUMMY_EN_4_BIT   15

Definition at line 764 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_FIELD

#define SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_OFFSET })

Definition at line 762 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_MASK

#define SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_MASK   0x7u

Definition at line 760 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_OFFSET

#define SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_OFFSET   12

Definition at line 761 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_MBYTE_EN_4_BIT

#define SPI_DEVICE_CMD_INFO_4_MBYTE_EN_4_BIT   11

Definition at line 759 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_OPCODE_4_FIELD

#define SPI_DEVICE_CMD_INFO_4_OPCODE_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_OPCODE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_OPCODE_4_OFFSET })

Definition at line 752 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_OPCODE_4_MASK

#define SPI_DEVICE_CMD_INFO_4_OPCODE_4_MASK   0xffu

Definition at line 750 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_OPCODE_4_OFFSET

#define SPI_DEVICE_CMD_INFO_4_OPCODE_4_OFFSET   0

Definition at line 751 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_PAYLOAD_DIR_4_BIT

#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_DIR_4_BIT   20

Definition at line 769 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_FIELD

#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_OFFSET })

Definition at line 767 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_MASK

#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_MASK   0xfu

Definition at line 765 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_OFFSET

#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_OFFSET   16

Definition at line 766 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_PAYLOAD_SWAP_EN_4_BIT

#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_SWAP_EN_4_BIT   21

Definition at line 770 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_FIELD

#define SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_OFFSET })

Definition at line 773 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_MASK

#define SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_MASK   0x3u

Definition at line 771 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_OFFSET

#define SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_OFFSET   22

Definition at line 772 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_4_REG_OFFSET   0x8c

Definition at line 748 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_4_REG_RESVAL   0x7000u

Definition at line 749 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_UPLOAD_4_BIT

#define SPI_DEVICE_CMD_INFO_4_UPLOAD_4_BIT   24

Definition at line 775 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_4_VALID_4_BIT

#define SPI_DEVICE_CMD_INFO_4_VALID_4_BIT   31

Definition at line 777 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_FIELD

#define SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_OFFSET })

Definition at line 788 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_MASK

#define SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_MASK   0x3u

Definition at line 786 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_OFFSET

#define SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_OFFSET   8

Definition at line 787 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_ADDR_SWAP_EN_5_BIT

#define SPI_DEVICE_CMD_INFO_5_ADDR_SWAP_EN_5_BIT   10

Definition at line 790 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_BUSY_5_BIT

#define SPI_DEVICE_CMD_INFO_5_BUSY_5_BIT   25

Definition at line 808 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_DUMMY_EN_5_BIT

#define SPI_DEVICE_CMD_INFO_5_DUMMY_EN_5_BIT   15

Definition at line 796 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_FIELD

#define SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_OFFSET })

Definition at line 794 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_MASK

#define SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_MASK   0x7u

Definition at line 792 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_OFFSET

#define SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_OFFSET   12

Definition at line 793 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_MBYTE_EN_5_BIT

#define SPI_DEVICE_CMD_INFO_5_MBYTE_EN_5_BIT   11

Definition at line 791 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_OPCODE_5_FIELD

#define SPI_DEVICE_CMD_INFO_5_OPCODE_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_OPCODE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_OPCODE_5_OFFSET })

Definition at line 784 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_OPCODE_5_MASK

#define SPI_DEVICE_CMD_INFO_5_OPCODE_5_MASK   0xffu

Definition at line 782 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_OPCODE_5_OFFSET

#define SPI_DEVICE_CMD_INFO_5_OPCODE_5_OFFSET   0

Definition at line 783 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_PAYLOAD_DIR_5_BIT

#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_DIR_5_BIT   20

Definition at line 801 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_FIELD

#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_OFFSET })

Definition at line 799 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_MASK

#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_MASK   0xfu

Definition at line 797 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_OFFSET

#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_OFFSET   16

Definition at line 798 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_PAYLOAD_SWAP_EN_5_BIT

#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_SWAP_EN_5_BIT   21

Definition at line 802 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_FIELD

#define SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_OFFSET })

Definition at line 805 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_MASK

#define SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_MASK   0x3u

Definition at line 803 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_OFFSET

#define SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_OFFSET   22

Definition at line 804 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_5_REG_OFFSET   0x90

Definition at line 780 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_5_REG_RESVAL   0x7000u

Definition at line 781 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_UPLOAD_5_BIT

#define SPI_DEVICE_CMD_INFO_5_UPLOAD_5_BIT   24

Definition at line 807 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_5_VALID_5_BIT

#define SPI_DEVICE_CMD_INFO_5_VALID_5_BIT   31

Definition at line 809 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_FIELD

#define SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_OFFSET })

Definition at line 820 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_MASK

#define SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_MASK   0x3u

Definition at line 818 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_OFFSET

#define SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_OFFSET   8

Definition at line 819 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_ADDR_SWAP_EN_6_BIT

#define SPI_DEVICE_CMD_INFO_6_ADDR_SWAP_EN_6_BIT   10

Definition at line 822 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_BUSY_6_BIT

#define SPI_DEVICE_CMD_INFO_6_BUSY_6_BIT   25

Definition at line 840 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_DUMMY_EN_6_BIT

#define SPI_DEVICE_CMD_INFO_6_DUMMY_EN_6_BIT   15

Definition at line 828 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_FIELD

#define SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_OFFSET })

Definition at line 826 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_MASK

#define SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_MASK   0x7u

Definition at line 824 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_OFFSET

#define SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_OFFSET   12

Definition at line 825 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_MBYTE_EN_6_BIT

#define SPI_DEVICE_CMD_INFO_6_MBYTE_EN_6_BIT   11

Definition at line 823 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_OPCODE_6_FIELD

#define SPI_DEVICE_CMD_INFO_6_OPCODE_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_OPCODE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_OPCODE_6_OFFSET })

Definition at line 816 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_OPCODE_6_MASK

#define SPI_DEVICE_CMD_INFO_6_OPCODE_6_MASK   0xffu

Definition at line 814 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_OPCODE_6_OFFSET

#define SPI_DEVICE_CMD_INFO_6_OPCODE_6_OFFSET   0

Definition at line 815 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_PAYLOAD_DIR_6_BIT

#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_DIR_6_BIT   20

Definition at line 833 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_FIELD

#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_OFFSET })

Definition at line 831 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_MASK

#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_MASK   0xfu

Definition at line 829 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_OFFSET

#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_OFFSET   16

Definition at line 830 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_PAYLOAD_SWAP_EN_6_BIT

#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_SWAP_EN_6_BIT   21

Definition at line 834 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_FIELD

#define SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_OFFSET })

Definition at line 837 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_MASK

#define SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_MASK   0x3u

Definition at line 835 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_OFFSET

#define SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_OFFSET   22

Definition at line 836 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_6_REG_OFFSET   0x94

Definition at line 812 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_6_REG_RESVAL   0x7000u

Definition at line 813 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_UPLOAD_6_BIT

#define SPI_DEVICE_CMD_INFO_6_UPLOAD_6_BIT   24

Definition at line 839 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_6_VALID_6_BIT

#define SPI_DEVICE_CMD_INFO_6_VALID_6_BIT   31

Definition at line 841 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_FIELD

#define SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_OFFSET })

Definition at line 852 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_MASK

#define SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_MASK   0x3u

Definition at line 850 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_OFFSET

#define SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_OFFSET   8

Definition at line 851 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_ADDR_SWAP_EN_7_BIT

#define SPI_DEVICE_CMD_INFO_7_ADDR_SWAP_EN_7_BIT   10

Definition at line 854 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_BUSY_7_BIT

#define SPI_DEVICE_CMD_INFO_7_BUSY_7_BIT   25

Definition at line 872 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_DUMMY_EN_7_BIT

#define SPI_DEVICE_CMD_INFO_7_DUMMY_EN_7_BIT   15

Definition at line 860 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_FIELD

#define SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_OFFSET })

Definition at line 858 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_MASK

#define SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_MASK   0x7u

Definition at line 856 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_OFFSET

#define SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_OFFSET   12

Definition at line 857 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_MBYTE_EN_7_BIT

#define SPI_DEVICE_CMD_INFO_7_MBYTE_EN_7_BIT   11

Definition at line 855 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_OPCODE_7_FIELD

#define SPI_DEVICE_CMD_INFO_7_OPCODE_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_OPCODE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_OPCODE_7_OFFSET })

Definition at line 848 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_OPCODE_7_MASK

#define SPI_DEVICE_CMD_INFO_7_OPCODE_7_MASK   0xffu

Definition at line 846 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_OPCODE_7_OFFSET

#define SPI_DEVICE_CMD_INFO_7_OPCODE_7_OFFSET   0

Definition at line 847 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_PAYLOAD_DIR_7_BIT

#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_DIR_7_BIT   20

Definition at line 865 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_FIELD

#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_OFFSET })

Definition at line 863 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_MASK

#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_MASK   0xfu

Definition at line 861 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_OFFSET

#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_OFFSET   16

Definition at line 862 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_PAYLOAD_SWAP_EN_7_BIT

#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_SWAP_EN_7_BIT   21

Definition at line 866 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_FIELD

#define SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_OFFSET })

Definition at line 869 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_MASK

#define SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_MASK   0x3u

Definition at line 867 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_OFFSET

#define SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_OFFSET   22

Definition at line 868 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_7_REG_OFFSET   0x98

Definition at line 844 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_7_REG_RESVAL   0x7000u

Definition at line 845 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_UPLOAD_7_BIT

#define SPI_DEVICE_CMD_INFO_7_UPLOAD_7_BIT   24

Definition at line 871 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_7_VALID_7_BIT

#define SPI_DEVICE_CMD_INFO_7_VALID_7_BIT   31

Definition at line 873 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_FIELD

#define SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_OFFSET })

Definition at line 884 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_MASK

#define SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_MASK   0x3u

Definition at line 882 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_OFFSET

#define SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_OFFSET   8

Definition at line 883 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_ADDR_SWAP_EN_8_BIT

#define SPI_DEVICE_CMD_INFO_8_ADDR_SWAP_EN_8_BIT   10

Definition at line 886 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_BUSY_8_BIT

#define SPI_DEVICE_CMD_INFO_8_BUSY_8_BIT   25

Definition at line 904 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_DUMMY_EN_8_BIT

#define SPI_DEVICE_CMD_INFO_8_DUMMY_EN_8_BIT   15

Definition at line 892 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_FIELD

#define SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_OFFSET })

Definition at line 890 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_MASK

#define SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_MASK   0x7u

Definition at line 888 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_OFFSET

#define SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_OFFSET   12

Definition at line 889 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_MBYTE_EN_8_BIT

#define SPI_DEVICE_CMD_INFO_8_MBYTE_EN_8_BIT   11

Definition at line 887 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_OPCODE_8_FIELD

#define SPI_DEVICE_CMD_INFO_8_OPCODE_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_OPCODE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_OPCODE_8_OFFSET })

Definition at line 880 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_OPCODE_8_MASK

#define SPI_DEVICE_CMD_INFO_8_OPCODE_8_MASK   0xffu

Definition at line 878 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_OPCODE_8_OFFSET

#define SPI_DEVICE_CMD_INFO_8_OPCODE_8_OFFSET   0

Definition at line 879 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_PAYLOAD_DIR_8_BIT

#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_DIR_8_BIT   20

Definition at line 897 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_FIELD

#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_OFFSET })

Definition at line 895 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_MASK

#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_MASK   0xfu

Definition at line 893 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_OFFSET

#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_OFFSET   16

Definition at line 894 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_PAYLOAD_SWAP_EN_8_BIT

#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_SWAP_EN_8_BIT   21

Definition at line 898 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_FIELD

#define SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_OFFSET })

Definition at line 901 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_MASK

#define SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_MASK   0x3u

Definition at line 899 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_OFFSET

#define SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_OFFSET   22

Definition at line 900 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_8_REG_OFFSET   0x9c

Definition at line 876 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_8_REG_RESVAL   0x7000u

Definition at line 877 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_UPLOAD_8_BIT

#define SPI_DEVICE_CMD_INFO_8_UPLOAD_8_BIT   24

Definition at line 903 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_8_VALID_8_BIT

#define SPI_DEVICE_CMD_INFO_8_VALID_8_BIT   31

Definition at line 905 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_FIELD

#define SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_OFFSET })

Definition at line 916 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_MASK

#define SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_MASK   0x3u

Definition at line 914 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_OFFSET

#define SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_OFFSET   8

Definition at line 915 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_ADDR_SWAP_EN_9_BIT

#define SPI_DEVICE_CMD_INFO_9_ADDR_SWAP_EN_9_BIT   10

Definition at line 918 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_BUSY_9_BIT

#define SPI_DEVICE_CMD_INFO_9_BUSY_9_BIT   25

Definition at line 936 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_DUMMY_EN_9_BIT

#define SPI_DEVICE_CMD_INFO_9_DUMMY_EN_9_BIT   15

Definition at line 924 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_FIELD

#define SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_OFFSET })

Definition at line 922 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_MASK

#define SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_MASK   0x7u

Definition at line 920 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_OFFSET

#define SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_OFFSET   12

Definition at line 921 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_MBYTE_EN_9_BIT

#define SPI_DEVICE_CMD_INFO_9_MBYTE_EN_9_BIT   11

Definition at line 919 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_OPCODE_9_FIELD

#define SPI_DEVICE_CMD_INFO_9_OPCODE_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_OPCODE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_OPCODE_9_OFFSET })

Definition at line 912 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_OPCODE_9_MASK

#define SPI_DEVICE_CMD_INFO_9_OPCODE_9_MASK   0xffu

Definition at line 910 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_OPCODE_9_OFFSET

#define SPI_DEVICE_CMD_INFO_9_OPCODE_9_OFFSET   0

Definition at line 911 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_PAYLOAD_DIR_9_BIT

#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_DIR_9_BIT   20

Definition at line 929 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_FIELD

#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_OFFSET })

Definition at line 927 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_MASK

#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_MASK   0xfu

Definition at line 925 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_OFFSET

#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_OFFSET   16

Definition at line 926 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_PAYLOAD_SWAP_EN_9_BIT

#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_SWAP_EN_9_BIT   21

Definition at line 930 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_FIELD

#define SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_OFFSET })

Definition at line 933 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_MASK

#define SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_MASK   0x3u

Definition at line 931 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_OFFSET

#define SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_OFFSET   22

Definition at line 932 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_9_REG_OFFSET   0xa0

Definition at line 908 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_9_REG_RESVAL   0x7000u

Definition at line 909 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_UPLOAD_9_BIT

#define SPI_DEVICE_CMD_INFO_9_UPLOAD_9_BIT   24

Definition at line 935 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_9_VALID_9_BIT

#define SPI_DEVICE_CMD_INFO_9_VALID_9_BIT   31

Definition at line 937 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_ADDR_MODE_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_ADDR_MODE_FIELD_WIDTH   2

Definition at line 594 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_ADDR_SWAP_EN_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_ADDR_SWAP_EN_FIELD_WIDTH   1

Definition at line 595 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_BUSY_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_BUSY_FIELD_WIDTH   1

Definition at line 604 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_DUMMY_EN_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_DUMMY_EN_FIELD_WIDTH   1

Definition at line 598 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_DUMMY_SIZE_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_DUMMY_SIZE_FIELD_WIDTH   3

Definition at line 597 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EN4B_OPCODE_FIELD

#define SPI_DEVICE_CMD_INFO_EN4B_OPCODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_EN4B_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_EN4B_OPCODE_OFFSET })

Definition at line 1392 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EN4B_OPCODE_MASK

#define SPI_DEVICE_CMD_INFO_EN4B_OPCODE_MASK   0xffu

Definition at line 1390 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EN4B_OPCODE_OFFSET

#define SPI_DEVICE_CMD_INFO_EN4B_OPCODE_OFFSET   0

Definition at line 1391 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EN4B_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_EN4B_REG_OFFSET   0xdc

Definition at line 1388 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EN4B_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_EN4B_REG_RESVAL   0x0u

Definition at line 1389 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EN4B_VALID_BIT

#define SPI_DEVICE_CMD_INFO_EN4B_VALID_BIT   31

Definition at line 1394 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EX4B_OPCODE_FIELD

#define SPI_DEVICE_CMD_INFO_EX4B_OPCODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_EX4B_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_EX4B_OPCODE_OFFSET })

Definition at line 1401 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EX4B_OPCODE_MASK

#define SPI_DEVICE_CMD_INFO_EX4B_OPCODE_MASK   0xffu

Definition at line 1399 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EX4B_OPCODE_OFFSET

#define SPI_DEVICE_CMD_INFO_EX4B_OPCODE_OFFSET   0

Definition at line 1400 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EX4B_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_EX4B_REG_OFFSET   0xe0

Definition at line 1397 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EX4B_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_EX4B_REG_RESVAL   0x0u

Definition at line 1398 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_EX4B_VALID_BIT

#define SPI_DEVICE_CMD_INFO_EX4B_VALID_BIT   31

Definition at line 1403 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_MBYTE_EN_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_MBYTE_EN_FIELD_WIDTH   1

Definition at line 596 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_MULTIREG_COUNT

#define SPI_DEVICE_CMD_INFO_MULTIREG_COUNT   24

Definition at line 606 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_OPCODE_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_OPCODE_FIELD_WIDTH   8

Definition at line 593 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_PAYLOAD_DIR_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_PAYLOAD_DIR_FIELD_WIDTH   1

Definition at line 600 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_PAYLOAD_EN_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_PAYLOAD_EN_FIELD_WIDTH   4

Definition at line 599 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_PAYLOAD_SWAP_EN_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_PAYLOAD_SWAP_EN_FIELD_WIDTH   1

Definition at line 601 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_READ_PIPELINE_MODE_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_READ_PIPELINE_MODE_FIELD_WIDTH   2

Definition at line 602 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_UPLOAD_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_UPLOAD_FIELD_WIDTH   1

Definition at line 603 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_VALID_FIELD_WIDTH

#define SPI_DEVICE_CMD_INFO_VALID_FIELD_WIDTH   1

Definition at line 605 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WRDI_OPCODE_FIELD

#define SPI_DEVICE_CMD_INFO_WRDI_OPCODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_WRDI_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_WRDI_OPCODE_OFFSET })

Definition at line 1419 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WRDI_OPCODE_MASK

#define SPI_DEVICE_CMD_INFO_WRDI_OPCODE_MASK   0xffu

Definition at line 1417 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WRDI_OPCODE_OFFSET

#define SPI_DEVICE_CMD_INFO_WRDI_OPCODE_OFFSET   0

Definition at line 1418 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WRDI_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_WRDI_REG_OFFSET   0xe8

Definition at line 1415 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WRDI_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_WRDI_REG_RESVAL   0x0u

Definition at line 1416 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WRDI_VALID_BIT

#define SPI_DEVICE_CMD_INFO_WRDI_VALID_BIT   31

Definition at line 1421 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WREN_OPCODE_FIELD

#define SPI_DEVICE_CMD_INFO_WREN_OPCODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_WREN_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_WREN_OPCODE_OFFSET })

Definition at line 1410 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WREN_OPCODE_MASK

#define SPI_DEVICE_CMD_INFO_WREN_OPCODE_MASK   0xffu

Definition at line 1408 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WREN_OPCODE_OFFSET

#define SPI_DEVICE_CMD_INFO_WREN_OPCODE_OFFSET   0

Definition at line 1409 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WREN_REG_OFFSET

#define SPI_DEVICE_CMD_INFO_WREN_REG_OFFSET   0xe4

Definition at line 1406 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WREN_REG_RESVAL

#define SPI_DEVICE_CMD_INFO_WREN_REG_RESVAL   0x0u

Definition at line 1407 of file spi_device_regs.h.

SPI_DEVICE_CMD_INFO_WREN_VALID_BIT

#define SPI_DEVICE_CMD_INFO_WREN_VALID_BIT   31

Definition at line 1412 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_FLASH_READ_BUFFER_CLR_BIT

#define SPI_DEVICE_CONTROL_FLASH_READ_BUFFER_CLR_BIT   1

Definition at line 157 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_FLASH_STATUS_FIFO_CLR_BIT

#define SPI_DEVICE_CONTROL_FLASH_STATUS_FIFO_CLR_BIT   0

Definition at line 156 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_MODE_FIELD

#define SPI_DEVICE_CONTROL_MODE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_CONTROL_MODE_MASK, .index = SPI_DEVICE_CONTROL_MODE_OFFSET })

Definition at line 160 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_MODE_MASK

#define SPI_DEVICE_CONTROL_MODE_MASK   0x3u

Definition at line 158 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_MODE_OFFSET

#define SPI_DEVICE_CONTROL_MODE_OFFSET   4

Definition at line 159 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_MODE_VALUE_DISABLED

#define SPI_DEVICE_CONTROL_MODE_VALUE_DISABLED   0x0

Definition at line 162 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_MODE_VALUE_FLASHMODE

#define SPI_DEVICE_CONTROL_MODE_VALUE_FLASHMODE   0x1

Definition at line 163 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_MODE_VALUE_PASSTHROUGH

#define SPI_DEVICE_CONTROL_MODE_VALUE_PASSTHROUGH   0x2

Definition at line 164 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_REG_OFFSET

#define SPI_DEVICE_CONTROL_REG_OFFSET   0x10

Definition at line 154 of file spi_device_regs.h.

SPI_DEVICE_CONTROL_REG_RESVAL

#define SPI_DEVICE_CONTROL_REG_RESVAL   0x10u

Definition at line 155 of file spi_device_regs.h.

SPI_DEVICE_EGRESS_BUFFER_REG_OFFSET

#define SPI_DEVICE_EGRESS_BUFFER_REG_OFFSET   0x1000

Definition at line 1549 of file spi_device_regs.h.

SPI_DEVICE_EGRESS_BUFFER_SIZE_BYTES

#define SPI_DEVICE_EGRESS_BUFFER_SIZE_BYTES   3392

Definition at line 1551 of file spi_device_regs.h.

SPI_DEVICE_EGRESS_BUFFER_SIZE_WORDS

#define SPI_DEVICE_EGRESS_BUFFER_SIZE_WORDS   848

Definition at line 1550 of file spi_device_regs.h.

SPI_DEVICE_FLASH_STATUS_BUSY_BIT

#define SPI_DEVICE_FLASH_STATUS_BUSY_BIT   0

Definition at line 200 of file spi_device_regs.h.

SPI_DEVICE_FLASH_STATUS_REG_OFFSET

#define SPI_DEVICE_FLASH_STATUS_REG_OFFSET   0x28

Definition at line 198 of file spi_device_regs.h.

SPI_DEVICE_FLASH_STATUS_REG_RESVAL

#define SPI_DEVICE_FLASH_STATUS_REG_RESVAL   0x0u

Definition at line 199 of file spi_device_regs.h.

SPI_DEVICE_FLASH_STATUS_STATUS_FIELD

#define SPI_DEVICE_FLASH_STATUS_STATUS_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_FLASH_STATUS_STATUS_MASK, .index = SPI_DEVICE_FLASH_STATUS_STATUS_OFFSET })

Definition at line 204 of file spi_device_regs.h.

SPI_DEVICE_FLASH_STATUS_STATUS_MASK

#define SPI_DEVICE_FLASH_STATUS_STATUS_MASK   0x3fffffu

Definition at line 202 of file spi_device_regs.h.

SPI_DEVICE_FLASH_STATUS_STATUS_OFFSET

#define SPI_DEVICE_FLASH_STATUS_STATUS_OFFSET   2

Definition at line 203 of file spi_device_regs.h.

SPI_DEVICE_FLASH_STATUS_WEL_BIT

#define SPI_DEVICE_FLASH_STATUS_WEL_BIT   1

Definition at line 201 of file spi_device_regs.h.

SPI_DEVICE_INGRESS_BUFFER_REG_OFFSET

#define SPI_DEVICE_INGRESS_BUFFER_REG_OFFSET   0x1e00

Definition at line 1553 of file spi_device_regs.h.

SPI_DEVICE_INGRESS_BUFFER_SIZE_BYTES

#define SPI_DEVICE_INGRESS_BUFFER_SIZE_BYTES   448

Definition at line 1555 of file spi_device_regs.h.

SPI_DEVICE_INGRESS_BUFFER_SIZE_WORDS

#define SPI_DEVICE_INGRESS_BUFFER_SIZE_WORDS   112

Definition at line 1554 of file spi_device_regs.h.

SPI_DEVICE_INTERCEPT_EN_JEDEC_BIT

#define SPI_DEVICE_INTERCEPT_EN_JEDEC_BIT   1

Definition at line 183 of file spi_device_regs.h.

SPI_DEVICE_INTERCEPT_EN_MBX_BIT

#define SPI_DEVICE_INTERCEPT_EN_MBX_BIT   3

Definition at line 185 of file spi_device_regs.h.

SPI_DEVICE_INTERCEPT_EN_REG_OFFSET

#define SPI_DEVICE_INTERCEPT_EN_REG_OFFSET   0x1c

Definition at line 180 of file spi_device_regs.h.

SPI_DEVICE_INTERCEPT_EN_REG_RESVAL

#define SPI_DEVICE_INTERCEPT_EN_REG_RESVAL   0x0u

Definition at line 181 of file spi_device_regs.h.

SPI_DEVICE_INTERCEPT_EN_SFDP_BIT

#define SPI_DEVICE_INTERCEPT_EN_SFDP_BIT   2

Definition at line 184 of file spi_device_regs.h.

SPI_DEVICE_INTERCEPT_EN_STATUS_BIT

#define SPI_DEVICE_INTERCEPT_EN_STATUS_BIT   0

Definition at line 182 of file spi_device_regs.h.

SPI_DEVICE_INTR_COMMON_READBUF_FLIP_BIT

#define SPI_DEVICE_INTR_COMMON_READBUF_FLIP_BIT   4

Definition at line 107 of file spi_device_regs.h.

SPI_DEVICE_INTR_COMMON_READBUF_WATERMARK_BIT

#define SPI_DEVICE_INTR_COMMON_READBUF_WATERMARK_BIT   3

Definition at line 106 of file spi_device_regs.h.

SPI_DEVICE_INTR_COMMON_TPM_HEADER_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_COMMON_TPM_HEADER_NOT_EMPTY_BIT   5

Definition at line 108 of file spi_device_regs.h.

SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_CMD_END_BIT

#define SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_CMD_END_BIT   6

Definition at line 109 of file spi_device_regs.h.

SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_DROP_BIT

#define SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_DROP_BIT   7

Definition at line 110 of file spi_device_regs.h.

SPI_DEVICE_INTR_COMMON_UPLOAD_CMDFIFO_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_COMMON_UPLOAD_CMDFIFO_NOT_EMPTY_BIT   0

Definition at line 103 of file spi_device_regs.h.

SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_NOT_EMPTY_BIT   1

Definition at line 104 of file spi_device_regs.h.

SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_OVERFLOW_BIT

#define SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_OVERFLOW_BIT   2

Definition at line 105 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_READBUF_FLIP_BIT

#define SPI_DEVICE_INTR_ENABLE_READBUF_FLIP_BIT   4

Definition at line 131 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_READBUF_WATERMARK_BIT

#define SPI_DEVICE_INTR_ENABLE_READBUF_WATERMARK_BIT   3

Definition at line 130 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_REG_OFFSET

#define SPI_DEVICE_INTR_ENABLE_REG_OFFSET   0x4

Definition at line 125 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_REG_RESVAL

#define SPI_DEVICE_INTR_ENABLE_REG_RESVAL   0x0u

Definition at line 126 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_TPM_HEADER_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_ENABLE_TPM_HEADER_NOT_EMPTY_BIT   5

Definition at line 132 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_TPM_RDFIFO_CMD_END_BIT

#define SPI_DEVICE_INTR_ENABLE_TPM_RDFIFO_CMD_END_BIT   6

Definition at line 133 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_TPM_RDFIFO_DROP_BIT

#define SPI_DEVICE_INTR_ENABLE_TPM_RDFIFO_DROP_BIT   7

Definition at line 134 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_UPLOAD_CMDFIFO_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_ENABLE_UPLOAD_CMDFIFO_NOT_EMPTY_BIT   0

Definition at line 127 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_UPLOAD_PAYLOAD_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_ENABLE_UPLOAD_PAYLOAD_NOT_EMPTY_BIT   1

Definition at line 128 of file spi_device_regs.h.

SPI_DEVICE_INTR_ENABLE_UPLOAD_PAYLOAD_OVERFLOW_BIT

#define SPI_DEVICE_INTR_ENABLE_UPLOAD_PAYLOAD_OVERFLOW_BIT   2

Definition at line 129 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_READBUF_FLIP_BIT

#define SPI_DEVICE_INTR_STATE_READBUF_FLIP_BIT   4

Definition at line 119 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_READBUF_WATERMARK_BIT

#define SPI_DEVICE_INTR_STATE_READBUF_WATERMARK_BIT   3

Definition at line 118 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_REG_OFFSET

#define SPI_DEVICE_INTR_STATE_REG_OFFSET   0x0

Definition at line 113 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_REG_RESVAL

#define SPI_DEVICE_INTR_STATE_REG_RESVAL   0x0u

Definition at line 114 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_TPM_HEADER_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_STATE_TPM_HEADER_NOT_EMPTY_BIT   5

Definition at line 120 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_TPM_RDFIFO_CMD_END_BIT

#define SPI_DEVICE_INTR_STATE_TPM_RDFIFO_CMD_END_BIT   6

Definition at line 121 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_TPM_RDFIFO_DROP_BIT

#define SPI_DEVICE_INTR_STATE_TPM_RDFIFO_DROP_BIT   7

Definition at line 122 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_UPLOAD_CMDFIFO_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_STATE_UPLOAD_CMDFIFO_NOT_EMPTY_BIT   0

Definition at line 115 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_UPLOAD_PAYLOAD_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_STATE_UPLOAD_PAYLOAD_NOT_EMPTY_BIT   1

Definition at line 116 of file spi_device_regs.h.

SPI_DEVICE_INTR_STATE_UPLOAD_PAYLOAD_OVERFLOW_BIT

#define SPI_DEVICE_INTR_STATE_UPLOAD_PAYLOAD_OVERFLOW_BIT   2

Definition at line 117 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_READBUF_FLIP_BIT

#define SPI_DEVICE_INTR_TEST_READBUF_FLIP_BIT   4

Definition at line 143 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_READBUF_WATERMARK_BIT

#define SPI_DEVICE_INTR_TEST_READBUF_WATERMARK_BIT   3

Definition at line 142 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_REG_OFFSET

#define SPI_DEVICE_INTR_TEST_REG_OFFSET   0x8

Definition at line 137 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_REG_RESVAL

#define SPI_DEVICE_INTR_TEST_REG_RESVAL   0x0u

Definition at line 138 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_TPM_HEADER_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_TEST_TPM_HEADER_NOT_EMPTY_BIT   5

Definition at line 144 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_TPM_RDFIFO_CMD_END_BIT

#define SPI_DEVICE_INTR_TEST_TPM_RDFIFO_CMD_END_BIT   6

Definition at line 145 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_TPM_RDFIFO_DROP_BIT

#define SPI_DEVICE_INTR_TEST_TPM_RDFIFO_DROP_BIT   7

Definition at line 146 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_UPLOAD_CMDFIFO_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_TEST_UPLOAD_CMDFIFO_NOT_EMPTY_BIT   0

Definition at line 139 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_NOT_EMPTY_BIT

#define SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_NOT_EMPTY_BIT   1

Definition at line 140 of file spi_device_regs.h.

SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_OVERFLOW_BIT

#define SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_OVERFLOW_BIT   2

Definition at line 141 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_CC_CC_FIELD

#define SPI_DEVICE_JEDEC_CC_CC_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_CC_CC_MASK, .index = SPI_DEVICE_JEDEC_CC_CC_OFFSET })

Definition at line 212 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_CC_CC_MASK

#define SPI_DEVICE_JEDEC_CC_CC_MASK   0xffu

Definition at line 210 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_CC_CC_OFFSET

#define SPI_DEVICE_JEDEC_CC_CC_OFFSET   0

Definition at line 211 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_CC_NUM_CC_FIELD

#define SPI_DEVICE_JEDEC_CC_NUM_CC_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_CC_NUM_CC_MASK, .index = SPI_DEVICE_JEDEC_CC_NUM_CC_OFFSET })

Definition at line 216 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_CC_NUM_CC_MASK

#define SPI_DEVICE_JEDEC_CC_NUM_CC_MASK   0xffu

Definition at line 214 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_CC_NUM_CC_OFFSET

#define SPI_DEVICE_JEDEC_CC_NUM_CC_OFFSET   8

Definition at line 215 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_CC_REG_OFFSET

#define SPI_DEVICE_JEDEC_CC_REG_OFFSET   0x2c

Definition at line 208 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_CC_REG_RESVAL

#define SPI_DEVICE_JEDEC_CC_REG_RESVAL   0x7fu

Definition at line 209 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_ID_ID_FIELD

#define SPI_DEVICE_JEDEC_ID_ID_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_ID_ID_MASK, .index = SPI_DEVICE_JEDEC_ID_ID_OFFSET })

Definition at line 224 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_ID_ID_MASK

#define SPI_DEVICE_JEDEC_ID_ID_MASK   0xffffu

Definition at line 222 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_ID_ID_OFFSET

#define SPI_DEVICE_JEDEC_ID_ID_OFFSET   0

Definition at line 223 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_ID_MF_FIELD

#define SPI_DEVICE_JEDEC_ID_MF_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_ID_MF_MASK, .index = SPI_DEVICE_JEDEC_ID_MF_OFFSET })

Definition at line 228 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_ID_MF_MASK

#define SPI_DEVICE_JEDEC_ID_MF_MASK   0xffu

Definition at line 226 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_ID_MF_OFFSET

#define SPI_DEVICE_JEDEC_ID_MF_OFFSET   16

Definition at line 227 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_ID_REG_OFFSET

#define SPI_DEVICE_JEDEC_ID_REG_OFFSET   0x30

Definition at line 220 of file spi_device_regs.h.

SPI_DEVICE_JEDEC_ID_REG_RESVAL

#define SPI_DEVICE_JEDEC_ID_REG_RESVAL   0x0u

Definition at line 221 of file spi_device_regs.h.

SPI_DEVICE_LAST_READ_ADDR_REG_OFFSET

#define SPI_DEVICE_LAST_READ_ADDR_REG_OFFSET   0x24

Definition at line 194 of file spi_device_regs.h.

SPI_DEVICE_LAST_READ_ADDR_REG_RESVAL

#define SPI_DEVICE_LAST_READ_ADDR_REG_RESVAL   0x0u

Definition at line 195 of file spi_device_regs.h.

SPI_DEVICE_MAILBOX_ADDR_REG_OFFSET

#define SPI_DEVICE_MAILBOX_ADDR_REG_OFFSET   0x38

Definition at line 240 of file spi_device_regs.h.

SPI_DEVICE_MAILBOX_ADDR_REG_RESVAL

#define SPI_DEVICE_MAILBOX_ADDR_REG_RESVAL   0x0u

Definition at line 241 of file spi_device_regs.h.

SPI_DEVICE_PARAM_NUM_ALERTS

#define SPI_DEVICE_PARAM_NUM_ALERTS   1

Definition at line 97 of file spi_device_regs.h.

SPI_DEVICE_PARAM_NUM_CMD_INFO

#define SPI_DEVICE_PARAM_NUM_CMD_INFO   24

Definition at line 85 of file spi_device_regs.h.

SPI_DEVICE_PARAM_NUM_LOCALITY

#define SPI_DEVICE_PARAM_NUM_LOCALITY   5

Definition at line 88 of file spi_device_regs.h.

SPI_DEVICE_PARAM_REG_WIDTH

#define SPI_DEVICE_PARAM_REG_WIDTH   32

Definition at line 100 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_ADDR_FIFO_DEPTH

#define SPI_DEVICE_PARAM_SRAM_ADDR_FIFO_DEPTH   16

Definition at line 75 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_ADDR_FIFO_OFFSET

#define SPI_DEVICE_PARAM_SRAM_ADDR_FIFO_OFFSET   80

Definition at line 72 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_CMD_FIFO_DEPTH

#define SPI_DEVICE_PARAM_SRAM_CMD_FIFO_DEPTH   16

Definition at line 68 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_CMD_FIFO_OFFSET

#define SPI_DEVICE_PARAM_SRAM_CMD_FIFO_OFFSET   64

Definition at line 65 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_DEPTH

#define SPI_DEVICE_PARAM_SRAM_DEPTH   1024

Definition at line 20 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_EGRESS_DEPTH

#define SPI_DEVICE_PARAM_SRAM_EGRESS_DEPTH   848

Definition at line 23 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_INGRESS_DEPTH

#define SPI_DEVICE_PARAM_SRAM_INGRESS_DEPTH   112

Definition at line 26 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_MAILBOX_DEPTH

#define SPI_DEVICE_PARAM_SRAM_MAILBOX_DEPTH   256

Definition at line 40 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_MAILBOX_OFFSET

#define SPI_DEVICE_PARAM_SRAM_MAILBOX_OFFSET   512

Definition at line 37 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_PAYLOAD_DEPTH

#define SPI_DEVICE_PARAM_SRAM_PAYLOAD_DEPTH   64

Definition at line 61 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_PAYLOAD_OFFSET

#define SPI_DEVICE_PARAM_SRAM_PAYLOAD_OFFSET   0

Definition at line 58 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_READ_BUFFER_DEPTH

#define SPI_DEVICE_PARAM_SRAM_READ_BUFFER_DEPTH   512

Definition at line 33 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_READ_BUFFER_OFFSET

#define SPI_DEVICE_PARAM_SRAM_READ_BUFFER_OFFSET   0

Definition at line 30 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_SFDP_DEPTH

#define SPI_DEVICE_PARAM_SRAM_SFDP_DEPTH   64

Definition at line 47 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_SFDP_OFFSET

#define SPI_DEVICE_PARAM_SRAM_SFDP_OFFSET   768

Definition at line 44 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_TPM_RD_FIFO_DEPTH

#define SPI_DEVICE_PARAM_SRAM_TPM_RD_FIFO_DEPTH   16

Definition at line 54 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_TPM_RD_FIFO_OFFSET

#define SPI_DEVICE_PARAM_SRAM_TPM_RD_FIFO_OFFSET   832

Definition at line 51 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_TPM_WR_FIFO_DEPTH

#define SPI_DEVICE_PARAM_SRAM_TPM_WR_FIFO_DEPTH   16

Definition at line 82 of file spi_device_regs.h.

SPI_DEVICE_PARAM_SRAM_TPM_WR_FIFO_OFFSET

#define SPI_DEVICE_PARAM_SRAM_TPM_WR_FIFO_OFFSET   96

Definition at line 79 of file spi_device_regs.h.

SPI_DEVICE_PARAM_TPM_RD_FIFO_PTR_W

#define SPI_DEVICE_PARAM_TPM_RD_FIFO_PTR_W   5

Definition at line 91 of file spi_device_regs.h.

SPI_DEVICE_PARAM_TPM_RD_FIFO_WIDTH

#define SPI_DEVICE_PARAM_TPM_RD_FIFO_WIDTH   32

Definition at line 94 of file spi_device_regs.h.

SPI_DEVICE_PAYLOAD_SWAP_DATA_REG_OFFSET

#define SPI_DEVICE_PAYLOAD_SWAP_DATA_REG_OFFSET   0x78

Definition at line 589 of file spi_device_regs.h.

SPI_DEVICE_PAYLOAD_SWAP_DATA_REG_RESVAL

#define SPI_DEVICE_PAYLOAD_SWAP_DATA_REG_RESVAL   0x0u

Definition at line 590 of file spi_device_regs.h.

SPI_DEVICE_PAYLOAD_SWAP_MASK_REG_OFFSET

#define SPI_DEVICE_PAYLOAD_SWAP_MASK_REG_OFFSET   0x74

Definition at line 585 of file spi_device_regs.h.

SPI_DEVICE_PAYLOAD_SWAP_MASK_REG_RESVAL

#define SPI_DEVICE_PAYLOAD_SWAP_MASK_REG_RESVAL   0x0u

Definition at line 586 of file spi_device_regs.h.

SPI_DEVICE_READ_THRESHOLD_REG_OFFSET

#define SPI_DEVICE_READ_THRESHOLD_REG_OFFSET   0x34

Definition at line 232 of file spi_device_regs.h.

SPI_DEVICE_READ_THRESHOLD_REG_RESVAL

#define SPI_DEVICE_READ_THRESHOLD_REG_RESVAL   0x0u

Definition at line 233 of file spi_device_regs.h.

SPI_DEVICE_READ_THRESHOLD_THRESHOLD_FIELD

#define SPI_DEVICE_READ_THRESHOLD_THRESHOLD_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_READ_THRESHOLD_THRESHOLD_MASK, .index = SPI_DEVICE_READ_THRESHOLD_THRESHOLD_OFFSET })

Definition at line 236 of file spi_device_regs.h.

SPI_DEVICE_READ_THRESHOLD_THRESHOLD_MASK

#define SPI_DEVICE_READ_THRESHOLD_THRESHOLD_MASK   0x3ffu

Definition at line 234 of file spi_device_regs.h.

SPI_DEVICE_READ_THRESHOLD_THRESHOLD_OFFSET

#define SPI_DEVICE_READ_THRESHOLD_THRESHOLD_OFFSET   0

Definition at line 235 of file spi_device_regs.h.

SPI_DEVICE_STATUS_CSB_BIT

#define SPI_DEVICE_STATUS_CSB_BIT   5

Definition at line 176 of file spi_device_regs.h.

SPI_DEVICE_STATUS_REG_OFFSET

#define SPI_DEVICE_STATUS_REG_OFFSET   0x18

Definition at line 174 of file spi_device_regs.h.

SPI_DEVICE_STATUS_REG_RESVAL

#define SPI_DEVICE_STATUS_REG_RESVAL   0x60u

Definition at line 175 of file spi_device_regs.h.

SPI_DEVICE_STATUS_TPM_CSB_BIT

#define SPI_DEVICE_STATUS_TPM_CSB_BIT   6

Definition at line 177 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_FIELD

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_OFFSET })

Definition at line 1465 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_MASK

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_MASK   0xffu

Definition at line 1463 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_OFFSET

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_OFFSET   0

Definition at line 1464 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_FIELD

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_OFFSET })

Definition at line 1469 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_MASK

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_MASK   0xffu

Definition at line 1467 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_OFFSET

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_OFFSET   8

Definition at line 1468 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_FIELD

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_OFFSET })

Definition at line 1473 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_MASK

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_MASK   0xffu

Definition at line 1471 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_OFFSET

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_OFFSET   16

Definition at line 1472 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_FIELD

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_OFFSET })

Definition at line 1477 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_MASK

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_MASK   0xffu

Definition at line 1475 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_OFFSET

#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_OFFSET   24

Definition at line 1476 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_REG_OFFSET

#define SPI_DEVICE_TPM_ACCESS_0_REG_OFFSET   0x80c

Definition at line 1461 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_0_REG_RESVAL

#define SPI_DEVICE_TPM_ACCESS_0_REG_RESVAL   0x0u

Definition at line 1462 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_FIELD

#define SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_MASK, .index = SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_OFFSET })

Definition at line 1485 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_MASK

#define SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_MASK   0xffu

Definition at line 1483 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_OFFSET

#define SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_OFFSET   0

Definition at line 1484 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_1_REG_OFFSET

#define SPI_DEVICE_TPM_ACCESS_1_REG_OFFSET   0x810

Definition at line 1481 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_1_REG_RESVAL

#define SPI_DEVICE_TPM_ACCESS_1_REG_RESVAL   0x0u

Definition at line 1482 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_ACCESS_FIELD_WIDTH

#define SPI_DEVICE_TPM_ACCESS_ACCESS_FIELD_WIDTH   8

Definition at line 1457 of file spi_device_regs.h.

SPI_DEVICE_TPM_ACCESS_MULTIREG_COUNT

#define SPI_DEVICE_TPM_ACCESS_MULTIREG_COUNT   2

Definition at line 1458 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_LOCALITY_BIT

#define SPI_DEVICE_TPM_CAP_LOCALITY_BIT   8

Definition at line 1430 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_FIELD

#define SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_MASK, .index = SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_OFFSET })

Definition at line 1437 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_MASK

#define SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_MASK   0x7u

Definition at line 1435 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_OFFSET

#define SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_OFFSET   20

Definition at line 1436 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_FIELD

#define SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_MASK, .index = SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_OFFSET })

Definition at line 1433 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_MASK

#define SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_MASK   0x7u

Definition at line 1431 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_OFFSET

#define SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_OFFSET   16

Definition at line 1432 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_REG_OFFSET

#define SPI_DEVICE_TPM_CAP_REG_OFFSET   0x800

Definition at line 1424 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_REG_RESVAL

#define SPI_DEVICE_TPM_CAP_REG_RESVAL   0x660100u

Definition at line 1425 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_REV_FIELD

#define SPI_DEVICE_TPM_CAP_REV_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CAP_REV_MASK, .index = SPI_DEVICE_TPM_CAP_REV_OFFSET })

Definition at line 1428 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_REV_MASK

#define SPI_DEVICE_TPM_CAP_REV_MASK   0xffu

Definition at line 1426 of file spi_device_regs.h.

SPI_DEVICE_TPM_CAP_REV_OFFSET

#define SPI_DEVICE_TPM_CAP_REV_OFFSET   0

Definition at line 1427 of file spi_device_regs.h.

SPI_DEVICE_TPM_CFG_EN_BIT

#define SPI_DEVICE_TPM_CFG_EN_BIT   0

Definition at line 1443 of file spi_device_regs.h.

SPI_DEVICE_TPM_CFG_HW_REG_DIS_BIT

#define SPI_DEVICE_TPM_CFG_HW_REG_DIS_BIT   2

Definition at line 1445 of file spi_device_regs.h.

SPI_DEVICE_TPM_CFG_INVALID_LOCALITY_BIT

#define SPI_DEVICE_TPM_CFG_INVALID_LOCALITY_BIT   4

Definition at line 1447 of file spi_device_regs.h.

SPI_DEVICE_TPM_CFG_REG_OFFSET

#define SPI_DEVICE_TPM_CFG_REG_OFFSET   0x804

Definition at line 1441 of file spi_device_regs.h.

SPI_DEVICE_TPM_CFG_REG_RESVAL

#define SPI_DEVICE_TPM_CFG_REG_RESVAL   0x0u

Definition at line 1442 of file spi_device_regs.h.

SPI_DEVICE_TPM_CFG_TPM_MODE_BIT

#define SPI_DEVICE_TPM_CFG_TPM_MODE_BIT   1

Definition at line 1444 of file spi_device_regs.h.

SPI_DEVICE_TPM_CFG_TPM_REG_CHK_DIS_BIT

#define SPI_DEVICE_TPM_CFG_TPM_REG_CHK_DIS_BIT   3

Definition at line 1446 of file spi_device_regs.h.

SPI_DEVICE_TPM_CMD_ADDR_ADDR_FIELD

#define SPI_DEVICE_TPM_CMD_ADDR_ADDR_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CMD_ADDR_ADDR_MASK, .index = SPI_DEVICE_TPM_CMD_ADDR_ADDR_OFFSET })

Definition at line 1537 of file spi_device_regs.h.

SPI_DEVICE_TPM_CMD_ADDR_ADDR_MASK

#define SPI_DEVICE_TPM_CMD_ADDR_ADDR_MASK   0xffffffu

Definition at line 1535 of file spi_device_regs.h.

SPI_DEVICE_TPM_CMD_ADDR_ADDR_OFFSET

#define SPI_DEVICE_TPM_CMD_ADDR_ADDR_OFFSET   0

Definition at line 1536 of file spi_device_regs.h.

SPI_DEVICE_TPM_CMD_ADDR_CMD_FIELD

#define SPI_DEVICE_TPM_CMD_ADDR_CMD_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CMD_ADDR_CMD_MASK, .index = SPI_DEVICE_TPM_CMD_ADDR_CMD_OFFSET })

Definition at line 1541 of file spi_device_regs.h.

SPI_DEVICE_TPM_CMD_ADDR_CMD_MASK

#define SPI_DEVICE_TPM_CMD_ADDR_CMD_MASK   0xffu

Definition at line 1539 of file spi_device_regs.h.

SPI_DEVICE_TPM_CMD_ADDR_CMD_OFFSET

#define SPI_DEVICE_TPM_CMD_ADDR_CMD_OFFSET   24

Definition at line 1540 of file spi_device_regs.h.

SPI_DEVICE_TPM_CMD_ADDR_REG_OFFSET

#define SPI_DEVICE_TPM_CMD_ADDR_REG_OFFSET   0x830

Definition at line 1533 of file spi_device_regs.h.

SPI_DEVICE_TPM_CMD_ADDR_REG_RESVAL

#define SPI_DEVICE_TPM_CMD_ADDR_REG_RESVAL   0x0u

Definition at line 1534 of file spi_device_regs.h.

SPI_DEVICE_TPM_DID_VID_DID_FIELD

#define SPI_DEVICE_TPM_DID_VID_DID_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_DID_VID_DID_MASK, .index = SPI_DEVICE_TPM_DID_VID_DID_OFFSET })

Definition at line 1521 of file spi_device_regs.h.

SPI_DEVICE_TPM_DID_VID_DID_MASK

#define SPI_DEVICE_TPM_DID_VID_DID_MASK   0xffffu

Definition at line 1519 of file spi_device_regs.h.

SPI_DEVICE_TPM_DID_VID_DID_OFFSET

#define SPI_DEVICE_TPM_DID_VID_DID_OFFSET   16

Definition at line 1520 of file spi_device_regs.h.

SPI_DEVICE_TPM_DID_VID_REG_OFFSET

#define SPI_DEVICE_TPM_DID_VID_REG_OFFSET   0x828

Definition at line 1513 of file spi_device_regs.h.

SPI_DEVICE_TPM_DID_VID_REG_RESVAL

#define SPI_DEVICE_TPM_DID_VID_REG_RESVAL   0x0u

Definition at line 1514 of file spi_device_regs.h.

SPI_DEVICE_TPM_DID_VID_VID_FIELD

#define SPI_DEVICE_TPM_DID_VID_VID_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_DID_VID_VID_MASK, .index = SPI_DEVICE_TPM_DID_VID_VID_OFFSET })

Definition at line 1517 of file spi_device_regs.h.

SPI_DEVICE_TPM_DID_VID_VID_MASK

#define SPI_DEVICE_TPM_DID_VID_VID_MASK   0xffffu

Definition at line 1515 of file spi_device_regs.h.

SPI_DEVICE_TPM_DID_VID_VID_OFFSET

#define SPI_DEVICE_TPM_DID_VID_VID_OFFSET   0

Definition at line 1516 of file spi_device_regs.h.

SPI_DEVICE_TPM_INT_ENABLE_REG_OFFSET

#define SPI_DEVICE_TPM_INT_ENABLE_REG_OFFSET   0x81c

Definition at line 1497 of file spi_device_regs.h.

SPI_DEVICE_TPM_INT_ENABLE_REG_RESVAL

#define SPI_DEVICE_TPM_INT_ENABLE_REG_RESVAL   0x0u

Definition at line 1498 of file spi_device_regs.h.

SPI_DEVICE_TPM_INT_STATUS_REG_OFFSET

#define SPI_DEVICE_TPM_INT_STATUS_REG_OFFSET   0x824

Definition at line 1509 of file spi_device_regs.h.

SPI_DEVICE_TPM_INT_STATUS_REG_RESVAL

#define SPI_DEVICE_TPM_INT_STATUS_REG_RESVAL   0x0u

Definition at line 1510 of file spi_device_regs.h.

SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_FIELD

#define SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_MASK, .index = SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_OFFSET })

Definition at line 1505 of file spi_device_regs.h.

SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_MASK

#define SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_MASK   0xffu

Definition at line 1503 of file spi_device_regs.h.

SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_OFFSET

#define SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_OFFSET   0

Definition at line 1504 of file spi_device_regs.h.

SPI_DEVICE_TPM_INT_VECTOR_REG_OFFSET

#define SPI_DEVICE_TPM_INT_VECTOR_REG_OFFSET   0x820

Definition at line 1501 of file spi_device_regs.h.

SPI_DEVICE_TPM_INT_VECTOR_REG_RESVAL

#define SPI_DEVICE_TPM_INT_VECTOR_REG_RESVAL   0x0u

Definition at line 1502 of file spi_device_regs.h.

SPI_DEVICE_TPM_INTF_CAPABILITY_REG_OFFSET

#define SPI_DEVICE_TPM_INTF_CAPABILITY_REG_OFFSET   0x818

Definition at line 1493 of file spi_device_regs.h.

SPI_DEVICE_TPM_INTF_CAPABILITY_REG_RESVAL

#define SPI_DEVICE_TPM_INTF_CAPABILITY_REG_RESVAL   0x0u

Definition at line 1494 of file spi_device_regs.h.

SPI_DEVICE_TPM_READ_FIFO_REG_OFFSET

#define SPI_DEVICE_TPM_READ_FIFO_REG_OFFSET   0x834

Definition at line 1545 of file spi_device_regs.h.

SPI_DEVICE_TPM_READ_FIFO_REG_RESVAL

#define SPI_DEVICE_TPM_READ_FIFO_REG_RESVAL   0x0u

Definition at line 1546 of file spi_device_regs.h.

SPI_DEVICE_TPM_RID_REG_OFFSET

#define SPI_DEVICE_TPM_RID_REG_OFFSET   0x82c

Definition at line 1525 of file spi_device_regs.h.

SPI_DEVICE_TPM_RID_REG_RESVAL

#define SPI_DEVICE_TPM_RID_REG_RESVAL   0x0u

Definition at line 1526 of file spi_device_regs.h.

SPI_DEVICE_TPM_RID_RID_FIELD

#define SPI_DEVICE_TPM_RID_RID_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_RID_RID_MASK, .index = SPI_DEVICE_TPM_RID_RID_OFFSET })

Definition at line 1529 of file spi_device_regs.h.

SPI_DEVICE_TPM_RID_RID_MASK

#define SPI_DEVICE_TPM_RID_RID_MASK   0xffu

Definition at line 1527 of file spi_device_regs.h.

SPI_DEVICE_TPM_RID_RID_OFFSET

#define SPI_DEVICE_TPM_RID_RID_OFFSET   0

Definition at line 1528 of file spi_device_regs.h.

SPI_DEVICE_TPM_STATUS_CMDADDR_NOTEMPTY_BIT

#define SPI_DEVICE_TPM_STATUS_CMDADDR_NOTEMPTY_BIT   0

Definition at line 1452 of file spi_device_regs.h.

SPI_DEVICE_TPM_STATUS_RDFIFO_ABORTED_BIT

#define SPI_DEVICE_TPM_STATUS_RDFIFO_ABORTED_BIT   2

Definition at line 1454 of file spi_device_regs.h.

SPI_DEVICE_TPM_STATUS_REG_OFFSET

#define SPI_DEVICE_TPM_STATUS_REG_OFFSET   0x808

Definition at line 1450 of file spi_device_regs.h.

SPI_DEVICE_TPM_STATUS_REG_RESVAL

#define SPI_DEVICE_TPM_STATUS_REG_RESVAL   0x0u

Definition at line 1451 of file spi_device_regs.h.

SPI_DEVICE_TPM_STATUS_WRFIFO_PENDING_BIT

#define SPI_DEVICE_TPM_STATUS_WRFIFO_PENDING_BIT   1

Definition at line 1453 of file spi_device_regs.h.

SPI_DEVICE_TPM_STS_REG_OFFSET

#define SPI_DEVICE_TPM_STS_REG_OFFSET   0x814

Definition at line 1489 of file spi_device_regs.h.

SPI_DEVICE_TPM_STS_REG_RESVAL

#define SPI_DEVICE_TPM_STS_REG_RESVAL   0x0u

Definition at line 1490 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_ADDRFIFO_REG_OFFSET

#define SPI_DEVICE_UPLOAD_ADDRFIFO_REG_OFFSET   0x48

Definition at line 281 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_ADDRFIFO_REG_RESVAL

#define SPI_DEVICE_UPLOAD_ADDRFIFO_REG_RESVAL   0x0u

Definition at line 282 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_CMDFIFO_ADDR4B_MODE_BIT

#define SPI_DEVICE_UPLOAD_CMDFIFO_ADDR4B_MODE_BIT   15

Definition at line 278 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_CMDFIFO_BUSY_BIT

#define SPI_DEVICE_UPLOAD_CMDFIFO_BUSY_BIT   13

Definition at line 276 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_CMDFIFO_DATA_FIELD

#define SPI_DEVICE_UPLOAD_CMDFIFO_DATA_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_CMDFIFO_DATA_MASK, .index = SPI_DEVICE_UPLOAD_CMDFIFO_DATA_OFFSET })

Definition at line 274 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_CMDFIFO_DATA_MASK

#define SPI_DEVICE_UPLOAD_CMDFIFO_DATA_MASK   0xffu

Definition at line 272 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_CMDFIFO_DATA_OFFSET

#define SPI_DEVICE_UPLOAD_CMDFIFO_DATA_OFFSET   0

Definition at line 273 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_CMDFIFO_REG_OFFSET

#define SPI_DEVICE_UPLOAD_CMDFIFO_REG_OFFSET   0x44

Definition at line 270 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_CMDFIFO_REG_RESVAL

#define SPI_DEVICE_UPLOAD_CMDFIFO_REG_RESVAL   0x0u

Definition at line 271 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_CMDFIFO_WEL_BIT

#define SPI_DEVICE_UPLOAD_CMDFIFO_WEL_BIT   14

Definition at line 277 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_FIELD

#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_MASK, .index = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_OFFSET })

Definition at line 262 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_MASK

#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_MASK   0x1ffu

Definition at line 260 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_OFFSET

#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_OFFSET   0

Definition at line 261 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_FIELD

#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_MASK, .index = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_OFFSET })

Definition at line 266 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_MASK

#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_MASK   0xffu

Definition at line 264 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_OFFSET

#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_OFFSET   16

Definition at line 265 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS2_REG_OFFSET

#define SPI_DEVICE_UPLOAD_STATUS2_REG_OFFSET   0x40

Definition at line 258 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS2_REG_RESVAL

#define SPI_DEVICE_UPLOAD_STATUS2_REG_RESVAL   0x0u

Definition at line 259 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_FIELD

#define SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_MASK, .index = SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_OFFSET })

Definition at line 253 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_MASK

#define SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_MASK   0x1fu

Definition at line 251 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_OFFSET

#define SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_OFFSET   8

Definition at line 252 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_NOTEMPTY_BIT

#define SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_NOTEMPTY_BIT   15

Definition at line 255 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_FIELD

#define SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_FIELD    ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_MASK, .index = SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_OFFSET })

Definition at line 248 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_MASK

#define SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_MASK   0x1fu

Definition at line 246 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_OFFSET

#define SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_OFFSET   0

Definition at line 247 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_NOTEMPTY_BIT

#define SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_NOTEMPTY_BIT   7

Definition at line 250 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_REG_OFFSET

#define SPI_DEVICE_UPLOAD_STATUS_REG_OFFSET   0x3c

Definition at line 244 of file spi_device_regs.h.

SPI_DEVICE_UPLOAD_STATUS_REG_RESVAL

#define SPI_DEVICE_UPLOAD_STATUS_REG_RESVAL   0x0u

Definition at line 245 of file spi_device_regs.h.