spi_device_regs.h

Go to the documentation of this file.

/**
 * @file
 * @brief Generated register defines for spi_device
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _SPI_DEVICE_REG_DEFS_
#define _SPI_DEVICE_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Sram Entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_DEPTH 1024
 
// Sram Egress Entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_EGRESS_DEPTH 848
 
// Sram Ingress Entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_INGRESS_DEPTH 112
 
// Sram eFlash read buffer offset (from egress buffer start). Word size is
// 32bit width.
#define SPI_DEVICE_PARAM_SRAM_READ_BUFFER_OFFSET 0
 
// Sram eFlash read buffer entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_READ_BUFFER_DEPTH 512
 
// Sram mailbox buffer offset (from egress buffer start). Word size is 32bit
// width.
#define SPI_DEVICE_PARAM_SRAM_MAILBOX_OFFSET 512
 
// Sram mailbox entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_MAILBOX_DEPTH 256
 
// Sram SFDP buffer offset (from egress buffer start). Word size is 32bit
// width.
#define SPI_DEVICE_PARAM_SRAM_SFDP_OFFSET 768
 
// Sram SFDP entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_SFDP_DEPTH 64
 
// Sram TPM RdFIFO offset (from egress buffer start). Word size is 32bit
// width.
#define SPI_DEVICE_PARAM_SRAM_TPM_RD_FIFO_OFFSET 832
 
// Sram TPM RdFIFO entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_TPM_RD_FIFO_DEPTH 16
 
// Sram payload FIFO offset (from ingress buffer start). Word size is 32bit
// width.
#define SPI_DEVICE_PARAM_SRAM_PAYLOAD_OFFSET 0
 
// Sram payload FIFO entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_PAYLOAD_DEPTH 64
 
// Sram command FIFO offset (from ingress buffer start). Word size is 32bit
// width.
#define SPI_DEVICE_PARAM_SRAM_CMD_FIFO_OFFSET 64
 
// Sram command FIFO entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_CMD_FIFO_DEPTH 16
 
// Sram address FIFO offset (from ingress buffer start). Word size is 32bit
// width.
#define SPI_DEVICE_PARAM_SRAM_ADDR_FIFO_OFFSET 80
 
// Sram address FIFO entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_ADDR_FIFO_DEPTH 16
 
// Sram TPM Write FIFO offset (from ingress buffer start). Word size is 32bit
// width.
#define SPI_DEVICE_PARAM_SRAM_TPM_WR_FIFO_OFFSET 96
 
// Sram TPM Write FIFO entries. Word size is 32bit width.
#define SPI_DEVICE_PARAM_SRAM_TPM_WR_FIFO_DEPTH 16
 
// Define the number of Command Info slots.
#define SPI_DEVICE_PARAM_NUM_CMD_INFO 24
 
// The number of locality TPM module supports.
#define SPI_DEVICE_PARAM_NUM_LOCALITY 5
 
// TPM RdFIFO Pointer Bit Width. clog2(Depth(16+1))
#define SPI_DEVICE_PARAM_TPM_RD_FIFO_PTR_W 5
 
// TPM Read FIFO Data Width. (TpmRdFifoWidth/8) shall be power of two
#define SPI_DEVICE_PARAM_TPM_RD_FIFO_WIDTH 32
 
// Number of alerts
#define SPI_DEVICE_PARAM_NUM_ALERTS 1
 
// Register width
#define SPI_DEVICE_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define SPI_DEVICE_INTR_COMMON_UPLOAD_CMDFIFO_NOT_EMPTY_BIT 0
#define SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_NOT_EMPTY_BIT 1
#define SPI_DEVICE_INTR_COMMON_UPLOAD_PAYLOAD_OVERFLOW_BIT 2
#define SPI_DEVICE_INTR_COMMON_READBUF_WATERMARK_BIT 3
#define SPI_DEVICE_INTR_COMMON_READBUF_FLIP_BIT 4
#define SPI_DEVICE_INTR_COMMON_TPM_HEADER_NOT_EMPTY_BIT 5
#define SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_CMD_END_BIT 6
#define SPI_DEVICE_INTR_COMMON_TPM_RDFIFO_DROP_BIT 7
 
// Interrupt State Register
#define SPI_DEVICE_INTR_STATE_REG_OFFSET 0x0
#define SPI_DEVICE_INTR_STATE_REG_RESVAL 0x0u
#define SPI_DEVICE_INTR_STATE_UPLOAD_CMDFIFO_NOT_EMPTY_BIT 0
#define SPI_DEVICE_INTR_STATE_UPLOAD_PAYLOAD_NOT_EMPTY_BIT 1
#define SPI_DEVICE_INTR_STATE_UPLOAD_PAYLOAD_OVERFLOW_BIT 2
#define SPI_DEVICE_INTR_STATE_READBUF_WATERMARK_BIT 3
#define SPI_DEVICE_INTR_STATE_READBUF_FLIP_BIT 4
#define SPI_DEVICE_INTR_STATE_TPM_HEADER_NOT_EMPTY_BIT 5
#define SPI_DEVICE_INTR_STATE_TPM_RDFIFO_CMD_END_BIT 6
#define SPI_DEVICE_INTR_STATE_TPM_RDFIFO_DROP_BIT 7
 
// Interrupt Enable Register
#define SPI_DEVICE_INTR_ENABLE_REG_OFFSET 0x4
#define SPI_DEVICE_INTR_ENABLE_REG_RESVAL 0x0u
#define SPI_DEVICE_INTR_ENABLE_UPLOAD_CMDFIFO_NOT_EMPTY_BIT 0
#define SPI_DEVICE_INTR_ENABLE_UPLOAD_PAYLOAD_NOT_EMPTY_BIT 1
#define SPI_DEVICE_INTR_ENABLE_UPLOAD_PAYLOAD_OVERFLOW_BIT 2
#define SPI_DEVICE_INTR_ENABLE_READBUF_WATERMARK_BIT 3
#define SPI_DEVICE_INTR_ENABLE_READBUF_FLIP_BIT 4
#define SPI_DEVICE_INTR_ENABLE_TPM_HEADER_NOT_EMPTY_BIT 5
#define SPI_DEVICE_INTR_ENABLE_TPM_RDFIFO_CMD_END_BIT 6
#define SPI_DEVICE_INTR_ENABLE_TPM_RDFIFO_DROP_BIT 7
 
// Interrupt Test Register
#define SPI_DEVICE_INTR_TEST_REG_OFFSET 0x8
#define SPI_DEVICE_INTR_TEST_REG_RESVAL 0x0u
#define SPI_DEVICE_INTR_TEST_UPLOAD_CMDFIFO_NOT_EMPTY_BIT 0
#define SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_NOT_EMPTY_BIT 1
#define SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_OVERFLOW_BIT 2
#define SPI_DEVICE_INTR_TEST_READBUF_WATERMARK_BIT 3
#define SPI_DEVICE_INTR_TEST_READBUF_FLIP_BIT 4
#define SPI_DEVICE_INTR_TEST_TPM_HEADER_NOT_EMPTY_BIT 5
#define SPI_DEVICE_INTR_TEST_TPM_RDFIFO_CMD_END_BIT 6
#define SPI_DEVICE_INTR_TEST_TPM_RDFIFO_DROP_BIT 7
 
// Alert Test Register
#define SPI_DEVICE_ALERT_TEST_REG_OFFSET 0xc
#define SPI_DEVICE_ALERT_TEST_REG_RESVAL 0x0u
#define SPI_DEVICE_ALERT_TEST_FATAL_FAULT_BIT 0
 
// Control register
#define SPI_DEVICE_CONTROL_REG_OFFSET 0x10
#define SPI_DEVICE_CONTROL_REG_RESVAL 0x10u
#define SPI_DEVICE_CONTROL_FLASH_STATUS_FIFO_CLR_BIT 0
#define SPI_DEVICE_CONTROL_FLASH_READ_BUFFER_CLR_BIT 1
#define SPI_DEVICE_CONTROL_MODE_MASK 0x3u
#define SPI_DEVICE_CONTROL_MODE_OFFSET 4
#define SPI_DEVICE_CONTROL_MODE_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CONTROL_MODE_MASK, .index = SPI_DEVICE_CONTROL_MODE_OFFSET })
#define SPI_DEVICE_CONTROL_MODE_VALUE_DISABLED 0x0
#define SPI_DEVICE_CONTROL_MODE_VALUE_FLASHMODE 0x1
#define SPI_DEVICE_CONTROL_MODE_VALUE_PASSTHROUGH 0x2
 
// Configuration Register
#define SPI_DEVICE_CFG_REG_OFFSET 0x14
#define SPI_DEVICE_CFG_REG_RESVAL 0x0u
#define SPI_DEVICE_CFG_TX_ORDER_BIT 2
#define SPI_DEVICE_CFG_RX_ORDER_BIT 3
#define SPI_DEVICE_CFG_MAILBOX_EN_BIT 24
 
// SPI Device status register
#define SPI_DEVICE_STATUS_REG_OFFSET 0x18
#define SPI_DEVICE_STATUS_REG_RESVAL 0x60u
#define SPI_DEVICE_STATUS_CSB_BIT 5
#define SPI_DEVICE_STATUS_TPM_CSB_BIT 6
 
// Intercept Passthrough datapath.
#define SPI_DEVICE_INTERCEPT_EN_REG_OFFSET 0x1c
#define SPI_DEVICE_INTERCEPT_EN_REG_RESVAL 0x0u
#define SPI_DEVICE_INTERCEPT_EN_STATUS_BIT 0
#define SPI_DEVICE_INTERCEPT_EN_JEDEC_BIT 1
#define SPI_DEVICE_INTERCEPT_EN_SFDP_BIT 2
#define SPI_DEVICE_INTERCEPT_EN_MBX_BIT 3
 
// Flash address mode configuration
#define SPI_DEVICE_ADDR_MODE_REG_OFFSET 0x20
#define SPI_DEVICE_ADDR_MODE_REG_RESVAL 0x0u
#define SPI_DEVICE_ADDR_MODE_ADDR_4B_EN_BIT 0
#define SPI_DEVICE_ADDR_MODE_PENDING_BIT 31
 
// Last Read Address
#define SPI_DEVICE_LAST_READ_ADDR_REG_OFFSET 0x24
#define SPI_DEVICE_LAST_READ_ADDR_REG_RESVAL 0x0u
 
// SPI Flash Status register.
#define SPI_DEVICE_FLASH_STATUS_REG_OFFSET 0x28
#define SPI_DEVICE_FLASH_STATUS_REG_RESVAL 0x0u
#define SPI_DEVICE_FLASH_STATUS_BUSY_BIT 0
#define SPI_DEVICE_FLASH_STATUS_WEL_BIT 1
#define SPI_DEVICE_FLASH_STATUS_STATUS_MASK 0x3fffffu
#define SPI_DEVICE_FLASH_STATUS_STATUS_OFFSET 2
#define SPI_DEVICE_FLASH_STATUS_STATUS_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_FLASH_STATUS_STATUS_MASK, .index = SPI_DEVICE_FLASH_STATUS_STATUS_OFFSET })
 
// JEDEC Continuation Code configuration register.
#define SPI_DEVICE_JEDEC_CC_REG_OFFSET 0x2c
#define SPI_DEVICE_JEDEC_CC_REG_RESVAL 0x7fu
#define SPI_DEVICE_JEDEC_CC_CC_MASK 0xffu
#define SPI_DEVICE_JEDEC_CC_CC_OFFSET 0
#define SPI_DEVICE_JEDEC_CC_CC_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_CC_CC_MASK, .index = SPI_DEVICE_JEDEC_CC_CC_OFFSET })
#define SPI_DEVICE_JEDEC_CC_NUM_CC_MASK 0xffu
#define SPI_DEVICE_JEDEC_CC_NUM_CC_OFFSET 8
#define SPI_DEVICE_JEDEC_CC_NUM_CC_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_CC_NUM_CC_MASK, .index = SPI_DEVICE_JEDEC_CC_NUM_CC_OFFSET })
 
// JEDEC ID register.
#define SPI_DEVICE_JEDEC_ID_REG_OFFSET 0x30
#define SPI_DEVICE_JEDEC_ID_REG_RESVAL 0x0u
#define SPI_DEVICE_JEDEC_ID_ID_MASK 0xffffu
#define SPI_DEVICE_JEDEC_ID_ID_OFFSET 0
#define SPI_DEVICE_JEDEC_ID_ID_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_ID_ID_MASK, .index = SPI_DEVICE_JEDEC_ID_ID_OFFSET })
#define SPI_DEVICE_JEDEC_ID_MF_MASK 0xffu
#define SPI_DEVICE_JEDEC_ID_MF_OFFSET 16
#define SPI_DEVICE_JEDEC_ID_MF_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_JEDEC_ID_MF_MASK, .index = SPI_DEVICE_JEDEC_ID_MF_OFFSET })
 
// Read Buffer threshold register.
#define SPI_DEVICE_READ_THRESHOLD_REG_OFFSET 0x34
#define SPI_DEVICE_READ_THRESHOLD_REG_RESVAL 0x0u
#define SPI_DEVICE_READ_THRESHOLD_THRESHOLD_MASK 0x3ffu
#define SPI_DEVICE_READ_THRESHOLD_THRESHOLD_OFFSET 0
#define SPI_DEVICE_READ_THRESHOLD_THRESHOLD_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_READ_THRESHOLD_THRESHOLD_MASK, .index = SPI_DEVICE_READ_THRESHOLD_THRESHOLD_OFFSET })
 
// Mailbox Base address register.
#define SPI_DEVICE_MAILBOX_ADDR_REG_OFFSET 0x38
#define SPI_DEVICE_MAILBOX_ADDR_REG_RESVAL 0x0u
 
// Upload module status register.
#define SPI_DEVICE_UPLOAD_STATUS_REG_OFFSET 0x3c
#define SPI_DEVICE_UPLOAD_STATUS_REG_RESVAL 0x0u
#define SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_MASK 0x1fu
#define SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_OFFSET 0
#define SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_MASK, .index = SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_DEPTH_OFFSET })
#define SPI_DEVICE_UPLOAD_STATUS_CMDFIFO_NOTEMPTY_BIT 7
#define SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_MASK 0x1fu
#define SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_OFFSET 8
#define SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_MASK, .index = SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_DEPTH_OFFSET })
#define SPI_DEVICE_UPLOAD_STATUS_ADDRFIFO_NOTEMPTY_BIT 15
 
// Upload module status 2 register.
#define SPI_DEVICE_UPLOAD_STATUS2_REG_OFFSET 0x40
#define SPI_DEVICE_UPLOAD_STATUS2_REG_RESVAL 0x0u
#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_MASK 0x1ffu
#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_OFFSET 0
#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_MASK, .index = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_DEPTH_OFFSET })
#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_MASK 0xffu
#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_OFFSET 16
#define SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_MASK, .index = SPI_DEVICE_UPLOAD_STATUS2_PAYLOAD_START_IDX_OFFSET })
 
// Command Fifo Read Port.
#define SPI_DEVICE_UPLOAD_CMDFIFO_REG_OFFSET 0x44
#define SPI_DEVICE_UPLOAD_CMDFIFO_REG_RESVAL 0x0u
#define SPI_DEVICE_UPLOAD_CMDFIFO_DATA_MASK 0xffu
#define SPI_DEVICE_UPLOAD_CMDFIFO_DATA_OFFSET 0
#define SPI_DEVICE_UPLOAD_CMDFIFO_DATA_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_UPLOAD_CMDFIFO_DATA_MASK, .index = SPI_DEVICE_UPLOAD_CMDFIFO_DATA_OFFSET })
#define SPI_DEVICE_UPLOAD_CMDFIFO_BUSY_BIT 13
#define SPI_DEVICE_UPLOAD_CMDFIFO_WEL_BIT 14
#define SPI_DEVICE_UPLOAD_CMDFIFO_ADDR4B_MODE_BIT 15
 
// Address Fifo Read Port.
#define SPI_DEVICE_UPLOAD_ADDRFIFO_REG_OFFSET 0x48
#define SPI_DEVICE_UPLOAD_ADDRFIFO_REG_RESVAL 0x0u
 
// Command Filter
#define SPI_DEVICE_CMD_FILTER_FILTER_FIELD_WIDTH 1
#define SPI_DEVICE_CMD_FILTER_MULTIREG_COUNT 8
 
// Command Filter
#define SPI_DEVICE_CMD_FILTER_0_REG_OFFSET 0x4c
#define SPI_DEVICE_CMD_FILTER_0_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_FILTER_0_FILTER_0_BIT 0
#define SPI_DEVICE_CMD_FILTER_0_FILTER_1_BIT 1
#define SPI_DEVICE_CMD_FILTER_0_FILTER_2_BIT 2
#define SPI_DEVICE_CMD_FILTER_0_FILTER_3_BIT 3
#define SPI_DEVICE_CMD_FILTER_0_FILTER_4_BIT 4
#define SPI_DEVICE_CMD_FILTER_0_FILTER_5_BIT 5
#define SPI_DEVICE_CMD_FILTER_0_FILTER_6_BIT 6
#define SPI_DEVICE_CMD_FILTER_0_FILTER_7_BIT 7
#define SPI_DEVICE_CMD_FILTER_0_FILTER_8_BIT 8
#define SPI_DEVICE_CMD_FILTER_0_FILTER_9_BIT 9
#define SPI_DEVICE_CMD_FILTER_0_FILTER_10_BIT 10
#define SPI_DEVICE_CMD_FILTER_0_FILTER_11_BIT 11
#define SPI_DEVICE_CMD_FILTER_0_FILTER_12_BIT 12
#define SPI_DEVICE_CMD_FILTER_0_FILTER_13_BIT 13
#define SPI_DEVICE_CMD_FILTER_0_FILTER_14_BIT 14
#define SPI_DEVICE_CMD_FILTER_0_FILTER_15_BIT 15
#define SPI_DEVICE_CMD_FILTER_0_FILTER_16_BIT 16
#define SPI_DEVICE_CMD_FILTER_0_FILTER_17_BIT 17
#define SPI_DEVICE_CMD_FILTER_0_FILTER_18_BIT 18
#define SPI_DEVICE_CMD_FILTER_0_FILTER_19_BIT 19
#define SPI_DEVICE_CMD_FILTER_0_FILTER_20_BIT 20
#define SPI_DEVICE_CMD_FILTER_0_FILTER_21_BIT 21
#define SPI_DEVICE_CMD_FILTER_0_FILTER_22_BIT 22
#define SPI_DEVICE_CMD_FILTER_0_FILTER_23_BIT 23
#define SPI_DEVICE_CMD_FILTER_0_FILTER_24_BIT 24
#define SPI_DEVICE_CMD_FILTER_0_FILTER_25_BIT 25
#define SPI_DEVICE_CMD_FILTER_0_FILTER_26_BIT 26
#define SPI_DEVICE_CMD_FILTER_0_FILTER_27_BIT 27
#define SPI_DEVICE_CMD_FILTER_0_FILTER_28_BIT 28
#define SPI_DEVICE_CMD_FILTER_0_FILTER_29_BIT 29
#define SPI_DEVICE_CMD_FILTER_0_FILTER_30_BIT 30
#define SPI_DEVICE_CMD_FILTER_0_FILTER_31_BIT 31
 
// Command Filter
#define SPI_DEVICE_CMD_FILTER_1_REG_OFFSET 0x50
#define SPI_DEVICE_CMD_FILTER_1_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_FILTER_1_FILTER_32_BIT 0
#define SPI_DEVICE_CMD_FILTER_1_FILTER_33_BIT 1
#define SPI_DEVICE_CMD_FILTER_1_FILTER_34_BIT 2
#define SPI_DEVICE_CMD_FILTER_1_FILTER_35_BIT 3
#define SPI_DEVICE_CMD_FILTER_1_FILTER_36_BIT 4
#define SPI_DEVICE_CMD_FILTER_1_FILTER_37_BIT 5
#define SPI_DEVICE_CMD_FILTER_1_FILTER_38_BIT 6
#define SPI_DEVICE_CMD_FILTER_1_FILTER_39_BIT 7
#define SPI_DEVICE_CMD_FILTER_1_FILTER_40_BIT 8
#define SPI_DEVICE_CMD_FILTER_1_FILTER_41_BIT 9
#define SPI_DEVICE_CMD_FILTER_1_FILTER_42_BIT 10
#define SPI_DEVICE_CMD_FILTER_1_FILTER_43_BIT 11
#define SPI_DEVICE_CMD_FILTER_1_FILTER_44_BIT 12
#define SPI_DEVICE_CMD_FILTER_1_FILTER_45_BIT 13
#define SPI_DEVICE_CMD_FILTER_1_FILTER_46_BIT 14
#define SPI_DEVICE_CMD_FILTER_1_FILTER_47_BIT 15
#define SPI_DEVICE_CMD_FILTER_1_FILTER_48_BIT 16
#define SPI_DEVICE_CMD_FILTER_1_FILTER_49_BIT 17
#define SPI_DEVICE_CMD_FILTER_1_FILTER_50_BIT 18
#define SPI_DEVICE_CMD_FILTER_1_FILTER_51_BIT 19
#define SPI_DEVICE_CMD_FILTER_1_FILTER_52_BIT 20
#define SPI_DEVICE_CMD_FILTER_1_FILTER_53_BIT 21
#define SPI_DEVICE_CMD_FILTER_1_FILTER_54_BIT 22
#define SPI_DEVICE_CMD_FILTER_1_FILTER_55_BIT 23
#define SPI_DEVICE_CMD_FILTER_1_FILTER_56_BIT 24
#define SPI_DEVICE_CMD_FILTER_1_FILTER_57_BIT 25
#define SPI_DEVICE_CMD_FILTER_1_FILTER_58_BIT 26
#define SPI_DEVICE_CMD_FILTER_1_FILTER_59_BIT 27
#define SPI_DEVICE_CMD_FILTER_1_FILTER_60_BIT 28
#define SPI_DEVICE_CMD_FILTER_1_FILTER_61_BIT 29
#define SPI_DEVICE_CMD_FILTER_1_FILTER_62_BIT 30
#define SPI_DEVICE_CMD_FILTER_1_FILTER_63_BIT 31
 
// Command Filter
#define SPI_DEVICE_CMD_FILTER_2_REG_OFFSET 0x54
#define SPI_DEVICE_CMD_FILTER_2_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_FILTER_2_FILTER_64_BIT 0
#define SPI_DEVICE_CMD_FILTER_2_FILTER_65_BIT 1
#define SPI_DEVICE_CMD_FILTER_2_FILTER_66_BIT 2
#define SPI_DEVICE_CMD_FILTER_2_FILTER_67_BIT 3
#define SPI_DEVICE_CMD_FILTER_2_FILTER_68_BIT 4
#define SPI_DEVICE_CMD_FILTER_2_FILTER_69_BIT 5
#define SPI_DEVICE_CMD_FILTER_2_FILTER_70_BIT 6
#define SPI_DEVICE_CMD_FILTER_2_FILTER_71_BIT 7
#define SPI_DEVICE_CMD_FILTER_2_FILTER_72_BIT 8
#define SPI_DEVICE_CMD_FILTER_2_FILTER_73_BIT 9
#define SPI_DEVICE_CMD_FILTER_2_FILTER_74_BIT 10
#define SPI_DEVICE_CMD_FILTER_2_FILTER_75_BIT 11
#define SPI_DEVICE_CMD_FILTER_2_FILTER_76_BIT 12
#define SPI_DEVICE_CMD_FILTER_2_FILTER_77_BIT 13
#define SPI_DEVICE_CMD_FILTER_2_FILTER_78_BIT 14
#define SPI_DEVICE_CMD_FILTER_2_FILTER_79_BIT 15
#define SPI_DEVICE_CMD_FILTER_2_FILTER_80_BIT 16
#define SPI_DEVICE_CMD_FILTER_2_FILTER_81_BIT 17
#define SPI_DEVICE_CMD_FILTER_2_FILTER_82_BIT 18
#define SPI_DEVICE_CMD_FILTER_2_FILTER_83_BIT 19
#define SPI_DEVICE_CMD_FILTER_2_FILTER_84_BIT 20
#define SPI_DEVICE_CMD_FILTER_2_FILTER_85_BIT 21
#define SPI_DEVICE_CMD_FILTER_2_FILTER_86_BIT 22
#define SPI_DEVICE_CMD_FILTER_2_FILTER_87_BIT 23
#define SPI_DEVICE_CMD_FILTER_2_FILTER_88_BIT 24
#define SPI_DEVICE_CMD_FILTER_2_FILTER_89_BIT 25
#define SPI_DEVICE_CMD_FILTER_2_FILTER_90_BIT 26
#define SPI_DEVICE_CMD_FILTER_2_FILTER_91_BIT 27
#define SPI_DEVICE_CMD_FILTER_2_FILTER_92_BIT 28
#define SPI_DEVICE_CMD_FILTER_2_FILTER_93_BIT 29
#define SPI_DEVICE_CMD_FILTER_2_FILTER_94_BIT 30
#define SPI_DEVICE_CMD_FILTER_2_FILTER_95_BIT 31
 
// Command Filter
#define SPI_DEVICE_CMD_FILTER_3_REG_OFFSET 0x58
#define SPI_DEVICE_CMD_FILTER_3_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_FILTER_3_FILTER_96_BIT 0
#define SPI_DEVICE_CMD_FILTER_3_FILTER_97_BIT 1
#define SPI_DEVICE_CMD_FILTER_3_FILTER_98_BIT 2
#define SPI_DEVICE_CMD_FILTER_3_FILTER_99_BIT 3
#define SPI_DEVICE_CMD_FILTER_3_FILTER_100_BIT 4
#define SPI_DEVICE_CMD_FILTER_3_FILTER_101_BIT 5
#define SPI_DEVICE_CMD_FILTER_3_FILTER_102_BIT 6
#define SPI_DEVICE_CMD_FILTER_3_FILTER_103_BIT 7
#define SPI_DEVICE_CMD_FILTER_3_FILTER_104_BIT 8
#define SPI_DEVICE_CMD_FILTER_3_FILTER_105_BIT 9
#define SPI_DEVICE_CMD_FILTER_3_FILTER_106_BIT 10
#define SPI_DEVICE_CMD_FILTER_3_FILTER_107_BIT 11
#define SPI_DEVICE_CMD_FILTER_3_FILTER_108_BIT 12
#define SPI_DEVICE_CMD_FILTER_3_FILTER_109_BIT 13
#define SPI_DEVICE_CMD_FILTER_3_FILTER_110_BIT 14
#define SPI_DEVICE_CMD_FILTER_3_FILTER_111_BIT 15
#define SPI_DEVICE_CMD_FILTER_3_FILTER_112_BIT 16
#define SPI_DEVICE_CMD_FILTER_3_FILTER_113_BIT 17
#define SPI_DEVICE_CMD_FILTER_3_FILTER_114_BIT 18
#define SPI_DEVICE_CMD_FILTER_3_FILTER_115_BIT 19
#define SPI_DEVICE_CMD_FILTER_3_FILTER_116_BIT 20
#define SPI_DEVICE_CMD_FILTER_3_FILTER_117_BIT 21
#define SPI_DEVICE_CMD_FILTER_3_FILTER_118_BIT 22
#define SPI_DEVICE_CMD_FILTER_3_FILTER_119_BIT 23
#define SPI_DEVICE_CMD_FILTER_3_FILTER_120_BIT 24
#define SPI_DEVICE_CMD_FILTER_3_FILTER_121_BIT 25
#define SPI_DEVICE_CMD_FILTER_3_FILTER_122_BIT 26
#define SPI_DEVICE_CMD_FILTER_3_FILTER_123_BIT 27
#define SPI_DEVICE_CMD_FILTER_3_FILTER_124_BIT 28
#define SPI_DEVICE_CMD_FILTER_3_FILTER_125_BIT 29
#define SPI_DEVICE_CMD_FILTER_3_FILTER_126_BIT 30
#define SPI_DEVICE_CMD_FILTER_3_FILTER_127_BIT 31
 
// Command Filter
#define SPI_DEVICE_CMD_FILTER_4_REG_OFFSET 0x5c
#define SPI_DEVICE_CMD_FILTER_4_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_FILTER_4_FILTER_128_BIT 0
#define SPI_DEVICE_CMD_FILTER_4_FILTER_129_BIT 1
#define SPI_DEVICE_CMD_FILTER_4_FILTER_130_BIT 2
#define SPI_DEVICE_CMD_FILTER_4_FILTER_131_BIT 3
#define SPI_DEVICE_CMD_FILTER_4_FILTER_132_BIT 4
#define SPI_DEVICE_CMD_FILTER_4_FILTER_133_BIT 5
#define SPI_DEVICE_CMD_FILTER_4_FILTER_134_BIT 6
#define SPI_DEVICE_CMD_FILTER_4_FILTER_135_BIT 7
#define SPI_DEVICE_CMD_FILTER_4_FILTER_136_BIT 8
#define SPI_DEVICE_CMD_FILTER_4_FILTER_137_BIT 9
#define SPI_DEVICE_CMD_FILTER_4_FILTER_138_BIT 10
#define SPI_DEVICE_CMD_FILTER_4_FILTER_139_BIT 11
#define SPI_DEVICE_CMD_FILTER_4_FILTER_140_BIT 12
#define SPI_DEVICE_CMD_FILTER_4_FILTER_141_BIT 13
#define SPI_DEVICE_CMD_FILTER_4_FILTER_142_BIT 14
#define SPI_DEVICE_CMD_FILTER_4_FILTER_143_BIT 15
#define SPI_DEVICE_CMD_FILTER_4_FILTER_144_BIT 16
#define SPI_DEVICE_CMD_FILTER_4_FILTER_145_BIT 17
#define SPI_DEVICE_CMD_FILTER_4_FILTER_146_BIT 18
#define SPI_DEVICE_CMD_FILTER_4_FILTER_147_BIT 19
#define SPI_DEVICE_CMD_FILTER_4_FILTER_148_BIT 20
#define SPI_DEVICE_CMD_FILTER_4_FILTER_149_BIT 21
#define SPI_DEVICE_CMD_FILTER_4_FILTER_150_BIT 22
#define SPI_DEVICE_CMD_FILTER_4_FILTER_151_BIT 23
#define SPI_DEVICE_CMD_FILTER_4_FILTER_152_BIT 24
#define SPI_DEVICE_CMD_FILTER_4_FILTER_153_BIT 25
#define SPI_DEVICE_CMD_FILTER_4_FILTER_154_BIT 26
#define SPI_DEVICE_CMD_FILTER_4_FILTER_155_BIT 27
#define SPI_DEVICE_CMD_FILTER_4_FILTER_156_BIT 28
#define SPI_DEVICE_CMD_FILTER_4_FILTER_157_BIT 29
#define SPI_DEVICE_CMD_FILTER_4_FILTER_158_BIT 30
#define SPI_DEVICE_CMD_FILTER_4_FILTER_159_BIT 31
 
// Command Filter
#define SPI_DEVICE_CMD_FILTER_5_REG_OFFSET 0x60
#define SPI_DEVICE_CMD_FILTER_5_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_FILTER_5_FILTER_160_BIT 0
#define SPI_DEVICE_CMD_FILTER_5_FILTER_161_BIT 1
#define SPI_DEVICE_CMD_FILTER_5_FILTER_162_BIT 2
#define SPI_DEVICE_CMD_FILTER_5_FILTER_163_BIT 3
#define SPI_DEVICE_CMD_FILTER_5_FILTER_164_BIT 4
#define SPI_DEVICE_CMD_FILTER_5_FILTER_165_BIT 5
#define SPI_DEVICE_CMD_FILTER_5_FILTER_166_BIT 6
#define SPI_DEVICE_CMD_FILTER_5_FILTER_167_BIT 7
#define SPI_DEVICE_CMD_FILTER_5_FILTER_168_BIT 8
#define SPI_DEVICE_CMD_FILTER_5_FILTER_169_BIT 9
#define SPI_DEVICE_CMD_FILTER_5_FILTER_170_BIT 10
#define SPI_DEVICE_CMD_FILTER_5_FILTER_171_BIT 11
#define SPI_DEVICE_CMD_FILTER_5_FILTER_172_BIT 12
#define SPI_DEVICE_CMD_FILTER_5_FILTER_173_BIT 13
#define SPI_DEVICE_CMD_FILTER_5_FILTER_174_BIT 14
#define SPI_DEVICE_CMD_FILTER_5_FILTER_175_BIT 15
#define SPI_DEVICE_CMD_FILTER_5_FILTER_176_BIT 16
#define SPI_DEVICE_CMD_FILTER_5_FILTER_177_BIT 17
#define SPI_DEVICE_CMD_FILTER_5_FILTER_178_BIT 18
#define SPI_DEVICE_CMD_FILTER_5_FILTER_179_BIT 19
#define SPI_DEVICE_CMD_FILTER_5_FILTER_180_BIT 20
#define SPI_DEVICE_CMD_FILTER_5_FILTER_181_BIT 21
#define SPI_DEVICE_CMD_FILTER_5_FILTER_182_BIT 22
#define SPI_DEVICE_CMD_FILTER_5_FILTER_183_BIT 23
#define SPI_DEVICE_CMD_FILTER_5_FILTER_184_BIT 24
#define SPI_DEVICE_CMD_FILTER_5_FILTER_185_BIT 25
#define SPI_DEVICE_CMD_FILTER_5_FILTER_186_BIT 26
#define SPI_DEVICE_CMD_FILTER_5_FILTER_187_BIT 27
#define SPI_DEVICE_CMD_FILTER_5_FILTER_188_BIT 28
#define SPI_DEVICE_CMD_FILTER_5_FILTER_189_BIT 29
#define SPI_DEVICE_CMD_FILTER_5_FILTER_190_BIT 30
#define SPI_DEVICE_CMD_FILTER_5_FILTER_191_BIT 31
 
// Command Filter
#define SPI_DEVICE_CMD_FILTER_6_REG_OFFSET 0x64
#define SPI_DEVICE_CMD_FILTER_6_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_FILTER_6_FILTER_192_BIT 0
#define SPI_DEVICE_CMD_FILTER_6_FILTER_193_BIT 1
#define SPI_DEVICE_CMD_FILTER_6_FILTER_194_BIT 2
#define SPI_DEVICE_CMD_FILTER_6_FILTER_195_BIT 3
#define SPI_DEVICE_CMD_FILTER_6_FILTER_196_BIT 4
#define SPI_DEVICE_CMD_FILTER_6_FILTER_197_BIT 5
#define SPI_DEVICE_CMD_FILTER_6_FILTER_198_BIT 6
#define SPI_DEVICE_CMD_FILTER_6_FILTER_199_BIT 7
#define SPI_DEVICE_CMD_FILTER_6_FILTER_200_BIT 8
#define SPI_DEVICE_CMD_FILTER_6_FILTER_201_BIT 9
#define SPI_DEVICE_CMD_FILTER_6_FILTER_202_BIT 10
#define SPI_DEVICE_CMD_FILTER_6_FILTER_203_BIT 11
#define SPI_DEVICE_CMD_FILTER_6_FILTER_204_BIT 12
#define SPI_DEVICE_CMD_FILTER_6_FILTER_205_BIT 13
#define SPI_DEVICE_CMD_FILTER_6_FILTER_206_BIT 14
#define SPI_DEVICE_CMD_FILTER_6_FILTER_207_BIT 15
#define SPI_DEVICE_CMD_FILTER_6_FILTER_208_BIT 16
#define SPI_DEVICE_CMD_FILTER_6_FILTER_209_BIT 17
#define SPI_DEVICE_CMD_FILTER_6_FILTER_210_BIT 18
#define SPI_DEVICE_CMD_FILTER_6_FILTER_211_BIT 19
#define SPI_DEVICE_CMD_FILTER_6_FILTER_212_BIT 20
#define SPI_DEVICE_CMD_FILTER_6_FILTER_213_BIT 21
#define SPI_DEVICE_CMD_FILTER_6_FILTER_214_BIT 22
#define SPI_DEVICE_CMD_FILTER_6_FILTER_215_BIT 23
#define SPI_DEVICE_CMD_FILTER_6_FILTER_216_BIT 24
#define SPI_DEVICE_CMD_FILTER_6_FILTER_217_BIT 25
#define SPI_DEVICE_CMD_FILTER_6_FILTER_218_BIT 26
#define SPI_DEVICE_CMD_FILTER_6_FILTER_219_BIT 27
#define SPI_DEVICE_CMD_FILTER_6_FILTER_220_BIT 28
#define SPI_DEVICE_CMD_FILTER_6_FILTER_221_BIT 29
#define SPI_DEVICE_CMD_FILTER_6_FILTER_222_BIT 30
#define SPI_DEVICE_CMD_FILTER_6_FILTER_223_BIT 31
 
// Command Filter
#define SPI_DEVICE_CMD_FILTER_7_REG_OFFSET 0x68
#define SPI_DEVICE_CMD_FILTER_7_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_FILTER_7_FILTER_224_BIT 0
#define SPI_DEVICE_CMD_FILTER_7_FILTER_225_BIT 1
#define SPI_DEVICE_CMD_FILTER_7_FILTER_226_BIT 2
#define SPI_DEVICE_CMD_FILTER_7_FILTER_227_BIT 3
#define SPI_DEVICE_CMD_FILTER_7_FILTER_228_BIT 4
#define SPI_DEVICE_CMD_FILTER_7_FILTER_229_BIT 5
#define SPI_DEVICE_CMD_FILTER_7_FILTER_230_BIT 6
#define SPI_DEVICE_CMD_FILTER_7_FILTER_231_BIT 7
#define SPI_DEVICE_CMD_FILTER_7_FILTER_232_BIT 8
#define SPI_DEVICE_CMD_FILTER_7_FILTER_233_BIT 9
#define SPI_DEVICE_CMD_FILTER_7_FILTER_234_BIT 10
#define SPI_DEVICE_CMD_FILTER_7_FILTER_235_BIT 11
#define SPI_DEVICE_CMD_FILTER_7_FILTER_236_BIT 12
#define SPI_DEVICE_CMD_FILTER_7_FILTER_237_BIT 13
#define SPI_DEVICE_CMD_FILTER_7_FILTER_238_BIT 14
#define SPI_DEVICE_CMD_FILTER_7_FILTER_239_BIT 15
#define SPI_DEVICE_CMD_FILTER_7_FILTER_240_BIT 16
#define SPI_DEVICE_CMD_FILTER_7_FILTER_241_BIT 17
#define SPI_DEVICE_CMD_FILTER_7_FILTER_242_BIT 18
#define SPI_DEVICE_CMD_FILTER_7_FILTER_243_BIT 19
#define SPI_DEVICE_CMD_FILTER_7_FILTER_244_BIT 20
#define SPI_DEVICE_CMD_FILTER_7_FILTER_245_BIT 21
#define SPI_DEVICE_CMD_FILTER_7_FILTER_246_BIT 22
#define SPI_DEVICE_CMD_FILTER_7_FILTER_247_BIT 23
#define SPI_DEVICE_CMD_FILTER_7_FILTER_248_BIT 24
#define SPI_DEVICE_CMD_FILTER_7_FILTER_249_BIT 25
#define SPI_DEVICE_CMD_FILTER_7_FILTER_250_BIT 26
#define SPI_DEVICE_CMD_FILTER_7_FILTER_251_BIT 27
#define SPI_DEVICE_CMD_FILTER_7_FILTER_252_BIT 28
#define SPI_DEVICE_CMD_FILTER_7_FILTER_253_BIT 29
#define SPI_DEVICE_CMD_FILTER_7_FILTER_254_BIT 30
#define SPI_DEVICE_CMD_FILTER_7_FILTER_255_BIT 31
 
// Address Swap Mask register.
#define SPI_DEVICE_ADDR_SWAP_MASK_REG_OFFSET 0x6c
#define SPI_DEVICE_ADDR_SWAP_MASK_REG_RESVAL 0x0u
 
// The address value for the address swap feature.
#define SPI_DEVICE_ADDR_SWAP_DATA_REG_OFFSET 0x70
#define SPI_DEVICE_ADDR_SWAP_DATA_REG_RESVAL 0x0u
 
// Write Data Swap in the passthrough mode.
#define SPI_DEVICE_PAYLOAD_SWAP_MASK_REG_OFFSET 0x74
#define SPI_DEVICE_PAYLOAD_SWAP_MASK_REG_RESVAL 0x0u
 
// Write Data Swap in the passthrough mode.
#define SPI_DEVICE_PAYLOAD_SWAP_DATA_REG_OFFSET 0x78
#define SPI_DEVICE_PAYLOAD_SWAP_DATA_REG_RESVAL 0x0u
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_OPCODE_FIELD_WIDTH 8
#define SPI_DEVICE_CMD_INFO_ADDR_MODE_FIELD_WIDTH 2
#define SPI_DEVICE_CMD_INFO_ADDR_SWAP_EN_FIELD_WIDTH 1
#define SPI_DEVICE_CMD_INFO_MBYTE_EN_FIELD_WIDTH 1
#define SPI_DEVICE_CMD_INFO_DUMMY_SIZE_FIELD_WIDTH 3
#define SPI_DEVICE_CMD_INFO_DUMMY_EN_FIELD_WIDTH 1
#define SPI_DEVICE_CMD_INFO_PAYLOAD_EN_FIELD_WIDTH 4
#define SPI_DEVICE_CMD_INFO_PAYLOAD_DIR_FIELD_WIDTH 1
#define SPI_DEVICE_CMD_INFO_PAYLOAD_SWAP_EN_FIELD_WIDTH 1
#define SPI_DEVICE_CMD_INFO_READ_PIPELINE_MODE_FIELD_WIDTH 2
#define SPI_DEVICE_CMD_INFO_UPLOAD_FIELD_WIDTH 1
#define SPI_DEVICE_CMD_INFO_BUSY_FIELD_WIDTH 1
#define SPI_DEVICE_CMD_INFO_VALID_FIELD_WIDTH 1
#define SPI_DEVICE_CMD_INFO_MULTIREG_COUNT 24
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_0_REG_OFFSET 0x7c
#define SPI_DEVICE_CMD_INFO_0_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_0_OPCODE_0_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_0_OPCODE_0_OFFSET 0
#define SPI_DEVICE_CMD_INFO_0_OPCODE_0_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_OPCODE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_OPCODE_0_OFFSET })
#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_OFFSET 8
#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_OFFSET })
#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDRDISABLED 0x0
#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDRCFG 0x1
#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDR3B 0x2
#define SPI_DEVICE_CMD_INFO_0_ADDR_MODE_0_VALUE_ADDR4B 0x3
#define SPI_DEVICE_CMD_INFO_0_ADDR_SWAP_EN_0_BIT 10
#define SPI_DEVICE_CMD_INFO_0_MBYTE_EN_0_BIT 11
#define SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_OFFSET 12
#define SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_DUMMY_SIZE_0_OFFSET })
#define SPI_DEVICE_CMD_INFO_0_DUMMY_EN_0_BIT 15
#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_OFFSET 16
#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_PAYLOAD_EN_0_OFFSET })
#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_BIT 20
#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_VALUE_PAYLOADIN 0x0
#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_DIR_0_VALUE_PAYLOADOUT 0x1
#define SPI_DEVICE_CMD_INFO_0_PAYLOAD_SWAP_EN_0_BIT 21
#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_OFFSET 22
#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_MASK, .index = SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_OFFSET })
#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_ZERO_STAGES 0x0
#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_TWO_STAGES_HALF_CYCLE \
  0x1
#define SPI_DEVICE_CMD_INFO_0_READ_PIPELINE_MODE_0_VALUE_TWO_STAGES_FULL_CYCLE \
  0x2
#define SPI_DEVICE_CMD_INFO_0_UPLOAD_0_BIT 24
#define SPI_DEVICE_CMD_INFO_0_BUSY_0_BIT 25
#define SPI_DEVICE_CMD_INFO_0_VALID_0_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_1_REG_OFFSET 0x80
#define SPI_DEVICE_CMD_INFO_1_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_1_OPCODE_1_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_1_OPCODE_1_OFFSET 0
#define SPI_DEVICE_CMD_INFO_1_OPCODE_1_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_OPCODE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_OPCODE_1_OFFSET })
#define SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_OFFSET 8
#define SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_ADDR_MODE_1_OFFSET })
#define SPI_DEVICE_CMD_INFO_1_ADDR_SWAP_EN_1_BIT 10
#define SPI_DEVICE_CMD_INFO_1_MBYTE_EN_1_BIT 11
#define SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_OFFSET 12
#define SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_DUMMY_SIZE_1_OFFSET })
#define SPI_DEVICE_CMD_INFO_1_DUMMY_EN_1_BIT 15
#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_OFFSET 16
#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_PAYLOAD_EN_1_OFFSET })
#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_DIR_1_BIT 20
#define SPI_DEVICE_CMD_INFO_1_PAYLOAD_SWAP_EN_1_BIT 21
#define SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_OFFSET 22
#define SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_MASK, .index = SPI_DEVICE_CMD_INFO_1_READ_PIPELINE_MODE_1_OFFSET })
#define SPI_DEVICE_CMD_INFO_1_UPLOAD_1_BIT 24
#define SPI_DEVICE_CMD_INFO_1_BUSY_1_BIT 25
#define SPI_DEVICE_CMD_INFO_1_VALID_1_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_2_REG_OFFSET 0x84
#define SPI_DEVICE_CMD_INFO_2_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_2_OPCODE_2_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_2_OPCODE_2_OFFSET 0
#define SPI_DEVICE_CMD_INFO_2_OPCODE_2_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_OPCODE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_OPCODE_2_OFFSET })
#define SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_OFFSET 8
#define SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_ADDR_MODE_2_OFFSET })
#define SPI_DEVICE_CMD_INFO_2_ADDR_SWAP_EN_2_BIT 10
#define SPI_DEVICE_CMD_INFO_2_MBYTE_EN_2_BIT 11
#define SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_OFFSET 12
#define SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_DUMMY_SIZE_2_OFFSET })
#define SPI_DEVICE_CMD_INFO_2_DUMMY_EN_2_BIT 15
#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_OFFSET 16
#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_PAYLOAD_EN_2_OFFSET })
#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_DIR_2_BIT 20
#define SPI_DEVICE_CMD_INFO_2_PAYLOAD_SWAP_EN_2_BIT 21
#define SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_OFFSET 22
#define SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_MASK, .index = SPI_DEVICE_CMD_INFO_2_READ_PIPELINE_MODE_2_OFFSET })
#define SPI_DEVICE_CMD_INFO_2_UPLOAD_2_BIT 24
#define SPI_DEVICE_CMD_INFO_2_BUSY_2_BIT 25
#define SPI_DEVICE_CMD_INFO_2_VALID_2_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_3_REG_OFFSET 0x88
#define SPI_DEVICE_CMD_INFO_3_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_3_OPCODE_3_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_3_OPCODE_3_OFFSET 0
#define SPI_DEVICE_CMD_INFO_3_OPCODE_3_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_OPCODE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_OPCODE_3_OFFSET })
#define SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_OFFSET 8
#define SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_ADDR_MODE_3_OFFSET })
#define SPI_DEVICE_CMD_INFO_3_ADDR_SWAP_EN_3_BIT 10
#define SPI_DEVICE_CMD_INFO_3_MBYTE_EN_3_BIT 11
#define SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_OFFSET 12
#define SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_DUMMY_SIZE_3_OFFSET })
#define SPI_DEVICE_CMD_INFO_3_DUMMY_EN_3_BIT 15
#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_OFFSET 16
#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_PAYLOAD_EN_3_OFFSET })
#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_DIR_3_BIT 20
#define SPI_DEVICE_CMD_INFO_3_PAYLOAD_SWAP_EN_3_BIT 21
#define SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_OFFSET 22
#define SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_MASK, .index = SPI_DEVICE_CMD_INFO_3_READ_PIPELINE_MODE_3_OFFSET })
#define SPI_DEVICE_CMD_INFO_3_UPLOAD_3_BIT 24
#define SPI_DEVICE_CMD_INFO_3_BUSY_3_BIT 25
#define SPI_DEVICE_CMD_INFO_3_VALID_3_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_4_REG_OFFSET 0x8c
#define SPI_DEVICE_CMD_INFO_4_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_4_OPCODE_4_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_4_OPCODE_4_OFFSET 0
#define SPI_DEVICE_CMD_INFO_4_OPCODE_4_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_OPCODE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_OPCODE_4_OFFSET })
#define SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_OFFSET 8
#define SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_ADDR_MODE_4_OFFSET })
#define SPI_DEVICE_CMD_INFO_4_ADDR_SWAP_EN_4_BIT 10
#define SPI_DEVICE_CMD_INFO_4_MBYTE_EN_4_BIT 11
#define SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_OFFSET 12
#define SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_DUMMY_SIZE_4_OFFSET })
#define SPI_DEVICE_CMD_INFO_4_DUMMY_EN_4_BIT 15
#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_OFFSET 16
#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_PAYLOAD_EN_4_OFFSET })
#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_DIR_4_BIT 20
#define SPI_DEVICE_CMD_INFO_4_PAYLOAD_SWAP_EN_4_BIT 21
#define SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_OFFSET 22
#define SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_MASK, .index = SPI_DEVICE_CMD_INFO_4_READ_PIPELINE_MODE_4_OFFSET })
#define SPI_DEVICE_CMD_INFO_4_UPLOAD_4_BIT 24
#define SPI_DEVICE_CMD_INFO_4_BUSY_4_BIT 25
#define SPI_DEVICE_CMD_INFO_4_VALID_4_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_5_REG_OFFSET 0x90
#define SPI_DEVICE_CMD_INFO_5_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_5_OPCODE_5_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_5_OPCODE_5_OFFSET 0
#define SPI_DEVICE_CMD_INFO_5_OPCODE_5_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_OPCODE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_OPCODE_5_OFFSET })
#define SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_OFFSET 8
#define SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_ADDR_MODE_5_OFFSET })
#define SPI_DEVICE_CMD_INFO_5_ADDR_SWAP_EN_5_BIT 10
#define SPI_DEVICE_CMD_INFO_5_MBYTE_EN_5_BIT 11
#define SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_OFFSET 12
#define SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_DUMMY_SIZE_5_OFFSET })
#define SPI_DEVICE_CMD_INFO_5_DUMMY_EN_5_BIT 15
#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_OFFSET 16
#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_PAYLOAD_EN_5_OFFSET })
#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_DIR_5_BIT 20
#define SPI_DEVICE_CMD_INFO_5_PAYLOAD_SWAP_EN_5_BIT 21
#define SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_OFFSET 22
#define SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_MASK, .index = SPI_DEVICE_CMD_INFO_5_READ_PIPELINE_MODE_5_OFFSET })
#define SPI_DEVICE_CMD_INFO_5_UPLOAD_5_BIT 24
#define SPI_DEVICE_CMD_INFO_5_BUSY_5_BIT 25
#define SPI_DEVICE_CMD_INFO_5_VALID_5_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_6_REG_OFFSET 0x94
#define SPI_DEVICE_CMD_INFO_6_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_6_OPCODE_6_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_6_OPCODE_6_OFFSET 0
#define SPI_DEVICE_CMD_INFO_6_OPCODE_6_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_OPCODE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_OPCODE_6_OFFSET })
#define SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_OFFSET 8
#define SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_ADDR_MODE_6_OFFSET })
#define SPI_DEVICE_CMD_INFO_6_ADDR_SWAP_EN_6_BIT 10
#define SPI_DEVICE_CMD_INFO_6_MBYTE_EN_6_BIT 11
#define SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_OFFSET 12
#define SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_DUMMY_SIZE_6_OFFSET })
#define SPI_DEVICE_CMD_INFO_6_DUMMY_EN_6_BIT 15
#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_OFFSET 16
#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_PAYLOAD_EN_6_OFFSET })
#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_DIR_6_BIT 20
#define SPI_DEVICE_CMD_INFO_6_PAYLOAD_SWAP_EN_6_BIT 21
#define SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_OFFSET 22
#define SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_MASK, .index = SPI_DEVICE_CMD_INFO_6_READ_PIPELINE_MODE_6_OFFSET })
#define SPI_DEVICE_CMD_INFO_6_UPLOAD_6_BIT 24
#define SPI_DEVICE_CMD_INFO_6_BUSY_6_BIT 25
#define SPI_DEVICE_CMD_INFO_6_VALID_6_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_7_REG_OFFSET 0x98
#define SPI_DEVICE_CMD_INFO_7_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_7_OPCODE_7_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_7_OPCODE_7_OFFSET 0
#define SPI_DEVICE_CMD_INFO_7_OPCODE_7_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_OPCODE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_OPCODE_7_OFFSET })
#define SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_OFFSET 8
#define SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_ADDR_MODE_7_OFFSET })
#define SPI_DEVICE_CMD_INFO_7_ADDR_SWAP_EN_7_BIT 10
#define SPI_DEVICE_CMD_INFO_7_MBYTE_EN_7_BIT 11
#define SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_OFFSET 12
#define SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_DUMMY_SIZE_7_OFFSET })
#define SPI_DEVICE_CMD_INFO_7_DUMMY_EN_7_BIT 15
#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_OFFSET 16
#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_PAYLOAD_EN_7_OFFSET })
#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_DIR_7_BIT 20
#define SPI_DEVICE_CMD_INFO_7_PAYLOAD_SWAP_EN_7_BIT 21
#define SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_OFFSET 22
#define SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_MASK, .index = SPI_DEVICE_CMD_INFO_7_READ_PIPELINE_MODE_7_OFFSET })
#define SPI_DEVICE_CMD_INFO_7_UPLOAD_7_BIT 24
#define SPI_DEVICE_CMD_INFO_7_BUSY_7_BIT 25
#define SPI_DEVICE_CMD_INFO_7_VALID_7_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_8_REG_OFFSET 0x9c
#define SPI_DEVICE_CMD_INFO_8_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_8_OPCODE_8_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_8_OPCODE_8_OFFSET 0
#define SPI_DEVICE_CMD_INFO_8_OPCODE_8_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_OPCODE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_OPCODE_8_OFFSET })
#define SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_OFFSET 8
#define SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_ADDR_MODE_8_OFFSET })
#define SPI_DEVICE_CMD_INFO_8_ADDR_SWAP_EN_8_BIT 10
#define SPI_DEVICE_CMD_INFO_8_MBYTE_EN_8_BIT 11
#define SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_OFFSET 12
#define SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_DUMMY_SIZE_8_OFFSET })
#define SPI_DEVICE_CMD_INFO_8_DUMMY_EN_8_BIT 15
#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_OFFSET 16
#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_PAYLOAD_EN_8_OFFSET })
#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_DIR_8_BIT 20
#define SPI_DEVICE_CMD_INFO_8_PAYLOAD_SWAP_EN_8_BIT 21
#define SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_OFFSET 22
#define SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_MASK, .index = SPI_DEVICE_CMD_INFO_8_READ_PIPELINE_MODE_8_OFFSET })
#define SPI_DEVICE_CMD_INFO_8_UPLOAD_8_BIT 24
#define SPI_DEVICE_CMD_INFO_8_BUSY_8_BIT 25
#define SPI_DEVICE_CMD_INFO_8_VALID_8_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_9_REG_OFFSET 0xa0
#define SPI_DEVICE_CMD_INFO_9_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_9_OPCODE_9_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_9_OPCODE_9_OFFSET 0
#define SPI_DEVICE_CMD_INFO_9_OPCODE_9_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_OPCODE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_OPCODE_9_OFFSET })
#define SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_OFFSET 8
#define SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_ADDR_MODE_9_OFFSET })
#define SPI_DEVICE_CMD_INFO_9_ADDR_SWAP_EN_9_BIT 10
#define SPI_DEVICE_CMD_INFO_9_MBYTE_EN_9_BIT 11
#define SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_OFFSET 12
#define SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_DUMMY_SIZE_9_OFFSET })
#define SPI_DEVICE_CMD_INFO_9_DUMMY_EN_9_BIT 15
#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_OFFSET 16
#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_PAYLOAD_EN_9_OFFSET })
#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_DIR_9_BIT 20
#define SPI_DEVICE_CMD_INFO_9_PAYLOAD_SWAP_EN_9_BIT 21
#define SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_OFFSET 22
#define SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_MASK, .index = SPI_DEVICE_CMD_INFO_9_READ_PIPELINE_MODE_9_OFFSET })
#define SPI_DEVICE_CMD_INFO_9_UPLOAD_9_BIT 24
#define SPI_DEVICE_CMD_INFO_9_BUSY_9_BIT 25
#define SPI_DEVICE_CMD_INFO_9_VALID_9_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_10_REG_OFFSET 0xa4
#define SPI_DEVICE_CMD_INFO_10_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_10_OPCODE_10_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_10_OPCODE_10_OFFSET 0
#define SPI_DEVICE_CMD_INFO_10_OPCODE_10_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_OPCODE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_OPCODE_10_OFFSET })
#define SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_OFFSET 8
#define SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_ADDR_MODE_10_OFFSET })
#define SPI_DEVICE_CMD_INFO_10_ADDR_SWAP_EN_10_BIT 10
#define SPI_DEVICE_CMD_INFO_10_MBYTE_EN_10_BIT 11
#define SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_OFFSET 12
#define SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_DUMMY_SIZE_10_OFFSET })
#define SPI_DEVICE_CMD_INFO_10_DUMMY_EN_10_BIT 15
#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_OFFSET 16
#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_PAYLOAD_EN_10_OFFSET })
#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_DIR_10_BIT 20
#define SPI_DEVICE_CMD_INFO_10_PAYLOAD_SWAP_EN_10_BIT 21
#define SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_OFFSET 22
#define SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_MASK, .index = SPI_DEVICE_CMD_INFO_10_READ_PIPELINE_MODE_10_OFFSET })
#define SPI_DEVICE_CMD_INFO_10_UPLOAD_10_BIT 24
#define SPI_DEVICE_CMD_INFO_10_BUSY_10_BIT 25
#define SPI_DEVICE_CMD_INFO_10_VALID_10_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_11_REG_OFFSET 0xa8
#define SPI_DEVICE_CMD_INFO_11_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_11_OPCODE_11_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_11_OPCODE_11_OFFSET 0
#define SPI_DEVICE_CMD_INFO_11_OPCODE_11_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_OPCODE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_OPCODE_11_OFFSET })
#define SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_OFFSET 8
#define SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_ADDR_MODE_11_OFFSET })
#define SPI_DEVICE_CMD_INFO_11_ADDR_SWAP_EN_11_BIT 10
#define SPI_DEVICE_CMD_INFO_11_MBYTE_EN_11_BIT 11
#define SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_OFFSET 12
#define SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_DUMMY_SIZE_11_OFFSET })
#define SPI_DEVICE_CMD_INFO_11_DUMMY_EN_11_BIT 15
#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_OFFSET 16
#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_PAYLOAD_EN_11_OFFSET })
#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_DIR_11_BIT 20
#define SPI_DEVICE_CMD_INFO_11_PAYLOAD_SWAP_EN_11_BIT 21
#define SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_OFFSET 22
#define SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_MASK, .index = SPI_DEVICE_CMD_INFO_11_READ_PIPELINE_MODE_11_OFFSET })
#define SPI_DEVICE_CMD_INFO_11_UPLOAD_11_BIT 24
#define SPI_DEVICE_CMD_INFO_11_BUSY_11_BIT 25
#define SPI_DEVICE_CMD_INFO_11_VALID_11_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_12_REG_OFFSET 0xac
#define SPI_DEVICE_CMD_INFO_12_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_12_OPCODE_12_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_12_OPCODE_12_OFFSET 0
#define SPI_DEVICE_CMD_INFO_12_OPCODE_12_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_OPCODE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_OPCODE_12_OFFSET })
#define SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_OFFSET 8
#define SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_ADDR_MODE_12_OFFSET })
#define SPI_DEVICE_CMD_INFO_12_ADDR_SWAP_EN_12_BIT 10
#define SPI_DEVICE_CMD_INFO_12_MBYTE_EN_12_BIT 11
#define SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_OFFSET 12
#define SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_DUMMY_SIZE_12_OFFSET })
#define SPI_DEVICE_CMD_INFO_12_DUMMY_EN_12_BIT 15
#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_OFFSET 16
#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_PAYLOAD_EN_12_OFFSET })
#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_DIR_12_BIT 20
#define SPI_DEVICE_CMD_INFO_12_PAYLOAD_SWAP_EN_12_BIT 21
#define SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_OFFSET 22
#define SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_MASK, .index = SPI_DEVICE_CMD_INFO_12_READ_PIPELINE_MODE_12_OFFSET })
#define SPI_DEVICE_CMD_INFO_12_UPLOAD_12_BIT 24
#define SPI_DEVICE_CMD_INFO_12_BUSY_12_BIT 25
#define SPI_DEVICE_CMD_INFO_12_VALID_12_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_13_REG_OFFSET 0xb0
#define SPI_DEVICE_CMD_INFO_13_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_13_OPCODE_13_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_13_OPCODE_13_OFFSET 0
#define SPI_DEVICE_CMD_INFO_13_OPCODE_13_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_OPCODE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_OPCODE_13_OFFSET })
#define SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_OFFSET 8
#define SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_ADDR_MODE_13_OFFSET })
#define SPI_DEVICE_CMD_INFO_13_ADDR_SWAP_EN_13_BIT 10
#define SPI_DEVICE_CMD_INFO_13_MBYTE_EN_13_BIT 11
#define SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_OFFSET 12
#define SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_DUMMY_SIZE_13_OFFSET })
#define SPI_DEVICE_CMD_INFO_13_DUMMY_EN_13_BIT 15
#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_OFFSET 16
#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_PAYLOAD_EN_13_OFFSET })
#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_DIR_13_BIT 20
#define SPI_DEVICE_CMD_INFO_13_PAYLOAD_SWAP_EN_13_BIT 21
#define SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_OFFSET 22
#define SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_MASK, .index = SPI_DEVICE_CMD_INFO_13_READ_PIPELINE_MODE_13_OFFSET })
#define SPI_DEVICE_CMD_INFO_13_UPLOAD_13_BIT 24
#define SPI_DEVICE_CMD_INFO_13_BUSY_13_BIT 25
#define SPI_DEVICE_CMD_INFO_13_VALID_13_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_14_REG_OFFSET 0xb4
#define SPI_DEVICE_CMD_INFO_14_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_14_OPCODE_14_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_14_OPCODE_14_OFFSET 0
#define SPI_DEVICE_CMD_INFO_14_OPCODE_14_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_OPCODE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_OPCODE_14_OFFSET })
#define SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_OFFSET 8
#define SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_ADDR_MODE_14_OFFSET })
#define SPI_DEVICE_CMD_INFO_14_ADDR_SWAP_EN_14_BIT 10
#define SPI_DEVICE_CMD_INFO_14_MBYTE_EN_14_BIT 11
#define SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_OFFSET 12
#define SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_DUMMY_SIZE_14_OFFSET })
#define SPI_DEVICE_CMD_INFO_14_DUMMY_EN_14_BIT 15
#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_OFFSET 16
#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_PAYLOAD_EN_14_OFFSET })
#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_DIR_14_BIT 20
#define SPI_DEVICE_CMD_INFO_14_PAYLOAD_SWAP_EN_14_BIT 21
#define SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_OFFSET 22
#define SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_MASK, .index = SPI_DEVICE_CMD_INFO_14_READ_PIPELINE_MODE_14_OFFSET })
#define SPI_DEVICE_CMD_INFO_14_UPLOAD_14_BIT 24
#define SPI_DEVICE_CMD_INFO_14_BUSY_14_BIT 25
#define SPI_DEVICE_CMD_INFO_14_VALID_14_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_15_REG_OFFSET 0xb8
#define SPI_DEVICE_CMD_INFO_15_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_15_OPCODE_15_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_15_OPCODE_15_OFFSET 0
#define SPI_DEVICE_CMD_INFO_15_OPCODE_15_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_OPCODE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_OPCODE_15_OFFSET })
#define SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_OFFSET 8
#define SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_ADDR_MODE_15_OFFSET })
#define SPI_DEVICE_CMD_INFO_15_ADDR_SWAP_EN_15_BIT 10
#define SPI_DEVICE_CMD_INFO_15_MBYTE_EN_15_BIT 11
#define SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_OFFSET 12
#define SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_DUMMY_SIZE_15_OFFSET })
#define SPI_DEVICE_CMD_INFO_15_DUMMY_EN_15_BIT 15
#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_OFFSET 16
#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_PAYLOAD_EN_15_OFFSET })
#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_DIR_15_BIT 20
#define SPI_DEVICE_CMD_INFO_15_PAYLOAD_SWAP_EN_15_BIT 21
#define SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_OFFSET 22
#define SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_MASK, .index = SPI_DEVICE_CMD_INFO_15_READ_PIPELINE_MODE_15_OFFSET })
#define SPI_DEVICE_CMD_INFO_15_UPLOAD_15_BIT 24
#define SPI_DEVICE_CMD_INFO_15_BUSY_15_BIT 25
#define SPI_DEVICE_CMD_INFO_15_VALID_15_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_16_REG_OFFSET 0xbc
#define SPI_DEVICE_CMD_INFO_16_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_16_OPCODE_16_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_16_OPCODE_16_OFFSET 0
#define SPI_DEVICE_CMD_INFO_16_OPCODE_16_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_OPCODE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_OPCODE_16_OFFSET })
#define SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_OFFSET 8
#define SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_ADDR_MODE_16_OFFSET })
#define SPI_DEVICE_CMD_INFO_16_ADDR_SWAP_EN_16_BIT 10
#define SPI_DEVICE_CMD_INFO_16_MBYTE_EN_16_BIT 11
#define SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_OFFSET 12
#define SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_DUMMY_SIZE_16_OFFSET })
#define SPI_DEVICE_CMD_INFO_16_DUMMY_EN_16_BIT 15
#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_OFFSET 16
#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_PAYLOAD_EN_16_OFFSET })
#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_DIR_16_BIT 20
#define SPI_DEVICE_CMD_INFO_16_PAYLOAD_SWAP_EN_16_BIT 21
#define SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_OFFSET 22
#define SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_MASK, .index = SPI_DEVICE_CMD_INFO_16_READ_PIPELINE_MODE_16_OFFSET })
#define SPI_DEVICE_CMD_INFO_16_UPLOAD_16_BIT 24
#define SPI_DEVICE_CMD_INFO_16_BUSY_16_BIT 25
#define SPI_DEVICE_CMD_INFO_16_VALID_16_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_17_REG_OFFSET 0xc0
#define SPI_DEVICE_CMD_INFO_17_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_17_OPCODE_17_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_17_OPCODE_17_OFFSET 0
#define SPI_DEVICE_CMD_INFO_17_OPCODE_17_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_OPCODE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_OPCODE_17_OFFSET })
#define SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_OFFSET 8
#define SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_ADDR_MODE_17_OFFSET })
#define SPI_DEVICE_CMD_INFO_17_ADDR_SWAP_EN_17_BIT 10
#define SPI_DEVICE_CMD_INFO_17_MBYTE_EN_17_BIT 11
#define SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_OFFSET 12
#define SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_DUMMY_SIZE_17_OFFSET })
#define SPI_DEVICE_CMD_INFO_17_DUMMY_EN_17_BIT 15
#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_OFFSET 16
#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_PAYLOAD_EN_17_OFFSET })
#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_DIR_17_BIT 20
#define SPI_DEVICE_CMD_INFO_17_PAYLOAD_SWAP_EN_17_BIT 21
#define SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_OFFSET 22
#define SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_MASK, .index = SPI_DEVICE_CMD_INFO_17_READ_PIPELINE_MODE_17_OFFSET })
#define SPI_DEVICE_CMD_INFO_17_UPLOAD_17_BIT 24
#define SPI_DEVICE_CMD_INFO_17_BUSY_17_BIT 25
#define SPI_DEVICE_CMD_INFO_17_VALID_17_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_18_REG_OFFSET 0xc4
#define SPI_DEVICE_CMD_INFO_18_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_18_OPCODE_18_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_18_OPCODE_18_OFFSET 0
#define SPI_DEVICE_CMD_INFO_18_OPCODE_18_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_OPCODE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_OPCODE_18_OFFSET })
#define SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_OFFSET 8
#define SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_ADDR_MODE_18_OFFSET })
#define SPI_DEVICE_CMD_INFO_18_ADDR_SWAP_EN_18_BIT 10
#define SPI_DEVICE_CMD_INFO_18_MBYTE_EN_18_BIT 11
#define SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_OFFSET 12
#define SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_DUMMY_SIZE_18_OFFSET })
#define SPI_DEVICE_CMD_INFO_18_DUMMY_EN_18_BIT 15
#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_OFFSET 16
#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_PAYLOAD_EN_18_OFFSET })
#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_DIR_18_BIT 20
#define SPI_DEVICE_CMD_INFO_18_PAYLOAD_SWAP_EN_18_BIT 21
#define SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_OFFSET 22
#define SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_MASK, .index = SPI_DEVICE_CMD_INFO_18_READ_PIPELINE_MODE_18_OFFSET })
#define SPI_DEVICE_CMD_INFO_18_UPLOAD_18_BIT 24
#define SPI_DEVICE_CMD_INFO_18_BUSY_18_BIT 25
#define SPI_DEVICE_CMD_INFO_18_VALID_18_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_19_REG_OFFSET 0xc8
#define SPI_DEVICE_CMD_INFO_19_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_19_OPCODE_19_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_19_OPCODE_19_OFFSET 0
#define SPI_DEVICE_CMD_INFO_19_OPCODE_19_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_OPCODE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_OPCODE_19_OFFSET })
#define SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_OFFSET 8
#define SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_ADDR_MODE_19_OFFSET })
#define SPI_DEVICE_CMD_INFO_19_ADDR_SWAP_EN_19_BIT 10
#define SPI_DEVICE_CMD_INFO_19_MBYTE_EN_19_BIT 11
#define SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_OFFSET 12
#define SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_DUMMY_SIZE_19_OFFSET })
#define SPI_DEVICE_CMD_INFO_19_DUMMY_EN_19_BIT 15
#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_OFFSET 16
#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_PAYLOAD_EN_19_OFFSET })
#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_DIR_19_BIT 20
#define SPI_DEVICE_CMD_INFO_19_PAYLOAD_SWAP_EN_19_BIT 21
#define SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_OFFSET 22
#define SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_MASK, .index = SPI_DEVICE_CMD_INFO_19_READ_PIPELINE_MODE_19_OFFSET })
#define SPI_DEVICE_CMD_INFO_19_UPLOAD_19_BIT 24
#define SPI_DEVICE_CMD_INFO_19_BUSY_19_BIT 25
#define SPI_DEVICE_CMD_INFO_19_VALID_19_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_20_REG_OFFSET 0xcc
#define SPI_DEVICE_CMD_INFO_20_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_20_OPCODE_20_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_20_OPCODE_20_OFFSET 0
#define SPI_DEVICE_CMD_INFO_20_OPCODE_20_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_OPCODE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_OPCODE_20_OFFSET })
#define SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_OFFSET 8
#define SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_ADDR_MODE_20_OFFSET })
#define SPI_DEVICE_CMD_INFO_20_ADDR_SWAP_EN_20_BIT 10
#define SPI_DEVICE_CMD_INFO_20_MBYTE_EN_20_BIT 11
#define SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_OFFSET 12
#define SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_DUMMY_SIZE_20_OFFSET })
#define SPI_DEVICE_CMD_INFO_20_DUMMY_EN_20_BIT 15
#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_OFFSET 16
#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_PAYLOAD_EN_20_OFFSET })
#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_DIR_20_BIT 20
#define SPI_DEVICE_CMD_INFO_20_PAYLOAD_SWAP_EN_20_BIT 21
#define SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_OFFSET 22
#define SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_MASK, .index = SPI_DEVICE_CMD_INFO_20_READ_PIPELINE_MODE_20_OFFSET })
#define SPI_DEVICE_CMD_INFO_20_UPLOAD_20_BIT 24
#define SPI_DEVICE_CMD_INFO_20_BUSY_20_BIT 25
#define SPI_DEVICE_CMD_INFO_20_VALID_20_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_21_REG_OFFSET 0xd0
#define SPI_DEVICE_CMD_INFO_21_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_21_OPCODE_21_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_21_OPCODE_21_OFFSET 0
#define SPI_DEVICE_CMD_INFO_21_OPCODE_21_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_OPCODE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_OPCODE_21_OFFSET })
#define SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_OFFSET 8
#define SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_ADDR_MODE_21_OFFSET })
#define SPI_DEVICE_CMD_INFO_21_ADDR_SWAP_EN_21_BIT 10
#define SPI_DEVICE_CMD_INFO_21_MBYTE_EN_21_BIT 11
#define SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_OFFSET 12
#define SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_DUMMY_SIZE_21_OFFSET })
#define SPI_DEVICE_CMD_INFO_21_DUMMY_EN_21_BIT 15
#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_OFFSET 16
#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_PAYLOAD_EN_21_OFFSET })
#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_DIR_21_BIT 20
#define SPI_DEVICE_CMD_INFO_21_PAYLOAD_SWAP_EN_21_BIT 21
#define SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_OFFSET 22
#define SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_MASK, .index = SPI_DEVICE_CMD_INFO_21_READ_PIPELINE_MODE_21_OFFSET })
#define SPI_DEVICE_CMD_INFO_21_UPLOAD_21_BIT 24
#define SPI_DEVICE_CMD_INFO_21_BUSY_21_BIT 25
#define SPI_DEVICE_CMD_INFO_21_VALID_21_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_22_REG_OFFSET 0xd4
#define SPI_DEVICE_CMD_INFO_22_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_22_OPCODE_22_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_22_OPCODE_22_OFFSET 0
#define SPI_DEVICE_CMD_INFO_22_OPCODE_22_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_OPCODE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_OPCODE_22_OFFSET })
#define SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_OFFSET 8
#define SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_ADDR_MODE_22_OFFSET })
#define SPI_DEVICE_CMD_INFO_22_ADDR_SWAP_EN_22_BIT 10
#define SPI_DEVICE_CMD_INFO_22_MBYTE_EN_22_BIT 11
#define SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_OFFSET 12
#define SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_DUMMY_SIZE_22_OFFSET })
#define SPI_DEVICE_CMD_INFO_22_DUMMY_EN_22_BIT 15
#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_OFFSET 16
#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_PAYLOAD_EN_22_OFFSET })
#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_DIR_22_BIT 20
#define SPI_DEVICE_CMD_INFO_22_PAYLOAD_SWAP_EN_22_BIT 21
#define SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_OFFSET 22
#define SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_MASK, .index = SPI_DEVICE_CMD_INFO_22_READ_PIPELINE_MODE_22_OFFSET })
#define SPI_DEVICE_CMD_INFO_22_UPLOAD_22_BIT 24
#define SPI_DEVICE_CMD_INFO_22_BUSY_22_BIT 25
#define SPI_DEVICE_CMD_INFO_22_VALID_22_BIT 31
 
// Command Info register.
#define SPI_DEVICE_CMD_INFO_23_REG_OFFSET 0xd8
#define SPI_DEVICE_CMD_INFO_23_REG_RESVAL 0x7000u
#define SPI_DEVICE_CMD_INFO_23_OPCODE_23_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_23_OPCODE_23_OFFSET 0
#define SPI_DEVICE_CMD_INFO_23_OPCODE_23_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_OPCODE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_OPCODE_23_OFFSET })
#define SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_OFFSET 8
#define SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_ADDR_MODE_23_OFFSET })
#define SPI_DEVICE_CMD_INFO_23_ADDR_SWAP_EN_23_BIT 10
#define SPI_DEVICE_CMD_INFO_23_MBYTE_EN_23_BIT 11
#define SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_MASK 0x7u
#define SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_OFFSET 12
#define SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_DUMMY_SIZE_23_OFFSET })
#define SPI_DEVICE_CMD_INFO_23_DUMMY_EN_23_BIT 15
#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_MASK 0xfu
#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_OFFSET 16
#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_PAYLOAD_EN_23_OFFSET })
#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_DIR_23_BIT 20
#define SPI_DEVICE_CMD_INFO_23_PAYLOAD_SWAP_EN_23_BIT 21
#define SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_MASK 0x3u
#define SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_OFFSET 22
#define SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_MASK, .index = SPI_DEVICE_CMD_INFO_23_READ_PIPELINE_MODE_23_OFFSET })
#define SPI_DEVICE_CMD_INFO_23_UPLOAD_23_BIT 24
#define SPI_DEVICE_CMD_INFO_23_BUSY_23_BIT 25
#define SPI_DEVICE_CMD_INFO_23_VALID_23_BIT 31
 
// Opcode for EN4B.
#define SPI_DEVICE_CMD_INFO_EN4B_REG_OFFSET 0xdc
#define SPI_DEVICE_CMD_INFO_EN4B_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_INFO_EN4B_OPCODE_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_EN4B_OPCODE_OFFSET 0
#define SPI_DEVICE_CMD_INFO_EN4B_OPCODE_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_EN4B_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_EN4B_OPCODE_OFFSET })
#define SPI_DEVICE_CMD_INFO_EN4B_VALID_BIT 31
 
// Opcode for EX4B
#define SPI_DEVICE_CMD_INFO_EX4B_REG_OFFSET 0xe0
#define SPI_DEVICE_CMD_INFO_EX4B_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_INFO_EX4B_OPCODE_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_EX4B_OPCODE_OFFSET 0
#define SPI_DEVICE_CMD_INFO_EX4B_OPCODE_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_EX4B_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_EX4B_OPCODE_OFFSET })
#define SPI_DEVICE_CMD_INFO_EX4B_VALID_BIT 31
 
// Opcode for Write Enable (WREN)
#define SPI_DEVICE_CMD_INFO_WREN_REG_OFFSET 0xe4
#define SPI_DEVICE_CMD_INFO_WREN_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_INFO_WREN_OPCODE_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_WREN_OPCODE_OFFSET 0
#define SPI_DEVICE_CMD_INFO_WREN_OPCODE_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_WREN_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_WREN_OPCODE_OFFSET })
#define SPI_DEVICE_CMD_INFO_WREN_VALID_BIT 31
 
// Opcode for Write Disable (WRDI)
#define SPI_DEVICE_CMD_INFO_WRDI_REG_OFFSET 0xe8
#define SPI_DEVICE_CMD_INFO_WRDI_REG_RESVAL 0x0u
#define SPI_DEVICE_CMD_INFO_WRDI_OPCODE_MASK 0xffu
#define SPI_DEVICE_CMD_INFO_WRDI_OPCODE_OFFSET 0
#define SPI_DEVICE_CMD_INFO_WRDI_OPCODE_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_CMD_INFO_WRDI_OPCODE_MASK, .index = SPI_DEVICE_CMD_INFO_WRDI_OPCODE_OFFSET })
#define SPI_DEVICE_CMD_INFO_WRDI_VALID_BIT 31
 
// TPM HWIP Capability register.
#define SPI_DEVICE_TPM_CAP_REG_OFFSET 0x800
#define SPI_DEVICE_TPM_CAP_REG_RESVAL 0x660100u
#define SPI_DEVICE_TPM_CAP_REV_MASK 0xffu
#define SPI_DEVICE_TPM_CAP_REV_OFFSET 0
#define SPI_DEVICE_TPM_CAP_REV_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CAP_REV_MASK, .index = SPI_DEVICE_TPM_CAP_REV_OFFSET })
#define SPI_DEVICE_TPM_CAP_LOCALITY_BIT 8
#define SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_MASK 0x7u
#define SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_OFFSET 16
#define SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_MASK, .index = SPI_DEVICE_TPM_CAP_MAX_WR_SIZE_OFFSET })
#define SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_MASK 0x7u
#define SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_OFFSET 20
#define SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_MASK, .index = SPI_DEVICE_TPM_CAP_MAX_RD_SIZE_OFFSET })
 
// TPM Configuration register.
#define SPI_DEVICE_TPM_CFG_REG_OFFSET 0x804
#define SPI_DEVICE_TPM_CFG_REG_RESVAL 0x0u
#define SPI_DEVICE_TPM_CFG_EN_BIT 0
#define SPI_DEVICE_TPM_CFG_TPM_MODE_BIT 1
#define SPI_DEVICE_TPM_CFG_HW_REG_DIS_BIT 2
#define SPI_DEVICE_TPM_CFG_TPM_REG_CHK_DIS_BIT 3
#define SPI_DEVICE_TPM_CFG_INVALID_LOCALITY_BIT 4
 
// TPM submodule state register.
#define SPI_DEVICE_TPM_STATUS_REG_OFFSET 0x808
#define SPI_DEVICE_TPM_STATUS_REG_RESVAL 0x0u
#define SPI_DEVICE_TPM_STATUS_CMDADDR_NOTEMPTY_BIT 0
#define SPI_DEVICE_TPM_STATUS_WRFIFO_PENDING_BIT 1
#define SPI_DEVICE_TPM_STATUS_RDFIFO_ABORTED_BIT 2
 
// TPM_ACCESS_x register. (common parameters)
#define SPI_DEVICE_TPM_ACCESS_ACCESS_FIELD_WIDTH 8
#define SPI_DEVICE_TPM_ACCESS_MULTIREG_COUNT 2
 
// TPM_ACCESS_x register.
#define SPI_DEVICE_TPM_ACCESS_0_REG_OFFSET 0x80c
#define SPI_DEVICE_TPM_ACCESS_0_REG_RESVAL 0x0u
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_MASK 0xffu
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_OFFSET 0
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_0_OFFSET })
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_MASK 0xffu
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_OFFSET 8
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_1_OFFSET })
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_MASK 0xffu
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_OFFSET 16
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_2_OFFSET })
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_MASK 0xffu
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_OFFSET 24
#define SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_MASK, .index = SPI_DEVICE_TPM_ACCESS_0_ACCESS_3_OFFSET })
 
// TPM_ACCESS_x register.
#define SPI_DEVICE_TPM_ACCESS_1_REG_OFFSET 0x810
#define SPI_DEVICE_TPM_ACCESS_1_REG_RESVAL 0x0u
#define SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_MASK 0xffu
#define SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_OFFSET 0
#define SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_MASK, .index = SPI_DEVICE_TPM_ACCESS_1_ACCESS_4_OFFSET })
 
// TPM_STS_x register.
#define SPI_DEVICE_TPM_STS_REG_OFFSET 0x814
#define SPI_DEVICE_TPM_STS_REG_RESVAL 0x0u
 
// TPM_INTF_CAPABILITY
#define SPI_DEVICE_TPM_INTF_CAPABILITY_REG_OFFSET 0x818
#define SPI_DEVICE_TPM_INTF_CAPABILITY_REG_RESVAL 0x0u
 
// TPM_INT_ENABLE
#define SPI_DEVICE_TPM_INT_ENABLE_REG_OFFSET 0x81c
#define SPI_DEVICE_TPM_INT_ENABLE_REG_RESVAL 0x0u
 
// TPM_INT_VECTOR
#define SPI_DEVICE_TPM_INT_VECTOR_REG_OFFSET 0x820
#define SPI_DEVICE_TPM_INT_VECTOR_REG_RESVAL 0x0u
#define SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_MASK 0xffu
#define SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_OFFSET 0
#define SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_MASK, .index = SPI_DEVICE_TPM_INT_VECTOR_INT_VECTOR_OFFSET })
 
// TPM_INT_STATUS
#define SPI_DEVICE_TPM_INT_STATUS_REG_OFFSET 0x824
#define SPI_DEVICE_TPM_INT_STATUS_REG_RESVAL 0x0u
 
// TPM_DID/ TPM_VID register
#define SPI_DEVICE_TPM_DID_VID_REG_OFFSET 0x828
#define SPI_DEVICE_TPM_DID_VID_REG_RESVAL 0x0u
#define SPI_DEVICE_TPM_DID_VID_VID_MASK 0xffffu
#define SPI_DEVICE_TPM_DID_VID_VID_OFFSET 0
#define SPI_DEVICE_TPM_DID_VID_VID_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_DID_VID_VID_MASK, .index = SPI_DEVICE_TPM_DID_VID_VID_OFFSET })
#define SPI_DEVICE_TPM_DID_VID_DID_MASK 0xffffu
#define SPI_DEVICE_TPM_DID_VID_DID_OFFSET 16
#define SPI_DEVICE_TPM_DID_VID_DID_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_DID_VID_DID_MASK, .index = SPI_DEVICE_TPM_DID_VID_DID_OFFSET })
 
// TPM_RID
#define SPI_DEVICE_TPM_RID_REG_OFFSET 0x82c
#define SPI_DEVICE_TPM_RID_REG_RESVAL 0x0u
#define SPI_DEVICE_TPM_RID_RID_MASK 0xffu
#define SPI_DEVICE_TPM_RID_RID_OFFSET 0
#define SPI_DEVICE_TPM_RID_RID_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_RID_RID_MASK, .index = SPI_DEVICE_TPM_RID_RID_OFFSET })
 
// TPM Command and Address buffer
#define SPI_DEVICE_TPM_CMD_ADDR_REG_OFFSET 0x830
#define SPI_DEVICE_TPM_CMD_ADDR_REG_RESVAL 0x0u
#define SPI_DEVICE_TPM_CMD_ADDR_ADDR_MASK 0xffffffu
#define SPI_DEVICE_TPM_CMD_ADDR_ADDR_OFFSET 0
#define SPI_DEVICE_TPM_CMD_ADDR_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CMD_ADDR_ADDR_MASK, .index = SPI_DEVICE_TPM_CMD_ADDR_ADDR_OFFSET })
#define SPI_DEVICE_TPM_CMD_ADDR_CMD_MASK 0xffu
#define SPI_DEVICE_TPM_CMD_ADDR_CMD_OFFSET 24
#define SPI_DEVICE_TPM_CMD_ADDR_CMD_FIELD \
  ((bitfield_field32_t) { .mask = SPI_DEVICE_TPM_CMD_ADDR_CMD_MASK, .index = SPI_DEVICE_TPM_CMD_ADDR_CMD_OFFSET })
 
// TPM Read command return data FIFO.
#define SPI_DEVICE_TPM_READ_FIFO_REG_OFFSET 0x834
#define SPI_DEVICE_TPM_READ_FIFO_REG_RESVAL 0x0u
 
// Memory area: SPI internal egress buffer.
#define SPI_DEVICE_EGRESS_BUFFER_REG_OFFSET 0x1000
#define SPI_DEVICE_EGRESS_BUFFER_SIZE_WORDS 848
#define SPI_DEVICE_EGRESS_BUFFER_SIZE_BYTES 3392
// Memory area: SPI internal ingress buffer.
#define SPI_DEVICE_INGRESS_BUFFER_REG_OFFSET 0x1e00
#define SPI_DEVICE_INGRESS_BUFFER_SIZE_WORDS 112
#define SPI_DEVICE_INGRESS_BUFFER_SIZE_BYTES 448
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _SPI_DEVICE_REG_DEFS_
// End generated register defines for spi_device