Generated register defines for pinmux. More...
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Generated register defines for pinmux.
Definition in file pinmux_regs.h.
| #define PINMUX_ALERT_TEST_FATAL_FAULT_BIT 0 |
Definition at line 46 of file pinmux_regs.h.
| #define PINMUX_ALERT_TEST_REG_OFFSET 0x0 |
Definition at line 44 of file pinmux_regs.h.
| #define PINMUX_ALERT_TEST_REG_RESVAL 0x80000000u |
Definition at line 45 of file pinmux_regs.h.
| #define PINMUX_ALERT_TEST_REGWEN_BIT 31 |
Definition at line 47 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET }) |
Definition at line 3250 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xfu |
Definition at line 3248 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20 |
Definition at line 3249 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_INPUT_DISABLE_0_BIT 7 |
Definition at line 3243 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_INVERT_0_BIT 0 |
Definition at line 3234 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4 |
Definition at line 3240 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_OD_EN_0_BIT 6 |
Definition at line 3242 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_PULL_EN_0_BIT 2 |
Definition at line 3236 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3 |
Definition at line 3237 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_DOWN 0x0 |
Definition at line 3238 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_UP 0x1 |
Definition at line 3239 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_REG_OFFSET 0x63c |
Definition at line 3232 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_REG_RESVAL 0x0u |
Definition at line 3233 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5 |
Definition at line 3241 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET }) |
Definition at line 3246 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3u |
Definition at line 3244 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16 |
Definition at line 3245 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1 |
Definition at line 3235 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET }) |
Definition at line 3450 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xfu |
Definition at line 3448 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20 |
Definition at line 3449 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_INPUT_DISABLE_10_BIT 7 |
Definition at line 3443 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_INVERT_10_BIT 0 |
Definition at line 3436 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4 |
Definition at line 3440 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_OD_EN_10_BIT 6 |
Definition at line 3442 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_PULL_EN_10_BIT 2 |
Definition at line 3438 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3 |
Definition at line 3439 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_REG_OFFSET 0x664 |
Definition at line 3434 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_REG_RESVAL 0x0u |
Definition at line 3435 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5 |
Definition at line 3441 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET }) |
Definition at line 3446 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3u |
Definition at line 3444 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16 |
Definition at line 3445 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1 |
Definition at line 3437 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET }) |
Definition at line 3470 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xfu |
Definition at line 3468 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20 |
Definition at line 3469 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_INPUT_DISABLE_11_BIT 7 |
Definition at line 3463 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_INVERT_11_BIT 0 |
Definition at line 3456 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4 |
Definition at line 3460 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_OD_EN_11_BIT 6 |
Definition at line 3462 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_PULL_EN_11_BIT 2 |
Definition at line 3458 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3 |
Definition at line 3459 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_REG_OFFSET 0x668 |
Definition at line 3454 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_REG_RESVAL 0x0u |
Definition at line 3455 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5 |
Definition at line 3461 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET }) |
Definition at line 3466 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3u |
Definition at line 3464 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16 |
Definition at line 3465 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1 |
Definition at line 3457 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET }) |
Definition at line 3490 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK 0xfu |
Definition at line 3488 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET 20 |
Definition at line 3489 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_INPUT_DISABLE_12_BIT 7 |
Definition at line 3483 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_INVERT_12_BIT 0 |
Definition at line 3476 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_KEEPER_EN_12_BIT 4 |
Definition at line 3480 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_OD_EN_12_BIT 6 |
Definition at line 3482 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_PULL_EN_12_BIT 2 |
Definition at line 3478 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_PULL_SELECT_12_BIT 3 |
Definition at line 3479 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_REG_OFFSET 0x66c |
Definition at line 3474 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_REG_RESVAL 0x0u |
Definition at line 3475 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_SCHMITT_EN_12_BIT 5 |
Definition at line 3481 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET }) |
Definition at line 3486 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK 0x3u |
Definition at line 3484 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET 16 |
Definition at line 3485 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_BIT 1 |
Definition at line 3477 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET }) |
Definition at line 3510 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK 0xfu |
Definition at line 3508 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET 20 |
Definition at line 3509 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_INPUT_DISABLE_13_BIT 7 |
Definition at line 3503 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_INVERT_13_BIT 0 |
Definition at line 3496 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_KEEPER_EN_13_BIT 4 |
Definition at line 3500 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_OD_EN_13_BIT 6 |
Definition at line 3502 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_PULL_EN_13_BIT 2 |
Definition at line 3498 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_PULL_SELECT_13_BIT 3 |
Definition at line 3499 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_REG_OFFSET 0x670 |
Definition at line 3494 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_REG_RESVAL 0x0u |
Definition at line 3495 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_SCHMITT_EN_13_BIT 5 |
Definition at line 3501 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET }) |
Definition at line 3506 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK 0x3u |
Definition at line 3504 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET 16 |
Definition at line 3505 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_BIT 1 |
Definition at line 3497 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET }) |
Definition at line 3530 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK 0xfu |
Definition at line 3528 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET 20 |
Definition at line 3529 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_INPUT_DISABLE_14_BIT 7 |
Definition at line 3523 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_INVERT_14_BIT 0 |
Definition at line 3516 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_KEEPER_EN_14_BIT 4 |
Definition at line 3520 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_OD_EN_14_BIT 6 |
Definition at line 3522 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_PULL_EN_14_BIT 2 |
Definition at line 3518 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_PULL_SELECT_14_BIT 3 |
Definition at line 3519 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_REG_OFFSET 0x674 |
Definition at line 3514 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_REG_RESVAL 0x0u |
Definition at line 3515 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_SCHMITT_EN_14_BIT 5 |
Definition at line 3521 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET }) |
Definition at line 3526 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK 0x3u |
Definition at line 3524 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET 16 |
Definition at line 3525 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_BIT 1 |
Definition at line 3517 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET }) |
Definition at line 3550 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK 0xfu |
Definition at line 3548 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET 20 |
Definition at line 3549 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_INPUT_DISABLE_15_BIT 7 |
Definition at line 3543 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_INVERT_15_BIT 0 |
Definition at line 3536 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_KEEPER_EN_15_BIT 4 |
Definition at line 3540 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_OD_EN_15_BIT 6 |
Definition at line 3542 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_PULL_EN_15_BIT 2 |
Definition at line 3538 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_PULL_SELECT_15_BIT 3 |
Definition at line 3539 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_REG_OFFSET 0x678 |
Definition at line 3534 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_REG_RESVAL 0x0u |
Definition at line 3535 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_SCHMITT_EN_15_BIT 5 |
Definition at line 3541 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET }) |
Definition at line 3546 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK 0x3u |
Definition at line 3544 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET 16 |
Definition at line 3545 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_BIT 1 |
Definition at line 3537 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET }) |
Definition at line 3270 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xfu |
Definition at line 3268 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20 |
Definition at line 3269 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT 7 |
Definition at line 3263 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_INVERT_1_BIT 0 |
Definition at line 3256 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4 |
Definition at line 3260 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_OD_EN_1_BIT 6 |
Definition at line 3262 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_PULL_EN_1_BIT 2 |
Definition at line 3258 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3 |
Definition at line 3259 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_REG_OFFSET 0x640 |
Definition at line 3254 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_REG_RESVAL 0x0u |
Definition at line 3255 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5 |
Definition at line 3261 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET }) |
Definition at line 3266 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3u |
Definition at line 3264 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16 |
Definition at line 3265 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1 |
Definition at line 3257 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET }) |
Definition at line 3290 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xfu |
Definition at line 3288 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20 |
Definition at line 3289 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_INPUT_DISABLE_2_BIT 7 |
Definition at line 3283 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_INVERT_2_BIT 0 |
Definition at line 3276 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4 |
Definition at line 3280 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_OD_EN_2_BIT 6 |
Definition at line 3282 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_PULL_EN_2_BIT 2 |
Definition at line 3278 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3 |
Definition at line 3279 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_REG_OFFSET 0x644 |
Definition at line 3274 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_REG_RESVAL 0x0u |
Definition at line 3275 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5 |
Definition at line 3281 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET }) |
Definition at line 3286 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3u |
Definition at line 3284 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16 |
Definition at line 3285 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1 |
Definition at line 3277 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET }) |
Definition at line 3310 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xfu |
Definition at line 3308 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20 |
Definition at line 3309 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT 7 |
Definition at line 3303 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_INVERT_3_BIT 0 |
Definition at line 3296 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4 |
Definition at line 3300 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_OD_EN_3_BIT 6 |
Definition at line 3302 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_BIT 2 |
Definition at line 3298 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3 |
Definition at line 3299 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_REG_OFFSET 0x648 |
Definition at line 3294 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_REG_RESVAL 0x0u |
Definition at line 3295 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5 |
Definition at line 3301 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET }) |
Definition at line 3306 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3u |
Definition at line 3304 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16 |
Definition at line 3305 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1 |
Definition at line 3297 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET }) |
Definition at line 3330 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xfu |
Definition at line 3328 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20 |
Definition at line 3329 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_INPUT_DISABLE_4_BIT 7 |
Definition at line 3323 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_INVERT_4_BIT 0 |
Definition at line 3316 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4 |
Definition at line 3320 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_OD_EN_4_BIT 6 |
Definition at line 3322 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_PULL_EN_4_BIT 2 |
Definition at line 3318 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3 |
Definition at line 3319 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_REG_OFFSET 0x64c |
Definition at line 3314 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_REG_RESVAL 0x0u |
Definition at line 3315 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5 |
Definition at line 3321 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET }) |
Definition at line 3326 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3u |
Definition at line 3324 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16 |
Definition at line 3325 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1 |
Definition at line 3317 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET }) |
Definition at line 3350 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xfu |
Definition at line 3348 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20 |
Definition at line 3349 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_INPUT_DISABLE_5_BIT 7 |
Definition at line 3343 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_INVERT_5_BIT 0 |
Definition at line 3336 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4 |
Definition at line 3340 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_OD_EN_5_BIT 6 |
Definition at line 3342 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_PULL_EN_5_BIT 2 |
Definition at line 3338 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3 |
Definition at line 3339 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_REG_OFFSET 0x650 |
Definition at line 3334 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_REG_RESVAL 0x0u |
Definition at line 3335 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5 |
Definition at line 3341 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET }) |
Definition at line 3346 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3u |
Definition at line 3344 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16 |
Definition at line 3345 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1 |
Definition at line 3337 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET }) |
Definition at line 3370 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xfu |
Definition at line 3368 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20 |
Definition at line 3369 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_INPUT_DISABLE_6_BIT 7 |
Definition at line 3363 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_INVERT_6_BIT 0 |
Definition at line 3356 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4 |
Definition at line 3360 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_OD_EN_6_BIT 6 |
Definition at line 3362 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_PULL_EN_6_BIT 2 |
Definition at line 3358 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3 |
Definition at line 3359 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_REG_OFFSET 0x654 |
Definition at line 3354 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_REG_RESVAL 0x0u |
Definition at line 3355 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5 |
Definition at line 3361 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET }) |
Definition at line 3366 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3u |
Definition at line 3364 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16 |
Definition at line 3365 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1 |
Definition at line 3357 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET }) |
Definition at line 3390 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xfu |
Definition at line 3388 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20 |
Definition at line 3389 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_INPUT_DISABLE_7_BIT 7 |
Definition at line 3383 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_INVERT_7_BIT 0 |
Definition at line 3376 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4 |
Definition at line 3380 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_OD_EN_7_BIT 6 |
Definition at line 3382 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_PULL_EN_7_BIT 2 |
Definition at line 3378 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3 |
Definition at line 3379 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_REG_OFFSET 0x658 |
Definition at line 3374 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_REG_RESVAL 0x0u |
Definition at line 3375 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5 |
Definition at line 3381 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET }) |
Definition at line 3386 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3u |
Definition at line 3384 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16 |
Definition at line 3385 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1 |
Definition at line 3377 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET }) |
Definition at line 3410 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xfu |
Definition at line 3408 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20 |
Definition at line 3409 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_INPUT_DISABLE_8_BIT 7 |
Definition at line 3403 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_INVERT_8_BIT 0 |
Definition at line 3396 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4 |
Definition at line 3400 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_OD_EN_8_BIT 6 |
Definition at line 3402 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_PULL_EN_8_BIT 2 |
Definition at line 3398 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3 |
Definition at line 3399 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_REG_OFFSET 0x65c |
Definition at line 3394 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_REG_RESVAL 0x0u |
Definition at line 3395 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5 |
Definition at line 3401 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET }) |
Definition at line 3406 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3u |
Definition at line 3404 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16 |
Definition at line 3405 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1 |
Definition at line 3397 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET }) |
Definition at line 3430 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xfu |
Definition at line 3428 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20 |
Definition at line 3429 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_INPUT_DISABLE_9_BIT 7 |
Definition at line 3423 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_INVERT_9_BIT 0 |
Definition at line 3416 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4 |
Definition at line 3420 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_OD_EN_9_BIT 6 |
Definition at line 3422 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_PULL_EN_9_BIT 2 |
Definition at line 3418 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3 |
Definition at line 3419 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_REG_OFFSET 0x660 |
Definition at line 3414 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_REG_RESVAL 0x0u |
Definition at line 3415 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5 |
Definition at line 3421 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET }) |
Definition at line 3426 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3u |
Definition at line 3424 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16 |
Definition at line 3425 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1 |
Definition at line 3417 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4 |
Definition at line 3228 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_INPUT_DISABLE_FIELD_WIDTH 1 |
Definition at line 3226 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_INVERT_FIELD_WIDTH 1 |
Definition at line 3219 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1 |
Definition at line 3223 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_MULTIREG_COUNT 16 |
Definition at line 3229 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1 |
Definition at line 3225 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1 |
Definition at line 3221 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1 |
Definition at line 3222 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0 |
Definition at line 3141 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0x5fc |
Definition at line 3139 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1u |
Definition at line 3140 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0 |
Definition at line 3191 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0x624 |
Definition at line 3189 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1u |
Definition at line 3190 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0 |
Definition at line 3196 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0x628 |
Definition at line 3194 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1u |
Definition at line 3195 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_12_EN_12_BIT 0 |
Definition at line 3201 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_OFFSET 0x62c |
Definition at line 3199 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_RESVAL 0x1u |
Definition at line 3200 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_13_EN_13_BIT 0 |
Definition at line 3206 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_OFFSET 0x630 |
Definition at line 3204 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_RESVAL 0x1u |
Definition at line 3205 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_14_EN_14_BIT 0 |
Definition at line 3211 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_OFFSET 0x634 |
Definition at line 3209 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_RESVAL 0x1u |
Definition at line 3210 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_15_EN_15_BIT 0 |
Definition at line 3216 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_OFFSET 0x638 |
Definition at line 3214 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_RESVAL 0x1u |
Definition at line 3215 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0 |
Definition at line 3146 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0x600 |
Definition at line 3144 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1u |
Definition at line 3145 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0 |
Definition at line 3151 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0x604 |
Definition at line 3149 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1u |
Definition at line 3150 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0 |
Definition at line 3156 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0x608 |
Definition at line 3154 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1u |
Definition at line 3155 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0 |
Definition at line 3161 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0x60c |
Definition at line 3159 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1u |
Definition at line 3160 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0 |
Definition at line 3166 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0x610 |
Definition at line 3164 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1u |
Definition at line 3165 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0 |
Definition at line 3171 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0x614 |
Definition at line 3169 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1u |
Definition at line 3170 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0 |
Definition at line 3176 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0x618 |
Definition at line 3174 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1u |
Definition at line 3175 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0 |
Definition at line 3181 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0x61c |
Definition at line 3179 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1u |
Definition at line 3180 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0 |
Definition at line 3186 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0x620 |
Definition at line 3184 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1u |
Definition at line 3185 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1 |
Definition at line 3135 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 16 |
Definition at line 3136 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1 |
Definition at line 3224 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2 |
Definition at line 3227 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1 |
Definition at line 3220 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_0_EN_0_BIT 0 |
Definition at line 4594 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_0_REG_OFFSET 0x8fc |
Definition at line 4592 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0u |
Definition at line 4593 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_10_EN_10_BIT 0 |
Definition at line 4644 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_10_REG_OFFSET 0x924 |
Definition at line 4642 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0u |
Definition at line 4643 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_11_EN_11_BIT 0 |
Definition at line 4649 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_11_REG_OFFSET 0x928 |
Definition at line 4647 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0u |
Definition at line 4648 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_12_EN_12_BIT 0 |
Definition at line 4654 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_12_REG_OFFSET 0x92c |
Definition at line 4652 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_12_REG_RESVAL 0x0u |
Definition at line 4653 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_13_EN_13_BIT 0 |
Definition at line 4659 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_13_REG_OFFSET 0x930 |
Definition at line 4657 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_13_REG_RESVAL 0x0u |
Definition at line 4658 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_14_EN_14_BIT 0 |
Definition at line 4664 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_14_REG_OFFSET 0x934 |
Definition at line 4662 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_14_REG_RESVAL 0x0u |
Definition at line 4663 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_15_EN_15_BIT 0 |
Definition at line 4669 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_15_REG_OFFSET 0x938 |
Definition at line 4667 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_15_REG_RESVAL 0x0u |
Definition at line 4668 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_1_EN_1_BIT 0 |
Definition at line 4599 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_1_REG_OFFSET 0x900 |
Definition at line 4597 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0u |
Definition at line 4598 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_2_EN_2_BIT 0 |
Definition at line 4604 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_2_REG_OFFSET 0x904 |
Definition at line 4602 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0u |
Definition at line 4603 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_3_EN_3_BIT 0 |
Definition at line 4609 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_3_REG_OFFSET 0x908 |
Definition at line 4607 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0u |
Definition at line 4608 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_4_EN_4_BIT 0 |
Definition at line 4614 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_4_REG_OFFSET 0x90c |
Definition at line 4612 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0u |
Definition at line 4613 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_5_EN_5_BIT 0 |
Definition at line 4619 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_5_REG_OFFSET 0x910 |
Definition at line 4617 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0u |
Definition at line 4618 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_6_EN_6_BIT 0 |
Definition at line 4624 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_6_REG_OFFSET 0x914 |
Definition at line 4622 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0u |
Definition at line 4623 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_7_EN_7_BIT 0 |
Definition at line 4629 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_7_REG_OFFSET 0x918 |
Definition at line 4627 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0u |
Definition at line 4628 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_8_EN_8_BIT 0 |
Definition at line 4634 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_8_REG_OFFSET 0x91c |
Definition at line 4632 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0u |
Definition at line 4633 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_9_EN_9_BIT 0 |
Definition at line 4639 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_9_REG_OFFSET 0x920 |
Definition at line 4637 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0u |
Definition at line 4638 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1 |
Definition at line 4588 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_EN_MULTIREG_COUNT 16 |
Definition at line 4589 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET }) |
Definition at line 4681 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3u |
Definition at line 4679 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0 |
Definition at line 4680 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2 |
Definition at line 4685 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3 |
Definition at line 4686 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1 |
Definition at line 4684 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0 |
Definition at line 4683 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x93c |
Definition at line 4677 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2u |
Definition at line 4678 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET }) |
Definition at line 4765 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3u |
Definition at line 4763 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0 |
Definition at line 4764 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x964 |
Definition at line 4761 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2u |
Definition at line 4762 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET }) |
Definition at line 4773 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3u |
Definition at line 4771 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0 |
Definition at line 4772 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x968 |
Definition at line 4769 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2u |
Definition at line 4770 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET }) |
Definition at line 4781 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK 0x3u |
Definition at line 4779 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET 0 |
Definition at line 4780 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_12_REG_OFFSET 0x96c |
Definition at line 4777 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_12_REG_RESVAL 0x2u |
Definition at line 4778 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET }) |
Definition at line 4789 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK 0x3u |
Definition at line 4787 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET 0 |
Definition at line 4788 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_13_REG_OFFSET 0x970 |
Definition at line 4785 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_13_REG_RESVAL 0x2u |
Definition at line 4786 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET }) |
Definition at line 4797 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK 0x3u |
Definition at line 4795 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET 0 |
Definition at line 4796 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_14_REG_OFFSET 0x974 |
Definition at line 4793 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_14_REG_RESVAL 0x2u |
Definition at line 4794 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET }) |
Definition at line 4805 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK 0x3u |
Definition at line 4803 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET 0 |
Definition at line 4804 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_15_REG_OFFSET 0x978 |
Definition at line 4801 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_15_REG_RESVAL 0x2u |
Definition at line 4802 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET }) |
Definition at line 4693 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3u |
Definition at line 4691 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0 |
Definition at line 4692 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x940 |
Definition at line 4689 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2u |
Definition at line 4690 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET }) |
Definition at line 4701 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3u |
Definition at line 4699 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0 |
Definition at line 4700 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x944 |
Definition at line 4697 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2u |
Definition at line 4698 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET }) |
Definition at line 4709 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3u |
Definition at line 4707 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0 |
Definition at line 4708 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x948 |
Definition at line 4705 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2u |
Definition at line 4706 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET }) |
Definition at line 4717 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3u |
Definition at line 4715 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0 |
Definition at line 4716 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x94c |
Definition at line 4713 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2u |
Definition at line 4714 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET }) |
Definition at line 4725 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3u |
Definition at line 4723 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0 |
Definition at line 4724 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x950 |
Definition at line 4721 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2u |
Definition at line 4722 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET }) |
Definition at line 4733 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3u |
Definition at line 4731 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0 |
Definition at line 4732 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x954 |
Definition at line 4729 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2u |
Definition at line 4730 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET }) |
Definition at line 4741 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3u |
Definition at line 4739 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0 |
Definition at line 4740 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x958 |
Definition at line 4737 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2u |
Definition at line 4738 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET }) |
Definition at line 4749 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3u |
Definition at line 4747 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0 |
Definition at line 4748 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x95c |
Definition at line 4745 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2u |
Definition at line 4746 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET }) |
Definition at line 4757 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3u |
Definition at line 4755 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0 |
Definition at line 4756 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x960 |
Definition at line 4753 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2u |
Definition at line 4754 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_MULTIREG_COUNT 16 |
Definition at line 4674 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2 |
Definition at line 4673 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0 |
Definition at line 4509 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x8bc |
Definition at line 4507 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1u |
Definition at line 4508 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0 |
Definition at line 4559 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x8e4 |
Definition at line 4557 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1u |
Definition at line 4558 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0 |
Definition at line 4564 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x8e8 |
Definition at line 4562 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1u |
Definition at line 4563 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_12_EN_12_BIT 0 |
Definition at line 4569 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_OFFSET 0x8ec |
Definition at line 4567 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_RESVAL 0x1u |
Definition at line 4568 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_13_EN_13_BIT 0 |
Definition at line 4574 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_OFFSET 0x8f0 |
Definition at line 4572 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_RESVAL 0x1u |
Definition at line 4573 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_14_EN_14_BIT 0 |
Definition at line 4579 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_OFFSET 0x8f4 |
Definition at line 4577 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_RESVAL 0x1u |
Definition at line 4578 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_15_EN_15_BIT 0 |
Definition at line 4584 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_OFFSET 0x8f8 |
Definition at line 4582 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_RESVAL 0x1u |
Definition at line 4583 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0 |
Definition at line 4514 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x8c0 |
Definition at line 4512 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1u |
Definition at line 4513 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0 |
Definition at line 4519 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x8c4 |
Definition at line 4517 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1u |
Definition at line 4518 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0 |
Definition at line 4524 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x8c8 |
Definition at line 4522 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1u |
Definition at line 4523 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0 |
Definition at line 4529 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x8cc |
Definition at line 4527 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1u |
Definition at line 4528 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0 |
Definition at line 4534 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x8d0 |
Definition at line 4532 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1u |
Definition at line 4533 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0 |
Definition at line 4539 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x8d4 |
Definition at line 4537 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1u |
Definition at line 4538 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0 |
Definition at line 4544 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x8d8 |
Definition at line 4542 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1u |
Definition at line 4543 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0 |
Definition at line 4549 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x8dc |
Definition at line 4547 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1u |
Definition at line 4548 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0 |
Definition at line 4554 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x8e0 |
Definition at line 4552 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1u |
Definition at line 4553 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1 |
Definition at line 4503 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 16 |
Definition at line 4504 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_0_BIT 0 |
Definition at line 4484 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_10_BIT 10 |
Definition at line 4494 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_11_BIT 11 |
Definition at line 4495 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_12_BIT 12 |
Definition at line 4496 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_13_BIT 13 |
Definition at line 4497 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_14_BIT 14 |
Definition at line 4498 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_15_BIT 15 |
Definition at line 4499 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_1_BIT 1 |
Definition at line 4485 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_2_BIT 2 |
Definition at line 4486 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_3_BIT 3 |
Definition at line 4487 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_4_BIT 4 |
Definition at line 4488 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_5_BIT 5 |
Definition at line 4489 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_6_BIT 6 |
Definition at line 4490 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_7_BIT 7 |
Definition at line 4491 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_8_BIT 8 |
Definition at line 4492 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_9_BIT 9 |
Definition at line 4493 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1 |
Definition at line 4478 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 1 |
Definition at line 4479 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_REG_OFFSET 0x8b8 |
Definition at line 4482 of file pinmux_regs.h.
| #define PINMUX_DIO_PAD_SLEEP_STATUS_REG_RESVAL 0x0u |
Definition at line 4483 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_0_OUT_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_0_OUT_0_MASK, .index = PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET }) |
Definition at line 1569 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_0_OUT_0_MASK 0x7fu |
Definition at line 1567 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET 0 |
Definition at line 1568 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_0_REG_OFFSET 0x3c8 |
Definition at line 1565 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_0_REG_RESVAL 0x2u |
Definition at line 1566 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_10_OUT_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_10_OUT_10_MASK, .index = PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET }) |
Definition at line 1649 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_10_OUT_10_MASK 0x7fu |
Definition at line 1647 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET 0 |
Definition at line 1648 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_10_REG_OFFSET 0x3f0 |
Definition at line 1645 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_10_REG_RESVAL 0x2u |
Definition at line 1646 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_11_OUT_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_11_OUT_11_MASK, .index = PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET }) |
Definition at line 1657 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_11_OUT_11_MASK 0x7fu |
Definition at line 1655 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET 0 |
Definition at line 1656 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_11_REG_OFFSET 0x3f4 |
Definition at line 1653 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_11_REG_RESVAL 0x2u |
Definition at line 1654 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_12_OUT_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_12_OUT_12_MASK, .index = PINMUX_MIO_OUTSEL_12_OUT_12_OFFSET }) |
Definition at line 1665 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_12_OUT_12_MASK 0x7fu |
Definition at line 1663 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_12_OUT_12_OFFSET 0 |
Definition at line 1664 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_12_REG_OFFSET 0x3f8 |
Definition at line 1661 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_12_REG_RESVAL 0x2u |
Definition at line 1662 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_13_OUT_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_13_OUT_13_MASK, .index = PINMUX_MIO_OUTSEL_13_OUT_13_OFFSET }) |
Definition at line 1673 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_13_OUT_13_MASK 0x7fu |
Definition at line 1671 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_13_OUT_13_OFFSET 0 |
Definition at line 1672 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_13_REG_OFFSET 0x3fc |
Definition at line 1669 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_13_REG_RESVAL 0x2u |
Definition at line 1670 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_14_OUT_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_14_OUT_14_MASK, .index = PINMUX_MIO_OUTSEL_14_OUT_14_OFFSET }) |
Definition at line 1681 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_14_OUT_14_MASK 0x7fu |
Definition at line 1679 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_14_OUT_14_OFFSET 0 |
Definition at line 1680 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_14_REG_OFFSET 0x400 |
Definition at line 1677 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_14_REG_RESVAL 0x2u |
Definition at line 1678 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_15_OUT_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_15_OUT_15_MASK, .index = PINMUX_MIO_OUTSEL_15_OUT_15_OFFSET }) |
Definition at line 1689 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_15_OUT_15_MASK 0x7fu |
Definition at line 1687 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_15_OUT_15_OFFSET 0 |
Definition at line 1688 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_15_REG_OFFSET 0x404 |
Definition at line 1685 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_15_REG_RESVAL 0x2u |
Definition at line 1686 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_16_OUT_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_16_OUT_16_MASK, .index = PINMUX_MIO_OUTSEL_16_OUT_16_OFFSET }) |
Definition at line 1697 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_16_OUT_16_MASK 0x7fu |
Definition at line 1695 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_16_OUT_16_OFFSET 0 |
Definition at line 1696 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_16_REG_OFFSET 0x408 |
Definition at line 1693 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_16_REG_RESVAL 0x2u |
Definition at line 1694 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_17_OUT_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_17_OUT_17_MASK, .index = PINMUX_MIO_OUTSEL_17_OUT_17_OFFSET }) |
Definition at line 1705 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_17_OUT_17_MASK 0x7fu |
Definition at line 1703 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_17_OUT_17_OFFSET 0 |
Definition at line 1704 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_17_REG_OFFSET 0x40c |
Definition at line 1701 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_17_REG_RESVAL 0x2u |
Definition at line 1702 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_18_OUT_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_18_OUT_18_MASK, .index = PINMUX_MIO_OUTSEL_18_OUT_18_OFFSET }) |
Definition at line 1713 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_18_OUT_18_MASK 0x7fu |
Definition at line 1711 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_18_OUT_18_OFFSET 0 |
Definition at line 1712 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_18_REG_OFFSET 0x410 |
Definition at line 1709 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_18_REG_RESVAL 0x2u |
Definition at line 1710 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_19_OUT_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_19_OUT_19_MASK, .index = PINMUX_MIO_OUTSEL_19_OUT_19_OFFSET }) |
Definition at line 1721 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_19_OUT_19_MASK 0x7fu |
Definition at line 1719 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_19_OUT_19_OFFSET 0 |
Definition at line 1720 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_19_REG_OFFSET 0x414 |
Definition at line 1717 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_19_REG_RESVAL 0x2u |
Definition at line 1718 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_1_OUT_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_1_OUT_1_MASK, .index = PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET }) |
Definition at line 1577 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_1_OUT_1_MASK 0x7fu |
Definition at line 1575 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET 0 |
Definition at line 1576 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_1_REG_OFFSET 0x3cc |
Definition at line 1573 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_1_REG_RESVAL 0x2u |
Definition at line 1574 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_20_OUT_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_20_OUT_20_MASK, .index = PINMUX_MIO_OUTSEL_20_OUT_20_OFFSET }) |
Definition at line 1729 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_20_OUT_20_MASK 0x7fu |
Definition at line 1727 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_20_OUT_20_OFFSET 0 |
Definition at line 1728 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_20_REG_OFFSET 0x418 |
Definition at line 1725 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_20_REG_RESVAL 0x2u |
Definition at line 1726 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_21_OUT_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_21_OUT_21_MASK, .index = PINMUX_MIO_OUTSEL_21_OUT_21_OFFSET }) |
Definition at line 1737 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_21_OUT_21_MASK 0x7fu |
Definition at line 1735 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_21_OUT_21_OFFSET 0 |
Definition at line 1736 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_21_REG_OFFSET 0x41c |
Definition at line 1733 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_21_REG_RESVAL 0x2u |
Definition at line 1734 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_22_OUT_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_22_OUT_22_MASK, .index = PINMUX_MIO_OUTSEL_22_OUT_22_OFFSET }) |
Definition at line 1745 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_22_OUT_22_MASK 0x7fu |
Definition at line 1743 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_22_OUT_22_OFFSET 0 |
Definition at line 1744 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_22_REG_OFFSET 0x420 |
Definition at line 1741 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_22_REG_RESVAL 0x2u |
Definition at line 1742 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_23_OUT_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_23_OUT_23_MASK, .index = PINMUX_MIO_OUTSEL_23_OUT_23_OFFSET }) |
Definition at line 1753 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_23_OUT_23_MASK 0x7fu |
Definition at line 1751 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_23_OUT_23_OFFSET 0 |
Definition at line 1752 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_23_REG_OFFSET 0x424 |
Definition at line 1749 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_23_REG_RESVAL 0x2u |
Definition at line 1750 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_24_OUT_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_24_OUT_24_MASK, .index = PINMUX_MIO_OUTSEL_24_OUT_24_OFFSET }) |
Definition at line 1761 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_24_OUT_24_MASK 0x7fu |
Definition at line 1759 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_24_OUT_24_OFFSET 0 |
Definition at line 1760 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_24_REG_OFFSET 0x428 |
Definition at line 1757 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_24_REG_RESVAL 0x2u |
Definition at line 1758 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_25_OUT_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_25_OUT_25_MASK, .index = PINMUX_MIO_OUTSEL_25_OUT_25_OFFSET }) |
Definition at line 1769 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_25_OUT_25_MASK 0x7fu |
Definition at line 1767 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_25_OUT_25_OFFSET 0 |
Definition at line 1768 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_25_REG_OFFSET 0x42c |
Definition at line 1765 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_25_REG_RESVAL 0x2u |
Definition at line 1766 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_26_OUT_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_26_OUT_26_MASK, .index = PINMUX_MIO_OUTSEL_26_OUT_26_OFFSET }) |
Definition at line 1777 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_26_OUT_26_MASK 0x7fu |
Definition at line 1775 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_26_OUT_26_OFFSET 0 |
Definition at line 1776 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_26_REG_OFFSET 0x430 |
Definition at line 1773 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_26_REG_RESVAL 0x2u |
Definition at line 1774 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_27_OUT_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_27_OUT_27_MASK, .index = PINMUX_MIO_OUTSEL_27_OUT_27_OFFSET }) |
Definition at line 1785 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_27_OUT_27_MASK 0x7fu |
Definition at line 1783 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_27_OUT_27_OFFSET 0 |
Definition at line 1784 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_27_REG_OFFSET 0x434 |
Definition at line 1781 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_27_REG_RESVAL 0x2u |
Definition at line 1782 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_28_OUT_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_28_OUT_28_MASK, .index = PINMUX_MIO_OUTSEL_28_OUT_28_OFFSET }) |
Definition at line 1793 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_28_OUT_28_MASK 0x7fu |
Definition at line 1791 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_28_OUT_28_OFFSET 0 |
Definition at line 1792 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_28_REG_OFFSET 0x438 |
Definition at line 1789 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_28_REG_RESVAL 0x2u |
Definition at line 1790 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_29_OUT_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_29_OUT_29_MASK, .index = PINMUX_MIO_OUTSEL_29_OUT_29_OFFSET }) |
Definition at line 1801 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_29_OUT_29_MASK 0x7fu |
Definition at line 1799 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_29_OUT_29_OFFSET 0 |
Definition at line 1800 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_29_REG_OFFSET 0x43c |
Definition at line 1797 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_29_REG_RESVAL 0x2u |
Definition at line 1798 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_2_OUT_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_2_OUT_2_MASK, .index = PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET }) |
Definition at line 1585 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_2_OUT_2_MASK 0x7fu |
Definition at line 1583 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET 0 |
Definition at line 1584 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_2_REG_OFFSET 0x3d0 |
Definition at line 1581 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_2_REG_RESVAL 0x2u |
Definition at line 1582 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_30_OUT_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_30_OUT_30_MASK, .index = PINMUX_MIO_OUTSEL_30_OUT_30_OFFSET }) |
Definition at line 1809 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_30_OUT_30_MASK 0x7fu |
Definition at line 1807 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_30_OUT_30_OFFSET 0 |
Definition at line 1808 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_30_REG_OFFSET 0x440 |
Definition at line 1805 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_30_REG_RESVAL 0x2u |
Definition at line 1806 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_31_OUT_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_31_OUT_31_MASK, .index = PINMUX_MIO_OUTSEL_31_OUT_31_OFFSET }) |
Definition at line 1817 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_31_OUT_31_MASK 0x7fu |
Definition at line 1815 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_31_OUT_31_OFFSET 0 |
Definition at line 1816 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_31_REG_OFFSET 0x444 |
Definition at line 1813 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_31_REG_RESVAL 0x2u |
Definition at line 1814 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_32_OUT_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_32_OUT_32_MASK, .index = PINMUX_MIO_OUTSEL_32_OUT_32_OFFSET }) |
Definition at line 1825 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_32_OUT_32_MASK 0x7fu |
Definition at line 1823 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_32_OUT_32_OFFSET 0 |
Definition at line 1824 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_32_REG_OFFSET 0x448 |
Definition at line 1821 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_32_REG_RESVAL 0x2u |
Definition at line 1822 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_33_OUT_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_33_OUT_33_MASK, .index = PINMUX_MIO_OUTSEL_33_OUT_33_OFFSET }) |
Definition at line 1833 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_33_OUT_33_MASK 0x7fu |
Definition at line 1831 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_33_OUT_33_OFFSET 0 |
Definition at line 1832 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_33_REG_OFFSET 0x44c |
Definition at line 1829 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_33_REG_RESVAL 0x2u |
Definition at line 1830 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_34_OUT_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_34_OUT_34_MASK, .index = PINMUX_MIO_OUTSEL_34_OUT_34_OFFSET }) |
Definition at line 1841 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_34_OUT_34_MASK 0x7fu |
Definition at line 1839 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_34_OUT_34_OFFSET 0 |
Definition at line 1840 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_34_REG_OFFSET 0x450 |
Definition at line 1837 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_34_REG_RESVAL 0x2u |
Definition at line 1838 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_35_OUT_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_35_OUT_35_MASK, .index = PINMUX_MIO_OUTSEL_35_OUT_35_OFFSET }) |
Definition at line 1849 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_35_OUT_35_MASK 0x7fu |
Definition at line 1847 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_35_OUT_35_OFFSET 0 |
Definition at line 1848 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_35_REG_OFFSET 0x454 |
Definition at line 1845 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_35_REG_RESVAL 0x2u |
Definition at line 1846 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_36_OUT_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_36_OUT_36_MASK, .index = PINMUX_MIO_OUTSEL_36_OUT_36_OFFSET }) |
Definition at line 1857 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_36_OUT_36_MASK 0x7fu |
Definition at line 1855 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_36_OUT_36_OFFSET 0 |
Definition at line 1856 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_36_REG_OFFSET 0x458 |
Definition at line 1853 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_36_REG_RESVAL 0x2u |
Definition at line 1854 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_37_OUT_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_37_OUT_37_MASK, .index = PINMUX_MIO_OUTSEL_37_OUT_37_OFFSET }) |
Definition at line 1865 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_37_OUT_37_MASK 0x7fu |
Definition at line 1863 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_37_OUT_37_OFFSET 0 |
Definition at line 1864 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_37_REG_OFFSET 0x45c |
Definition at line 1861 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_37_REG_RESVAL 0x2u |
Definition at line 1862 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_38_OUT_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_38_OUT_38_MASK, .index = PINMUX_MIO_OUTSEL_38_OUT_38_OFFSET }) |
Definition at line 1873 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_38_OUT_38_MASK 0x7fu |
Definition at line 1871 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_38_OUT_38_OFFSET 0 |
Definition at line 1872 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_38_REG_OFFSET 0x460 |
Definition at line 1869 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_38_REG_RESVAL 0x2u |
Definition at line 1870 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_39_OUT_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_39_OUT_39_MASK, .index = PINMUX_MIO_OUTSEL_39_OUT_39_OFFSET }) |
Definition at line 1881 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_39_OUT_39_MASK 0x7fu |
Definition at line 1879 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_39_OUT_39_OFFSET 0 |
Definition at line 1880 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_39_REG_OFFSET 0x464 |
Definition at line 1877 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_39_REG_RESVAL 0x2u |
Definition at line 1878 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_3_OUT_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_3_OUT_3_MASK, .index = PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET }) |
Definition at line 1593 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_3_OUT_3_MASK 0x7fu |
Definition at line 1591 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET 0 |
Definition at line 1592 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_3_REG_OFFSET 0x3d4 |
Definition at line 1589 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_3_REG_RESVAL 0x2u |
Definition at line 1590 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_40_OUT_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_40_OUT_40_MASK, .index = PINMUX_MIO_OUTSEL_40_OUT_40_OFFSET }) |
Definition at line 1889 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_40_OUT_40_MASK 0x7fu |
Definition at line 1887 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_40_OUT_40_OFFSET 0 |
Definition at line 1888 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_40_REG_OFFSET 0x468 |
Definition at line 1885 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_40_REG_RESVAL 0x2u |
Definition at line 1886 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_41_OUT_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_41_OUT_41_MASK, .index = PINMUX_MIO_OUTSEL_41_OUT_41_OFFSET }) |
Definition at line 1897 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_41_OUT_41_MASK 0x7fu |
Definition at line 1895 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_41_OUT_41_OFFSET 0 |
Definition at line 1896 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_41_REG_OFFSET 0x46c |
Definition at line 1893 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_41_REG_RESVAL 0x2u |
Definition at line 1894 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_42_OUT_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_42_OUT_42_MASK, .index = PINMUX_MIO_OUTSEL_42_OUT_42_OFFSET }) |
Definition at line 1905 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_42_OUT_42_MASK 0x7fu |
Definition at line 1903 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_42_OUT_42_OFFSET 0 |
Definition at line 1904 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_42_REG_OFFSET 0x470 |
Definition at line 1901 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_42_REG_RESVAL 0x2u |
Definition at line 1902 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_43_OUT_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_43_OUT_43_MASK, .index = PINMUX_MIO_OUTSEL_43_OUT_43_OFFSET }) |
Definition at line 1913 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_43_OUT_43_MASK 0x7fu |
Definition at line 1911 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_43_OUT_43_OFFSET 0 |
Definition at line 1912 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_43_REG_OFFSET 0x474 |
Definition at line 1909 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_43_REG_RESVAL 0x2u |
Definition at line 1910 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_44_OUT_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_44_OUT_44_MASK, .index = PINMUX_MIO_OUTSEL_44_OUT_44_OFFSET }) |
Definition at line 1921 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_44_OUT_44_MASK 0x7fu |
Definition at line 1919 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_44_OUT_44_OFFSET 0 |
Definition at line 1920 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_44_REG_OFFSET 0x478 |
Definition at line 1917 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_44_REG_RESVAL 0x2u |
Definition at line 1918 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_45_OUT_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_45_OUT_45_MASK, .index = PINMUX_MIO_OUTSEL_45_OUT_45_OFFSET }) |
Definition at line 1929 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_45_OUT_45_MASK 0x7fu |
Definition at line 1927 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_45_OUT_45_OFFSET 0 |
Definition at line 1928 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_45_REG_OFFSET 0x47c |
Definition at line 1925 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_45_REG_RESVAL 0x2u |
Definition at line 1926 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_46_OUT_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_46_OUT_46_MASK, .index = PINMUX_MIO_OUTSEL_46_OUT_46_OFFSET }) |
Definition at line 1937 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_46_OUT_46_MASK 0x7fu |
Definition at line 1935 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_46_OUT_46_OFFSET 0 |
Definition at line 1936 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_46_REG_OFFSET 0x480 |
Definition at line 1933 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_46_REG_RESVAL 0x2u |
Definition at line 1934 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_4_OUT_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_4_OUT_4_MASK, .index = PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET }) |
Definition at line 1601 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_4_OUT_4_MASK 0x7fu |
Definition at line 1599 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET 0 |
Definition at line 1600 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_4_REG_OFFSET 0x3d8 |
Definition at line 1597 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_4_REG_RESVAL 0x2u |
Definition at line 1598 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_5_OUT_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_5_OUT_5_MASK, .index = PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET }) |
Definition at line 1609 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_5_OUT_5_MASK 0x7fu |
Definition at line 1607 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET 0 |
Definition at line 1608 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_5_REG_OFFSET 0x3dc |
Definition at line 1605 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_5_REG_RESVAL 0x2u |
Definition at line 1606 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_6_OUT_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_6_OUT_6_MASK, .index = PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET }) |
Definition at line 1617 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_6_OUT_6_MASK 0x7fu |
Definition at line 1615 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET 0 |
Definition at line 1616 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_6_REG_OFFSET 0x3e0 |
Definition at line 1613 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_6_REG_RESVAL 0x2u |
Definition at line 1614 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_7_OUT_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_7_OUT_7_MASK, .index = PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET }) |
Definition at line 1625 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_7_OUT_7_MASK 0x7fu |
Definition at line 1623 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET 0 |
Definition at line 1624 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_7_REG_OFFSET 0x3e4 |
Definition at line 1621 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_7_REG_RESVAL 0x2u |
Definition at line 1622 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_8_OUT_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_8_OUT_8_MASK, .index = PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET }) |
Definition at line 1633 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_8_OUT_8_MASK 0x7fu |
Definition at line 1631 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET 0 |
Definition at line 1632 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_8_REG_OFFSET 0x3e8 |
Definition at line 1629 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_8_REG_RESVAL 0x2u |
Definition at line 1630 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_9_OUT_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_9_OUT_9_MASK, .index = PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET }) |
Definition at line 1641 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_9_OUT_9_MASK 0x7fu |
Definition at line 1639 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET 0 |
Definition at line 1640 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_9_REG_OFFSET 0x3ec |
Definition at line 1637 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_9_REG_RESVAL 0x2u |
Definition at line 1638 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_MULTIREG_COUNT 47 |
Definition at line 1562 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_OUT_FIELD_WIDTH 7 |
Definition at line 1561 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_0_EN_0_BIT 0 |
Definition at line 1327 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_0_REG_OFFSET 0x30c |
Definition at line 1325 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_0_REG_RESVAL 0x1u |
Definition at line 1326 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_10_EN_10_BIT 0 |
Definition at line 1377 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_10_REG_OFFSET 0x334 |
Definition at line 1375 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_10_REG_RESVAL 0x1u |
Definition at line 1376 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_11_EN_11_BIT 0 |
Definition at line 1382 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_11_REG_OFFSET 0x338 |
Definition at line 1380 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_11_REG_RESVAL 0x1u |
Definition at line 1381 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_12_EN_12_BIT 0 |
Definition at line 1387 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_12_REG_OFFSET 0x33c |
Definition at line 1385 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_12_REG_RESVAL 0x1u |
Definition at line 1386 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_13_EN_13_BIT 0 |
Definition at line 1392 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_13_REG_OFFSET 0x340 |
Definition at line 1390 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_13_REG_RESVAL 0x1u |
Definition at line 1391 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_14_EN_14_BIT 0 |
Definition at line 1397 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_14_REG_OFFSET 0x344 |
Definition at line 1395 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_14_REG_RESVAL 0x1u |
Definition at line 1396 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_15_EN_15_BIT 0 |
Definition at line 1402 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_15_REG_OFFSET 0x348 |
Definition at line 1400 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_15_REG_RESVAL 0x1u |
Definition at line 1401 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_16_EN_16_BIT 0 |
Definition at line 1407 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_16_REG_OFFSET 0x34c |
Definition at line 1405 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_16_REG_RESVAL 0x1u |
Definition at line 1406 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_17_EN_17_BIT 0 |
Definition at line 1412 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_17_REG_OFFSET 0x350 |
Definition at line 1410 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_17_REG_RESVAL 0x1u |
Definition at line 1411 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_18_EN_18_BIT 0 |
Definition at line 1417 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_18_REG_OFFSET 0x354 |
Definition at line 1415 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_18_REG_RESVAL 0x1u |
Definition at line 1416 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_19_EN_19_BIT 0 |
Definition at line 1422 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_19_REG_OFFSET 0x358 |
Definition at line 1420 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_19_REG_RESVAL 0x1u |
Definition at line 1421 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_1_EN_1_BIT 0 |
Definition at line 1332 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_1_REG_OFFSET 0x310 |
Definition at line 1330 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_1_REG_RESVAL 0x1u |
Definition at line 1331 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_20_EN_20_BIT 0 |
Definition at line 1427 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_20_REG_OFFSET 0x35c |
Definition at line 1425 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_20_REG_RESVAL 0x1u |
Definition at line 1426 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_21_EN_21_BIT 0 |
Definition at line 1432 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_21_REG_OFFSET 0x360 |
Definition at line 1430 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_21_REG_RESVAL 0x1u |
Definition at line 1431 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_22_EN_22_BIT 0 |
Definition at line 1437 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_22_REG_OFFSET 0x364 |
Definition at line 1435 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_22_REG_RESVAL 0x1u |
Definition at line 1436 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_23_EN_23_BIT 0 |
Definition at line 1442 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_23_REG_OFFSET 0x368 |
Definition at line 1440 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_23_REG_RESVAL 0x1u |
Definition at line 1441 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_24_EN_24_BIT 0 |
Definition at line 1447 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_24_REG_OFFSET 0x36c |
Definition at line 1445 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_24_REG_RESVAL 0x1u |
Definition at line 1446 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_25_EN_25_BIT 0 |
Definition at line 1452 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_25_REG_OFFSET 0x370 |
Definition at line 1450 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_25_REG_RESVAL 0x1u |
Definition at line 1451 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_26_EN_26_BIT 0 |
Definition at line 1457 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_26_REG_OFFSET 0x374 |
Definition at line 1455 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_26_REG_RESVAL 0x1u |
Definition at line 1456 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_27_EN_27_BIT 0 |
Definition at line 1462 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_27_REG_OFFSET 0x378 |
Definition at line 1460 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_27_REG_RESVAL 0x1u |
Definition at line 1461 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_28_EN_28_BIT 0 |
Definition at line 1467 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_28_REG_OFFSET 0x37c |
Definition at line 1465 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_28_REG_RESVAL 0x1u |
Definition at line 1466 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_29_EN_29_BIT 0 |
Definition at line 1472 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_29_REG_OFFSET 0x380 |
Definition at line 1470 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_29_REG_RESVAL 0x1u |
Definition at line 1471 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_2_EN_2_BIT 0 |
Definition at line 1337 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_2_REG_OFFSET 0x314 |
Definition at line 1335 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_2_REG_RESVAL 0x1u |
Definition at line 1336 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_30_EN_30_BIT 0 |
Definition at line 1477 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_30_REG_OFFSET 0x384 |
Definition at line 1475 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_30_REG_RESVAL 0x1u |
Definition at line 1476 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_31_EN_31_BIT 0 |
Definition at line 1482 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_31_REG_OFFSET 0x388 |
Definition at line 1480 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_31_REG_RESVAL 0x1u |
Definition at line 1481 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_32_EN_32_BIT 0 |
Definition at line 1487 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_32_REG_OFFSET 0x38c |
Definition at line 1485 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_32_REG_RESVAL 0x1u |
Definition at line 1486 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_33_EN_33_BIT 0 |
Definition at line 1492 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_33_REG_OFFSET 0x390 |
Definition at line 1490 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_33_REG_RESVAL 0x1u |
Definition at line 1491 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_34_EN_34_BIT 0 |
Definition at line 1497 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_34_REG_OFFSET 0x394 |
Definition at line 1495 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_34_REG_RESVAL 0x1u |
Definition at line 1496 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_35_EN_35_BIT 0 |
Definition at line 1502 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_35_REG_OFFSET 0x398 |
Definition at line 1500 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_35_REG_RESVAL 0x1u |
Definition at line 1501 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_36_EN_36_BIT 0 |
Definition at line 1507 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_36_REG_OFFSET 0x39c |
Definition at line 1505 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_36_REG_RESVAL 0x1u |
Definition at line 1506 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_37_EN_37_BIT 0 |
Definition at line 1512 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_37_REG_OFFSET 0x3a0 |
Definition at line 1510 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_37_REG_RESVAL 0x1u |
Definition at line 1511 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_38_EN_38_BIT 0 |
Definition at line 1517 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_38_REG_OFFSET 0x3a4 |
Definition at line 1515 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_38_REG_RESVAL 0x1u |
Definition at line 1516 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_39_EN_39_BIT 0 |
Definition at line 1522 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_39_REG_OFFSET 0x3a8 |
Definition at line 1520 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_39_REG_RESVAL 0x1u |
Definition at line 1521 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_3_EN_3_BIT 0 |
Definition at line 1342 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_3_REG_OFFSET 0x318 |
Definition at line 1340 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_3_REG_RESVAL 0x1u |
Definition at line 1341 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_40_EN_40_BIT 0 |
Definition at line 1527 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_40_REG_OFFSET 0x3ac |
Definition at line 1525 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_40_REG_RESVAL 0x1u |
Definition at line 1526 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_41_EN_41_BIT 0 |
Definition at line 1532 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_41_REG_OFFSET 0x3b0 |
Definition at line 1530 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_41_REG_RESVAL 0x1u |
Definition at line 1531 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_42_EN_42_BIT 0 |
Definition at line 1537 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_42_REG_OFFSET 0x3b4 |
Definition at line 1535 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_42_REG_RESVAL 0x1u |
Definition at line 1536 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_43_EN_43_BIT 0 |
Definition at line 1542 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_43_REG_OFFSET 0x3b8 |
Definition at line 1540 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_43_REG_RESVAL 0x1u |
Definition at line 1541 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_44_EN_44_BIT 0 |
Definition at line 1547 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_44_REG_OFFSET 0x3bc |
Definition at line 1545 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_44_REG_RESVAL 0x1u |
Definition at line 1546 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_45_EN_45_BIT 0 |
Definition at line 1552 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_45_REG_OFFSET 0x3c0 |
Definition at line 1550 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_45_REG_RESVAL 0x1u |
Definition at line 1551 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_46_EN_46_BIT 0 |
Definition at line 1557 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_46_REG_OFFSET 0x3c4 |
Definition at line 1555 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_46_REG_RESVAL 0x1u |
Definition at line 1556 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_4_EN_4_BIT 0 |
Definition at line 1347 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_4_REG_OFFSET 0x31c |
Definition at line 1345 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_4_REG_RESVAL 0x1u |
Definition at line 1346 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_5_EN_5_BIT 0 |
Definition at line 1352 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_5_REG_OFFSET 0x320 |
Definition at line 1350 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_5_REG_RESVAL 0x1u |
Definition at line 1351 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_6_EN_6_BIT 0 |
Definition at line 1357 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_6_REG_OFFSET 0x324 |
Definition at line 1355 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_6_REG_RESVAL 0x1u |
Definition at line 1356 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_7_EN_7_BIT 0 |
Definition at line 1362 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_7_REG_OFFSET 0x328 |
Definition at line 1360 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_7_REG_RESVAL 0x1u |
Definition at line 1361 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_8_EN_8_BIT 0 |
Definition at line 1367 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_8_REG_OFFSET 0x32c |
Definition at line 1365 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_8_REG_RESVAL 0x1u |
Definition at line 1366 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_9_EN_9_BIT 0 |
Definition at line 1372 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_9_REG_OFFSET 0x330 |
Definition at line 1370 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_9_REG_RESVAL 0x1u |
Definition at line 1371 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_EN_FIELD_WIDTH 1 |
Definition at line 1321 of file pinmux_regs.h.
| #define PINMUX_MIO_OUTSEL_REGWEN_MULTIREG_COUNT 47 |
Definition at line 1322 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET }) |
Definition at line 2211 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xfu |
Definition at line 2209 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20 |
Definition at line 2210 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_INPUT_DISABLE_0_BIT 7 |
Definition at line 2204 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_INVERT_0_BIT 0 |
Definition at line 2195 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4 |
Definition at line 2201 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_OD_EN_0_BIT 6 |
Definition at line 2203 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_BIT 2 |
Definition at line 2197 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3 |
Definition at line 2198 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_DOWN 0x0 |
Definition at line 2199 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_UP 0x1 |
Definition at line 2200 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_REG_OFFSET 0x540 |
Definition at line 2193 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_REG_RESVAL 0x0u |
Definition at line 2194 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5 |
Definition at line 2202 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET }) |
Definition at line 2207 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3u |
Definition at line 2205 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16 |
Definition at line 2206 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1 |
Definition at line 2196 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET }) |
Definition at line 2411 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xfu |
Definition at line 2409 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20 |
Definition at line 2410 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_INPUT_DISABLE_10_BIT 7 |
Definition at line 2404 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_INVERT_10_BIT 0 |
Definition at line 2397 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4 |
Definition at line 2401 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_OD_EN_10_BIT 6 |
Definition at line 2403 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_PULL_EN_10_BIT 2 |
Definition at line 2399 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3 |
Definition at line 2400 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_REG_OFFSET 0x568 |
Definition at line 2395 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_REG_RESVAL 0x0u |
Definition at line 2396 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5 |
Definition at line 2402 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET }) |
Definition at line 2407 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3u |
Definition at line 2405 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16 |
Definition at line 2406 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1 |
Definition at line 2398 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET }) |
Definition at line 2431 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xfu |
Definition at line 2429 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20 |
Definition at line 2430 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_INPUT_DISABLE_11_BIT 7 |
Definition at line 2424 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_INVERT_11_BIT 0 |
Definition at line 2417 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4 |
Definition at line 2421 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_OD_EN_11_BIT 6 |
Definition at line 2423 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_PULL_EN_11_BIT 2 |
Definition at line 2419 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3 |
Definition at line 2420 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_REG_OFFSET 0x56c |
Definition at line 2415 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_REG_RESVAL 0x0u |
Definition at line 2416 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5 |
Definition at line 2422 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET }) |
Definition at line 2427 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3u |
Definition at line 2425 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16 |
Definition at line 2426 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1 |
Definition at line 2418 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK, .index = PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET }) |
Definition at line 2451 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK 0xfu |
Definition at line 2449 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET 20 |
Definition at line 2450 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_INPUT_DISABLE_12_BIT 7 |
Definition at line 2444 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_INVERT_12_BIT 0 |
Definition at line 2437 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_KEEPER_EN_12_BIT 4 |
Definition at line 2441 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_OD_EN_12_BIT 6 |
Definition at line 2443 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_PULL_EN_12_BIT 2 |
Definition at line 2439 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_PULL_SELECT_12_BIT 3 |
Definition at line 2440 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_REG_OFFSET 0x570 |
Definition at line 2435 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_REG_RESVAL 0x0u |
Definition at line 2436 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_SCHMITT_EN_12_BIT 5 |
Definition at line 2442 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_MASK, .index = PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET }) |
Definition at line 2447 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_MASK 0x3u |
Definition at line 2445 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET 16 |
Definition at line 2446 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_BIT 1 |
Definition at line 2438 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK, .index = PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET }) |
Definition at line 2471 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK 0xfu |
Definition at line 2469 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET 20 |
Definition at line 2470 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_INPUT_DISABLE_13_BIT 7 |
Definition at line 2464 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_INVERT_13_BIT 0 |
Definition at line 2457 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_KEEPER_EN_13_BIT 4 |
Definition at line 2461 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_OD_EN_13_BIT 6 |
Definition at line 2463 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_PULL_EN_13_BIT 2 |
Definition at line 2459 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_PULL_SELECT_13_BIT 3 |
Definition at line 2460 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_REG_OFFSET 0x574 |
Definition at line 2455 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_REG_RESVAL 0x0u |
Definition at line 2456 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_SCHMITT_EN_13_BIT 5 |
Definition at line 2462 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_MASK, .index = PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET }) |
Definition at line 2467 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_MASK 0x3u |
Definition at line 2465 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET 16 |
Definition at line 2466 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_BIT 1 |
Definition at line 2458 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK, .index = PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET }) |
Definition at line 2491 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK 0xfu |
Definition at line 2489 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET 20 |
Definition at line 2490 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_INPUT_DISABLE_14_BIT 7 |
Definition at line 2484 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_INVERT_14_BIT 0 |
Definition at line 2477 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_KEEPER_EN_14_BIT 4 |
Definition at line 2481 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_OD_EN_14_BIT 6 |
Definition at line 2483 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_PULL_EN_14_BIT 2 |
Definition at line 2479 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_PULL_SELECT_14_BIT 3 |
Definition at line 2480 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_REG_OFFSET 0x578 |
Definition at line 2475 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_REG_RESVAL 0x0u |
Definition at line 2476 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_SCHMITT_EN_14_BIT 5 |
Definition at line 2482 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_MASK, .index = PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET }) |
Definition at line 2487 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_MASK 0x3u |
Definition at line 2485 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET 16 |
Definition at line 2486 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_BIT 1 |
Definition at line 2478 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK, .index = PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET }) |
Definition at line 2511 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK 0xfu |
Definition at line 2509 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET 20 |
Definition at line 2510 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_INPUT_DISABLE_15_BIT 7 |
Definition at line 2504 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_INVERT_15_BIT 0 |
Definition at line 2497 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_KEEPER_EN_15_BIT 4 |
Definition at line 2501 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_OD_EN_15_BIT 6 |
Definition at line 2503 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_PULL_EN_15_BIT 2 |
Definition at line 2499 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_PULL_SELECT_15_BIT 3 |
Definition at line 2500 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_REG_OFFSET 0x57c |
Definition at line 2495 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_REG_RESVAL 0x0u |
Definition at line 2496 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_SCHMITT_EN_15_BIT 5 |
Definition at line 2502 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_MASK, .index = PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET }) |
Definition at line 2507 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_MASK 0x3u |
Definition at line 2505 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET 16 |
Definition at line 2506 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_BIT 1 |
Definition at line 2498 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK, .index = PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET }) |
Definition at line 2531 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK 0xfu |
Definition at line 2529 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET 20 |
Definition at line 2530 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_INPUT_DISABLE_16_BIT 7 |
Definition at line 2524 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_INVERT_16_BIT 0 |
Definition at line 2517 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_KEEPER_EN_16_BIT 4 |
Definition at line 2521 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_OD_EN_16_BIT 6 |
Definition at line 2523 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_PULL_EN_16_BIT 2 |
Definition at line 2519 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_PULL_SELECT_16_BIT 3 |
Definition at line 2520 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_REG_OFFSET 0x580 |
Definition at line 2515 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_REG_RESVAL 0x0u |
Definition at line 2516 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_SCHMITT_EN_16_BIT 5 |
Definition at line 2522 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_MASK, .index = PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET }) |
Definition at line 2527 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_MASK 0x3u |
Definition at line 2525 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET 16 |
Definition at line 2526 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_16_VIRTUAL_OD_EN_16_BIT 1 |
Definition at line 2518 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK, .index = PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET }) |
Definition at line 2551 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK 0xfu |
Definition at line 2549 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET 20 |
Definition at line 2550 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_INPUT_DISABLE_17_BIT 7 |
Definition at line 2544 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_INVERT_17_BIT 0 |
Definition at line 2537 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_KEEPER_EN_17_BIT 4 |
Definition at line 2541 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_OD_EN_17_BIT 6 |
Definition at line 2543 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_PULL_EN_17_BIT 2 |
Definition at line 2539 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_PULL_SELECT_17_BIT 3 |
Definition at line 2540 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_REG_OFFSET 0x584 |
Definition at line 2535 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_REG_RESVAL 0x0u |
Definition at line 2536 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_SCHMITT_EN_17_BIT 5 |
Definition at line 2542 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_MASK, .index = PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET }) |
Definition at line 2547 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_MASK 0x3u |
Definition at line 2545 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET 16 |
Definition at line 2546 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_17_VIRTUAL_OD_EN_17_BIT 1 |
Definition at line 2538 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK, .index = PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET }) |
Definition at line 2571 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK 0xfu |
Definition at line 2569 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET 20 |
Definition at line 2570 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_INPUT_DISABLE_18_BIT 7 |
Definition at line 2564 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_INVERT_18_BIT 0 |
Definition at line 2557 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_KEEPER_EN_18_BIT 4 |
Definition at line 2561 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_OD_EN_18_BIT 6 |
Definition at line 2563 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_PULL_EN_18_BIT 2 |
Definition at line 2559 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_PULL_SELECT_18_BIT 3 |
Definition at line 2560 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_REG_OFFSET 0x588 |
Definition at line 2555 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_REG_RESVAL 0x0u |
Definition at line 2556 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_SCHMITT_EN_18_BIT 5 |
Definition at line 2562 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_MASK, .index = PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET }) |
Definition at line 2567 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_MASK 0x3u |
Definition at line 2565 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET 16 |
Definition at line 2566 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_18_VIRTUAL_OD_EN_18_BIT 1 |
Definition at line 2558 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK, .index = PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET }) |
Definition at line 2591 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK 0xfu |
Definition at line 2589 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET 20 |
Definition at line 2590 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_INPUT_DISABLE_19_BIT 7 |
Definition at line 2584 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_INVERT_19_BIT 0 |
Definition at line 2577 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_KEEPER_EN_19_BIT 4 |
Definition at line 2581 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_OD_EN_19_BIT 6 |
Definition at line 2583 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_PULL_EN_19_BIT 2 |
Definition at line 2579 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_PULL_SELECT_19_BIT 3 |
Definition at line 2580 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_REG_OFFSET 0x58c |
Definition at line 2575 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_REG_RESVAL 0x0u |
Definition at line 2576 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_SCHMITT_EN_19_BIT 5 |
Definition at line 2582 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_MASK, .index = PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET }) |
Definition at line 2587 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_MASK 0x3u |
Definition at line 2585 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET 16 |
Definition at line 2586 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_19_VIRTUAL_OD_EN_19_BIT 1 |
Definition at line 2578 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET }) |
Definition at line 2231 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xfu |
Definition at line 2229 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20 |
Definition at line 2230 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT 7 |
Definition at line 2224 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_INVERT_1_BIT 0 |
Definition at line 2217 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4 |
Definition at line 2221 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_OD_EN_1_BIT 6 |
Definition at line 2223 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_BIT 2 |
Definition at line 2219 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3 |
Definition at line 2220 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_REG_OFFSET 0x544 |
Definition at line 2215 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_REG_RESVAL 0x0u |
Definition at line 2216 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5 |
Definition at line 2222 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET }) |
Definition at line 2227 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3u |
Definition at line 2225 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16 |
Definition at line 2226 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1 |
Definition at line 2218 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK, .index = PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET }) |
Definition at line 2611 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK 0xfu |
Definition at line 2609 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET 20 |
Definition at line 2610 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_INPUT_DISABLE_20_BIT 7 |
Definition at line 2604 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_INVERT_20_BIT 0 |
Definition at line 2597 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_KEEPER_EN_20_BIT 4 |
Definition at line 2601 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_OD_EN_20_BIT 6 |
Definition at line 2603 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_PULL_EN_20_BIT 2 |
Definition at line 2599 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_PULL_SELECT_20_BIT 3 |
Definition at line 2600 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_REG_OFFSET 0x590 |
Definition at line 2595 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_REG_RESVAL 0x0u |
Definition at line 2596 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_SCHMITT_EN_20_BIT 5 |
Definition at line 2602 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_MASK, .index = PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET }) |
Definition at line 2607 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_MASK 0x3u |
Definition at line 2605 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET 16 |
Definition at line 2606 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_20_VIRTUAL_OD_EN_20_BIT 1 |
Definition at line 2598 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK, .index = PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET }) |
Definition at line 2631 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK 0xfu |
Definition at line 2629 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET 20 |
Definition at line 2630 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_INPUT_DISABLE_21_BIT 7 |
Definition at line 2624 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_INVERT_21_BIT 0 |
Definition at line 2617 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_KEEPER_EN_21_BIT 4 |
Definition at line 2621 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_OD_EN_21_BIT 6 |
Definition at line 2623 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_PULL_EN_21_BIT 2 |
Definition at line 2619 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_PULL_SELECT_21_BIT 3 |
Definition at line 2620 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_REG_OFFSET 0x594 |
Definition at line 2615 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_REG_RESVAL 0x0u |
Definition at line 2616 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_SCHMITT_EN_21_BIT 5 |
Definition at line 2622 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_MASK, .index = PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET }) |
Definition at line 2627 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_MASK 0x3u |
Definition at line 2625 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET 16 |
Definition at line 2626 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_21_VIRTUAL_OD_EN_21_BIT 1 |
Definition at line 2618 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK, .index = PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET }) |
Definition at line 2651 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK 0xfu |
Definition at line 2649 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET 20 |
Definition at line 2650 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_INPUT_DISABLE_22_BIT 7 |
Definition at line 2644 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_INVERT_22_BIT 0 |
Definition at line 2637 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_KEEPER_EN_22_BIT 4 |
Definition at line 2641 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_OD_EN_22_BIT 6 |
Definition at line 2643 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_PULL_EN_22_BIT 2 |
Definition at line 2639 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_PULL_SELECT_22_BIT 3 |
Definition at line 2640 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_REG_OFFSET 0x598 |
Definition at line 2635 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_REG_RESVAL 0x0u |
Definition at line 2636 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_SCHMITT_EN_22_BIT 5 |
Definition at line 2642 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_MASK, .index = PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET }) |
Definition at line 2647 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_MASK 0x3u |
Definition at line 2645 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET 16 |
Definition at line 2646 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_22_VIRTUAL_OD_EN_22_BIT 1 |
Definition at line 2638 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK, .index = PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET }) |
Definition at line 2671 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK 0xfu |
Definition at line 2669 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET 20 |
Definition at line 2670 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_INPUT_DISABLE_23_BIT 7 |
Definition at line 2664 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_INVERT_23_BIT 0 |
Definition at line 2657 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_KEEPER_EN_23_BIT 4 |
Definition at line 2661 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_OD_EN_23_BIT 6 |
Definition at line 2663 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_PULL_EN_23_BIT 2 |
Definition at line 2659 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_PULL_SELECT_23_BIT 3 |
Definition at line 2660 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_REG_OFFSET 0x59c |
Definition at line 2655 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_REG_RESVAL 0x0u |
Definition at line 2656 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_SCHMITT_EN_23_BIT 5 |
Definition at line 2662 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_MASK, .index = PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET }) |
Definition at line 2667 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_MASK 0x3u |
Definition at line 2665 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET 16 |
Definition at line 2666 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_23_VIRTUAL_OD_EN_23_BIT 1 |
Definition at line 2658 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK, .index = PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET }) |
Definition at line 2691 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK 0xfu |
Definition at line 2689 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET 20 |
Definition at line 2690 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_INPUT_DISABLE_24_BIT 7 |
Definition at line 2684 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_INVERT_24_BIT 0 |
Definition at line 2677 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_KEEPER_EN_24_BIT 4 |
Definition at line 2681 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_OD_EN_24_BIT 6 |
Definition at line 2683 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_PULL_EN_24_BIT 2 |
Definition at line 2679 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_PULL_SELECT_24_BIT 3 |
Definition at line 2680 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_REG_OFFSET 0x5a0 |
Definition at line 2675 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_REG_RESVAL 0x0u |
Definition at line 2676 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_SCHMITT_EN_24_BIT 5 |
Definition at line 2682 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_MASK, .index = PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET }) |
Definition at line 2687 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_MASK 0x3u |
Definition at line 2685 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET 16 |
Definition at line 2686 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_24_VIRTUAL_OD_EN_24_BIT 1 |
Definition at line 2678 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK, .index = PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET }) |
Definition at line 2711 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK 0xfu |
Definition at line 2709 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET 20 |
Definition at line 2710 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_INPUT_DISABLE_25_BIT 7 |
Definition at line 2704 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_INVERT_25_BIT 0 |
Definition at line 2697 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_KEEPER_EN_25_BIT 4 |
Definition at line 2701 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_OD_EN_25_BIT 6 |
Definition at line 2703 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_PULL_EN_25_BIT 2 |
Definition at line 2699 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_PULL_SELECT_25_BIT 3 |
Definition at line 2700 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_REG_OFFSET 0x5a4 |
Definition at line 2695 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_REG_RESVAL 0x0u |
Definition at line 2696 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_SCHMITT_EN_25_BIT 5 |
Definition at line 2702 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_MASK, .index = PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET }) |
Definition at line 2707 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_MASK 0x3u |
Definition at line 2705 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET 16 |
Definition at line 2706 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_25_VIRTUAL_OD_EN_25_BIT 1 |
Definition at line 2698 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK, .index = PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET }) |
Definition at line 2731 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK 0xfu |
Definition at line 2729 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET 20 |
Definition at line 2730 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_INPUT_DISABLE_26_BIT 7 |
Definition at line 2724 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_INVERT_26_BIT 0 |
Definition at line 2717 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_KEEPER_EN_26_BIT 4 |
Definition at line 2721 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_OD_EN_26_BIT 6 |
Definition at line 2723 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_PULL_EN_26_BIT 2 |
Definition at line 2719 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_PULL_SELECT_26_BIT 3 |
Definition at line 2720 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_REG_OFFSET 0x5a8 |
Definition at line 2715 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_REG_RESVAL 0x0u |
Definition at line 2716 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_SCHMITT_EN_26_BIT 5 |
Definition at line 2722 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_MASK, .index = PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET }) |
Definition at line 2727 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_MASK 0x3u |
Definition at line 2725 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET 16 |
Definition at line 2726 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_26_VIRTUAL_OD_EN_26_BIT 1 |
Definition at line 2718 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK, .index = PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET }) |
Definition at line 2751 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK 0xfu |
Definition at line 2749 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET 20 |
Definition at line 2750 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_INPUT_DISABLE_27_BIT 7 |
Definition at line 2744 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_INVERT_27_BIT 0 |
Definition at line 2737 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_KEEPER_EN_27_BIT 4 |
Definition at line 2741 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_OD_EN_27_BIT 6 |
Definition at line 2743 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_PULL_EN_27_BIT 2 |
Definition at line 2739 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_PULL_SELECT_27_BIT 3 |
Definition at line 2740 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_REG_OFFSET 0x5ac |
Definition at line 2735 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_REG_RESVAL 0x0u |
Definition at line 2736 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_SCHMITT_EN_27_BIT 5 |
Definition at line 2742 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_MASK, .index = PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET }) |
Definition at line 2747 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_MASK 0x3u |
Definition at line 2745 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET 16 |
Definition at line 2746 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_27_VIRTUAL_OD_EN_27_BIT 1 |
Definition at line 2738 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK, .index = PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET }) |
Definition at line 2771 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK 0xfu |
Definition at line 2769 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET 20 |
Definition at line 2770 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_INPUT_DISABLE_28_BIT 7 |
Definition at line 2764 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_INVERT_28_BIT 0 |
Definition at line 2757 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_KEEPER_EN_28_BIT 4 |
Definition at line 2761 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_OD_EN_28_BIT 6 |
Definition at line 2763 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_PULL_EN_28_BIT 2 |
Definition at line 2759 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_PULL_SELECT_28_BIT 3 |
Definition at line 2760 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_REG_OFFSET 0x5b0 |
Definition at line 2755 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_REG_RESVAL 0x0u |
Definition at line 2756 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_SCHMITT_EN_28_BIT 5 |
Definition at line 2762 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_MASK, .index = PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET }) |
Definition at line 2767 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_MASK 0x3u |
Definition at line 2765 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET 16 |
Definition at line 2766 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_28_VIRTUAL_OD_EN_28_BIT 1 |
Definition at line 2758 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK, .index = PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET }) |
Definition at line 2791 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK 0xfu |
Definition at line 2789 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET 20 |
Definition at line 2790 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_INPUT_DISABLE_29_BIT 7 |
Definition at line 2784 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_INVERT_29_BIT 0 |
Definition at line 2777 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_KEEPER_EN_29_BIT 4 |
Definition at line 2781 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_OD_EN_29_BIT 6 |
Definition at line 2783 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_PULL_EN_29_BIT 2 |
Definition at line 2779 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_PULL_SELECT_29_BIT 3 |
Definition at line 2780 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_REG_OFFSET 0x5b4 |
Definition at line 2775 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_REG_RESVAL 0x0u |
Definition at line 2776 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_SCHMITT_EN_29_BIT 5 |
Definition at line 2782 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_MASK, .index = PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET }) |
Definition at line 2787 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_MASK 0x3u |
Definition at line 2785 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET 16 |
Definition at line 2786 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_29_VIRTUAL_OD_EN_29_BIT 1 |
Definition at line 2778 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET }) |
Definition at line 2251 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xfu |
Definition at line 2249 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20 |
Definition at line 2250 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_INPUT_DISABLE_2_BIT 7 |
Definition at line 2244 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_INVERT_2_BIT 0 |
Definition at line 2237 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4 |
Definition at line 2241 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_OD_EN_2_BIT 6 |
Definition at line 2243 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_PULL_EN_2_BIT 2 |
Definition at line 2239 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3 |
Definition at line 2240 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_REG_OFFSET 0x548 |
Definition at line 2235 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_REG_RESVAL 0x0u |
Definition at line 2236 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5 |
Definition at line 2242 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET }) |
Definition at line 2247 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3u |
Definition at line 2245 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16 |
Definition at line 2246 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1 |
Definition at line 2238 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK, .index = PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET }) |
Definition at line 2811 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK 0xfu |
Definition at line 2809 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET 20 |
Definition at line 2810 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_INPUT_DISABLE_30_BIT 7 |
Definition at line 2804 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_INVERT_30_BIT 0 |
Definition at line 2797 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_KEEPER_EN_30_BIT 4 |
Definition at line 2801 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_OD_EN_30_BIT 6 |
Definition at line 2803 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_PULL_EN_30_BIT 2 |
Definition at line 2799 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_PULL_SELECT_30_BIT 3 |
Definition at line 2800 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_REG_OFFSET 0x5b8 |
Definition at line 2795 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_REG_RESVAL 0x0u |
Definition at line 2796 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_SCHMITT_EN_30_BIT 5 |
Definition at line 2802 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_MASK, .index = PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET }) |
Definition at line 2807 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_MASK 0x3u |
Definition at line 2805 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET 16 |
Definition at line 2806 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_30_VIRTUAL_OD_EN_30_BIT 1 |
Definition at line 2798 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK, .index = PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET }) |
Definition at line 2831 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK 0xfu |
Definition at line 2829 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET 20 |
Definition at line 2830 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_INPUT_DISABLE_31_BIT 7 |
Definition at line 2824 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_INVERT_31_BIT 0 |
Definition at line 2817 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_KEEPER_EN_31_BIT 4 |
Definition at line 2821 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_OD_EN_31_BIT 6 |
Definition at line 2823 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_PULL_EN_31_BIT 2 |
Definition at line 2819 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_PULL_SELECT_31_BIT 3 |
Definition at line 2820 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_REG_OFFSET 0x5bc |
Definition at line 2815 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_REG_RESVAL 0x0u |
Definition at line 2816 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_SCHMITT_EN_31_BIT 5 |
Definition at line 2822 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_MASK, .index = PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET }) |
Definition at line 2827 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_MASK 0x3u |
Definition at line 2825 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET 16 |
Definition at line 2826 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_31_VIRTUAL_OD_EN_31_BIT 1 |
Definition at line 2818 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK, .index = PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET }) |
Definition at line 2851 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK 0xfu |
Definition at line 2849 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET 20 |
Definition at line 2850 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_INPUT_DISABLE_32_BIT 7 |
Definition at line 2844 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_INVERT_32_BIT 0 |
Definition at line 2837 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_KEEPER_EN_32_BIT 4 |
Definition at line 2841 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_OD_EN_32_BIT 6 |
Definition at line 2843 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_PULL_EN_32_BIT 2 |
Definition at line 2839 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_PULL_SELECT_32_BIT 3 |
Definition at line 2840 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_REG_OFFSET 0x5c0 |
Definition at line 2835 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_REG_RESVAL 0x0u |
Definition at line 2836 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_SCHMITT_EN_32_BIT 5 |
Definition at line 2842 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_MASK, .index = PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET }) |
Definition at line 2847 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_MASK 0x3u |
Definition at line 2845 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET 16 |
Definition at line 2846 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_32_VIRTUAL_OD_EN_32_BIT 1 |
Definition at line 2838 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK, .index = PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET }) |
Definition at line 2871 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK 0xfu |
Definition at line 2869 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET 20 |
Definition at line 2870 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_INPUT_DISABLE_33_BIT 7 |
Definition at line 2864 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_INVERT_33_BIT 0 |
Definition at line 2857 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_KEEPER_EN_33_BIT 4 |
Definition at line 2861 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_OD_EN_33_BIT 6 |
Definition at line 2863 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_PULL_EN_33_BIT 2 |
Definition at line 2859 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_PULL_SELECT_33_BIT 3 |
Definition at line 2860 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_REG_OFFSET 0x5c4 |
Definition at line 2855 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_REG_RESVAL 0x0u |
Definition at line 2856 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_SCHMITT_EN_33_BIT 5 |
Definition at line 2862 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_MASK, .index = PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET }) |
Definition at line 2867 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_MASK 0x3u |
Definition at line 2865 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET 16 |
Definition at line 2866 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_33_VIRTUAL_OD_EN_33_BIT 1 |
Definition at line 2858 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK, .index = PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET }) |
Definition at line 2891 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK 0xfu |
Definition at line 2889 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET 20 |
Definition at line 2890 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_INPUT_DISABLE_34_BIT 7 |
Definition at line 2884 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_INVERT_34_BIT 0 |
Definition at line 2877 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_KEEPER_EN_34_BIT 4 |
Definition at line 2881 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_OD_EN_34_BIT 6 |
Definition at line 2883 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_PULL_EN_34_BIT 2 |
Definition at line 2879 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_PULL_SELECT_34_BIT 3 |
Definition at line 2880 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_REG_OFFSET 0x5c8 |
Definition at line 2875 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_REG_RESVAL 0x0u |
Definition at line 2876 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_SCHMITT_EN_34_BIT 5 |
Definition at line 2882 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_MASK, .index = PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET }) |
Definition at line 2887 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_MASK 0x3u |
Definition at line 2885 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET 16 |
Definition at line 2886 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_34_VIRTUAL_OD_EN_34_BIT 1 |
Definition at line 2878 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK, .index = PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET }) |
Definition at line 2911 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK 0xfu |
Definition at line 2909 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET 20 |
Definition at line 2910 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_INPUT_DISABLE_35_BIT 7 |
Definition at line 2904 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_INVERT_35_BIT 0 |
Definition at line 2897 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_KEEPER_EN_35_BIT 4 |
Definition at line 2901 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_OD_EN_35_BIT 6 |
Definition at line 2903 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_PULL_EN_35_BIT 2 |
Definition at line 2899 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_PULL_SELECT_35_BIT 3 |
Definition at line 2900 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_REG_OFFSET 0x5cc |
Definition at line 2895 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_REG_RESVAL 0x0u |
Definition at line 2896 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_SCHMITT_EN_35_BIT 5 |
Definition at line 2902 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_MASK, .index = PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET }) |
Definition at line 2907 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_MASK 0x3u |
Definition at line 2905 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET 16 |
Definition at line 2906 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_35_VIRTUAL_OD_EN_35_BIT 1 |
Definition at line 2898 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK, .index = PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET }) |
Definition at line 2931 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK 0xfu |
Definition at line 2929 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET 20 |
Definition at line 2930 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_INPUT_DISABLE_36_BIT 7 |
Definition at line 2924 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_INVERT_36_BIT 0 |
Definition at line 2917 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_KEEPER_EN_36_BIT 4 |
Definition at line 2921 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_OD_EN_36_BIT 6 |
Definition at line 2923 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_PULL_EN_36_BIT 2 |
Definition at line 2919 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_PULL_SELECT_36_BIT 3 |
Definition at line 2920 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_REG_OFFSET 0x5d0 |
Definition at line 2915 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_REG_RESVAL 0x0u |
Definition at line 2916 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_SCHMITT_EN_36_BIT 5 |
Definition at line 2922 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_MASK, .index = PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET }) |
Definition at line 2927 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_MASK 0x3u |
Definition at line 2925 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET 16 |
Definition at line 2926 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_36_VIRTUAL_OD_EN_36_BIT 1 |
Definition at line 2918 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK, .index = PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET }) |
Definition at line 2951 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK 0xfu |
Definition at line 2949 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET 20 |
Definition at line 2950 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_INPUT_DISABLE_37_BIT 7 |
Definition at line 2944 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_INVERT_37_BIT 0 |
Definition at line 2937 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_KEEPER_EN_37_BIT 4 |
Definition at line 2941 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_OD_EN_37_BIT 6 |
Definition at line 2943 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_PULL_EN_37_BIT 2 |
Definition at line 2939 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_PULL_SELECT_37_BIT 3 |
Definition at line 2940 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_REG_OFFSET 0x5d4 |
Definition at line 2935 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_REG_RESVAL 0x0u |
Definition at line 2936 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_SCHMITT_EN_37_BIT 5 |
Definition at line 2942 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_MASK, .index = PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET }) |
Definition at line 2947 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_MASK 0x3u |
Definition at line 2945 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET 16 |
Definition at line 2946 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_BIT 1 |
Definition at line 2938 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK, .index = PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET }) |
Definition at line 2971 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK 0xfu |
Definition at line 2969 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET 20 |
Definition at line 2970 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_INPUT_DISABLE_38_BIT 7 |
Definition at line 2964 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_INVERT_38_BIT 0 |
Definition at line 2957 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_KEEPER_EN_38_BIT 4 |
Definition at line 2961 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_OD_EN_38_BIT 6 |
Definition at line 2963 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_PULL_EN_38_BIT 2 |
Definition at line 2959 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_PULL_SELECT_38_BIT 3 |
Definition at line 2960 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_REG_OFFSET 0x5d8 |
Definition at line 2955 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_REG_RESVAL 0x0u |
Definition at line 2956 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_SCHMITT_EN_38_BIT 5 |
Definition at line 2962 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_MASK, .index = PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET }) |
Definition at line 2967 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_MASK 0x3u |
Definition at line 2965 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET 16 |
Definition at line 2966 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_BIT 1 |
Definition at line 2958 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK, .index = PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET }) |
Definition at line 2991 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK 0xfu |
Definition at line 2989 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET 20 |
Definition at line 2990 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_INPUT_DISABLE_39_BIT 7 |
Definition at line 2984 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_INVERT_39_BIT 0 |
Definition at line 2977 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_KEEPER_EN_39_BIT 4 |
Definition at line 2981 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_OD_EN_39_BIT 6 |
Definition at line 2983 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_PULL_EN_39_BIT 2 |
Definition at line 2979 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_PULL_SELECT_39_BIT 3 |
Definition at line 2980 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_REG_OFFSET 0x5dc |
Definition at line 2975 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_REG_RESVAL 0x0u |
Definition at line 2976 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_SCHMITT_EN_39_BIT 5 |
Definition at line 2982 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_MASK, .index = PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET }) |
Definition at line 2987 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_MASK 0x3u |
Definition at line 2985 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET 16 |
Definition at line 2986 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_BIT 1 |
Definition at line 2978 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET }) |
Definition at line 2271 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xfu |
Definition at line 2269 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20 |
Definition at line 2270 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT 7 |
Definition at line 2264 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_INVERT_3_BIT 0 |
Definition at line 2257 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4 |
Definition at line 2261 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_OD_EN_3_BIT 6 |
Definition at line 2263 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_PULL_EN_3_BIT 2 |
Definition at line 2259 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3 |
Definition at line 2260 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_REG_OFFSET 0x54c |
Definition at line 2255 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_REG_RESVAL 0x0u |
Definition at line 2256 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5 |
Definition at line 2262 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET }) |
Definition at line 2267 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3u |
Definition at line 2265 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16 |
Definition at line 2266 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1 |
Definition at line 2258 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK, .index = PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET }) |
Definition at line 3011 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK 0xfu |
Definition at line 3009 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET 20 |
Definition at line 3010 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_INPUT_DISABLE_40_BIT 7 |
Definition at line 3004 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_INVERT_40_BIT 0 |
Definition at line 2997 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_KEEPER_EN_40_BIT 4 |
Definition at line 3001 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_OD_EN_40_BIT 6 |
Definition at line 3003 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_PULL_EN_40_BIT 2 |
Definition at line 2999 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_PULL_SELECT_40_BIT 3 |
Definition at line 3000 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_REG_OFFSET 0x5e0 |
Definition at line 2995 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_REG_RESVAL 0x0u |
Definition at line 2996 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_SCHMITT_EN_40_BIT 5 |
Definition at line 3002 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_MASK, .index = PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET }) |
Definition at line 3007 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_MASK 0x3u |
Definition at line 3005 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET 16 |
Definition at line 3006 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_BIT 1 |
Definition at line 2998 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK, .index = PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET }) |
Definition at line 3031 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK 0xfu |
Definition at line 3029 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET 20 |
Definition at line 3030 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_INPUT_DISABLE_41_BIT 7 |
Definition at line 3024 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_INVERT_41_BIT 0 |
Definition at line 3017 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_KEEPER_EN_41_BIT 4 |
Definition at line 3021 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_OD_EN_41_BIT 6 |
Definition at line 3023 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_PULL_EN_41_BIT 2 |
Definition at line 3019 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_PULL_SELECT_41_BIT 3 |
Definition at line 3020 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_REG_OFFSET 0x5e4 |
Definition at line 3015 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_REG_RESVAL 0x0u |
Definition at line 3016 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_SCHMITT_EN_41_BIT 5 |
Definition at line 3022 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_MASK, .index = PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET }) |
Definition at line 3027 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_MASK 0x3u |
Definition at line 3025 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET 16 |
Definition at line 3026 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_BIT 1 |
Definition at line 3018 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK, .index = PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET }) |
Definition at line 3051 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK 0xfu |
Definition at line 3049 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET 20 |
Definition at line 3050 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_INPUT_DISABLE_42_BIT 7 |
Definition at line 3044 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_INVERT_42_BIT 0 |
Definition at line 3037 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_KEEPER_EN_42_BIT 4 |
Definition at line 3041 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_OD_EN_42_BIT 6 |
Definition at line 3043 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_PULL_EN_42_BIT 2 |
Definition at line 3039 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_PULL_SELECT_42_BIT 3 |
Definition at line 3040 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_REG_OFFSET 0x5e8 |
Definition at line 3035 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_REG_RESVAL 0x0u |
Definition at line 3036 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_SCHMITT_EN_42_BIT 5 |
Definition at line 3042 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_MASK, .index = PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET }) |
Definition at line 3047 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_MASK 0x3u |
Definition at line 3045 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET 16 |
Definition at line 3046 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_BIT 1 |
Definition at line 3038 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK, .index = PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET }) |
Definition at line 3071 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK 0xfu |
Definition at line 3069 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET 20 |
Definition at line 3070 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_INPUT_DISABLE_43_BIT 7 |
Definition at line 3064 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_INVERT_43_BIT 0 |
Definition at line 3057 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_KEEPER_EN_43_BIT 4 |
Definition at line 3061 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_OD_EN_43_BIT 6 |
Definition at line 3063 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_PULL_EN_43_BIT 2 |
Definition at line 3059 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_PULL_SELECT_43_BIT 3 |
Definition at line 3060 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_REG_OFFSET 0x5ec |
Definition at line 3055 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_REG_RESVAL 0x0u |
Definition at line 3056 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_SCHMITT_EN_43_BIT 5 |
Definition at line 3062 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_MASK, .index = PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET }) |
Definition at line 3067 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_MASK 0x3u |
Definition at line 3065 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET 16 |
Definition at line 3066 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_43_VIRTUAL_OD_EN_43_BIT 1 |
Definition at line 3058 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK, .index = PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET }) |
Definition at line 3091 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK 0xfu |
Definition at line 3089 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET 20 |
Definition at line 3090 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_INPUT_DISABLE_44_BIT 7 |
Definition at line 3084 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_INVERT_44_BIT 0 |
Definition at line 3077 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_KEEPER_EN_44_BIT 4 |
Definition at line 3081 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_OD_EN_44_BIT 6 |
Definition at line 3083 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_PULL_EN_44_BIT 2 |
Definition at line 3079 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_PULL_SELECT_44_BIT 3 |
Definition at line 3080 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_REG_OFFSET 0x5f0 |
Definition at line 3075 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_REG_RESVAL 0x0u |
Definition at line 3076 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_SCHMITT_EN_44_BIT 5 |
Definition at line 3082 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_MASK, .index = PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET }) |
Definition at line 3087 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_MASK 0x3u |
Definition at line 3085 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET 16 |
Definition at line 3086 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_44_VIRTUAL_OD_EN_44_BIT 1 |
Definition at line 3078 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK, .index = PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET }) |
Definition at line 3111 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK 0xfu |
Definition at line 3109 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET 20 |
Definition at line 3110 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_INPUT_DISABLE_45_BIT 7 |
Definition at line 3104 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_INVERT_45_BIT 0 |
Definition at line 3097 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_KEEPER_EN_45_BIT 4 |
Definition at line 3101 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_OD_EN_45_BIT 6 |
Definition at line 3103 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_PULL_EN_45_BIT 2 |
Definition at line 3099 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_PULL_SELECT_45_BIT 3 |
Definition at line 3100 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_REG_OFFSET 0x5f4 |
Definition at line 3095 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_REG_RESVAL 0x0u |
Definition at line 3096 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_SCHMITT_EN_45_BIT 5 |
Definition at line 3102 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_MASK, .index = PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET }) |
Definition at line 3107 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_MASK 0x3u |
Definition at line 3105 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET 16 |
Definition at line 3106 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_45_VIRTUAL_OD_EN_45_BIT 1 |
Definition at line 3098 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK, .index = PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET }) |
Definition at line 3131 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK 0xfu |
Definition at line 3129 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET 20 |
Definition at line 3130 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_INPUT_DISABLE_46_BIT 7 |
Definition at line 3124 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_INVERT_46_BIT 0 |
Definition at line 3117 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_KEEPER_EN_46_BIT 4 |
Definition at line 3121 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_OD_EN_46_BIT 6 |
Definition at line 3123 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_PULL_EN_46_BIT 2 |
Definition at line 3119 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_PULL_SELECT_46_BIT 3 |
Definition at line 3120 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_REG_OFFSET 0x5f8 |
Definition at line 3115 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_REG_RESVAL 0x0u |
Definition at line 3116 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_SCHMITT_EN_46_BIT 5 |
Definition at line 3122 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_MASK, .index = PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET }) |
Definition at line 3127 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_MASK 0x3u |
Definition at line 3125 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET 16 |
Definition at line 3126 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_46_VIRTUAL_OD_EN_46_BIT 1 |
Definition at line 3118 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET }) |
Definition at line 2291 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xfu |
Definition at line 2289 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20 |
Definition at line 2290 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_INPUT_DISABLE_4_BIT 7 |
Definition at line 2284 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_INVERT_4_BIT 0 |
Definition at line 2277 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4 |
Definition at line 2281 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_OD_EN_4_BIT 6 |
Definition at line 2283 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_PULL_EN_4_BIT 2 |
Definition at line 2279 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3 |
Definition at line 2280 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_REG_OFFSET 0x550 |
Definition at line 2275 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_REG_RESVAL 0x0u |
Definition at line 2276 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5 |
Definition at line 2282 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET }) |
Definition at line 2287 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3u |
Definition at line 2285 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16 |
Definition at line 2286 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1 |
Definition at line 2278 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET }) |
Definition at line 2311 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xfu |
Definition at line 2309 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20 |
Definition at line 2310 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_INPUT_DISABLE_5_BIT 7 |
Definition at line 2304 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_INVERT_5_BIT 0 |
Definition at line 2297 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4 |
Definition at line 2301 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_OD_EN_5_BIT 6 |
Definition at line 2303 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_PULL_EN_5_BIT 2 |
Definition at line 2299 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3 |
Definition at line 2300 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_REG_OFFSET 0x554 |
Definition at line 2295 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_REG_RESVAL 0x0u |
Definition at line 2296 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5 |
Definition at line 2302 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET }) |
Definition at line 2307 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3u |
Definition at line 2305 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16 |
Definition at line 2306 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1 |
Definition at line 2298 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET }) |
Definition at line 2331 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xfu |
Definition at line 2329 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20 |
Definition at line 2330 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_INPUT_DISABLE_6_BIT 7 |
Definition at line 2324 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_INVERT_6_BIT 0 |
Definition at line 2317 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4 |
Definition at line 2321 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_OD_EN_6_BIT 6 |
Definition at line 2323 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_PULL_EN_6_BIT 2 |
Definition at line 2319 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3 |
Definition at line 2320 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_REG_OFFSET 0x558 |
Definition at line 2315 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_REG_RESVAL 0x0u |
Definition at line 2316 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5 |
Definition at line 2322 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET }) |
Definition at line 2327 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3u |
Definition at line 2325 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16 |
Definition at line 2326 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1 |
Definition at line 2318 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET }) |
Definition at line 2351 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xfu |
Definition at line 2349 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20 |
Definition at line 2350 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_INPUT_DISABLE_7_BIT 7 |
Definition at line 2344 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_INVERT_7_BIT 0 |
Definition at line 2337 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4 |
Definition at line 2341 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_OD_EN_7_BIT 6 |
Definition at line 2343 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_PULL_EN_7_BIT 2 |
Definition at line 2339 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3 |
Definition at line 2340 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_REG_OFFSET 0x55c |
Definition at line 2335 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_REG_RESVAL 0x0u |
Definition at line 2336 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5 |
Definition at line 2342 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET }) |
Definition at line 2347 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3u |
Definition at line 2345 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16 |
Definition at line 2346 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1 |
Definition at line 2338 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET }) |
Definition at line 2371 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xfu |
Definition at line 2369 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20 |
Definition at line 2370 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_INPUT_DISABLE_8_BIT 7 |
Definition at line 2364 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_INVERT_8_BIT 0 |
Definition at line 2357 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4 |
Definition at line 2361 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_OD_EN_8_BIT 6 |
Definition at line 2363 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_PULL_EN_8_BIT 2 |
Definition at line 2359 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3 |
Definition at line 2360 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_REG_OFFSET 0x560 |
Definition at line 2355 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_REG_RESVAL 0x0u |
Definition at line 2356 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5 |
Definition at line 2362 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET }) |
Definition at line 2367 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3u |
Definition at line 2365 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16 |
Definition at line 2366 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1 |
Definition at line 2358 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET }) |
Definition at line 2391 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xfu |
Definition at line 2389 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20 |
Definition at line 2390 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_INPUT_DISABLE_9_BIT 7 |
Definition at line 2384 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_INVERT_9_BIT 0 |
Definition at line 2377 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4 |
Definition at line 2381 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_OD_EN_9_BIT 6 |
Definition at line 2383 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_PULL_EN_9_BIT 2 |
Definition at line 2379 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3 |
Definition at line 2380 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_REG_OFFSET 0x564 |
Definition at line 2375 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_REG_RESVAL 0x0u |
Definition at line 2376 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5 |
Definition at line 2382 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET }) |
Definition at line 2387 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3u |
Definition at line 2385 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16 |
Definition at line 2386 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1 |
Definition at line 2378 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4 |
Definition at line 2189 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_INPUT_DISABLE_FIELD_WIDTH 1 |
Definition at line 2187 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_INVERT_FIELD_WIDTH 1 |
Definition at line 2180 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1 |
Definition at line 2184 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_MULTIREG_COUNT 47 |
Definition at line 2190 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1 |
Definition at line 2186 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1 |
Definition at line 2182 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1 |
Definition at line 2183 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0 |
Definition at line 1947 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0x484 |
Definition at line 1945 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1u |
Definition at line 1946 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0 |
Definition at line 1997 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0x4ac |
Definition at line 1995 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1u |
Definition at line 1996 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0 |
Definition at line 2002 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0x4b0 |
Definition at line 2000 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1u |
Definition at line 2001 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_12_EN_12_BIT 0 |
Definition at line 2007 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_12_REG_OFFSET 0x4b4 |
Definition at line 2005 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_12_REG_RESVAL 0x1u |
Definition at line 2006 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_13_EN_13_BIT 0 |
Definition at line 2012 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_13_REG_OFFSET 0x4b8 |
Definition at line 2010 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_13_REG_RESVAL 0x1u |
Definition at line 2011 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_14_EN_14_BIT 0 |
Definition at line 2017 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_14_REG_OFFSET 0x4bc |
Definition at line 2015 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_14_REG_RESVAL 0x1u |
Definition at line 2016 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_15_EN_15_BIT 0 |
Definition at line 2022 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_15_REG_OFFSET 0x4c0 |
Definition at line 2020 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_15_REG_RESVAL 0x1u |
Definition at line 2021 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_16_EN_16_BIT 0 |
Definition at line 2027 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_16_REG_OFFSET 0x4c4 |
Definition at line 2025 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_16_REG_RESVAL 0x1u |
Definition at line 2026 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_17_EN_17_BIT 0 |
Definition at line 2032 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_17_REG_OFFSET 0x4c8 |
Definition at line 2030 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_17_REG_RESVAL 0x1u |
Definition at line 2031 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_18_EN_18_BIT 0 |
Definition at line 2037 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_18_REG_OFFSET 0x4cc |
Definition at line 2035 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_18_REG_RESVAL 0x1u |
Definition at line 2036 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_19_EN_19_BIT 0 |
Definition at line 2042 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_19_REG_OFFSET 0x4d0 |
Definition at line 2040 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_19_REG_RESVAL 0x1u |
Definition at line 2041 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0 |
Definition at line 1952 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0x488 |
Definition at line 1950 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1u |
Definition at line 1951 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_20_EN_20_BIT 0 |
Definition at line 2047 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_20_REG_OFFSET 0x4d4 |
Definition at line 2045 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_20_REG_RESVAL 0x1u |
Definition at line 2046 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_21_EN_21_BIT 0 |
Definition at line 2052 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_21_REG_OFFSET 0x4d8 |
Definition at line 2050 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_21_REG_RESVAL 0x1u |
Definition at line 2051 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_22_EN_22_BIT 0 |
Definition at line 2057 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_22_REG_OFFSET 0x4dc |
Definition at line 2055 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_22_REG_RESVAL 0x1u |
Definition at line 2056 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_23_EN_23_BIT 0 |
Definition at line 2062 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_23_REG_OFFSET 0x4e0 |
Definition at line 2060 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_23_REG_RESVAL 0x1u |
Definition at line 2061 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_24_EN_24_BIT 0 |
Definition at line 2067 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_24_REG_OFFSET 0x4e4 |
Definition at line 2065 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_24_REG_RESVAL 0x1u |
Definition at line 2066 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_25_EN_25_BIT 0 |
Definition at line 2072 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_25_REG_OFFSET 0x4e8 |
Definition at line 2070 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_25_REG_RESVAL 0x1u |
Definition at line 2071 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_26_EN_26_BIT 0 |
Definition at line 2077 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_26_REG_OFFSET 0x4ec |
Definition at line 2075 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_26_REG_RESVAL 0x1u |
Definition at line 2076 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_27_EN_27_BIT 0 |
Definition at line 2082 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_27_REG_OFFSET 0x4f0 |
Definition at line 2080 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_27_REG_RESVAL 0x1u |
Definition at line 2081 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_28_EN_28_BIT 0 |
Definition at line 2087 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_28_REG_OFFSET 0x4f4 |
Definition at line 2085 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_28_REG_RESVAL 0x1u |
Definition at line 2086 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_29_EN_29_BIT 0 |
Definition at line 2092 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_29_REG_OFFSET 0x4f8 |
Definition at line 2090 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_29_REG_RESVAL 0x1u |
Definition at line 2091 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0 |
Definition at line 1957 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0x48c |
Definition at line 1955 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1u |
Definition at line 1956 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_30_EN_30_BIT 0 |
Definition at line 2097 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_30_REG_OFFSET 0x4fc |
Definition at line 2095 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_30_REG_RESVAL 0x1u |
Definition at line 2096 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_31_EN_31_BIT 0 |
Definition at line 2102 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_31_REG_OFFSET 0x500 |
Definition at line 2100 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_31_REG_RESVAL 0x1u |
Definition at line 2101 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_32_EN_32_BIT 0 |
Definition at line 2107 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_32_REG_OFFSET 0x504 |
Definition at line 2105 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_32_REG_RESVAL 0x1u |
Definition at line 2106 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_33_EN_33_BIT 0 |
Definition at line 2112 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_33_REG_OFFSET 0x508 |
Definition at line 2110 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_33_REG_RESVAL 0x1u |
Definition at line 2111 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_34_EN_34_BIT 0 |
Definition at line 2117 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_34_REG_OFFSET 0x50c |
Definition at line 2115 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_34_REG_RESVAL 0x1u |
Definition at line 2116 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_35_EN_35_BIT 0 |
Definition at line 2122 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_35_REG_OFFSET 0x510 |
Definition at line 2120 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_35_REG_RESVAL 0x1u |
Definition at line 2121 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_36_EN_36_BIT 0 |
Definition at line 2127 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_36_REG_OFFSET 0x514 |
Definition at line 2125 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_36_REG_RESVAL 0x1u |
Definition at line 2126 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_37_EN_37_BIT 0 |
Definition at line 2132 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_37_REG_OFFSET 0x518 |
Definition at line 2130 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_37_REG_RESVAL 0x1u |
Definition at line 2131 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_38_EN_38_BIT 0 |
Definition at line 2137 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_38_REG_OFFSET 0x51c |
Definition at line 2135 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_38_REG_RESVAL 0x1u |
Definition at line 2136 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_39_EN_39_BIT 0 |
Definition at line 2142 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_39_REG_OFFSET 0x520 |
Definition at line 2140 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_39_REG_RESVAL 0x1u |
Definition at line 2141 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0 |
Definition at line 1962 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0x490 |
Definition at line 1960 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1u |
Definition at line 1961 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_40_EN_40_BIT 0 |
Definition at line 2147 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_40_REG_OFFSET 0x524 |
Definition at line 2145 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_40_REG_RESVAL 0x1u |
Definition at line 2146 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_41_EN_41_BIT 0 |
Definition at line 2152 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_41_REG_OFFSET 0x528 |
Definition at line 2150 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_41_REG_RESVAL 0x1u |
Definition at line 2151 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_42_EN_42_BIT 0 |
Definition at line 2157 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_42_REG_OFFSET 0x52c |
Definition at line 2155 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_42_REG_RESVAL 0x1u |
Definition at line 2156 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_43_EN_43_BIT 0 |
Definition at line 2162 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_43_REG_OFFSET 0x530 |
Definition at line 2160 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_43_REG_RESVAL 0x1u |
Definition at line 2161 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_44_EN_44_BIT 0 |
Definition at line 2167 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_44_REG_OFFSET 0x534 |
Definition at line 2165 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_44_REG_RESVAL 0x1u |
Definition at line 2166 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_45_EN_45_BIT 0 |
Definition at line 2172 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_45_REG_OFFSET 0x538 |
Definition at line 2170 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_45_REG_RESVAL 0x1u |
Definition at line 2171 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_46_EN_46_BIT 0 |
Definition at line 2177 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_46_REG_OFFSET 0x53c |
Definition at line 2175 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_46_REG_RESVAL 0x1u |
Definition at line 2176 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0 |
Definition at line 1967 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0x494 |
Definition at line 1965 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1u |
Definition at line 1966 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0 |
Definition at line 1972 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0x498 |
Definition at line 1970 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1u |
Definition at line 1971 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0 |
Definition at line 1977 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0x49c |
Definition at line 1975 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1u |
Definition at line 1976 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0 |
Definition at line 1982 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0x4a0 |
Definition at line 1980 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1u |
Definition at line 1981 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0 |
Definition at line 1987 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0x4a4 |
Definition at line 1985 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1u |
Definition at line 1986 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0 |
Definition at line 1992 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0x4a8 |
Definition at line 1990 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1u |
Definition at line 1991 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1 |
Definition at line 1941 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 47 |
Definition at line 1942 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1 |
Definition at line 2185 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2 |
Definition at line 2188 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1 |
Definition at line 2181 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_0_EN_0_BIT 0 |
Definition at line 3860 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_0_REG_OFFSET 0x740 |
Definition at line 3858 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0u |
Definition at line 3859 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_10_EN_10_BIT 0 |
Definition at line 3910 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_10_REG_OFFSET 0x768 |
Definition at line 3908 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0u |
Definition at line 3909 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_11_EN_11_BIT 0 |
Definition at line 3915 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_11_REG_OFFSET 0x76c |
Definition at line 3913 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0u |
Definition at line 3914 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_12_EN_12_BIT 0 |
Definition at line 3920 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_12_REG_OFFSET 0x770 |
Definition at line 3918 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_12_REG_RESVAL 0x0u |
Definition at line 3919 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_13_EN_13_BIT 0 |
Definition at line 3925 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_13_REG_OFFSET 0x774 |
Definition at line 3923 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_13_REG_RESVAL 0x0u |
Definition at line 3924 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_14_EN_14_BIT 0 |
Definition at line 3930 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_14_REG_OFFSET 0x778 |
Definition at line 3928 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_14_REG_RESVAL 0x0u |
Definition at line 3929 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_15_EN_15_BIT 0 |
Definition at line 3935 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_15_REG_OFFSET 0x77c |
Definition at line 3933 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_15_REG_RESVAL 0x0u |
Definition at line 3934 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_16_EN_16_BIT 0 |
Definition at line 3940 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_16_REG_OFFSET 0x780 |
Definition at line 3938 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_16_REG_RESVAL 0x0u |
Definition at line 3939 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_17_EN_17_BIT 0 |
Definition at line 3945 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_17_REG_OFFSET 0x784 |
Definition at line 3943 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_17_REG_RESVAL 0x0u |
Definition at line 3944 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_18_EN_18_BIT 0 |
Definition at line 3950 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_18_REG_OFFSET 0x788 |
Definition at line 3948 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_18_REG_RESVAL 0x0u |
Definition at line 3949 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_19_EN_19_BIT 0 |
Definition at line 3955 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_19_REG_OFFSET 0x78c |
Definition at line 3953 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_19_REG_RESVAL 0x0u |
Definition at line 3954 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_1_EN_1_BIT 0 |
Definition at line 3865 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_1_REG_OFFSET 0x744 |
Definition at line 3863 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0u |
Definition at line 3864 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_20_EN_20_BIT 0 |
Definition at line 3960 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_20_REG_OFFSET 0x790 |
Definition at line 3958 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_20_REG_RESVAL 0x0u |
Definition at line 3959 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_21_EN_21_BIT 0 |
Definition at line 3965 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_21_REG_OFFSET 0x794 |
Definition at line 3963 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_21_REG_RESVAL 0x0u |
Definition at line 3964 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_22_EN_22_BIT 0 |
Definition at line 3970 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_22_REG_OFFSET 0x798 |
Definition at line 3968 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_22_REG_RESVAL 0x0u |
Definition at line 3969 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_23_EN_23_BIT 0 |
Definition at line 3975 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_23_REG_OFFSET 0x79c |
Definition at line 3973 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_23_REG_RESVAL 0x0u |
Definition at line 3974 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_24_EN_24_BIT 0 |
Definition at line 3980 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_24_REG_OFFSET 0x7a0 |
Definition at line 3978 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_24_REG_RESVAL 0x0u |
Definition at line 3979 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_25_EN_25_BIT 0 |
Definition at line 3985 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_25_REG_OFFSET 0x7a4 |
Definition at line 3983 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_25_REG_RESVAL 0x0u |
Definition at line 3984 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_26_EN_26_BIT 0 |
Definition at line 3990 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_26_REG_OFFSET 0x7a8 |
Definition at line 3988 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_26_REG_RESVAL 0x0u |
Definition at line 3989 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_27_EN_27_BIT 0 |
Definition at line 3995 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_27_REG_OFFSET 0x7ac |
Definition at line 3993 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_27_REG_RESVAL 0x0u |
Definition at line 3994 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_28_EN_28_BIT 0 |
Definition at line 4000 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_28_REG_OFFSET 0x7b0 |
Definition at line 3998 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_28_REG_RESVAL 0x0u |
Definition at line 3999 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_29_EN_29_BIT 0 |
Definition at line 4005 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_29_REG_OFFSET 0x7b4 |
Definition at line 4003 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_29_REG_RESVAL 0x0u |
Definition at line 4004 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_2_EN_2_BIT 0 |
Definition at line 3870 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_2_REG_OFFSET 0x748 |
Definition at line 3868 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0u |
Definition at line 3869 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_30_EN_30_BIT 0 |
Definition at line 4010 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_30_REG_OFFSET 0x7b8 |
Definition at line 4008 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_30_REG_RESVAL 0x0u |
Definition at line 4009 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_31_EN_31_BIT 0 |
Definition at line 4015 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_31_REG_OFFSET 0x7bc |
Definition at line 4013 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_31_REG_RESVAL 0x0u |
Definition at line 4014 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_32_EN_32_BIT 0 |
Definition at line 4020 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_32_REG_OFFSET 0x7c0 |
Definition at line 4018 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_32_REG_RESVAL 0x0u |
Definition at line 4019 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_33_EN_33_BIT 0 |
Definition at line 4025 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_33_REG_OFFSET 0x7c4 |
Definition at line 4023 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_33_REG_RESVAL 0x0u |
Definition at line 4024 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_34_EN_34_BIT 0 |
Definition at line 4030 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_34_REG_OFFSET 0x7c8 |
Definition at line 4028 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_34_REG_RESVAL 0x0u |
Definition at line 4029 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_35_EN_35_BIT 0 |
Definition at line 4035 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_35_REG_OFFSET 0x7cc |
Definition at line 4033 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_35_REG_RESVAL 0x0u |
Definition at line 4034 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_36_EN_36_BIT 0 |
Definition at line 4040 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_36_REG_OFFSET 0x7d0 |
Definition at line 4038 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_36_REG_RESVAL 0x0u |
Definition at line 4039 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_37_EN_37_BIT 0 |
Definition at line 4045 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_37_REG_OFFSET 0x7d4 |
Definition at line 4043 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_37_REG_RESVAL 0x0u |
Definition at line 4044 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_38_EN_38_BIT 0 |
Definition at line 4050 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_38_REG_OFFSET 0x7d8 |
Definition at line 4048 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_38_REG_RESVAL 0x0u |
Definition at line 4049 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_39_EN_39_BIT 0 |
Definition at line 4055 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_39_REG_OFFSET 0x7dc |
Definition at line 4053 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_39_REG_RESVAL 0x0u |
Definition at line 4054 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_3_EN_3_BIT 0 |
Definition at line 3875 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_3_REG_OFFSET 0x74c |
Definition at line 3873 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0u |
Definition at line 3874 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_40_EN_40_BIT 0 |
Definition at line 4060 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_40_REG_OFFSET 0x7e0 |
Definition at line 4058 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_40_REG_RESVAL 0x0u |
Definition at line 4059 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_41_EN_41_BIT 0 |
Definition at line 4065 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_41_REG_OFFSET 0x7e4 |
Definition at line 4063 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_41_REG_RESVAL 0x0u |
Definition at line 4064 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_42_EN_42_BIT 0 |
Definition at line 4070 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_42_REG_OFFSET 0x7e8 |
Definition at line 4068 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_42_REG_RESVAL 0x0u |
Definition at line 4069 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_43_EN_43_BIT 0 |
Definition at line 4075 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_43_REG_OFFSET 0x7ec |
Definition at line 4073 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_43_REG_RESVAL 0x0u |
Definition at line 4074 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_44_EN_44_BIT 0 |
Definition at line 4080 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_44_REG_OFFSET 0x7f0 |
Definition at line 4078 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_44_REG_RESVAL 0x0u |
Definition at line 4079 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_45_EN_45_BIT 0 |
Definition at line 4085 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_45_REG_OFFSET 0x7f4 |
Definition at line 4083 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_45_REG_RESVAL 0x0u |
Definition at line 4084 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_46_EN_46_BIT 0 |
Definition at line 4090 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_46_REG_OFFSET 0x7f8 |
Definition at line 4088 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_46_REG_RESVAL 0x0u |
Definition at line 4089 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_4_EN_4_BIT 0 |
Definition at line 3880 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_4_REG_OFFSET 0x750 |
Definition at line 3878 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0u |
Definition at line 3879 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_5_EN_5_BIT 0 |
Definition at line 3885 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_5_REG_OFFSET 0x754 |
Definition at line 3883 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0u |
Definition at line 3884 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_6_EN_6_BIT 0 |
Definition at line 3890 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_6_REG_OFFSET 0x758 |
Definition at line 3888 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0u |
Definition at line 3889 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_7_EN_7_BIT 0 |
Definition at line 3895 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_7_REG_OFFSET 0x75c |
Definition at line 3893 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0u |
Definition at line 3894 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_8_EN_8_BIT 0 |
Definition at line 3900 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_8_REG_OFFSET 0x760 |
Definition at line 3898 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0u |
Definition at line 3899 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_9_EN_9_BIT 0 |
Definition at line 3905 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_9_REG_OFFSET 0x764 |
Definition at line 3903 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0u |
Definition at line 3904 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1 |
Definition at line 3854 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_EN_MULTIREG_COUNT 47 |
Definition at line 3855 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET }) |
Definition at line 4101 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3u |
Definition at line 4099 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0 |
Definition at line 4100 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2 |
Definition at line 4105 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3 |
Definition at line 4106 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1 |
Definition at line 4104 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0 |
Definition at line 4103 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x7fc |
Definition at line 4097 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2u |
Definition at line 4098 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET }) |
Definition at line 4185 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3u |
Definition at line 4183 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0 |
Definition at line 4184 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x824 |
Definition at line 4181 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2u |
Definition at line 4182 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET }) |
Definition at line 4193 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3u |
Definition at line 4191 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0 |
Definition at line 4192 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x828 |
Definition at line 4189 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2u |
Definition at line 4190 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET }) |
Definition at line 4201 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_MASK 0x3u |
Definition at line 4199 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET 0 |
Definition at line 4200 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_12_REG_OFFSET 0x82c |
Definition at line 4197 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_12_REG_RESVAL 0x2u |
Definition at line 4198 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET }) |
Definition at line 4209 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_MASK 0x3u |
Definition at line 4207 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET 0 |
Definition at line 4208 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_13_REG_OFFSET 0x830 |
Definition at line 4205 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_13_REG_RESVAL 0x2u |
Definition at line 4206 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET }) |
Definition at line 4217 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_MASK 0x3u |
Definition at line 4215 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET 0 |
Definition at line 4216 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_14_REG_OFFSET 0x834 |
Definition at line 4213 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_14_REG_RESVAL 0x2u |
Definition at line 4214 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET }) |
Definition at line 4225 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_MASK 0x3u |
Definition at line 4223 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET 0 |
Definition at line 4224 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_15_REG_OFFSET 0x838 |
Definition at line 4221 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_15_REG_RESVAL 0x2u |
Definition at line 4222 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET }) |
Definition at line 4233 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_MASK 0x3u |
Definition at line 4231 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET 0 |
Definition at line 4232 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_16_REG_OFFSET 0x83c |
Definition at line 4229 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_16_REG_RESVAL 0x2u |
Definition at line 4230 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET }) |
Definition at line 4241 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_MASK 0x3u |
Definition at line 4239 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET 0 |
Definition at line 4240 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_17_REG_OFFSET 0x840 |
Definition at line 4237 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_17_REG_RESVAL 0x2u |
Definition at line 4238 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET }) |
Definition at line 4249 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_MASK 0x3u |
Definition at line 4247 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET 0 |
Definition at line 4248 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_18_REG_OFFSET 0x844 |
Definition at line 4245 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_18_REG_RESVAL 0x2u |
Definition at line 4246 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET }) |
Definition at line 4257 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_MASK 0x3u |
Definition at line 4255 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET 0 |
Definition at line 4256 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_19_REG_OFFSET 0x848 |
Definition at line 4253 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_19_REG_RESVAL 0x2u |
Definition at line 4254 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET }) |
Definition at line 4113 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3u |
Definition at line 4111 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0 |
Definition at line 4112 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x800 |
Definition at line 4109 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2u |
Definition at line 4110 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET }) |
Definition at line 4265 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_MASK 0x3u |
Definition at line 4263 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET 0 |
Definition at line 4264 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_20_REG_OFFSET 0x84c |
Definition at line 4261 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_20_REG_RESVAL 0x2u |
Definition at line 4262 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET }) |
Definition at line 4273 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_MASK 0x3u |
Definition at line 4271 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET 0 |
Definition at line 4272 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_21_REG_OFFSET 0x850 |
Definition at line 4269 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_21_REG_RESVAL 0x2u |
Definition at line 4270 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET }) |
Definition at line 4281 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_MASK 0x3u |
Definition at line 4279 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET 0 |
Definition at line 4280 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_22_REG_OFFSET 0x854 |
Definition at line 4277 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_22_REG_RESVAL 0x2u |
Definition at line 4278 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET }) |
Definition at line 4289 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_MASK 0x3u |
Definition at line 4287 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET 0 |
Definition at line 4288 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_23_REG_OFFSET 0x858 |
Definition at line 4285 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_23_REG_RESVAL 0x2u |
Definition at line 4286 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET }) |
Definition at line 4297 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_MASK 0x3u |
Definition at line 4295 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET 0 |
Definition at line 4296 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_24_REG_OFFSET 0x85c |
Definition at line 4293 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_24_REG_RESVAL 0x2u |
Definition at line 4294 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET }) |
Definition at line 4305 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_MASK 0x3u |
Definition at line 4303 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET 0 |
Definition at line 4304 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_25_REG_OFFSET 0x860 |
Definition at line 4301 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_25_REG_RESVAL 0x2u |
Definition at line 4302 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET }) |
Definition at line 4313 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_MASK 0x3u |
Definition at line 4311 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET 0 |
Definition at line 4312 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_26_REG_OFFSET 0x864 |
Definition at line 4309 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_26_REG_RESVAL 0x2u |
Definition at line 4310 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET }) |
Definition at line 4321 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_MASK 0x3u |
Definition at line 4319 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET 0 |
Definition at line 4320 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_27_REG_OFFSET 0x868 |
Definition at line 4317 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_27_REG_RESVAL 0x2u |
Definition at line 4318 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET }) |
Definition at line 4329 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_MASK 0x3u |
Definition at line 4327 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET 0 |
Definition at line 4328 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_28_REG_OFFSET 0x86c |
Definition at line 4325 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_28_REG_RESVAL 0x2u |
Definition at line 4326 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET }) |
Definition at line 4337 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_MASK 0x3u |
Definition at line 4335 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET 0 |
Definition at line 4336 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_29_REG_OFFSET 0x870 |
Definition at line 4333 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_29_REG_RESVAL 0x2u |
Definition at line 4334 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET }) |
Definition at line 4121 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3u |
Definition at line 4119 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0 |
Definition at line 4120 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x804 |
Definition at line 4117 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2u |
Definition at line 4118 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET }) |
Definition at line 4345 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_MASK 0x3u |
Definition at line 4343 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET 0 |
Definition at line 4344 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_30_REG_OFFSET 0x874 |
Definition at line 4341 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_30_REG_RESVAL 0x2u |
Definition at line 4342 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET }) |
Definition at line 4353 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_MASK 0x3u |
Definition at line 4351 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET 0 |
Definition at line 4352 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_31_REG_OFFSET 0x878 |
Definition at line 4349 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_31_REG_RESVAL 0x2u |
Definition at line 4350 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET }) |
Definition at line 4361 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_MASK 0x3u |
Definition at line 4359 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET 0 |
Definition at line 4360 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_32_REG_OFFSET 0x87c |
Definition at line 4357 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_32_REG_RESVAL 0x2u |
Definition at line 4358 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET }) |
Definition at line 4369 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_MASK 0x3u |
Definition at line 4367 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET 0 |
Definition at line 4368 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_33_REG_OFFSET 0x880 |
Definition at line 4365 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_33_REG_RESVAL 0x2u |
Definition at line 4366 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET }) |
Definition at line 4377 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_MASK 0x3u |
Definition at line 4375 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET 0 |
Definition at line 4376 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_34_REG_OFFSET 0x884 |
Definition at line 4373 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_34_REG_RESVAL 0x2u |
Definition at line 4374 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET }) |
Definition at line 4385 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_MASK 0x3u |
Definition at line 4383 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET 0 |
Definition at line 4384 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_35_REG_OFFSET 0x888 |
Definition at line 4381 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_35_REG_RESVAL 0x2u |
Definition at line 4382 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET }) |
Definition at line 4393 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_MASK 0x3u |
Definition at line 4391 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET 0 |
Definition at line 4392 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_36_REG_OFFSET 0x88c |
Definition at line 4389 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_36_REG_RESVAL 0x2u |
Definition at line 4390 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET }) |
Definition at line 4401 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_MASK 0x3u |
Definition at line 4399 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET 0 |
Definition at line 4400 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_37_REG_OFFSET 0x890 |
Definition at line 4397 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_37_REG_RESVAL 0x2u |
Definition at line 4398 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET }) |
Definition at line 4409 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_MASK 0x3u |
Definition at line 4407 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET 0 |
Definition at line 4408 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_38_REG_OFFSET 0x894 |
Definition at line 4405 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_38_REG_RESVAL 0x2u |
Definition at line 4406 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET }) |
Definition at line 4417 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_MASK 0x3u |
Definition at line 4415 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET 0 |
Definition at line 4416 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_39_REG_OFFSET 0x898 |
Definition at line 4413 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_39_REG_RESVAL 0x2u |
Definition at line 4414 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET }) |
Definition at line 4129 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3u |
Definition at line 4127 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0 |
Definition at line 4128 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x808 |
Definition at line 4125 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2u |
Definition at line 4126 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET }) |
Definition at line 4425 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_MASK 0x3u |
Definition at line 4423 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET 0 |
Definition at line 4424 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_40_REG_OFFSET 0x89c |
Definition at line 4421 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_40_REG_RESVAL 0x2u |
Definition at line 4422 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET }) |
Definition at line 4433 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_MASK 0x3u |
Definition at line 4431 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET 0 |
Definition at line 4432 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_41_REG_OFFSET 0x8a0 |
Definition at line 4429 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_41_REG_RESVAL 0x2u |
Definition at line 4430 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET }) |
Definition at line 4441 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_MASK 0x3u |
Definition at line 4439 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET 0 |
Definition at line 4440 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_42_REG_OFFSET 0x8a4 |
Definition at line 4437 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_42_REG_RESVAL 0x2u |
Definition at line 4438 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET }) |
Definition at line 4449 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_MASK 0x3u |
Definition at line 4447 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET 0 |
Definition at line 4448 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_43_REG_OFFSET 0x8a8 |
Definition at line 4445 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_43_REG_RESVAL 0x2u |
Definition at line 4446 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET }) |
Definition at line 4457 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_MASK 0x3u |
Definition at line 4455 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET 0 |
Definition at line 4456 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_44_REG_OFFSET 0x8ac |
Definition at line 4453 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_44_REG_RESVAL 0x2u |
Definition at line 4454 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET }) |
Definition at line 4465 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_MASK 0x3u |
Definition at line 4463 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET 0 |
Definition at line 4464 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_45_REG_OFFSET 0x8b0 |
Definition at line 4461 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_45_REG_RESVAL 0x2u |
Definition at line 4462 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET }) |
Definition at line 4473 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_MASK 0x3u |
Definition at line 4471 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET 0 |
Definition at line 4472 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_46_REG_OFFSET 0x8b4 |
Definition at line 4469 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_46_REG_RESVAL 0x2u |
Definition at line 4470 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET }) |
Definition at line 4137 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3u |
Definition at line 4135 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0 |
Definition at line 4136 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x80c |
Definition at line 4133 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2u |
Definition at line 4134 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET }) |
Definition at line 4145 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3u |
Definition at line 4143 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0 |
Definition at line 4144 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x810 |
Definition at line 4141 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2u |
Definition at line 4142 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET }) |
Definition at line 4153 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3u |
Definition at line 4151 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0 |
Definition at line 4152 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x814 |
Definition at line 4149 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2u |
Definition at line 4150 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET }) |
Definition at line 4161 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3u |
Definition at line 4159 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0 |
Definition at line 4160 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x818 |
Definition at line 4157 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2u |
Definition at line 4158 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET }) |
Definition at line 4169 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3u |
Definition at line 4167 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0 |
Definition at line 4168 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x81c |
Definition at line 4165 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2u |
Definition at line 4166 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET }) |
Definition at line 4177 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3u |
Definition at line 4175 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0 |
Definition at line 4176 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x820 |
Definition at line 4173 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2u |
Definition at line 4174 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_MULTIREG_COUNT 47 |
Definition at line 4094 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2 |
Definition at line 4093 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0 |
Definition at line 3621 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x684 |
Definition at line 3619 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1u |
Definition at line 3620 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0 |
Definition at line 3671 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x6ac |
Definition at line 3669 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1u |
Definition at line 3670 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0 |
Definition at line 3676 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x6b0 |
Definition at line 3674 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1u |
Definition at line 3675 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_12_EN_12_BIT 0 |
Definition at line 3681 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_12_REG_OFFSET 0x6b4 |
Definition at line 3679 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_12_REG_RESVAL 0x1u |
Definition at line 3680 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_13_EN_13_BIT 0 |
Definition at line 3686 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_13_REG_OFFSET 0x6b8 |
Definition at line 3684 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_13_REG_RESVAL 0x1u |
Definition at line 3685 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_14_EN_14_BIT 0 |
Definition at line 3691 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_14_REG_OFFSET 0x6bc |
Definition at line 3689 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_14_REG_RESVAL 0x1u |
Definition at line 3690 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_15_EN_15_BIT 0 |
Definition at line 3696 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_15_REG_OFFSET 0x6c0 |
Definition at line 3694 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_15_REG_RESVAL 0x1u |
Definition at line 3695 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_16_EN_16_BIT 0 |
Definition at line 3701 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_16_REG_OFFSET 0x6c4 |
Definition at line 3699 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_16_REG_RESVAL 0x1u |
Definition at line 3700 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_17_EN_17_BIT 0 |
Definition at line 3706 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_17_REG_OFFSET 0x6c8 |
Definition at line 3704 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_17_REG_RESVAL 0x1u |
Definition at line 3705 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_18_EN_18_BIT 0 |
Definition at line 3711 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_18_REG_OFFSET 0x6cc |
Definition at line 3709 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_18_REG_RESVAL 0x1u |
Definition at line 3710 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_19_EN_19_BIT 0 |
Definition at line 3716 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_19_REG_OFFSET 0x6d0 |
Definition at line 3714 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_19_REG_RESVAL 0x1u |
Definition at line 3715 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0 |
Definition at line 3626 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x688 |
Definition at line 3624 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1u |
Definition at line 3625 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_20_EN_20_BIT 0 |
Definition at line 3721 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_20_REG_OFFSET 0x6d4 |
Definition at line 3719 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_20_REG_RESVAL 0x1u |
Definition at line 3720 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_21_EN_21_BIT 0 |
Definition at line 3726 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_21_REG_OFFSET 0x6d8 |
Definition at line 3724 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_21_REG_RESVAL 0x1u |
Definition at line 3725 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_22_EN_22_BIT 0 |
Definition at line 3731 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_22_REG_OFFSET 0x6dc |
Definition at line 3729 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_22_REG_RESVAL 0x1u |
Definition at line 3730 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_23_EN_23_BIT 0 |
Definition at line 3736 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_23_REG_OFFSET 0x6e0 |
Definition at line 3734 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_23_REG_RESVAL 0x1u |
Definition at line 3735 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_24_EN_24_BIT 0 |
Definition at line 3741 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_24_REG_OFFSET 0x6e4 |
Definition at line 3739 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_24_REG_RESVAL 0x1u |
Definition at line 3740 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_25_EN_25_BIT 0 |
Definition at line 3746 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_25_REG_OFFSET 0x6e8 |
Definition at line 3744 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_25_REG_RESVAL 0x1u |
Definition at line 3745 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_26_EN_26_BIT 0 |
Definition at line 3751 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_26_REG_OFFSET 0x6ec |
Definition at line 3749 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_26_REG_RESVAL 0x1u |
Definition at line 3750 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_27_EN_27_BIT 0 |
Definition at line 3756 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_27_REG_OFFSET 0x6f0 |
Definition at line 3754 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_27_REG_RESVAL 0x1u |
Definition at line 3755 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_28_EN_28_BIT 0 |
Definition at line 3761 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_28_REG_OFFSET 0x6f4 |
Definition at line 3759 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_28_REG_RESVAL 0x1u |
Definition at line 3760 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_29_EN_29_BIT 0 |
Definition at line 3766 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_29_REG_OFFSET 0x6f8 |
Definition at line 3764 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_29_REG_RESVAL 0x1u |
Definition at line 3765 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0 |
Definition at line 3631 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x68c |
Definition at line 3629 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1u |
Definition at line 3630 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_30_EN_30_BIT 0 |
Definition at line 3771 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_30_REG_OFFSET 0x6fc |
Definition at line 3769 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_30_REG_RESVAL 0x1u |
Definition at line 3770 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_31_EN_31_BIT 0 |
Definition at line 3776 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_31_REG_OFFSET 0x700 |
Definition at line 3774 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_31_REG_RESVAL 0x1u |
Definition at line 3775 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_32_EN_32_BIT 0 |
Definition at line 3781 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_32_REG_OFFSET 0x704 |
Definition at line 3779 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_32_REG_RESVAL 0x1u |
Definition at line 3780 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_33_EN_33_BIT 0 |
Definition at line 3786 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_33_REG_OFFSET 0x708 |
Definition at line 3784 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_33_REG_RESVAL 0x1u |
Definition at line 3785 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_34_EN_34_BIT 0 |
Definition at line 3791 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_34_REG_OFFSET 0x70c |
Definition at line 3789 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_34_REG_RESVAL 0x1u |
Definition at line 3790 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_35_EN_35_BIT 0 |
Definition at line 3796 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_35_REG_OFFSET 0x710 |
Definition at line 3794 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_35_REG_RESVAL 0x1u |
Definition at line 3795 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_36_EN_36_BIT 0 |
Definition at line 3801 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_36_REG_OFFSET 0x714 |
Definition at line 3799 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_36_REG_RESVAL 0x1u |
Definition at line 3800 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_37_EN_37_BIT 0 |
Definition at line 3806 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_37_REG_OFFSET 0x718 |
Definition at line 3804 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_37_REG_RESVAL 0x1u |
Definition at line 3805 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_38_EN_38_BIT 0 |
Definition at line 3811 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_38_REG_OFFSET 0x71c |
Definition at line 3809 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_38_REG_RESVAL 0x1u |
Definition at line 3810 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_39_EN_39_BIT 0 |
Definition at line 3816 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_39_REG_OFFSET 0x720 |
Definition at line 3814 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_39_REG_RESVAL 0x1u |
Definition at line 3815 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0 |
Definition at line 3636 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x690 |
Definition at line 3634 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1u |
Definition at line 3635 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_40_EN_40_BIT 0 |
Definition at line 3821 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_40_REG_OFFSET 0x724 |
Definition at line 3819 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_40_REG_RESVAL 0x1u |
Definition at line 3820 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_41_EN_41_BIT 0 |
Definition at line 3826 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_41_REG_OFFSET 0x728 |
Definition at line 3824 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_41_REG_RESVAL 0x1u |
Definition at line 3825 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_42_EN_42_BIT 0 |
Definition at line 3831 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_42_REG_OFFSET 0x72c |
Definition at line 3829 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_42_REG_RESVAL 0x1u |
Definition at line 3830 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_43_EN_43_BIT 0 |
Definition at line 3836 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_43_REG_OFFSET 0x730 |
Definition at line 3834 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_43_REG_RESVAL 0x1u |
Definition at line 3835 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_44_EN_44_BIT 0 |
Definition at line 3841 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_44_REG_OFFSET 0x734 |
Definition at line 3839 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_44_REG_RESVAL 0x1u |
Definition at line 3840 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_45_EN_45_BIT 0 |
Definition at line 3846 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_45_REG_OFFSET 0x738 |
Definition at line 3844 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_45_REG_RESVAL 0x1u |
Definition at line 3845 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_46_EN_46_BIT 0 |
Definition at line 3851 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_46_REG_OFFSET 0x73c |
Definition at line 3849 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_46_REG_RESVAL 0x1u |
Definition at line 3850 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0 |
Definition at line 3641 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x694 |
Definition at line 3639 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1u |
Definition at line 3640 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0 |
Definition at line 3646 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x698 |
Definition at line 3644 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1u |
Definition at line 3645 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0 |
Definition at line 3651 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x69c |
Definition at line 3649 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1u |
Definition at line 3650 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0 |
Definition at line 3656 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x6a0 |
Definition at line 3654 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1u |
Definition at line 3655 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0 |
Definition at line 3661 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x6a4 |
Definition at line 3659 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1u |
Definition at line 3660 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0 |
Definition at line 3666 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x6a8 |
Definition at line 3664 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1u |
Definition at line 3665 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1 |
Definition at line 3615 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 47 |
Definition at line 3616 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_0_BIT 0 |
Definition at line 3561 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_10_BIT 10 |
Definition at line 3571 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_11_BIT 11 |
Definition at line 3572 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_12_BIT 12 |
Definition at line 3573 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_13_BIT 13 |
Definition at line 3574 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_14_BIT 14 |
Definition at line 3575 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_15_BIT 15 |
Definition at line 3576 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_16_BIT 16 |
Definition at line 3577 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_17_BIT 17 |
Definition at line 3578 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_18_BIT 18 |
Definition at line 3579 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_19_BIT 19 |
Definition at line 3580 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_1_BIT 1 |
Definition at line 3562 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_20_BIT 20 |
Definition at line 3581 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_21_BIT 21 |
Definition at line 3582 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_22_BIT 22 |
Definition at line 3583 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_23_BIT 23 |
Definition at line 3584 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_24_BIT 24 |
Definition at line 3585 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_25_BIT 25 |
Definition at line 3586 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_26_BIT 26 |
Definition at line 3587 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_27_BIT 27 |
Definition at line 3588 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_28_BIT 28 |
Definition at line 3589 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_29_BIT 29 |
Definition at line 3590 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_2_BIT 2 |
Definition at line 3563 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_30_BIT 30 |
Definition at line 3591 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_31_BIT 31 |
Definition at line 3592 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_3_BIT 3 |
Definition at line 3564 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_4_BIT 4 |
Definition at line 3565 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_5_BIT 5 |
Definition at line 3566 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_6_BIT 6 |
Definition at line 3567 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_7_BIT 7 |
Definition at line 3568 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_8_BIT 8 |
Definition at line 3569 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_9_BIT 9 |
Definition at line 3570 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_OFFSET 0x67c |
Definition at line 3559 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_RESVAL 0x0u |
Definition at line 3560 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_32_BIT 0 |
Definition at line 3597 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_33_BIT 1 |
Definition at line 3598 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_34_BIT 2 |
Definition at line 3599 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_35_BIT 3 |
Definition at line 3600 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_36_BIT 4 |
Definition at line 3601 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_37_BIT 5 |
Definition at line 3602 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_38_BIT 6 |
Definition at line 3603 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_39_BIT 7 |
Definition at line 3604 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_40_BIT 8 |
Definition at line 3605 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_41_BIT 9 |
Definition at line 3606 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_42_BIT 10 |
Definition at line 3607 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_43_BIT 11 |
Definition at line 3608 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_44_BIT 12 |
Definition at line 3609 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_45_BIT 13 |
Definition at line 3610 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_46_BIT 14 |
Definition at line 3611 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_REG_OFFSET 0x680 |
Definition at line 3595 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_1_REG_RESVAL 0x0u |
Definition at line 3596 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1 |
Definition at line 3555 of file pinmux_regs.h.
| #define PINMUX_MIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 2 |
Definition at line 3556 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_0_IN_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK, .index = PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET }) |
Definition at line 549 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK 0x3fu |
Definition at line 547 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET 0 |
Definition at line 548 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET 0x188 |
Definition at line 545 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_0_REG_RESVAL 0x0u |
Definition at line 546 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_10_IN_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_10_IN_10_MASK, .index = PINMUX_MIO_PERIPH_INSEL_10_IN_10_OFFSET }) |
Definition at line 629 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_10_IN_10_MASK 0x3fu |
Definition at line 627 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_10_IN_10_OFFSET 0 |
Definition at line 628 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_10_REG_OFFSET 0x1b0 |
Definition at line 625 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_10_REG_RESVAL 0x0u |
Definition at line 626 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_11_IN_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_11_IN_11_MASK, .index = PINMUX_MIO_PERIPH_INSEL_11_IN_11_OFFSET }) |
Definition at line 637 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_11_IN_11_MASK 0x3fu |
Definition at line 635 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_11_IN_11_OFFSET 0 |
Definition at line 636 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_11_REG_OFFSET 0x1b4 |
Definition at line 633 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_11_REG_RESVAL 0x0u |
Definition at line 634 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_12_IN_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_12_IN_12_MASK, .index = PINMUX_MIO_PERIPH_INSEL_12_IN_12_OFFSET }) |
Definition at line 645 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_12_IN_12_MASK 0x3fu |
Definition at line 643 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_12_IN_12_OFFSET 0 |
Definition at line 644 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_12_REG_OFFSET 0x1b8 |
Definition at line 641 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_12_REG_RESVAL 0x0u |
Definition at line 642 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_13_IN_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_13_IN_13_MASK, .index = PINMUX_MIO_PERIPH_INSEL_13_IN_13_OFFSET }) |
Definition at line 653 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_13_IN_13_MASK 0x3fu |
Definition at line 651 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_13_IN_13_OFFSET 0 |
Definition at line 652 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_13_REG_OFFSET 0x1bc |
Definition at line 649 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_13_REG_RESVAL 0x0u |
Definition at line 650 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_14_IN_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_14_IN_14_MASK, .index = PINMUX_MIO_PERIPH_INSEL_14_IN_14_OFFSET }) |
Definition at line 661 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_14_IN_14_MASK 0x3fu |
Definition at line 659 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_14_IN_14_OFFSET 0 |
Definition at line 660 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_14_REG_OFFSET 0x1c0 |
Definition at line 657 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_14_REG_RESVAL 0x0u |
Definition at line 658 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_15_IN_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_15_IN_15_MASK, .index = PINMUX_MIO_PERIPH_INSEL_15_IN_15_OFFSET }) |
Definition at line 669 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_15_IN_15_MASK 0x3fu |
Definition at line 667 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_15_IN_15_OFFSET 0 |
Definition at line 668 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_15_REG_OFFSET 0x1c4 |
Definition at line 665 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_15_REG_RESVAL 0x0u |
Definition at line 666 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_16_IN_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_16_IN_16_MASK, .index = PINMUX_MIO_PERIPH_INSEL_16_IN_16_OFFSET }) |
Definition at line 677 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_16_IN_16_MASK 0x3fu |
Definition at line 675 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_16_IN_16_OFFSET 0 |
Definition at line 676 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_16_REG_OFFSET 0x1c8 |
Definition at line 673 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_16_REG_RESVAL 0x0u |
Definition at line 674 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_17_IN_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_17_IN_17_MASK, .index = PINMUX_MIO_PERIPH_INSEL_17_IN_17_OFFSET }) |
Definition at line 685 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_17_IN_17_MASK 0x3fu |
Definition at line 683 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_17_IN_17_OFFSET 0 |
Definition at line 684 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_17_REG_OFFSET 0x1cc |
Definition at line 681 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_17_REG_RESVAL 0x0u |
Definition at line 682 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_18_IN_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_18_IN_18_MASK, .index = PINMUX_MIO_PERIPH_INSEL_18_IN_18_OFFSET }) |
Definition at line 693 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_18_IN_18_MASK 0x3fu |
Definition at line 691 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_18_IN_18_OFFSET 0 |
Definition at line 692 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_18_REG_OFFSET 0x1d0 |
Definition at line 689 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_18_REG_RESVAL 0x0u |
Definition at line 690 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_19_IN_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_19_IN_19_MASK, .index = PINMUX_MIO_PERIPH_INSEL_19_IN_19_OFFSET }) |
Definition at line 701 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_19_IN_19_MASK 0x3fu |
Definition at line 699 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_19_IN_19_OFFSET 0 |
Definition at line 700 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_19_REG_OFFSET 0x1d4 |
Definition at line 697 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_19_REG_RESVAL 0x0u |
Definition at line 698 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_1_IN_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK, .index = PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET }) |
Definition at line 557 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK 0x3fu |
Definition at line 555 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET 0 |
Definition at line 556 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_1_REG_OFFSET 0x18c |
Definition at line 553 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_1_REG_RESVAL 0x0u |
Definition at line 554 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_20_IN_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_20_IN_20_MASK, .index = PINMUX_MIO_PERIPH_INSEL_20_IN_20_OFFSET }) |
Definition at line 709 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_20_IN_20_MASK 0x3fu |
Definition at line 707 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_20_IN_20_OFFSET 0 |
Definition at line 708 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_20_REG_OFFSET 0x1d8 |
Definition at line 705 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_20_REG_RESVAL 0x0u |
Definition at line 706 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_21_IN_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_21_IN_21_MASK, .index = PINMUX_MIO_PERIPH_INSEL_21_IN_21_OFFSET }) |
Definition at line 717 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_21_IN_21_MASK 0x3fu |
Definition at line 715 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_21_IN_21_OFFSET 0 |
Definition at line 716 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_21_REG_OFFSET 0x1dc |
Definition at line 713 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_21_REG_RESVAL 0x0u |
Definition at line 714 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_22_IN_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_22_IN_22_MASK, .index = PINMUX_MIO_PERIPH_INSEL_22_IN_22_OFFSET }) |
Definition at line 725 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_22_IN_22_MASK 0x3fu |
Definition at line 723 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_22_IN_22_OFFSET 0 |
Definition at line 724 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_22_REG_OFFSET 0x1e0 |
Definition at line 721 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_22_REG_RESVAL 0x0u |
Definition at line 722 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_23_IN_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_23_IN_23_MASK, .index = PINMUX_MIO_PERIPH_INSEL_23_IN_23_OFFSET }) |
Definition at line 733 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_23_IN_23_MASK 0x3fu |
Definition at line 731 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_23_IN_23_OFFSET 0 |
Definition at line 732 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_23_REG_OFFSET 0x1e4 |
Definition at line 729 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_23_REG_RESVAL 0x0u |
Definition at line 730 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_24_IN_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_24_IN_24_MASK, .index = PINMUX_MIO_PERIPH_INSEL_24_IN_24_OFFSET }) |
Definition at line 741 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_24_IN_24_MASK 0x3fu |
Definition at line 739 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_24_IN_24_OFFSET 0 |
Definition at line 740 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_24_REG_OFFSET 0x1e8 |
Definition at line 737 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_24_REG_RESVAL 0x0u |
Definition at line 738 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_25_IN_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_25_IN_25_MASK, .index = PINMUX_MIO_PERIPH_INSEL_25_IN_25_OFFSET }) |
Definition at line 749 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_25_IN_25_MASK 0x3fu |
Definition at line 747 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_25_IN_25_OFFSET 0 |
Definition at line 748 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_25_REG_OFFSET 0x1ec |
Definition at line 745 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_25_REG_RESVAL 0x0u |
Definition at line 746 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_26_IN_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_26_IN_26_MASK, .index = PINMUX_MIO_PERIPH_INSEL_26_IN_26_OFFSET }) |
Definition at line 757 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_26_IN_26_MASK 0x3fu |
Definition at line 755 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_26_IN_26_OFFSET 0 |
Definition at line 756 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_26_REG_OFFSET 0x1f0 |
Definition at line 753 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_26_REG_RESVAL 0x0u |
Definition at line 754 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_27_IN_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_27_IN_27_MASK, .index = PINMUX_MIO_PERIPH_INSEL_27_IN_27_OFFSET }) |
Definition at line 765 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_27_IN_27_MASK 0x3fu |
Definition at line 763 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_27_IN_27_OFFSET 0 |
Definition at line 764 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_27_REG_OFFSET 0x1f4 |
Definition at line 761 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_27_REG_RESVAL 0x0u |
Definition at line 762 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_28_IN_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_28_IN_28_MASK, .index = PINMUX_MIO_PERIPH_INSEL_28_IN_28_OFFSET }) |
Definition at line 773 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_28_IN_28_MASK 0x3fu |
Definition at line 771 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_28_IN_28_OFFSET 0 |
Definition at line 772 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_28_REG_OFFSET 0x1f8 |
Definition at line 769 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_28_REG_RESVAL 0x0u |
Definition at line 770 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_29_IN_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_29_IN_29_MASK, .index = PINMUX_MIO_PERIPH_INSEL_29_IN_29_OFFSET }) |
Definition at line 781 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_29_IN_29_MASK 0x3fu |
Definition at line 779 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_29_IN_29_OFFSET 0 |
Definition at line 780 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_29_REG_OFFSET 0x1fc |
Definition at line 777 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_29_REG_RESVAL 0x0u |
Definition at line 778 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_2_IN_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK, .index = PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET }) |
Definition at line 565 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK 0x3fu |
Definition at line 563 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET 0 |
Definition at line 564 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_2_REG_OFFSET 0x190 |
Definition at line 561 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_2_REG_RESVAL 0x0u |
Definition at line 562 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_30_IN_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_30_IN_30_MASK, .index = PINMUX_MIO_PERIPH_INSEL_30_IN_30_OFFSET }) |
Definition at line 789 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_30_IN_30_MASK 0x3fu |
Definition at line 787 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_30_IN_30_OFFSET 0 |
Definition at line 788 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_30_REG_OFFSET 0x200 |
Definition at line 785 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_30_REG_RESVAL 0x0u |
Definition at line 786 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_31_IN_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_31_IN_31_MASK, .index = PINMUX_MIO_PERIPH_INSEL_31_IN_31_OFFSET }) |
Definition at line 797 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_31_IN_31_MASK 0x3fu |
Definition at line 795 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_31_IN_31_OFFSET 0 |
Definition at line 796 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_31_REG_OFFSET 0x204 |
Definition at line 793 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_31_REG_RESVAL 0x0u |
Definition at line 794 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_32_IN_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_32_IN_32_MASK, .index = PINMUX_MIO_PERIPH_INSEL_32_IN_32_OFFSET }) |
Definition at line 805 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_32_IN_32_MASK 0x3fu |
Definition at line 803 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_32_IN_32_OFFSET 0 |
Definition at line 804 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_32_REG_OFFSET 0x208 |
Definition at line 801 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_32_REG_RESVAL 0x0u |
Definition at line 802 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_33_IN_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_33_IN_33_MASK, .index = PINMUX_MIO_PERIPH_INSEL_33_IN_33_OFFSET }) |
Definition at line 813 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_33_IN_33_MASK 0x3fu |
Definition at line 811 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_33_IN_33_OFFSET 0 |
Definition at line 812 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_33_REG_OFFSET 0x20c |
Definition at line 809 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_33_REG_RESVAL 0x0u |
Definition at line 810 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_34_IN_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_34_IN_34_MASK, .index = PINMUX_MIO_PERIPH_INSEL_34_IN_34_OFFSET }) |
Definition at line 821 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_34_IN_34_MASK 0x3fu |
Definition at line 819 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_34_IN_34_OFFSET 0 |
Definition at line 820 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_34_REG_OFFSET 0x210 |
Definition at line 817 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_34_REG_RESVAL 0x0u |
Definition at line 818 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_35_IN_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_35_IN_35_MASK, .index = PINMUX_MIO_PERIPH_INSEL_35_IN_35_OFFSET }) |
Definition at line 829 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_35_IN_35_MASK 0x3fu |
Definition at line 827 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_35_IN_35_OFFSET 0 |
Definition at line 828 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_35_REG_OFFSET 0x214 |
Definition at line 825 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_35_REG_RESVAL 0x0u |
Definition at line 826 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_36_IN_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_36_IN_36_MASK, .index = PINMUX_MIO_PERIPH_INSEL_36_IN_36_OFFSET }) |
Definition at line 837 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_36_IN_36_MASK 0x3fu |
Definition at line 835 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_36_IN_36_OFFSET 0 |
Definition at line 836 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_36_REG_OFFSET 0x218 |
Definition at line 833 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_36_REG_RESVAL 0x0u |
Definition at line 834 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_37_IN_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_37_IN_37_MASK, .index = PINMUX_MIO_PERIPH_INSEL_37_IN_37_OFFSET }) |
Definition at line 845 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_37_IN_37_MASK 0x3fu |
Definition at line 843 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_37_IN_37_OFFSET 0 |
Definition at line 844 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_37_REG_OFFSET 0x21c |
Definition at line 841 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_37_REG_RESVAL 0x0u |
Definition at line 842 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_38_IN_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_38_IN_38_MASK, .index = PINMUX_MIO_PERIPH_INSEL_38_IN_38_OFFSET }) |
Definition at line 853 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_38_IN_38_MASK 0x3fu |
Definition at line 851 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_38_IN_38_OFFSET 0 |
Definition at line 852 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_38_REG_OFFSET 0x220 |
Definition at line 849 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_38_REG_RESVAL 0x0u |
Definition at line 850 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_39_IN_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_39_IN_39_MASK, .index = PINMUX_MIO_PERIPH_INSEL_39_IN_39_OFFSET }) |
Definition at line 861 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_39_IN_39_MASK 0x3fu |
Definition at line 859 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_39_IN_39_OFFSET 0 |
Definition at line 860 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_39_REG_OFFSET 0x224 |
Definition at line 857 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_39_REG_RESVAL 0x0u |
Definition at line 858 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_3_IN_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK, .index = PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET }) |
Definition at line 573 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK 0x3fu |
Definition at line 571 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET 0 |
Definition at line 572 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_3_REG_OFFSET 0x194 |
Definition at line 569 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_3_REG_RESVAL 0x0u |
Definition at line 570 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_40_IN_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_40_IN_40_MASK, .index = PINMUX_MIO_PERIPH_INSEL_40_IN_40_OFFSET }) |
Definition at line 869 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_40_IN_40_MASK 0x3fu |
Definition at line 867 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_40_IN_40_OFFSET 0 |
Definition at line 868 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_40_REG_OFFSET 0x228 |
Definition at line 865 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_40_REG_RESVAL 0x0u |
Definition at line 866 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_41_IN_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_41_IN_41_MASK, .index = PINMUX_MIO_PERIPH_INSEL_41_IN_41_OFFSET }) |
Definition at line 877 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_41_IN_41_MASK 0x3fu |
Definition at line 875 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_41_IN_41_OFFSET 0 |
Definition at line 876 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_41_REG_OFFSET 0x22c |
Definition at line 873 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_41_REG_RESVAL 0x0u |
Definition at line 874 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_42_IN_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_42_IN_42_MASK, .index = PINMUX_MIO_PERIPH_INSEL_42_IN_42_OFFSET }) |
Definition at line 885 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_42_IN_42_MASK 0x3fu |
Definition at line 883 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_42_IN_42_OFFSET 0 |
Definition at line 884 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_42_REG_OFFSET 0x230 |
Definition at line 881 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_42_REG_RESVAL 0x0u |
Definition at line 882 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_43_IN_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_43_IN_43_MASK, .index = PINMUX_MIO_PERIPH_INSEL_43_IN_43_OFFSET }) |
Definition at line 893 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_43_IN_43_MASK 0x3fu |
Definition at line 891 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_43_IN_43_OFFSET 0 |
Definition at line 892 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_43_REG_OFFSET 0x234 |
Definition at line 889 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_43_REG_RESVAL 0x0u |
Definition at line 890 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_44_IN_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_44_IN_44_MASK, .index = PINMUX_MIO_PERIPH_INSEL_44_IN_44_OFFSET }) |
Definition at line 901 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_44_IN_44_MASK 0x3fu |
Definition at line 899 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_44_IN_44_OFFSET 0 |
Definition at line 900 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_44_REG_OFFSET 0x238 |
Definition at line 897 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_44_REG_RESVAL 0x0u |
Definition at line 898 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_45_IN_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_45_IN_45_MASK, .index = PINMUX_MIO_PERIPH_INSEL_45_IN_45_OFFSET }) |
Definition at line 909 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_45_IN_45_MASK 0x3fu |
Definition at line 907 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_45_IN_45_OFFSET 0 |
Definition at line 908 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_45_REG_OFFSET 0x23c |
Definition at line 905 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_45_REG_RESVAL 0x0u |
Definition at line 906 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_46_IN_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_46_IN_46_MASK, .index = PINMUX_MIO_PERIPH_INSEL_46_IN_46_OFFSET }) |
Definition at line 917 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_46_IN_46_MASK 0x3fu |
Definition at line 915 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_46_IN_46_OFFSET 0 |
Definition at line 916 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_46_REG_OFFSET 0x240 |
Definition at line 913 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_46_REG_RESVAL 0x0u |
Definition at line 914 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_47_IN_47_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_47_IN_47_MASK, .index = PINMUX_MIO_PERIPH_INSEL_47_IN_47_OFFSET }) |
Definition at line 925 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_47_IN_47_MASK 0x3fu |
Definition at line 923 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_47_IN_47_OFFSET 0 |
Definition at line 924 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_47_REG_OFFSET 0x244 |
Definition at line 921 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_47_REG_RESVAL 0x0u |
Definition at line 922 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_48_IN_48_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_48_IN_48_MASK, .index = PINMUX_MIO_PERIPH_INSEL_48_IN_48_OFFSET }) |
Definition at line 933 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_48_IN_48_MASK 0x3fu |
Definition at line 931 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_48_IN_48_OFFSET 0 |
Definition at line 932 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_48_REG_OFFSET 0x248 |
Definition at line 929 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_48_REG_RESVAL 0x0u |
Definition at line 930 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_49_IN_49_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_49_IN_49_MASK, .index = PINMUX_MIO_PERIPH_INSEL_49_IN_49_OFFSET }) |
Definition at line 941 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_49_IN_49_MASK 0x3fu |
Definition at line 939 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_49_IN_49_OFFSET 0 |
Definition at line 940 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_49_REG_OFFSET 0x24c |
Definition at line 937 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_49_REG_RESVAL 0x0u |
Definition at line 938 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_4_IN_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_4_IN_4_MASK, .index = PINMUX_MIO_PERIPH_INSEL_4_IN_4_OFFSET }) |
Definition at line 581 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_4_IN_4_MASK 0x3fu |
Definition at line 579 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_4_IN_4_OFFSET 0 |
Definition at line 580 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_4_REG_OFFSET 0x198 |
Definition at line 577 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_4_REG_RESVAL 0x0u |
Definition at line 578 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_50_IN_50_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_50_IN_50_MASK, .index = PINMUX_MIO_PERIPH_INSEL_50_IN_50_OFFSET }) |
Definition at line 949 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_50_IN_50_MASK 0x3fu |
Definition at line 947 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_50_IN_50_OFFSET 0 |
Definition at line 948 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_50_REG_OFFSET 0x250 |
Definition at line 945 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_50_REG_RESVAL 0x0u |
Definition at line 946 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_51_IN_51_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_51_IN_51_MASK, .index = PINMUX_MIO_PERIPH_INSEL_51_IN_51_OFFSET }) |
Definition at line 957 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_51_IN_51_MASK 0x3fu |
Definition at line 955 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_51_IN_51_OFFSET 0 |
Definition at line 956 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_51_REG_OFFSET 0x254 |
Definition at line 953 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_51_REG_RESVAL 0x0u |
Definition at line 954 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_52_IN_52_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_52_IN_52_MASK, .index = PINMUX_MIO_PERIPH_INSEL_52_IN_52_OFFSET }) |
Definition at line 965 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_52_IN_52_MASK 0x3fu |
Definition at line 963 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_52_IN_52_OFFSET 0 |
Definition at line 964 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_52_REG_OFFSET 0x258 |
Definition at line 961 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_52_REG_RESVAL 0x0u |
Definition at line 962 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_53_IN_53_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_53_IN_53_MASK, .index = PINMUX_MIO_PERIPH_INSEL_53_IN_53_OFFSET }) |
Definition at line 973 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_53_IN_53_MASK 0x3fu |
Definition at line 971 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_53_IN_53_OFFSET 0 |
Definition at line 972 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_53_REG_OFFSET 0x25c |
Definition at line 969 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_53_REG_RESVAL 0x0u |
Definition at line 970 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_54_IN_54_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_54_IN_54_MASK, .index = PINMUX_MIO_PERIPH_INSEL_54_IN_54_OFFSET }) |
Definition at line 981 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_54_IN_54_MASK 0x3fu |
Definition at line 979 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_54_IN_54_OFFSET 0 |
Definition at line 980 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_54_REG_OFFSET 0x260 |
Definition at line 977 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_54_REG_RESVAL 0x0u |
Definition at line 978 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_55_IN_55_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_55_IN_55_MASK, .index = PINMUX_MIO_PERIPH_INSEL_55_IN_55_OFFSET }) |
Definition at line 989 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_55_IN_55_MASK 0x3fu |
Definition at line 987 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_55_IN_55_OFFSET 0 |
Definition at line 988 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_55_REG_OFFSET 0x264 |
Definition at line 985 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_55_REG_RESVAL 0x0u |
Definition at line 986 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_56_IN_56_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_56_IN_56_MASK, .index = PINMUX_MIO_PERIPH_INSEL_56_IN_56_OFFSET }) |
Definition at line 997 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_56_IN_56_MASK 0x3fu |
Definition at line 995 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_56_IN_56_OFFSET 0 |
Definition at line 996 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_56_REG_OFFSET 0x268 |
Definition at line 993 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_56_REG_RESVAL 0x0u |
Definition at line 994 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_57_IN_57_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_57_IN_57_MASK, .index = PINMUX_MIO_PERIPH_INSEL_57_IN_57_OFFSET }) |
Definition at line 1005 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_57_IN_57_MASK 0x3fu |
Definition at line 1003 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_57_IN_57_OFFSET 0 |
Definition at line 1004 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_57_REG_OFFSET 0x26c |
Definition at line 1001 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_57_REG_RESVAL 0x0u |
Definition at line 1002 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_58_IN_58_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_58_IN_58_MASK, .index = PINMUX_MIO_PERIPH_INSEL_58_IN_58_OFFSET }) |
Definition at line 1013 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_58_IN_58_MASK 0x3fu |
Definition at line 1011 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_58_IN_58_OFFSET 0 |
Definition at line 1012 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_58_REG_OFFSET 0x270 |
Definition at line 1009 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_58_REG_RESVAL 0x0u |
Definition at line 1010 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_59_IN_59_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_59_IN_59_MASK, .index = PINMUX_MIO_PERIPH_INSEL_59_IN_59_OFFSET }) |
Definition at line 1021 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_59_IN_59_MASK 0x3fu |
Definition at line 1019 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_59_IN_59_OFFSET 0 |
Definition at line 1020 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_59_REG_OFFSET 0x274 |
Definition at line 1017 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_59_REG_RESVAL 0x0u |
Definition at line 1018 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_5_IN_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_5_IN_5_MASK, .index = PINMUX_MIO_PERIPH_INSEL_5_IN_5_OFFSET }) |
Definition at line 589 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_5_IN_5_MASK 0x3fu |
Definition at line 587 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_5_IN_5_OFFSET 0 |
Definition at line 588 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_5_REG_OFFSET 0x19c |
Definition at line 585 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_5_REG_RESVAL 0x0u |
Definition at line 586 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_60_IN_60_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_60_IN_60_MASK, .index = PINMUX_MIO_PERIPH_INSEL_60_IN_60_OFFSET }) |
Definition at line 1029 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_60_IN_60_MASK 0x3fu |
Definition at line 1027 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_60_IN_60_OFFSET 0 |
Definition at line 1028 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_60_REG_OFFSET 0x278 |
Definition at line 1025 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_60_REG_RESVAL 0x0u |
Definition at line 1026 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_61_IN_61_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_61_IN_61_MASK, .index = PINMUX_MIO_PERIPH_INSEL_61_IN_61_OFFSET }) |
Definition at line 1037 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_61_IN_61_MASK 0x3fu |
Definition at line 1035 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_61_IN_61_OFFSET 0 |
Definition at line 1036 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_61_REG_OFFSET 0x27c |
Definition at line 1033 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_61_REG_RESVAL 0x0u |
Definition at line 1034 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_62_IN_62_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_62_IN_62_MASK, .index = PINMUX_MIO_PERIPH_INSEL_62_IN_62_OFFSET }) |
Definition at line 1045 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_62_IN_62_MASK 0x3fu |
Definition at line 1043 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_62_IN_62_OFFSET 0 |
Definition at line 1044 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_62_REG_OFFSET 0x280 |
Definition at line 1041 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_62_REG_RESVAL 0x0u |
Definition at line 1042 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_63_IN_63_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_63_IN_63_MASK, .index = PINMUX_MIO_PERIPH_INSEL_63_IN_63_OFFSET }) |
Definition at line 1053 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_63_IN_63_MASK 0x3fu |
Definition at line 1051 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_63_IN_63_OFFSET 0 |
Definition at line 1052 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_63_REG_OFFSET 0x284 |
Definition at line 1049 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_63_REG_RESVAL 0x0u |
Definition at line 1050 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_64_IN_64_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_64_IN_64_MASK, .index = PINMUX_MIO_PERIPH_INSEL_64_IN_64_OFFSET }) |
Definition at line 1061 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_64_IN_64_MASK 0x3fu |
Definition at line 1059 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_64_IN_64_OFFSET 0 |
Definition at line 1060 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_64_REG_OFFSET 0x288 |
Definition at line 1057 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_64_REG_RESVAL 0x0u |
Definition at line 1058 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_65_IN_65_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_65_IN_65_MASK, .index = PINMUX_MIO_PERIPH_INSEL_65_IN_65_OFFSET }) |
Definition at line 1069 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_65_IN_65_MASK 0x3fu |
Definition at line 1067 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_65_IN_65_OFFSET 0 |
Definition at line 1068 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_65_REG_OFFSET 0x28c |
Definition at line 1065 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_65_REG_RESVAL 0x0u |
Definition at line 1066 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_66_IN_66_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_66_IN_66_MASK, .index = PINMUX_MIO_PERIPH_INSEL_66_IN_66_OFFSET }) |
Definition at line 1077 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_66_IN_66_MASK 0x3fu |
Definition at line 1075 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_66_IN_66_OFFSET 0 |
Definition at line 1076 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_66_REG_OFFSET 0x290 |
Definition at line 1073 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_66_REG_RESVAL 0x0u |
Definition at line 1074 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_67_IN_67_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_67_IN_67_MASK, .index = PINMUX_MIO_PERIPH_INSEL_67_IN_67_OFFSET }) |
Definition at line 1085 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_67_IN_67_MASK 0x3fu |
Definition at line 1083 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_67_IN_67_OFFSET 0 |
Definition at line 1084 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_67_REG_OFFSET 0x294 |
Definition at line 1081 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_67_REG_RESVAL 0x0u |
Definition at line 1082 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_68_IN_68_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_68_IN_68_MASK, .index = PINMUX_MIO_PERIPH_INSEL_68_IN_68_OFFSET }) |
Definition at line 1093 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_68_IN_68_MASK 0x3fu |
Definition at line 1091 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_68_IN_68_OFFSET 0 |
Definition at line 1092 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_68_REG_OFFSET 0x298 |
Definition at line 1089 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_68_REG_RESVAL 0x0u |
Definition at line 1090 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_69_IN_69_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_69_IN_69_MASK, .index = PINMUX_MIO_PERIPH_INSEL_69_IN_69_OFFSET }) |
Definition at line 1101 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_69_IN_69_MASK 0x3fu |
Definition at line 1099 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_69_IN_69_OFFSET 0 |
Definition at line 1100 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_69_REG_OFFSET 0x29c |
Definition at line 1097 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_69_REG_RESVAL 0x0u |
Definition at line 1098 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_6_IN_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_6_IN_6_MASK, .index = PINMUX_MIO_PERIPH_INSEL_6_IN_6_OFFSET }) |
Definition at line 597 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_6_IN_6_MASK 0x3fu |
Definition at line 595 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_6_IN_6_OFFSET 0 |
Definition at line 596 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_6_REG_OFFSET 0x1a0 |
Definition at line 593 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_6_REG_RESVAL 0x0u |
Definition at line 594 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_70_IN_70_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_70_IN_70_MASK, .index = PINMUX_MIO_PERIPH_INSEL_70_IN_70_OFFSET }) |
Definition at line 1109 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_70_IN_70_MASK 0x3fu |
Definition at line 1107 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_70_IN_70_OFFSET 0 |
Definition at line 1108 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_70_REG_OFFSET 0x2a0 |
Definition at line 1105 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_70_REG_RESVAL 0x0u |
Definition at line 1106 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_71_IN_71_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_71_IN_71_MASK, .index = PINMUX_MIO_PERIPH_INSEL_71_IN_71_OFFSET }) |
Definition at line 1117 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_71_IN_71_MASK 0x3fu |
Definition at line 1115 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_71_IN_71_OFFSET 0 |
Definition at line 1116 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_71_REG_OFFSET 0x2a4 |
Definition at line 1113 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_71_REG_RESVAL 0x0u |
Definition at line 1114 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_72_IN_72_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_72_IN_72_MASK, .index = PINMUX_MIO_PERIPH_INSEL_72_IN_72_OFFSET }) |
Definition at line 1125 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_72_IN_72_MASK 0x3fu |
Definition at line 1123 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_72_IN_72_OFFSET 0 |
Definition at line 1124 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_72_REG_OFFSET 0x2a8 |
Definition at line 1121 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_72_REG_RESVAL 0x0u |
Definition at line 1122 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_73_IN_73_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_73_IN_73_MASK, .index = PINMUX_MIO_PERIPH_INSEL_73_IN_73_OFFSET }) |
Definition at line 1133 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_73_IN_73_MASK 0x3fu |
Definition at line 1131 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_73_IN_73_OFFSET 0 |
Definition at line 1132 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_73_REG_OFFSET 0x2ac |
Definition at line 1129 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_73_REG_RESVAL 0x0u |
Definition at line 1130 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_74_IN_74_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_74_IN_74_MASK, .index = PINMUX_MIO_PERIPH_INSEL_74_IN_74_OFFSET }) |
Definition at line 1141 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_74_IN_74_MASK 0x3fu |
Definition at line 1139 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_74_IN_74_OFFSET 0 |
Definition at line 1140 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_74_REG_OFFSET 0x2b0 |
Definition at line 1137 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_74_REG_RESVAL 0x0u |
Definition at line 1138 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_75_IN_75_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_75_IN_75_MASK, .index = PINMUX_MIO_PERIPH_INSEL_75_IN_75_OFFSET }) |
Definition at line 1149 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_75_IN_75_MASK 0x3fu |
Definition at line 1147 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_75_IN_75_OFFSET 0 |
Definition at line 1148 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_75_REG_OFFSET 0x2b4 |
Definition at line 1145 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_75_REG_RESVAL 0x0u |
Definition at line 1146 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_76_IN_76_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_76_IN_76_MASK, .index = PINMUX_MIO_PERIPH_INSEL_76_IN_76_OFFSET }) |
Definition at line 1157 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_76_IN_76_MASK 0x3fu |
Definition at line 1155 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_76_IN_76_OFFSET 0 |
Definition at line 1156 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_76_REG_OFFSET 0x2b8 |
Definition at line 1153 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_76_REG_RESVAL 0x0u |
Definition at line 1154 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_77_IN_77_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_77_IN_77_MASK, .index = PINMUX_MIO_PERIPH_INSEL_77_IN_77_OFFSET }) |
Definition at line 1165 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_77_IN_77_MASK 0x3fu |
Definition at line 1163 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_77_IN_77_OFFSET 0 |
Definition at line 1164 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_77_REG_OFFSET 0x2bc |
Definition at line 1161 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_77_REG_RESVAL 0x0u |
Definition at line 1162 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_78_IN_78_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_78_IN_78_MASK, .index = PINMUX_MIO_PERIPH_INSEL_78_IN_78_OFFSET }) |
Definition at line 1173 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_78_IN_78_MASK 0x3fu |
Definition at line 1171 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_78_IN_78_OFFSET 0 |
Definition at line 1172 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_78_REG_OFFSET 0x2c0 |
Definition at line 1169 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_78_REG_RESVAL 0x0u |
Definition at line 1170 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_79_IN_79_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_79_IN_79_MASK, .index = PINMUX_MIO_PERIPH_INSEL_79_IN_79_OFFSET }) |
Definition at line 1181 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_79_IN_79_MASK 0x3fu |
Definition at line 1179 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_79_IN_79_OFFSET 0 |
Definition at line 1180 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_79_REG_OFFSET 0x2c4 |
Definition at line 1177 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_79_REG_RESVAL 0x0u |
Definition at line 1178 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_7_IN_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_7_IN_7_MASK, .index = PINMUX_MIO_PERIPH_INSEL_7_IN_7_OFFSET }) |
Definition at line 605 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_7_IN_7_MASK 0x3fu |
Definition at line 603 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_7_IN_7_OFFSET 0 |
Definition at line 604 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_7_REG_OFFSET 0x1a4 |
Definition at line 601 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_7_REG_RESVAL 0x0u |
Definition at line 602 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_80_IN_80_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_80_IN_80_MASK, .index = PINMUX_MIO_PERIPH_INSEL_80_IN_80_OFFSET }) |
Definition at line 1189 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_80_IN_80_MASK 0x3fu |
Definition at line 1187 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_80_IN_80_OFFSET 0 |
Definition at line 1188 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_80_REG_OFFSET 0x2c8 |
Definition at line 1185 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_80_REG_RESVAL 0x0u |
Definition at line 1186 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_81_IN_81_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_81_IN_81_MASK, .index = PINMUX_MIO_PERIPH_INSEL_81_IN_81_OFFSET }) |
Definition at line 1197 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_81_IN_81_MASK 0x3fu |
Definition at line 1195 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_81_IN_81_OFFSET 0 |
Definition at line 1196 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_81_REG_OFFSET 0x2cc |
Definition at line 1193 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_81_REG_RESVAL 0x0u |
Definition at line 1194 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_82_IN_82_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_82_IN_82_MASK, .index = PINMUX_MIO_PERIPH_INSEL_82_IN_82_OFFSET }) |
Definition at line 1205 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_82_IN_82_MASK 0x3fu |
Definition at line 1203 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_82_IN_82_OFFSET 0 |
Definition at line 1204 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_82_REG_OFFSET 0x2d0 |
Definition at line 1201 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_82_REG_RESVAL 0x0u |
Definition at line 1202 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_83_IN_83_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_83_IN_83_MASK, .index = PINMUX_MIO_PERIPH_INSEL_83_IN_83_OFFSET }) |
Definition at line 1213 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_83_IN_83_MASK 0x3fu |
Definition at line 1211 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_83_IN_83_OFFSET 0 |
Definition at line 1212 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_83_REG_OFFSET 0x2d4 |
Definition at line 1209 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_83_REG_RESVAL 0x0u |
Definition at line 1210 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_84_IN_84_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_84_IN_84_MASK, .index = PINMUX_MIO_PERIPH_INSEL_84_IN_84_OFFSET }) |
Definition at line 1221 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_84_IN_84_MASK 0x3fu |
Definition at line 1219 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_84_IN_84_OFFSET 0 |
Definition at line 1220 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_84_REG_OFFSET 0x2d8 |
Definition at line 1217 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_84_REG_RESVAL 0x0u |
Definition at line 1218 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_85_IN_85_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_85_IN_85_MASK, .index = PINMUX_MIO_PERIPH_INSEL_85_IN_85_OFFSET }) |
Definition at line 1229 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_85_IN_85_MASK 0x3fu |
Definition at line 1227 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_85_IN_85_OFFSET 0 |
Definition at line 1228 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_85_REG_OFFSET 0x2dc |
Definition at line 1225 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_85_REG_RESVAL 0x0u |
Definition at line 1226 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_86_IN_86_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_86_IN_86_MASK, .index = PINMUX_MIO_PERIPH_INSEL_86_IN_86_OFFSET }) |
Definition at line 1237 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_86_IN_86_MASK 0x3fu |
Definition at line 1235 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_86_IN_86_OFFSET 0 |
Definition at line 1236 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_86_REG_OFFSET 0x2e0 |
Definition at line 1233 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_86_REG_RESVAL 0x0u |
Definition at line 1234 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_87_IN_87_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_87_IN_87_MASK, .index = PINMUX_MIO_PERIPH_INSEL_87_IN_87_OFFSET }) |
Definition at line 1245 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_87_IN_87_MASK 0x3fu |
Definition at line 1243 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_87_IN_87_OFFSET 0 |
Definition at line 1244 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_87_REG_OFFSET 0x2e4 |
Definition at line 1241 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_87_REG_RESVAL 0x0u |
Definition at line 1242 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_88_IN_88_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_88_IN_88_MASK, .index = PINMUX_MIO_PERIPH_INSEL_88_IN_88_OFFSET }) |
Definition at line 1253 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_88_IN_88_MASK 0x3fu |
Definition at line 1251 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_88_IN_88_OFFSET 0 |
Definition at line 1252 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_88_REG_OFFSET 0x2e8 |
Definition at line 1249 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_88_REG_RESVAL 0x0u |
Definition at line 1250 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_89_IN_89_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_89_IN_89_MASK, .index = PINMUX_MIO_PERIPH_INSEL_89_IN_89_OFFSET }) |
Definition at line 1261 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_89_IN_89_MASK 0x3fu |
Definition at line 1259 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_89_IN_89_OFFSET 0 |
Definition at line 1260 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_89_REG_OFFSET 0x2ec |
Definition at line 1257 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_89_REG_RESVAL 0x0u |
Definition at line 1258 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_8_IN_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_8_IN_8_MASK, .index = PINMUX_MIO_PERIPH_INSEL_8_IN_8_OFFSET }) |
Definition at line 613 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_8_IN_8_MASK 0x3fu |
Definition at line 611 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_8_IN_8_OFFSET 0 |
Definition at line 612 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_8_REG_OFFSET 0x1a8 |
Definition at line 609 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_8_REG_RESVAL 0x0u |
Definition at line 610 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_90_IN_90_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_90_IN_90_MASK, .index = PINMUX_MIO_PERIPH_INSEL_90_IN_90_OFFSET }) |
Definition at line 1269 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_90_IN_90_MASK 0x3fu |
Definition at line 1267 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_90_IN_90_OFFSET 0 |
Definition at line 1268 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_90_REG_OFFSET 0x2f0 |
Definition at line 1265 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_90_REG_RESVAL 0x0u |
Definition at line 1266 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_91_IN_91_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_91_IN_91_MASK, .index = PINMUX_MIO_PERIPH_INSEL_91_IN_91_OFFSET }) |
Definition at line 1277 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_91_IN_91_MASK 0x3fu |
Definition at line 1275 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_91_IN_91_OFFSET 0 |
Definition at line 1276 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_91_REG_OFFSET 0x2f4 |
Definition at line 1273 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_91_REG_RESVAL 0x0u |
Definition at line 1274 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_92_IN_92_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_92_IN_92_MASK, .index = PINMUX_MIO_PERIPH_INSEL_92_IN_92_OFFSET }) |
Definition at line 1285 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_92_IN_92_MASK 0x3fu |
Definition at line 1283 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_92_IN_92_OFFSET 0 |
Definition at line 1284 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_92_REG_OFFSET 0x2f8 |
Definition at line 1281 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_92_REG_RESVAL 0x0u |
Definition at line 1282 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_93_IN_93_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_93_IN_93_MASK, .index = PINMUX_MIO_PERIPH_INSEL_93_IN_93_OFFSET }) |
Definition at line 1293 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_93_IN_93_MASK 0x3fu |
Definition at line 1291 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_93_IN_93_OFFSET 0 |
Definition at line 1292 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_93_REG_OFFSET 0x2fc |
Definition at line 1289 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_93_REG_RESVAL 0x0u |
Definition at line 1290 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_94_IN_94_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_94_IN_94_MASK, .index = PINMUX_MIO_PERIPH_INSEL_94_IN_94_OFFSET }) |
Definition at line 1301 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_94_IN_94_MASK 0x3fu |
Definition at line 1299 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_94_IN_94_OFFSET 0 |
Definition at line 1300 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_94_REG_OFFSET 0x300 |
Definition at line 1297 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_94_REG_RESVAL 0x0u |
Definition at line 1298 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_95_IN_95_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_95_IN_95_MASK, .index = PINMUX_MIO_PERIPH_INSEL_95_IN_95_OFFSET }) |
Definition at line 1309 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_95_IN_95_MASK 0x3fu |
Definition at line 1307 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_95_IN_95_OFFSET 0 |
Definition at line 1308 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_95_REG_OFFSET 0x304 |
Definition at line 1305 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_95_REG_RESVAL 0x0u |
Definition at line 1306 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_96_IN_96_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_96_IN_96_MASK, .index = PINMUX_MIO_PERIPH_INSEL_96_IN_96_OFFSET }) |
Definition at line 1317 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_96_IN_96_MASK 0x3fu |
Definition at line 1315 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_96_IN_96_OFFSET 0 |
Definition at line 1316 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_96_REG_OFFSET 0x308 |
Definition at line 1313 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_96_REG_RESVAL 0x0u |
Definition at line 1314 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_9_IN_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_9_IN_9_MASK, .index = PINMUX_MIO_PERIPH_INSEL_9_IN_9_OFFSET }) |
Definition at line 621 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_9_IN_9_MASK 0x3fu |
Definition at line 619 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_9_IN_9_OFFSET 0 |
Definition at line 620 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_9_REG_OFFSET 0x1ac |
Definition at line 617 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_9_REG_RESVAL 0x0u |
Definition at line 618 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_IN_FIELD_WIDTH 6 |
Definition at line 541 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_MULTIREG_COUNT 97 |
Definition at line 542 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_EN_0_BIT 0 |
Definition at line 57 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_OFFSET 0x4 |
Definition at line 55 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_RESVAL 0x1u |
Definition at line 56 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_10_EN_10_BIT 0 |
Definition at line 107 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_10_REG_OFFSET 0x2c |
Definition at line 105 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_10_REG_RESVAL 0x1u |
Definition at line 106 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_11_EN_11_BIT 0 |
Definition at line 112 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_11_REG_OFFSET 0x30 |
Definition at line 110 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_11_REG_RESVAL 0x1u |
Definition at line 111 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_12_EN_12_BIT 0 |
Definition at line 117 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_12_REG_OFFSET 0x34 |
Definition at line 115 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_12_REG_RESVAL 0x1u |
Definition at line 116 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_13_EN_13_BIT 0 |
Definition at line 122 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_13_REG_OFFSET 0x38 |
Definition at line 120 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_13_REG_RESVAL 0x1u |
Definition at line 121 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_14_EN_14_BIT 0 |
Definition at line 127 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_14_REG_OFFSET 0x3c |
Definition at line 125 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_14_REG_RESVAL 0x1u |
Definition at line 126 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_15_EN_15_BIT 0 |
Definition at line 132 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_15_REG_OFFSET 0x40 |
Definition at line 130 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_15_REG_RESVAL 0x1u |
Definition at line 131 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_16_EN_16_BIT 0 |
Definition at line 137 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_16_REG_OFFSET 0x44 |
Definition at line 135 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_16_REG_RESVAL 0x1u |
Definition at line 136 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_17_EN_17_BIT 0 |
Definition at line 142 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_17_REG_OFFSET 0x48 |
Definition at line 140 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_17_REG_RESVAL 0x1u |
Definition at line 141 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_18_EN_18_BIT 0 |
Definition at line 147 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_18_REG_OFFSET 0x4c |
Definition at line 145 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_18_REG_RESVAL 0x1u |
Definition at line 146 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_19_EN_19_BIT 0 |
Definition at line 152 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_19_REG_OFFSET 0x50 |
Definition at line 150 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_19_REG_RESVAL 0x1u |
Definition at line 151 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_EN_1_BIT 0 |
Definition at line 62 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_OFFSET 0x8 |
Definition at line 60 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_RESVAL 0x1u |
Definition at line 61 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_20_EN_20_BIT 0 |
Definition at line 157 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_20_REG_OFFSET 0x54 |
Definition at line 155 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_20_REG_RESVAL 0x1u |
Definition at line 156 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_21_EN_21_BIT 0 |
Definition at line 162 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_21_REG_OFFSET 0x58 |
Definition at line 160 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_21_REG_RESVAL 0x1u |
Definition at line 161 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_22_EN_22_BIT 0 |
Definition at line 167 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_22_REG_OFFSET 0x5c |
Definition at line 165 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_22_REG_RESVAL 0x1u |
Definition at line 166 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_23_EN_23_BIT 0 |
Definition at line 172 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_23_REG_OFFSET 0x60 |
Definition at line 170 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_23_REG_RESVAL 0x1u |
Definition at line 171 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_24_EN_24_BIT 0 |
Definition at line 177 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_24_REG_OFFSET 0x64 |
Definition at line 175 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_24_REG_RESVAL 0x1u |
Definition at line 176 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_25_EN_25_BIT 0 |
Definition at line 182 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_25_REG_OFFSET 0x68 |
Definition at line 180 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_25_REG_RESVAL 0x1u |
Definition at line 181 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_26_EN_26_BIT 0 |
Definition at line 187 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_26_REG_OFFSET 0x6c |
Definition at line 185 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_26_REG_RESVAL 0x1u |
Definition at line 186 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_27_EN_27_BIT 0 |
Definition at line 192 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_27_REG_OFFSET 0x70 |
Definition at line 190 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_27_REG_RESVAL 0x1u |
Definition at line 191 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_28_EN_28_BIT 0 |
Definition at line 197 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_28_REG_OFFSET 0x74 |
Definition at line 195 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_28_REG_RESVAL 0x1u |
Definition at line 196 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_29_EN_29_BIT 0 |
Definition at line 202 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_29_REG_OFFSET 0x78 |
Definition at line 200 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_29_REG_RESVAL 0x1u |
Definition at line 201 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_EN_2_BIT 0 |
Definition at line 67 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_OFFSET 0xc |
Definition at line 65 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_RESVAL 0x1u |
Definition at line 66 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_30_EN_30_BIT 0 |
Definition at line 207 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_30_REG_OFFSET 0x7c |
Definition at line 205 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_30_REG_RESVAL 0x1u |
Definition at line 206 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_31_EN_31_BIT 0 |
Definition at line 212 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_31_REG_OFFSET 0x80 |
Definition at line 210 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_31_REG_RESVAL 0x1u |
Definition at line 211 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_32_EN_32_BIT 0 |
Definition at line 217 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_32_REG_OFFSET 0x84 |
Definition at line 215 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_32_REG_RESVAL 0x1u |
Definition at line 216 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_33_EN_33_BIT 0 |
Definition at line 222 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_33_REG_OFFSET 0x88 |
Definition at line 220 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_33_REG_RESVAL 0x1u |
Definition at line 221 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_34_EN_34_BIT 0 |
Definition at line 227 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_34_REG_OFFSET 0x8c |
Definition at line 225 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_34_REG_RESVAL 0x1u |
Definition at line 226 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_35_EN_35_BIT 0 |
Definition at line 232 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_35_REG_OFFSET 0x90 |
Definition at line 230 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_35_REG_RESVAL 0x1u |
Definition at line 231 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_36_EN_36_BIT 0 |
Definition at line 237 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_36_REG_OFFSET 0x94 |
Definition at line 235 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_36_REG_RESVAL 0x1u |
Definition at line 236 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_37_EN_37_BIT 0 |
Definition at line 242 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_37_REG_OFFSET 0x98 |
Definition at line 240 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_37_REG_RESVAL 0x1u |
Definition at line 241 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_38_EN_38_BIT 0 |
Definition at line 247 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_38_REG_OFFSET 0x9c |
Definition at line 245 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_38_REG_RESVAL 0x1u |
Definition at line 246 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_39_EN_39_BIT 0 |
Definition at line 252 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_39_REG_OFFSET 0xa0 |
Definition at line 250 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_39_REG_RESVAL 0x1u |
Definition at line 251 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_EN_3_BIT 0 |
Definition at line 72 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_OFFSET 0x10 |
Definition at line 70 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_RESVAL 0x1u |
Definition at line 71 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_40_EN_40_BIT 0 |
Definition at line 257 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_40_REG_OFFSET 0xa4 |
Definition at line 255 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_40_REG_RESVAL 0x1u |
Definition at line 256 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_41_EN_41_BIT 0 |
Definition at line 262 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_41_REG_OFFSET 0xa8 |
Definition at line 260 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_41_REG_RESVAL 0x1u |
Definition at line 261 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_42_EN_42_BIT 0 |
Definition at line 267 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_42_REG_OFFSET 0xac |
Definition at line 265 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_42_REG_RESVAL 0x1u |
Definition at line 266 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_43_EN_43_BIT 0 |
Definition at line 272 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_43_REG_OFFSET 0xb0 |
Definition at line 270 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_43_REG_RESVAL 0x1u |
Definition at line 271 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_44_EN_44_BIT 0 |
Definition at line 277 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_44_REG_OFFSET 0xb4 |
Definition at line 275 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_44_REG_RESVAL 0x1u |
Definition at line 276 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_45_EN_45_BIT 0 |
Definition at line 282 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_45_REG_OFFSET 0xb8 |
Definition at line 280 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_45_REG_RESVAL 0x1u |
Definition at line 281 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_46_EN_46_BIT 0 |
Definition at line 287 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_46_REG_OFFSET 0xbc |
Definition at line 285 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_46_REG_RESVAL 0x1u |
Definition at line 286 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_47_EN_47_BIT 0 |
Definition at line 292 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_47_REG_OFFSET 0xc0 |
Definition at line 290 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_47_REG_RESVAL 0x1u |
Definition at line 291 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_48_EN_48_BIT 0 |
Definition at line 297 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_48_REG_OFFSET 0xc4 |
Definition at line 295 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_48_REG_RESVAL 0x1u |
Definition at line 296 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_49_EN_49_BIT 0 |
Definition at line 302 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_49_REG_OFFSET 0xc8 |
Definition at line 300 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_49_REG_RESVAL 0x1u |
Definition at line 301 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_4_EN_4_BIT 0 |
Definition at line 77 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_4_REG_OFFSET 0x14 |
Definition at line 75 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_4_REG_RESVAL 0x1u |
Definition at line 76 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_50_EN_50_BIT 0 |
Definition at line 307 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_50_REG_OFFSET 0xcc |
Definition at line 305 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_50_REG_RESVAL 0x1u |
Definition at line 306 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_51_EN_51_BIT 0 |
Definition at line 312 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_51_REG_OFFSET 0xd0 |
Definition at line 310 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_51_REG_RESVAL 0x1u |
Definition at line 311 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_52_EN_52_BIT 0 |
Definition at line 317 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_52_REG_OFFSET 0xd4 |
Definition at line 315 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_52_REG_RESVAL 0x1u |
Definition at line 316 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_53_EN_53_BIT 0 |
Definition at line 322 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_53_REG_OFFSET 0xd8 |
Definition at line 320 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_53_REG_RESVAL 0x1u |
Definition at line 321 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_54_EN_54_BIT 0 |
Definition at line 327 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_54_REG_OFFSET 0xdc |
Definition at line 325 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_54_REG_RESVAL 0x1u |
Definition at line 326 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_55_EN_55_BIT 0 |
Definition at line 332 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_55_REG_OFFSET 0xe0 |
Definition at line 330 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_55_REG_RESVAL 0x1u |
Definition at line 331 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_56_EN_56_BIT 0 |
Definition at line 337 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_56_REG_OFFSET 0xe4 |
Definition at line 335 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_56_REG_RESVAL 0x1u |
Definition at line 336 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_57_EN_57_BIT 0 |
Definition at line 342 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_57_REG_OFFSET 0xe8 |
Definition at line 340 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_57_REG_RESVAL 0x1u |
Definition at line 341 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_58_EN_58_BIT 0 |
Definition at line 347 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_58_REG_OFFSET 0xec |
Definition at line 345 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_58_REG_RESVAL 0x1u |
Definition at line 346 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_59_EN_59_BIT 0 |
Definition at line 352 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_59_REG_OFFSET 0xf0 |
Definition at line 350 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_59_REG_RESVAL 0x1u |
Definition at line 351 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_5_EN_5_BIT 0 |
Definition at line 82 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_5_REG_OFFSET 0x18 |
Definition at line 80 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_5_REG_RESVAL 0x1u |
Definition at line 81 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_60_EN_60_BIT 0 |
Definition at line 357 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_60_REG_OFFSET 0xf4 |
Definition at line 355 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_60_REG_RESVAL 0x1u |
Definition at line 356 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_61_EN_61_BIT 0 |
Definition at line 362 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_61_REG_OFFSET 0xf8 |
Definition at line 360 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_61_REG_RESVAL 0x1u |
Definition at line 361 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_62_EN_62_BIT 0 |
Definition at line 367 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_62_REG_OFFSET 0xfc |
Definition at line 365 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_62_REG_RESVAL 0x1u |
Definition at line 366 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_63_EN_63_BIT 0 |
Definition at line 372 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_63_REG_OFFSET 0x100 |
Definition at line 370 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_63_REG_RESVAL 0x1u |
Definition at line 371 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_64_EN_64_BIT 0 |
Definition at line 377 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_64_REG_OFFSET 0x104 |
Definition at line 375 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_64_REG_RESVAL 0x1u |
Definition at line 376 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_65_EN_65_BIT 0 |
Definition at line 382 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_65_REG_OFFSET 0x108 |
Definition at line 380 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_65_REG_RESVAL 0x1u |
Definition at line 381 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_66_EN_66_BIT 0 |
Definition at line 387 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_66_REG_OFFSET 0x10c |
Definition at line 385 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_66_REG_RESVAL 0x1u |
Definition at line 386 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_67_EN_67_BIT 0 |
Definition at line 392 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_67_REG_OFFSET 0x110 |
Definition at line 390 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_67_REG_RESVAL 0x1u |
Definition at line 391 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_68_EN_68_BIT 0 |
Definition at line 397 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_68_REG_OFFSET 0x114 |
Definition at line 395 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_68_REG_RESVAL 0x1u |
Definition at line 396 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_69_EN_69_BIT 0 |
Definition at line 402 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_69_REG_OFFSET 0x118 |
Definition at line 400 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_69_REG_RESVAL 0x1u |
Definition at line 401 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_6_EN_6_BIT 0 |
Definition at line 87 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_6_REG_OFFSET 0x1c |
Definition at line 85 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_6_REG_RESVAL 0x1u |
Definition at line 86 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_70_EN_70_BIT 0 |
Definition at line 407 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_70_REG_OFFSET 0x11c |
Definition at line 405 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_70_REG_RESVAL 0x1u |
Definition at line 406 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_71_EN_71_BIT 0 |
Definition at line 412 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_71_REG_OFFSET 0x120 |
Definition at line 410 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_71_REG_RESVAL 0x1u |
Definition at line 411 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_72_EN_72_BIT 0 |
Definition at line 417 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_72_REG_OFFSET 0x124 |
Definition at line 415 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_72_REG_RESVAL 0x1u |
Definition at line 416 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_73_EN_73_BIT 0 |
Definition at line 422 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_73_REG_OFFSET 0x128 |
Definition at line 420 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_73_REG_RESVAL 0x1u |
Definition at line 421 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_74_EN_74_BIT 0 |
Definition at line 427 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_74_REG_OFFSET 0x12c |
Definition at line 425 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_74_REG_RESVAL 0x1u |
Definition at line 426 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_75_EN_75_BIT 0 |
Definition at line 432 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_75_REG_OFFSET 0x130 |
Definition at line 430 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_75_REG_RESVAL 0x1u |
Definition at line 431 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_76_EN_76_BIT 0 |
Definition at line 437 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_76_REG_OFFSET 0x134 |
Definition at line 435 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_76_REG_RESVAL 0x1u |
Definition at line 436 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_77_EN_77_BIT 0 |
Definition at line 442 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_77_REG_OFFSET 0x138 |
Definition at line 440 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_77_REG_RESVAL 0x1u |
Definition at line 441 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_78_EN_78_BIT 0 |
Definition at line 447 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_78_REG_OFFSET 0x13c |
Definition at line 445 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_78_REG_RESVAL 0x1u |
Definition at line 446 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_79_EN_79_BIT 0 |
Definition at line 452 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_79_REG_OFFSET 0x140 |
Definition at line 450 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_79_REG_RESVAL 0x1u |
Definition at line 451 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_7_EN_7_BIT 0 |
Definition at line 92 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_7_REG_OFFSET 0x20 |
Definition at line 90 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_7_REG_RESVAL 0x1u |
Definition at line 91 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_80_EN_80_BIT 0 |
Definition at line 457 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_80_REG_OFFSET 0x144 |
Definition at line 455 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_80_REG_RESVAL 0x1u |
Definition at line 456 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_81_EN_81_BIT 0 |
Definition at line 462 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_81_REG_OFFSET 0x148 |
Definition at line 460 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_81_REG_RESVAL 0x1u |
Definition at line 461 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_82_EN_82_BIT 0 |
Definition at line 467 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_82_REG_OFFSET 0x14c |
Definition at line 465 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_82_REG_RESVAL 0x1u |
Definition at line 466 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_83_EN_83_BIT 0 |
Definition at line 472 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_83_REG_OFFSET 0x150 |
Definition at line 470 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_83_REG_RESVAL 0x1u |
Definition at line 471 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_84_EN_84_BIT 0 |
Definition at line 477 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_84_REG_OFFSET 0x154 |
Definition at line 475 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_84_REG_RESVAL 0x1u |
Definition at line 476 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_85_EN_85_BIT 0 |
Definition at line 482 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_85_REG_OFFSET 0x158 |
Definition at line 480 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_85_REG_RESVAL 0x1u |
Definition at line 481 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_86_EN_86_BIT 0 |
Definition at line 487 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_86_REG_OFFSET 0x15c |
Definition at line 485 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_86_REG_RESVAL 0x1u |
Definition at line 486 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_87_EN_87_BIT 0 |
Definition at line 492 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_87_REG_OFFSET 0x160 |
Definition at line 490 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_87_REG_RESVAL 0x1u |
Definition at line 491 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_88_EN_88_BIT 0 |
Definition at line 497 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_88_REG_OFFSET 0x164 |
Definition at line 495 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_88_REG_RESVAL 0x1u |
Definition at line 496 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_89_EN_89_BIT 0 |
Definition at line 502 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_89_REG_OFFSET 0x168 |
Definition at line 500 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_89_REG_RESVAL 0x1u |
Definition at line 501 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_8_EN_8_BIT 0 |
Definition at line 97 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_8_REG_OFFSET 0x24 |
Definition at line 95 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_8_REG_RESVAL 0x1u |
Definition at line 96 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_90_EN_90_BIT 0 |
Definition at line 507 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_90_REG_OFFSET 0x16c |
Definition at line 505 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_90_REG_RESVAL 0x1u |
Definition at line 506 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_91_EN_91_BIT 0 |
Definition at line 512 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_91_REG_OFFSET 0x170 |
Definition at line 510 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_91_REG_RESVAL 0x1u |
Definition at line 511 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_92_EN_92_BIT 0 |
Definition at line 517 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_92_REG_OFFSET 0x174 |
Definition at line 515 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_92_REG_RESVAL 0x1u |
Definition at line 516 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_93_EN_93_BIT 0 |
Definition at line 522 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_93_REG_OFFSET 0x178 |
Definition at line 520 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_93_REG_RESVAL 0x1u |
Definition at line 521 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_94_EN_94_BIT 0 |
Definition at line 527 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_94_REG_OFFSET 0x17c |
Definition at line 525 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_94_REG_RESVAL 0x1u |
Definition at line 526 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_95_EN_95_BIT 0 |
Definition at line 532 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_95_REG_OFFSET 0x180 |
Definition at line 530 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_95_REG_RESVAL 0x1u |
Definition at line 531 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_96_EN_96_BIT 0 |
Definition at line 537 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_96_REG_OFFSET 0x184 |
Definition at line 535 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_96_REG_RESVAL 0x1u |
Definition at line 536 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_9_EN_9_BIT 0 |
Definition at line 102 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_9_REG_OFFSET 0x28 |
Definition at line 100 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_9_REG_RESVAL 0x1u |
Definition at line 101 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_EN_FIELD_WIDTH 1 |
Definition at line 51 of file pinmux_regs.h.
| #define PINMUX_MIO_PERIPH_INSEL_REGWEN_MULTIREG_COUNT 97 |
Definition at line 52 of file pinmux_regs.h.
| #define PINMUX_PARAM_N_DIO_PADS 16 |
Definition at line 29 of file pinmux_regs.h.
| #define PINMUX_PARAM_N_MIO_PADS 47 |
Definition at line 26 of file pinmux_regs.h.
| #define PINMUX_PARAM_N_MIO_PERIPH_IN 97 |
Definition at line 20 of file pinmux_regs.h.
| #define PINMUX_PARAM_N_MIO_PERIPH_OUT 102 |
Definition at line 23 of file pinmux_regs.h.
| #define PINMUX_PARAM_N_WKUP_DETECT 8 |
Definition at line 32 of file pinmux_regs.h.
| #define PINMUX_PARAM_NUM_ALERTS 1 |
Definition at line 38 of file pinmux_regs.h.
| #define PINMUX_PARAM_REG_WIDTH 32 |
Definition at line 41 of file pinmux_regs.h.
| #define PINMUX_PARAM_WKUP_CNT_WIDTH 8 |
Definition at line 35 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_CAUSE_0_BIT 0 |
Definition at line 5130 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_CAUSE_1_BIT 1 |
Definition at line 5131 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_CAUSE_2_BIT 2 |
Definition at line 5132 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_CAUSE_3_BIT 3 |
Definition at line 5133 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_CAUSE_4_BIT 4 |
Definition at line 5134 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_CAUSE_5_BIT 5 |
Definition at line 5135 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_CAUSE_6_BIT 6 |
Definition at line 5136 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_CAUSE_7_BIT 7 |
Definition at line 5137 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_CAUSE_FIELD_WIDTH 1 |
Definition at line 5124 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_MULTIREG_COUNT 1 |
Definition at line 5125 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_REG_OFFSET 0xa1c |
Definition at line 5128 of file pinmux_regs.h.
| #define PINMUX_WKUP_CAUSE_REG_RESVAL 0x0u |
Definition at line 5129 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_FILTER_0_BIT 3 |
Definition at line 4914 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_MIODIO_0_BIT 4 |
Definition at line 4915 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_MODE_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_0_MODE_0_MASK, .index = PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET }) |
Definition at line 4907 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_MODE_0_MASK 0x7u |
Definition at line 4905 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET 0 |
Definition at line 4906 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_EDGE 0x2 |
Definition at line 4911 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_NEGEDGE 0x1 |
Definition at line 4910 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_POSEDGE 0x0 |
Definition at line 4909 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDHIGH 0x3 |
Definition at line 4912 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDLOW 0x4 |
Definition at line 4913 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_REG_OFFSET 0x9bc |
Definition at line 4903 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_0_REG_RESVAL 0x0u |
Definition at line 4904 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_1_FILTER_1_BIT 3 |
Definition at line 4924 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_1_MIODIO_1_BIT 4 |
Definition at line 4925 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_1_MODE_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_1_MODE_1_MASK, .index = PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET }) |
Definition at line 4922 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_1_MODE_1_MASK 0x7u |
Definition at line 4920 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET 0 |
Definition at line 4921 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_1_REG_OFFSET 0x9c0 |
Definition at line 4918 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_1_REG_RESVAL 0x0u |
Definition at line 4919 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_2_FILTER_2_BIT 3 |
Definition at line 4934 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_2_MIODIO_2_BIT 4 |
Definition at line 4935 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_2_MODE_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_2_MODE_2_MASK, .index = PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET }) |
Definition at line 4932 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_2_MODE_2_MASK 0x7u |
Definition at line 4930 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET 0 |
Definition at line 4931 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_2_REG_OFFSET 0x9c4 |
Definition at line 4928 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_2_REG_RESVAL 0x0u |
Definition at line 4929 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_3_FILTER_3_BIT 3 |
Definition at line 4944 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_3_MIODIO_3_BIT 4 |
Definition at line 4945 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_3_MODE_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_3_MODE_3_MASK, .index = PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET }) |
Definition at line 4942 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_3_MODE_3_MASK 0x7u |
Definition at line 4940 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET 0 |
Definition at line 4941 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_3_REG_OFFSET 0x9c8 |
Definition at line 4938 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_3_REG_RESVAL 0x0u |
Definition at line 4939 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_4_FILTER_4_BIT 3 |
Definition at line 4954 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_4_MIODIO_4_BIT 4 |
Definition at line 4955 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_4_MODE_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_4_MODE_4_MASK, .index = PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET }) |
Definition at line 4952 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_4_MODE_4_MASK 0x7u |
Definition at line 4950 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET 0 |
Definition at line 4951 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_4_REG_OFFSET 0x9cc |
Definition at line 4948 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_4_REG_RESVAL 0x0u |
Definition at line 4949 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_5_FILTER_5_BIT 3 |
Definition at line 4964 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_5_MIODIO_5_BIT 4 |
Definition at line 4965 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_5_MODE_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_5_MODE_5_MASK, .index = PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET }) |
Definition at line 4962 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_5_MODE_5_MASK 0x7u |
Definition at line 4960 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET 0 |
Definition at line 4961 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_5_REG_OFFSET 0x9d0 |
Definition at line 4958 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_5_REG_RESVAL 0x0u |
Definition at line 4959 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_6_FILTER_6_BIT 3 |
Definition at line 4974 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_6_MIODIO_6_BIT 4 |
Definition at line 4975 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_6_MODE_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_6_MODE_6_MASK, .index = PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET }) |
Definition at line 4972 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_6_MODE_6_MASK 0x7u |
Definition at line 4970 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET 0 |
Definition at line 4971 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_6_REG_OFFSET 0x9d4 |
Definition at line 4968 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_6_REG_RESVAL 0x0u |
Definition at line 4969 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_7_FILTER_7_BIT 3 |
Definition at line 4984 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_7_MIODIO_7_BIT 4 |
Definition at line 4985 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_7_MODE_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_7_MODE_7_MASK, .index = PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET }) |
Definition at line 4982 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_7_MODE_7_MASK 0x7u |
Definition at line 4980 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET 0 |
Definition at line 4981 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_7_REG_OFFSET 0x9d8 |
Definition at line 4978 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_7_REG_RESVAL 0x0u |
Definition at line 4979 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_OFFSET 0x9dc |
Definition at line 4992 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_RESVAL 0x0u |
Definition at line 4993 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET }) |
Definition at line 4996 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK 0xffu |
Definition at line 4994 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET 0 |
Definition at line 4995 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_OFFSET 0x9e0 |
Definition at line 5000 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_RESVAL 0x0u |
Definition at line 5001 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET }) |
Definition at line 5004 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK 0xffu |
Definition at line 5002 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET 0 |
Definition at line 5003 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_OFFSET 0x9e4 |
Definition at line 5008 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_RESVAL 0x0u |
Definition at line 5009 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET }) |
Definition at line 5012 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK 0xffu |
Definition at line 5010 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET 0 |
Definition at line 5011 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_OFFSET 0x9e8 |
Definition at line 5016 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_RESVAL 0x0u |
Definition at line 5017 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET }) |
Definition at line 5020 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK 0xffu |
Definition at line 5018 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET 0 |
Definition at line 5019 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_OFFSET 0x9ec |
Definition at line 5024 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_RESVAL 0x0u |
Definition at line 5025 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET }) |
Definition at line 5028 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK 0xffu |
Definition at line 5026 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET 0 |
Definition at line 5027 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_OFFSET 0x9f0 |
Definition at line 5032 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_RESVAL 0x0u |
Definition at line 5033 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET }) |
Definition at line 5036 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK 0xffu |
Definition at line 5034 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET 0 |
Definition at line 5035 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_OFFSET 0x9f4 |
Definition at line 5040 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_RESVAL 0x0u |
Definition at line 5041 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET }) |
Definition at line 5044 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK 0xffu |
Definition at line 5042 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET 0 |
Definition at line 5043 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_OFFSET 0x9f8 |
Definition at line 5048 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_RESVAL 0x0u |
Definition at line 5049 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET }) |
Definition at line 5052 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK 0xffu |
Definition at line 5050 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET 0 |
Definition at line 5051 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_MULTIREG_COUNT 8 |
Definition at line 4989 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_CNT_TH_TH_FIELD_WIDTH 8 |
Definition at line 4988 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_0_EN_0_BIT 0 |
Definition at line 4859 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_0_REG_OFFSET 0x99c |
Definition at line 4857 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_0_REG_RESVAL 0x0u |
Definition at line 4858 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_1_EN_1_BIT 0 |
Definition at line 4864 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_1_REG_OFFSET 0x9a0 |
Definition at line 4862 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_1_REG_RESVAL 0x0u |
Definition at line 4863 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_2_EN_2_BIT 0 |
Definition at line 4869 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_2_REG_OFFSET 0x9a4 |
Definition at line 4867 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_2_REG_RESVAL 0x0u |
Definition at line 4868 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_3_EN_3_BIT 0 |
Definition at line 4874 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET 0x9a8 |
Definition at line 4872 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_3_REG_RESVAL 0x0u |
Definition at line 4873 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_4_EN_4_BIT 0 |
Definition at line 4879 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_4_REG_OFFSET 0x9ac |
Definition at line 4877 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_4_REG_RESVAL 0x0u |
Definition at line 4878 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_5_EN_5_BIT 0 |
Definition at line 4884 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_5_REG_OFFSET 0x9b0 |
Definition at line 4882 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_5_REG_RESVAL 0x0u |
Definition at line 4883 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_6_EN_6_BIT 0 |
Definition at line 4889 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_6_REG_OFFSET 0x9b4 |
Definition at line 4887 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_6_REG_RESVAL 0x0u |
Definition at line 4888 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_7_EN_7_BIT 0 |
Definition at line 4894 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_7_REG_OFFSET 0x9b8 |
Definition at line 4892 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_7_REG_RESVAL 0x0u |
Definition at line 4893 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_EN_FIELD_WIDTH 1 |
Definition at line 4853 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_EN_MULTIREG_COUNT 8 |
Definition at line 4854 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_FILTER_FIELD_WIDTH 1 |
Definition at line 4898 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_MIODIO_FIELD_WIDTH 1 |
Definition at line 4899 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_MODE_FIELD_WIDTH 3 |
Definition at line 4897 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_MULTIREG_COUNT 8 |
Definition at line 4900 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_0_REG_OFFSET 0x9fc |
Definition at line 5060 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_0_REG_RESVAL 0x0u |
Definition at line 5061 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET }) |
Definition at line 5064 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK 0x3fu |
Definition at line 5062 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET 0 |
Definition at line 5063 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_1_REG_OFFSET 0xa00 |
Definition at line 5068 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_1_REG_RESVAL 0x0u |
Definition at line 5069 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET }) |
Definition at line 5072 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK 0x3fu |
Definition at line 5070 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET 0 |
Definition at line 5071 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_2_REG_OFFSET 0xa04 |
Definition at line 5076 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_2_REG_RESVAL 0x0u |
Definition at line 5077 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET }) |
Definition at line 5080 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK 0x3fu |
Definition at line 5078 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET 0 |
Definition at line 5079 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_3_REG_OFFSET 0xa08 |
Definition at line 5084 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_3_REG_RESVAL 0x0u |
Definition at line 5085 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET }) |
Definition at line 5088 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK 0x3fu |
Definition at line 5086 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET 0 |
Definition at line 5087 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_4_REG_OFFSET 0xa0c |
Definition at line 5092 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_4_REG_RESVAL 0x0u |
Definition at line 5093 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET }) |
Definition at line 5096 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK 0x3fu |
Definition at line 5094 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET 0 |
Definition at line 5095 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_5_REG_OFFSET 0xa10 |
Definition at line 5100 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_5_REG_RESVAL 0x0u |
Definition at line 5101 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET }) |
Definition at line 5104 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK 0x3fu |
Definition at line 5102 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET 0 |
Definition at line 5103 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_6_REG_OFFSET 0xa14 |
Definition at line 5108 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_6_REG_RESVAL 0x0u |
Definition at line 5109 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET }) |
Definition at line 5112 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK 0x3fu |
Definition at line 5110 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET 0 |
Definition at line 5111 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_7_REG_OFFSET 0xa18 |
Definition at line 5116 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_7_REG_RESVAL 0x0u |
Definition at line 5117 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET }) |
Definition at line 5120 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK 0x3fu |
Definition at line 5118 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET 0 |
Definition at line 5119 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_MULTIREG_COUNT 8 |
Definition at line 5057 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_PADSEL_SEL_FIELD_WIDTH 6 |
Definition at line 5056 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_0_EN_0_BIT 0 |
Definition at line 4815 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_0_REG_OFFSET 0x97c |
Definition at line 4813 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_0_REG_RESVAL 0x1u |
Definition at line 4814 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_1_EN_1_BIT 0 |
Definition at line 4820 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_1_REG_OFFSET 0x980 |
Definition at line 4818 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_1_REG_RESVAL 0x1u |
Definition at line 4819 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_2_EN_2_BIT 0 |
Definition at line 4825 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_2_REG_OFFSET 0x984 |
Definition at line 4823 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_2_REG_RESVAL 0x1u |
Definition at line 4824 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_3_EN_3_BIT 0 |
Definition at line 4830 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_3_REG_OFFSET 0x988 |
Definition at line 4828 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_3_REG_RESVAL 0x1u |
Definition at line 4829 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_4_EN_4_BIT 0 |
Definition at line 4835 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_4_REG_OFFSET 0x98c |
Definition at line 4833 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_4_REG_RESVAL 0x1u |
Definition at line 4834 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_5_EN_5_BIT 0 |
Definition at line 4840 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_5_REG_OFFSET 0x990 |
Definition at line 4838 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_5_REG_RESVAL 0x1u |
Definition at line 4839 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_6_EN_6_BIT 0 |
Definition at line 4845 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_6_REG_OFFSET 0x994 |
Definition at line 4843 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_6_REG_RESVAL 0x1u |
Definition at line 4844 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_7_EN_7_BIT 0 |
Definition at line 4850 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_7_REG_OFFSET 0x998 |
Definition at line 4848 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_7_REG_RESVAL 0x1u |
Definition at line 4849 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_EN_FIELD_WIDTH 1 |
Definition at line 4809 of file pinmux_regs.h.
| #define PINMUX_WKUP_DETECTOR_REGWEN_MULTIREG_COUNT 8 |
Definition at line 4810 of file pinmux_regs.h.