Software APIs
dt_rv_timer.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP rv_timer and top earlgrey.
10 */
11
12#include "hw/top/dt/dt_rv_timer.h"
13
14
15
16/**
17 * Description of instances.
18 */
19typedef struct dt_desc_rv_timer {
20 dt_instance_id_t inst_id; /**< Instance ID */
21 uint32_t reg_addr[kDtRvTimerRegBlockCount]; /**< Base address of each register block */
22 uint32_t mem_addr[kDtRvTimerMemoryCount]; /**< Base address of each memory */
23 uint32_t mem_size[kDtRvTimerMemoryCount]; /**< Size in bytes of each memory */
24 /**
25 * PLIC ID of the first IRQ of this instance
26 *
27 * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
28 */
30 /**
31 * Alert ID of the first Alert of this instance.
32 *
33 * This value is undefined if the block is not connected to the Alert Handler.
34 */
36 dt_clock_t clock[kDtRvTimerClockCount]; /**< Clock signal connected to each clock port */
37 dt_reset_t reset[kDtRvTimerResetCount]; /**< Reset signal connected to each reset port */
39
40
41
42
43static const dt_desc_rv_timer_t rv_timer_desc[kDtRvTimerCount] = {
44 [kDtRvTimer] = {
45 .inst_id = kDtInstanceIdRvTimer,
46 .reg_addr = {
47 [kDtRvTimerRegBlockCore] = 0x40100000,
48 },
49 .mem_addr = {
50 },
51 .mem_size = {
52 },
55 .clock = {
57 },
58 .reset = {
60 },
61 },
62};
63
64/**
65 * Return a pointer to the `dt_rv_timer_desc_t` structure of the requested
66 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
67 * the function) with the provided default value.
68 */
69#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_rv_timer_t)0 || (dt) >= kDtRvTimerCount) return (default); &rv_timer_desc[dt]; })
70
72 if (inst_id >= kDtInstanceIdRvTimer && inst_id <= kDtInstanceIdRvTimer) {
73 return (dt_rv_timer_t)(inst_id - kDtInstanceIdRvTimer);
74 }
75 return (dt_rv_timer_t)0;
76}
77
82
85 dt_rv_timer_reg_block_t reg_block) {
86 // Return a recognizable address in case of wrong argument.
87 return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
88}
89
93 // Return a recognizable address in case of wrong argument.
94 return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
95}
96
100 // Return an empty size in case of wrong argument.
101 return TRY_GET_DT(dt, 0)->mem_size[mem];
102}
103
105 dt_rv_timer_t dt,
106 dt_rv_timer_irq_t irq) {
107 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
108 if (first_irq == kDtPlicIrqIdNone) {
109 return kDtPlicIrqIdNone;
110 }
111 return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
112}
113
115 dt_rv_timer_t dt,
116 dt_plic_irq_id_t irq) {
117 dt_rv_timer_irq_t count = kDtRvTimerIrqCount;
118 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
119 if (first_irq == kDtPlicIrqIdNone) {
120 return count;
121 }
122 if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
123 return count;
124 }
125 return (dt_rv_timer_irq_t)(irq - first_irq);
126}
127
128
130 dt_rv_timer_t dt,
131 dt_rv_timer_alert_t alert) {
132 return (dt_alert_id_t)((uint32_t)rv_timer_desc[dt].first_alert + (uint32_t)alert);
133}
134
136 dt_rv_timer_t dt,
137 dt_alert_id_t alert) {
138 dt_rv_timer_alert_t count = kDtRvTimerAlertCount;
139 if (alert < rv_timer_desc[dt].first_alert || alert >= rv_timer_desc[dt].first_alert + (dt_alert_id_t)count) {
140 return count;
141 }
142 return (dt_rv_timer_alert_t)(alert - rv_timer_desc[dt].first_alert);
143}
144
145
146
148 dt_rv_timer_t dt,
150 // Return the first clock in case of invalid argument.
151 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
152}
153
155 dt_rv_timer_t dt,
157 const dt_rv_timer_reset_t count = kDtRvTimerResetCount;
158 if (rst >= count) {
159 return kDtResetUnknown;
160 }
161 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
162}
163
164