Registers

The RRAM controller maintains two separate access windows for the FIFOs. It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read).

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x3
• Reset mask: 0x7f

Fields

{"reg": [{"name": "wr_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "wr_lvl", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_lvl", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "op_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "corr1_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "corr2_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0x7f

Fields

{"reg": [{"name": "wr_empty", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "wr_lvl", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rd_full", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "rd_lvl", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "op_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "corr1_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "corr2_err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x7f

Fields

{"reg": [{"name": "wr_empty", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "wr_lvl", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rd_full", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "rd_lvl", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "op_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "corr1_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "corr2_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x80000000
• Reset mask: 0x8000001f

Fields

{"reg": [{"name": "recov_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_std_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_macro_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "recov_macro_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 26}, {"name": "regwen", "bits": 1, "attr": ["rw0c"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

DIS

Disable RRAM functionality

• Offset: 0x10
• Reset default: 0x99
• Reset mask: 0xff

Fields

{"reg": [{"name": "SW_DIS", "bits": 4, "attr": ["rw1s"], "rotate": 0}, {"name": "LOCAL_ESC_RELBL_ERR", "bits": 4, "attr": ["rw1s"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

DIS . LOCAL_ESC_RELBL_ERR

Enables local escalation for reliability errors. Once this config bit is set to any value other than MuBi4False, FAULT_STATUS.PHY_RELBL_ERR will disable the RRAM until the next reset. Otherwise FAULT_STATUS.PHY_RELBL_ERR is excluded from the local escalation, to deal with firmware selection during the boot process. The fatal_err alert is raised regardless of this setting. Since this register is rw1s instead of rw, this configuration cannot be reverted.

DIS . SW_DIS

Disables RRAM functionality completely. This is a shortcut mechanism used by the software to completely kill RRAM in case of emergency. Since this register is rw1s instead of rw, to disable, write the value MuBi4True to the register to disable the RRAM. Once disabled, RRAM functionality cannot be re-enabled until the next reset.

EXEC

Controls whether RRAM can be used for code execution fetches

• Offset: 0x14
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "EN", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INIT

Controller init register

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw1s"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_REGWEN

Controls the configurability of the CONTROL register. This register ensures the contents of CONTROL cannot be changed by software once a RRAM operation has begun. It unlocks whenever the existing RRAM operation completes, regardless of success or error.

• Offset: 0x1c
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CONTROL

Control register

• Offset: 0x20
• Reset default: 0x0
• Reset mask: 0x3ff0131
• Register enable: CTRL_REGWEN

Fields

{"reg": [{"name": "START", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "OP", "bits": 2, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "PARTITION", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "NUM", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

CONTROL . NUM

One fewer than the number of bus words the RRAM operation should read or write. For write operations, the number of bus words must be a multiple of 4. For example, to read 10 words, software should program this field with the value 9. To write 16 words, the software should program this field to 15.

CONTROL . PARTITION

When doing a read or write operation, selects either info or data partition for operation. When 0, select data partition - this is the portion of RRAM that is accessible both by the host and by the controller. When 1, select info partition - this is the portion of RRAM that is only accessible by the controller.

CONTROL . OP

RRAM operation selection

Other values are reserved.

CONTROL . START

Start RRAM transaction. This bit shall only be set at the same time or after the other fields of the CONTROL register and ADDR have been programmed.

ADDR

Address for RRAM operation

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0x1fffff
• Register enable: CTRL_REGWEN

Fields

{"reg": [{"name": "START", "bits": 21, "attr": ["rw"], "rotate": 0}, {"bits": 11}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ADDR . START

Start address of a RRAM transaction. This is a byte address relative to the RRAM only. I.e., an address of 0 will access address 0 of the requested partition.

For read operations, the RRAM controller will truncate to the closest, lower word aligned address. For example, if 0x13 is supplied, the controller will perform a read at address 0x10.

For write operations, the RRAM controller will truncate to the closest, lower RRAM-word (128b). For example, if 0x2F is supplied, the controller will perform a write at address 0x20.

REGION_CFG_REGWEN

Memory region registers configuration enable.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

REGION_CFG_REGWEN . REGION

Region register write enable. Once set to 0, it can no longer be configured to 1.

MP_REGION_CFG

Memory property configuration for data partition

• Reset default: 0x99999
• Reset mask: 0xfffff
• Register enable: REGION_CFG_REGWEN

Instances

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "WR_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

MP_REGION

Memory base and size configuration for data partition

• Reset default: 0x0
• Reset mask: 0xffffff
• Register enable: REGION_CFG_REGWEN

Instances

Fields

{"reg": [{"name": "BASE", "bits": 12, "attr": ["rw"], "rotate": 0}, {"name": "SIZE", "bits": 12, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DEFAULT_REGION

Default region properties

• Offset: 0xa0
• Reset default: 0x9999
• Reset mask: 0xffff

Fields

{"reg": [{"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "WR_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

INFO_REGWEN

Memory region registers configuration enable.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INFO_REGWEN . REGION

Info page write enable. Once set to 0, it can no longer be configured to 1.

INFO_PAGE_CFG

Memory property configuration for info partition. Unlike data partition, each page is individually configured.

• Reset default: 0x99999
• Reset mask: 0xfffff
• Register enable: INFO_REGWEN

Instances

Fields

{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "WR_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

EMUL_INFO_REGWEN

Emulated info region registers configuration enable. Subregions within a window are only considered once this is locked, see EMUL_INFO_SUBREGION.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EMUL_INFO_REGWEN . REGION

Region register write enable. Once set to 0, it can no longer be configured to 1.

EMUL_INFO_REGION

Base and size configuration for an emulated info page region (window). Unlike MP_REGION, this register carries no access permissions of its own. See EMUL_INFO_SUBREGION_CFG for per-subregion permissions. Host access to this window is always blocked in hardware. Once EN is set, any access to the window that is not covered by an enabled subregion is denied. Enabling this and locking it via EMUL_INFO_REGWEN is a precondition for using any subregions configured through EMUL_INFO_SUBREGION and EMUL_INFO_SUBREGION_CFG within this window.

• Reset default: 0x9000000
• Reset mask: 0xfffffff
• Register enable: EMUL_INFO_REGWEN

Instances

Fields

{"reg": [{"name": "BASE", "bits": 12, "attr": ["rw"], "rotate": 0}, {"name": "SIZE", "bits": 12, "attr": ["rw"], "rotate": 0}, {"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EMUL_INFO_REGION . EN

Window enabled. If enabled, accesses to the window that are not covered by an enabled subregion are denied. If two enabled windows overlap, the subregions of both windows are disabled and both windows are denied entirely. If disabled, neither the window nor any of its subregions is matched against any incoming transaction.

EMUL_INFO_REGION . SIZE

Region size, encoded as (number of pages - 1).

EMUL_INFO_REGION . BASE

Region base page. Note the granularity is page, not byte or word.

EMUL_INFO_SUBREGION_REGWEN

Emulated info subregion size registers configuration enable. Independent from EMUL_INFO_SUBREGION_CFG_REGWEN. A subregion’s placement and its permissions can be locked separately. A subregion is only considered once its placement is locked.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EMUL_INFO_SUBREGION_REGWEN . REGION

Subregion write enable. Once set to 0, it can no longer be configured to 1.

EMUL_INFO_SUBREGION

Subregions are configured with TOR (top of range) addressing, but relative to the window’s base. A subregion’s range runs from the prior subregion’s TOP plus one up to its own TOP. Configure subregions in increasing TOP order, locking each starting from the first subregion of its window. A subregion is enabled once all of the following hold. Its window is enabled via EMUL_INFO_REGION.EN and locked via EMUL_INFO_REGWEN. Its own placement and that of every lower-indexed subregion of its window are locked via EMUL_INFO_SUBREGION_REGWEN, i.e., the whole lock chain back to the first subregion of its window. Its TOP does not exceed its window’s SIZE. Its window does not overlap any other enabled window.

• Reset default: 0x0
• Reset mask: 0xff
• Register enable: EMUL_INFO_SUBREGION_REGWEN

Instances

Fields

{"reg": [{"name": "TOP", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EMUL_INFO_SUBREGION_CFG_REGWEN

Emulated info subregion permission registers configuration enable. Independent from EMUL_INFO_SUBREGION_REGWEN. A subregion’s permissions and its placement can be locked separately.

• Reset default: 0x1
• Reset mask: 0x1

Instances

Fields

{"reg": [{"name": "REGION", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EMUL_INFO_SUBREGION_CFG_REGWEN . REGION

Subregion write enable. Once set to 0, it can no longer be configured to 1.

EMUL_INFO_SUBREGION_CFG

Memory property configuration for an emulated info subregion. There is no separate EN field. Bits 3:0 are reserved, so RD_EN, WR_EN, SCRAMBLE_EN, and ECC_EN sit at the same bit positions as in MP_REGION_CFG and INFO_PAGE_CFG. See EMUL_INFO_SUBREGION for the full conditions under which a subregion is enabled.

• Reset default: 0x99990
• Reset mask: 0xffff0
• Register enable: EMUL_INFO_SUBREGION_CFG_REGWEN

Instances

Fields

{"reg": [{"bits": 4}, {"name": "RD_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "WR_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "SCRAMBLE_EN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

HW_INFO_CFG_OVERRIDE

HW interface info configuration rule overrides

• Offset: 0x274
• Reset default: 0x99
• Reset mask: 0xff

Fields

{"reg": [{"name": "SCRAMBLE_DIS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "ECC_DIS", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}}

OP_STATUS

RRAM Operation Status

• Offset: 0x278
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "err", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

STATUS

RRAM Controller Status

• Offset: 0x27c
• Reset default: 0xa
• Reset mask: 0x3f

Fields

{"reg": [{"name": "rd_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rd_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "wr_full", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "wr_empty", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "init_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "keys_valid", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

ERR_CODE

RRAM error code register. This register tabulates detailed error status of the RRAM. This is separate from OP_STATUS, which is used to indicate the current state of the software initiated RRAM operation.

Note, all errors in this register are considered recoverable errors, i.e., errors that could have been generated by software.

• Offset: 0x280
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "op_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "mp_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "rd_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "wr_err", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ERR_CODE . wr_err

RRAM write has an error. This could be a write integrity error, see STD_FAULT_STATUS. This is a synchronous error.

ERR_CODE . rd_err

RRAM read has an error. This could be a reliability ECC error or integrity error encountered during a software issued controller read, see STD_FAULT_STATUS. See ERR_ADDR for exact address. This is a synchronous error.

ERR_CODE . mp_err

RRAM access has encountered an access permission error. Please see ERR_ADDR for exact address. This is a synchronous error.

ERR_CODE . op_err

Software has supplied an undefined operation. See CONTROL.OP for list of valid operations. This error is also set if a software operation is started before the initialization has completed, see STATUS.INIT_DONE and STATUS.KEYS_VALID, or while software access is disabled from the start of the RMA entry process.

STD_FAULT_STATUS

This register tabulates standard fault status of the RRAM.

These represent errors that occur in the standard structures of the design. For example fsm integrity, counter integrity and tlul integrity.

• Offset: 0x284
• Reset default: 0x0
• Reset mask: 0x1fff

Fields

{"reg": [{"name": "reg_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lcmgr_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lcmgr_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_wr_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_fifo_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_fsm_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_cnt_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_arb_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ctrl_fsm_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ctrl_cnt_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ctrl_fifo_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

FAULT_STATUS

This register tabulates customized fault status of the RRAM.

These are errors that are impossible to have been caused by software or unrecoverable in nature.

All errors except for multi-bit ECC errors (FAULT_STATUS.PHY_RELBL_ERR). Once set, they remain set until reset.

• Offset: 0x288
• Reset default: 0x0
• Reset mask: 0x3fff

Fields

{"reg": [{"name": "lcmgr_op_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lcmgr_mp_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lcmgr_rd_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lcmgr_wr_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_op_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_mp_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_rd_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_wr_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "seed_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_relbl_err", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "phy_rd_intg_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "phy_rd_ctrl_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "spurious_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "host_gnt_err", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

FAULT_STATUS . host_gnt_err

A host transaction was granted with illegal properties.

FAULT_STATUS . spurious_done

The RRAM emitted an unexpected acknowledgement.

FAULT_STATUS . phy_rd_ctrl_err

The RRAM phy detected one of the following errors:

• a mismatch of command request integrity and command response integrity.
• a spurious valid.
• a spurious rram read request.

FAULT_STATUS . phy_rd_intg_err

The RRAM phy encountered an integrity error. The shadow response was not identical to the original response.

FAULT_STATUS . phy_relbl_err

The RRAM macro encountered a reliability ECC error that cannot be corrected.

Note that this error bit can be cleared to allow firmware dealing with multi-bit ECC errors during firmware selection and verification. After passing this stage, it is recommended that firmware classifies the corresponding alert as fatal on the receiver end, i.e, inside the alert handler. Clearing this bit does not revoke a local escalation it has already caused while DIS.LOCAL_ESC_RELBL_ERR was set.

FAULT_STATUS . seed_err

The seed reading process encountered an unexpected error.

FAULT_STATUS . otp_wr_err

The RRAM OTP interface encountered a write error. This could be a write integrity error, see STD_FAULT_STATUS for more details.

FAULT_STATUS . otp_rd_err

The RRAM OTP interface encountered a read error. This could be a reliability ECC error or an integrity ECC error encountered during a read, see STD_FAULT_STATUS for more details.

FAULT_STATUS . otp_mp_err

The RRAM OTP interface encountered a memory permission error.

FAULT_STATUS . otp_op_err

The RRAM OTP interface has supplied an undefined operation. See CONTROL.OP for list of valid operations.

FAULT_STATUS . lcmgr_wr_err

The RRAM life cycle management interface encountered a write error. This could be a write integrity error, see STD_FAULT_STATUS for more details.

FAULT_STATUS . lcmgr_rd_err

The RRAM life cycle management interface encountered a read error. This could be a reliability ECC error or an integrity ECC error encountered during a read, see STD_FAULT_STATUS for more details.

FAULT_STATUS . lcmgr_mp_err

The RRAM life cycle management interface encountered a memory permission error.

FAULT_STATUS . lcmgr_op_err

The RRAM life cycle management interface has supplied an undefined operation. See CONTROL.OP for list of valid operations.

ERR_ADDR

Synchronous error address

• Offset: 0x28c
• Reset default: 0x0
• Reset mask: 0x1fffff

Fields

{"reg": [{"name": "ERR_ADDR", "bits": 21, "attr": ["ro"], "rotate": 0}, {"bits": 11}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CORR1_ERR_CNT

Count of correctable single-bit ECC errors

• Offset: 0x290
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "val", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CORR2_ERR_CNT

Count of correctable double-bit ECC errors

• Offset: 0x294
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "val", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CORR1_ERR_LOC

Last address that was corrected by the ECC decoder with a single-bit error

• Offset: 0x298
• Reset default: 0x0
• Reset mask: 0x11fffff

Fields

{"reg": [{"name": "addr", "bits": 21, "attr": ["ro"], "rotate": 0}, {"bits": 3}, {"name": "part", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CORR2_ERR_LOC

Last address that was corrected by the ECC decoder with a double-bit error

• Offset: 0x29c
• Reset default: 0x0
• Reset mask: 0x11fffff

Fields

{"reg": [{"name": "addr", "bits": 21, "attr": ["ro"], "rotate": 0}, {"bits": 3}, {"name": "part", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PHY_STATUS

RRAM Phy Status

• Offset: 0x2a0
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "wr_busy", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "init_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

SCRATCH

RRAM Controller Scratch

• Offset: 0x2a4
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "data", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FIFO_LVL

Programmable depth where FIFOs should generate interrupts

• Offset: 0x2a8
• Reset default: 0xf0f
• Reset mask: 0x1f1f

Fields

{"reg": [{"name": "WR", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 3}, {"name": "RD", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FIFO_CLR

Clears RRAM controller FIFOs

• Offset: 0x2ac
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "WR", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RD", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CURR_FIFO_LVL

Current write and read fifo level

• Offset: 0x2b0
• Reset default: 0x0
• Reset mask: 0x1f1f

Fields

{"reg": [{"name": "WR", "bits": 5, "attr": ["ro"], "rotate": 0}, {"bits": 3}, {"name": "RD", "bits": 5, "attr": ["ro"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

wr_fifo

RRAM write FIFO.

The FIFO is 4 entries of 4B words. This FIFO can only be programmed by software after a write operation has been initiated via the CONTROL register. This ensures accidental programming of the write FIFO cannot lock up the system.

• Word Aligned Offset Range: 0x2b4to0x2b4
• Size (words): 1
• Access: wo
• Byte writes are not supported.

rd_fifo

RRAM read FIFO.

The FIFO is 16 entries of 4B words.

• Word Aligned Offset Range: 0x2b8to0x2b8
• Size (words): 1
• Access: ro
• Byte writes are not supported.