Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module rram_ctrl has the following hardware interfaces defined

Primary Clock: clk_i
Other Clocks: clk_otp_i
Bus Device Interfaces (TL-UL): core_tl, host_tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO: none

Inter-Module Signals

Port Name	Package::Struct	Type	Act	Width	Description
rram_macro	rram_ctrl_pkg::rram_macro	req_rsp	req	1
otp_key	otp_ctrl_pkg::nvm_otp_key	req_rsp	req	1
otp_macro	otp_ctrl_macro_pkg::otp_ctrl_macro	req_rsp	rsp	1	Data interface for the OTP macro.
lc_creator_seed_sw_rw_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_owner_seed_sw_rw_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_iso_part_sw_rd_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_iso_part_sw_wr_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_seed_hw_rd_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_escalate_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
rma_req	lc_ctrl_pkg::lc_tx	uni	rcv	1
rma_ack	lc_ctrl_pkg::lc_tx	uni	req	1
rma_seed	lc_ctrl_pkg::lc_nvm_rma_seed	uni	rcv	1
pwrmgr	pwrmgr_pkg::pwr_nvm	uni	req	1
keymgr	rram_ctrl_pkg::keymgr_rram	uni	req	1
core_tl	tlul_pkg::tl	req_rsp	rsp	1
host_tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts

Interrupt Name	Type	Description
wr_empty	Status	Write FIFO empty
wr_lvl	Status	Write FIFO drained to level
rd_full	Status	Read FIFO full
rd_lvl	Status	Read FIFO filled to level
op_done	Event	Operation complete
corr_err	Event	Correctable error encountered

Security Alerts

Alert Name	Description
recov_err	RRAM recoverable errors. Fired whenever a software initiated controller operation completes with any bit set in `ERR_CODE.`
fatal_std_err	RRAM standard fatal errors. Fired whenever any bit in `STD_FAULT_STATUS` is set.
fatal_err	RRAM fatal errors. Fired whenever any bit in `FAULT_STATUS` is set, including uncorrectable ECC errors. Note that this alert is not always fatal. The underlying error bits in the `FAULT_STATUS` register remain set until reset, meaning the alert keeps firing. This doesn’t hold for `FAULT_STATUS.PHY_RELBL_ERR.` To enable firmware dealing with multi-bit ECC errors during firmware selection and verification, these error bits can be cleared. After passing this stage, it is recommended that firmware classifies the corresponding alert as fatal on the receiver end, i.e, inside the alert handler.
fatal_macro_err	Fatal errors triggered inside the RRAM macro, including fatal TL-UL bus integrity faults of the test interface.
recov_macro_err	Recoverable errors triggered inside the RRAM macro.

Security Countermeasures

Countermeasure ID	Description
RRAM_CTRL.REG.BUS.INTEGRITY	End-to-end bus integrity scheme. Standard integrity protection to the register file
RRAM_CTRL.HOST.BUS.INTEGRITY	End-to-end bus integrity scheme. The integrity is added in rram_phy_rd and stored alongside the data in the read-buffer. From the read-buffer the integrity is passed through in u_tl_adapter_host to tl_host. The path from RRAM to the read-buffer is integrity protected through secondary read operation.
RRAM_CTRL.MEM.BUS.INTEGRITY	End-to-end bus integrity scheme. Integrity is added in rram_phy_rd and stored alongside the data in the read-buffer; for reads, the TL-UL requester is expected to check this integrity. For writes, integrity is checked in rram_phy_wr; software should perform a readback to fully verify a write completed correctly.
RRAM_CTRL.MEM.ADDR_INFECTION	The write data is XORed with its address in rram_phy_wr on every RRAM write operation. The XOR is then removed for every read operation. For host reads, the address is removed in u_tl_adapter_host. For all controller reads, the address is removed in u_rram_ctrl_rd.
RRAM_CTRL.SCRAMBLE.KEY.SIDELOAD	The scrambling key is sideloaded from OTP and thus unreadable by SW.
RRAM_CTRL.LC_CTRL.INTERSIG.MUBI	Life cycle control signals are used to control information partition access and RRAM debug access. See the documentation on the secret information partition, isolated information partitions, and JTAG connection for more details.
RRAM_CTRL.CTRL.CONFIG.REGWEN	Configurations cannot be changed when an operation is ongoing.
RRAM_CTRL.DATA_REGIONS.CONFIG.REGWEN	Each data region has a configurable REGWEN.
RRAM_CTRL.INFO_PAGE.CONFIG.REGWEN	Each info page has a configurable REGWEN.
RRAM_CTRL.MEM.CTRL.GLOBAL_ESC	Global escalation causes memory to no longer be accessible.
RRAM_CTRL.MEM.CTRL.LOCAL_ESC	A subset of fatal errors cause memory to no longer be accessible. This subset is defined in `STD_FAULT_STATUS.`
RRAM_CTRL.MEM_DISABLE.CONFIG.MUBI	Software control for RRAM disable is multibit. The register is `DIS.`
RRAM_CTRL.EXEC.CONFIG.REDUN	Software control for RRAM enable is 32-bit constant. The register is `EXEC.`
RRAM_CTRL.MEM.SCRAMBLE	The RRAM supports XEX scrambling. The cipher used is PRINCE. The scrambling scheme is enabled by software, please see RRAM scrambling in documentation for more details.
RRAM_CTRL.RMA_ENTRY.MEM.SEC_WIPE	RMA entry wipes RRAM memory and overwrites it with random data.
RRAM_CTRL.CTRL.FSM.SPARSE	The following controller FSMs are sparesly encoded: - rram_ctrl_lcmgr (RMA + seed FSM) - rram_ctrl_otp - rram_ctrl_arb - rram_ctrl_rd/wr
RRAM_CTRL.PHY_WR.FSM.SPARSE	The rram_phy_wr FSM is sparsely encoded.
RRAM_CTRL.CTR.REDUN	The following counters are redundantly encoded: - rram_ctrl_otp - rram_ctrl_rd/wr - rram_phy_wr This includes seed count and address count used during seed reading phase, as well as word count, page count and wipe index in RMA entry phase.
RRAM_CTRL.PHY_ARBITER.CTRL.REDUN	The phy arbiters for controller/host arbitration and in the shared scrambling module are redundant. The arbiters have two instances underneath that are constantly compared to each other.
RRAM_CTRL.PHY_HOST_GRANT.CTRL.CONSISTENCY	The host grant is consistency checked. If the host is ever granted with info partition access, it is an error. If the host is ever granted while no request has been sent, it is an error.
RRAM_CTRL.PHY_RSP.CTRL.CONSISTENCY	If the host or controller ever receive an unexpected transaction done signal, it is an error.
RRAM_CTRL.PHY_RD_RSP.CTRL.INTEGRITY	The following control flow errors are detected and result in an error: - data_valid_o is set while there is no pending request (meta_fifo empty). - data_valid_o is set while a verify operation completes. - A request is sent to the RRAM while no internal request is generated. - The integrity of the response in the read-buffer does not match the integrity of the current request in the meta fifo.
RRAM_CTRL.PHY_RD_BUF.CTRL.INTEGRITY	If the verify operation does not return the same data as the original read, it is an error.
RRAM_CTRL.FIFO.CTR.REDUN	The FIFO pointers of several FIFOs are implemented with duplicate counters.
RRAM_CTRL.HOST_TL_LC_GATE.FSM.SPARSE	The control FSM inside the TL-UL gating primitive is sparsely encoded.
RRAM_CTRL.WR_TL_LC_GATE.FSM.SPARSE	The control FSM inside the TL-UL gating primitive is sparsely encoded.
RRAM_CTRL.MEM.READBACK	Every RRAM read is issued twice (a shadow read). If the two results differ, it indicates the data was manipulated during the read process (e.g. by a fault injection attack), and a fatal alert is raised.
RRAM_CTRL.MEM.INTEGRITY	The RRAM macro computes ECC for every stored word. rram_ctrl controls whether ECC is enabled per region or info page (ecc_en), and captures the location and count of correctable errors in CORR_ERR_LOC/CORR_ERR_CNT.
RRAM_CTRL.OTP.MEM.INTEGRITY	Each OTP word is protected with an additional 8-bit Hamming(72,64) integrity syndrome, stored separately in the OTP integrity page, on top of the RRAM macro’s own ECC.