Enum opentitanlib::io::jtag::RiscvCsr
source · #[non_exhaustive]pub enum RiscvCsr {
Show 140 variants
MSTATUS,
MISA,
MIE,
MTVEC,
MCOUNTINHIBIT,
MHPMEVENT3,
MHPMEVENT4,
MHPMEVENT5,
MHPMEVENT6,
MHPMEVENT7,
MHPMEVENT8,
MHPMEVENT9,
MHPMEVENT10,
MHPMEVENT11,
MHPMEVENT12,
MHPMEVENT13,
MHPMEVENT14,
MHPMEVENT15,
MHPMEVENT16,
MHPMEVENT17,
MHPMEVENT18,
MHPMEVENT19,
MHPMEVENT20,
MHPMEVENT21,
MHPMEVENT22,
MHPMEVENT23,
MHPMEVENT24,
MHPMEVENT25,
MHPMEVENT26,
MHPMEVENT27,
MHPMEVENT28,
MHPMEVENT29,
MHPMEVENT30,
MHPMEVENT31,
MSCRATCH,
MEPC,
MCAUSE,
MTVAL,
MIP,
PMPCFG0,
PMPCFG1,
PMPCFG2,
PMPCFG3,
PMPADDR0,
PMPADDR1,
PMPADDR2,
PMPADDR3,
PMPADDR4,
PMPADDR5,
PMPADDR6,
PMPADDR7,
PMPADDR8,
PMPADDR9,
PMPADDR10,
PMPADDR11,
PMPADDR12,
PMPADDR13,
PMPADDR14,
PMPADDR15,
SCONTEXT,
MSECCFG,
MSECCFGH,
TSELECT,
TDATA1,
TDATA2,
TDATA3,
MCONTEXT,
MSCONTEXT,
DCSR,
DPC,
DSCRATCH0,
DSCRATCH1,
MCYCLE,
MINSTRET,
MHPMCOUNTER3,
MHPMCOUNTER4,
MHPMCOUNTER5,
MHPMCOUNTER6,
MHPMCOUNTER7,
MHPMCOUNTER8,
MHPMCOUNTER9,
MHPMCOUNTER10,
MHPMCOUNTER11,
MHPMCOUNTER12,
MHPMCOUNTER13,
MHPMCOUNTER14,
MHPMCOUNTER15,
MHPMCOUNTER16,
MHPMCOUNTER17,
MHPMCOUNTER18,
MHPMCOUNTER19,
MHPMCOUNTER20,
MHPMCOUNTER21,
MHPMCOUNTER22,
MHPMCOUNTER23,
MHPMCOUNTER24,
MHPMCOUNTER25,
MHPMCOUNTER26,
MHPMCOUNTER27,
MHPMCOUNTER28,
MHPMCOUNTER29,
MHPMCOUNTER30,
MHPMCOUNTER31,
MCYCLEH,
MINSTRETH,
MHPMCOUNTER3H,
MHPMCOUNTER4H,
MHPMCOUNTER5H,
MHPMCOUNTER6H,
MHPMCOUNTER7H,
MHPMCOUNTER8H,
MHPMCOUNTER9H,
MHPMCOUNTER10H,
MHPMCOUNTER11H,
MHPMCOUNTER12H,
MHPMCOUNTER13H,
MHPMCOUNTER14H,
MHPMCOUNTER15H,
MHPMCOUNTER16H,
MHPMCOUNTER17H,
MHPMCOUNTER18H,
MHPMCOUNTER19H,
MHPMCOUNTER20H,
MHPMCOUNTER21H,
MHPMCOUNTER22H,
MHPMCOUNTER23H,
MHPMCOUNTER24H,
MHPMCOUNTER25H,
MHPMCOUNTER26H,
MHPMCOUNTER27H,
MHPMCOUNTER28H,
MHPMCOUNTER29H,
MHPMCOUNTER30H,
MHPMCOUNTER31H,
MVENDORID,
MARCHID,
MIMPID,
MHARTID,
CPUCTRL,
SECURESEED,
}
Expand description
List of useful RISC-V control and status registers
Variants (Non-exhaustive)§
This enum is marked as non-exhaustive
Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.
MSTATUS
MISA
MIE
MTVEC
MCOUNTINHIBIT
MHPMEVENT3
MHPMEVENT4
MHPMEVENT5
MHPMEVENT6
MHPMEVENT7
MHPMEVENT8
MHPMEVENT9
MHPMEVENT10
MHPMEVENT11
MHPMEVENT12
MHPMEVENT13
MHPMEVENT14
MHPMEVENT15
MHPMEVENT16
MHPMEVENT17
MHPMEVENT18
MHPMEVENT19
MHPMEVENT20
MHPMEVENT21
MHPMEVENT22
MHPMEVENT23
MHPMEVENT24
MHPMEVENT25
MHPMEVENT26
MHPMEVENT27
MHPMEVENT28
MHPMEVENT29
MHPMEVENT30
MHPMEVENT31
MSCRATCH
MEPC
MCAUSE
MTVAL
MIP
PMPCFG0
PMPCFG1
PMPCFG2
PMPCFG3
PMPADDR0
PMPADDR1
PMPADDR2
PMPADDR3
PMPADDR4
PMPADDR5
PMPADDR6
PMPADDR7
PMPADDR8
PMPADDR9
PMPADDR10
PMPADDR11
PMPADDR12
PMPADDR13
PMPADDR14
PMPADDR15
SCONTEXT
MSECCFG
MSECCFGH
TSELECT
TDATA1
TDATA2
TDATA3
MCONTEXT
MSCONTEXT
DCSR
DPC
DSCRATCH0
DSCRATCH1
MCYCLE
MINSTRET
MHPMCOUNTER3
MHPMCOUNTER4
MHPMCOUNTER5
MHPMCOUNTER6
MHPMCOUNTER7
MHPMCOUNTER8
MHPMCOUNTER9
MHPMCOUNTER10
MHPMCOUNTER11
MHPMCOUNTER12
MHPMCOUNTER13
MHPMCOUNTER14
MHPMCOUNTER15
MHPMCOUNTER16
MHPMCOUNTER17
MHPMCOUNTER18
MHPMCOUNTER19
MHPMCOUNTER20
MHPMCOUNTER21
MHPMCOUNTER22
MHPMCOUNTER23
MHPMCOUNTER24
MHPMCOUNTER25
MHPMCOUNTER26
MHPMCOUNTER27
MHPMCOUNTER28
MHPMCOUNTER29
MHPMCOUNTER30
MHPMCOUNTER31
MCYCLEH
MINSTRETH
MHPMCOUNTER3H
MHPMCOUNTER4H
MHPMCOUNTER5H
MHPMCOUNTER6H
MHPMCOUNTER7H
MHPMCOUNTER8H
MHPMCOUNTER9H
MHPMCOUNTER10H
MHPMCOUNTER11H
MHPMCOUNTER12H
MHPMCOUNTER13H
MHPMCOUNTER14H
MHPMCOUNTER15H
MHPMCOUNTER16H
MHPMCOUNTER17H
MHPMCOUNTER18H
MHPMCOUNTER19H
MHPMCOUNTER20H
MHPMCOUNTER21H
MHPMCOUNTER22H
MHPMCOUNTER23H
MHPMCOUNTER24H
MHPMCOUNTER25H
MHPMCOUNTER26H
MHPMCOUNTER27H
MHPMCOUNTER28H
MHPMCOUNTER29H
MHPMCOUNTER30H
MHPMCOUNTER31H
MVENDORID
MARCHID
MIMPID
MHARTID
CPUCTRL
SECURESEED
Implementations§
Trait Implementations§
source§impl<'de> Deserialize<'de> for RiscvCsr
impl<'de> Deserialize<'de> for RiscvCsr
source§fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where
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fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where __D: Deserializer<'de>,
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impl Copy for RiscvCsr
Auto Trait Implementations§
impl RefUnwindSafe for RiscvCsr
impl Send for RiscvCsr
impl Sync for RiscvCsr
impl Unpin for RiscvCsr
impl UnwindSafe for RiscvCsr
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