10 #include "sw/device/lib/runtime/irq.h"
12 #include "sw/device/lib/testing/rv_plic_testutils.h"
13 #include "sw/device/lib/testing/sysrst_ctrl_testutils.h"
14 #include "sw/device/lib/testing/test_framework/check.h"
15 #include "sw/device/lib/testing/test_framework/ottf_console.h"
17 #include "sw/device/lib/testing/test_framework/ottf_utils.h"
23 OTTF_DEFINE_TEST_CONFIG(.enable_uart_flow_control =
true);
25 static dif_sysrst_ctrl_t sysrst_ctrl;
26 static dif_rv_plic_t plic;
29 kCurrentTestPhaseTimeoutUsecDV = 20,
30 kCurrentTestPhaseTimeoutUsecReal = 1000000,
34 static volatile bool irq_triggered;
43 static volatile const uint8_t kCurrentTestPhaseDV = 0;
44 static volatile uint8_t kCurrentTestPhaseReal = 0xff;
49 kOutputNumMioPads = 0x6,
75 void test_phase_sync(
void) {
76 test_status_set(kTestStatusInTest);
77 test_status_set(kTestStatusInWfi);
84 void sysrst_ctrl_input_change_detect(
86 const uint32_t kCurrentTestPhaseTimeoutUsec =
88 : kCurrentTestPhaseTimeoutUsecReal;
90 ? &kCurrentTestPhaseDV
91 : &kCurrentTestPhaseReal;
93 irq_triggered =
false;
94 LOG_INFO(
"Wait for test to start: want phase %d", phase);
95 OTTF_WAIT_FOR(phase == *kCurrentTestPhase, kCurrentTestPhaseTimeoutUsec);
102 .debounce_time_threshold = 1,
108 CHECK_DIF_OK(dif_sysrst_ctrl_irq_set_enabled(
114 OTTF_WAIT_FOR(phase == *kCurrentTestPhase, kCurrentTestPhaseTimeoutUsec);
117 CHECK(!irq_triggered,
"The interrupt is triggered during input glitch.");
118 LOG_INFO(
"Tell host we did not detect the glitch");
121 ATOMIC_WAIT_FOR_INTERRUPT(irq_triggered);
126 CHECK(causes == expected_key_intr_src,
"Intr cause do not match: %d vs %d!",
127 causes, (
int)expected_key_intr_src);
138 LOG_INFO(
"Tell host to finish the test");
148 uint32_t combo_keys) {
149 const uint32_t kCurrentTestPhaseTimeoutUsec =
151 : kCurrentTestPhaseTimeoutUsecReal;
153 ? &kCurrentTestPhaseDV
154 : &kCurrentTestPhaseReal;
156 irq_triggered =
false;
158 OTTF_WAIT_FOR(phase == *kCurrentTestPhase, kCurrentTestPhaseTimeoutUsec);
160 LOG_INFO(
"configure sysrst interrupt");
165 .detection_time_threshold = 1,
167 .embedded_controller_reset_duration = 1,
170 &sysrst_ctrl, key_combo, sysrst_ctrl_key_combo_config));
173 CHECK_DIF_OK(dif_sysrst_ctrl_irq_set_enabled(
179 OTTF_WAIT_FOR(phase == *kCurrentTestPhase, kCurrentTestPhaseTimeoutUsec);
182 CHECK(!irq_triggered,
"The interrupt is triggered during input glitch.");
183 LOG_INFO(
"tell host we did not detect the glitch");
187 ATOMIC_WAIT_FOR_INTERRUPT(irq_triggered);
188 LOG_INFO(
"interrupt triggered, checks causes");
192 CHECK(causes == key_combo,
"Intr cause do not match: %d vs %d!", causes,
199 sysrst_ctrl_key_combo_config.
keys = 0;
201 &sysrst_ctrl, key_combo, sysrst_ctrl_key_combo_config));
204 LOG_INFO(
"Tell host to finish the test");
212 void ottf_external_isr(uint32_t *exc_info) {
220 switch (peripheral) {
222 if (!ottf_console_flow_control_isr(exc_info)) {
229 dif_sysrst_ctrl_irq_t irq =
230 (dif_sysrst_ctrl_irq_t)(plic_irq_id -
233 CHECK(irq == kDifSysrstCtrlIrqEventDetected);
234 CHECK_DIF_OK(dif_sysrst_ctrl_irq_set_enabled(&sysrst_ctrl, irq,
236 irq_triggered =
true;
248 CHECK(
false,
"Unexpected external IRQ %d", plic_irq_id);
253 irq_global_ctrl(
true);
254 irq_external_ctrl(
true);
259 CHECK_DIF_OK(dif_rv_plic_init(plic_base_addr, &plic));
262 rv_plic_testutils_irq_range_enable(
267 CHECK_DIF_OK(dif_sysrst_ctrl_init(
273 CHECK_DIF_OK(dif_pinmux_init(
278 sysrst_ctrl_testutils_setup_dio(&pinmux);
280 sysrst_ctrl_testutils_release_dio(&sysrst_ctrl,
true,
true);
282 sysrst_ctrl_testutils_set_ec_rst_pulse_width(&sysrst_ctrl, 0);
286 for (
int i = 0; i < kOutputNumMioPads; ++i) {
295 sysrst_ctrl_input_change_detect(i);
303 uint32_t combo_keys_1 =
317 test_status_set(kTestStatusInTest);