racl_ctrl_regs.h

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/**
 * @file
 * @brief Generated register defines for racl_ctrl
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _RACL_CTRL_REG_DEFS_
#define _RACL_CTRL_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of alerts
#define RACL_CTRL_PARAM_NUM_ALERTS 2
 
// Register width
#define RACL_CTRL_PARAM_REG_WIDTH 32
 
// Read and write policy for ALL_RD_WR
#define RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_REG_OFFSET 0x0
#define RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_REG_RESVAL 0x70007u
#define RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_READ_PERM_MASK 0xffffu
#define RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_READ_PERM_OFFSET 0
#define RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_READ_PERM_FIELD \
  ((bitfield_field32_t) { .mask = RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_READ_PERM_MASK, .index = RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_READ_PERM_OFFSET })
#define RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_WRITE_PERM_MASK 0xffffu
#define RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_WRITE_PERM_OFFSET 16
#define RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_WRITE_PERM_FIELD \
  ((bitfield_field32_t) { .mask = RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_WRITE_PERM_MASK, .index = RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_WRITE_PERM_OFFSET })
 
// Read and write policy for ROT_PRIVATE
#define RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_REG_OFFSET 0x8
#define RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_REG_RESVAL 0x10001u
#define RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_READ_PERM_MASK 0xffffu
#define RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_READ_PERM_OFFSET 0
#define RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_READ_PERM_FIELD \
  ((bitfield_field32_t) { .mask = RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_READ_PERM_MASK, .index = RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_READ_PERM_OFFSET })
#define RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_WRITE_PERM_MASK 0xffffu
#define RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_WRITE_PERM_OFFSET 16
#define RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_WRITE_PERM_FIELD \
  ((bitfield_field32_t) { .mask = RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_WRITE_PERM_MASK, .index = RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_WRITE_PERM_OFFSET })
 
// Read and write policy for SOC_ROT
#define RACL_CTRL_POLICY_SOC_ROT_SHADOWED_REG_OFFSET 0x10
#define RACL_CTRL_POLICY_SOC_ROT_SHADOWED_REG_RESVAL 0x50005u
#define RACL_CTRL_POLICY_SOC_ROT_SHADOWED_READ_PERM_MASK 0xffffu
#define RACL_CTRL_POLICY_SOC_ROT_SHADOWED_READ_PERM_OFFSET 0
#define RACL_CTRL_POLICY_SOC_ROT_SHADOWED_READ_PERM_FIELD \
  ((bitfield_field32_t) { .mask = RACL_CTRL_POLICY_SOC_ROT_SHADOWED_READ_PERM_MASK, .index = RACL_CTRL_POLICY_SOC_ROT_SHADOWED_READ_PERM_OFFSET })
#define RACL_CTRL_POLICY_SOC_ROT_SHADOWED_WRITE_PERM_MASK 0xffffu
#define RACL_CTRL_POLICY_SOC_ROT_SHADOWED_WRITE_PERM_OFFSET 16
#define RACL_CTRL_POLICY_SOC_ROT_SHADOWED_WRITE_PERM_FIELD \
  ((bitfield_field32_t) { .mask = RACL_CTRL_POLICY_SOC_ROT_SHADOWED_WRITE_PERM_MASK, .index = RACL_CTRL_POLICY_SOC_ROT_SHADOWED_WRITE_PERM_OFFSET })
 
// Interrupt State Register
#define RACL_CTRL_INTR_STATE_REG_OFFSET 0xe8
#define RACL_CTRL_INTR_STATE_REG_RESVAL 0x0u
#define RACL_CTRL_INTR_STATE_RACL_ERROR_BIT 0
 
// Interrupt Enable Register
#define RACL_CTRL_INTR_ENABLE_REG_OFFSET 0xec
#define RACL_CTRL_INTR_ENABLE_REG_RESVAL 0x0u
#define RACL_CTRL_INTR_ENABLE_IE_BIT 0
 
// Interrupt Test Register
#define RACL_CTRL_INTR_TEST_REG_OFFSET 0xf0
#define RACL_CTRL_INTR_TEST_REG_RESVAL 0x0u
#define RACL_CTRL_INTR_TEST_RACL_ERROR_BIT 0
 
// Alert Test Register.
#define RACL_CTRL_ALERT_TEST_REG_OFFSET 0xf4
#define RACL_CTRL_ALERT_TEST_REG_RESVAL 0x0u
#define RACL_CTRL_ALERT_TEST_FATAL_FAULT_BIT 0
#define RACL_CTRL_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_BIT 1
 
// Error logging registers
#define RACL_CTRL_ERROR_LOG_REG_OFFSET 0xf8
#define RACL_CTRL_ERROR_LOG_REG_RESVAL 0x0u
#define RACL_CTRL_ERROR_LOG_VALID_BIT 0
#define RACL_CTRL_ERROR_LOG_OVERFLOW_BIT 1
#define RACL_CTRL_ERROR_LOG_READ_ACCESS_BIT 2
#define RACL_CTRL_ERROR_LOG_ROLE_MASK 0xfu
#define RACL_CTRL_ERROR_LOG_ROLE_OFFSET 3
#define RACL_CTRL_ERROR_LOG_ROLE_FIELD \
  ((bitfield_field32_t) { .mask = RACL_CTRL_ERROR_LOG_ROLE_MASK, .index = RACL_CTRL_ERROR_LOG_ROLE_OFFSET })
#define RACL_CTRL_ERROR_LOG_CTN_UID_MASK 0x1fu
#define RACL_CTRL_ERROR_LOG_CTN_UID_OFFSET 7
#define RACL_CTRL_ERROR_LOG_CTN_UID_FIELD \
  ((bitfield_field32_t) { .mask = RACL_CTRL_ERROR_LOG_CTN_UID_MASK, .index = RACL_CTRL_ERROR_LOG_CTN_UID_OFFSET })
 
// Contains the address on which a RACL violation occurred.
#define RACL_CTRL_ERROR_LOG_ADDRESS_REG_OFFSET 0xfc
#define RACL_CTRL_ERROR_LOG_ADDRESS_REG_RESVAL 0x0u
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _RACL_CTRL_REG_DEFS_
// End generated register defines for racl_ctrl