Software APIs
pwrmgr_random_sleep_power_glitch_reset_test.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include <assert.h>
6 #include <limits.h>
7 #include <stdbool.h>
8 #include <stdint.h>
9 
10 #include "dt/dt_adc_ctrl.h"
11 #include "sw/device/lib/base/abs_mmio.h"
12 #include "sw/device/lib/base/math.h"
13 #include "sw/device/lib/base/mmio.h"
14 #include "sw/device/lib/dif/dif_alert_handler.h"
15 #include "sw/device/lib/dif/dif_aon_timer.h"
16 #include "sw/device/lib/dif/dif_flash_ctrl.h"
17 #include "sw/device/lib/dif/dif_pinmux.h"
18 #include "sw/device/lib/dif/dif_pwrmgr.h"
19 #include "sw/device/lib/dif/dif_rstmgr.h"
20 #include "sw/device/lib/dif/dif_rv_plic.h"
21 #include "sw/device/lib/dif/dif_rv_timer.h"
22 #include "sw/device/lib/dif/dif_sysrst_ctrl.h"
23 #include "sw/device/lib/runtime/irq.h"
24 #include "sw/device/lib/runtime/log.h"
25 #include "sw/device/lib/testing/alert_handler_testutils.h"
26 #include "sw/device/lib/testing/aon_timer_testutils.h"
27 #include "sw/device/lib/testing/flash_ctrl_testutils.h"
28 #include "sw/device/lib/testing/nv_counter_testutils.h"
29 #include "sw/device/lib/testing/pwrmgr_testutils.h"
30 #include "sw/device/lib/testing/rstmgr_testutils.h"
31 #include "sw/device/lib/testing/rv_plic_testutils.h"
32 #include "sw/device/lib/testing/test_framework/FreeRTOSConfig.h"
33 #include "sw/device/lib/testing/test_framework/check.h"
34 #include "sw/device/lib/testing/test_framework/ottf_main.h"
35 
36 #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
37 
38 OTTF_DEFINE_TEST_CONFIG();
39 static volatile const uint8_t RST_IDX[12] = {0, 1, 2, 3, 4, 5,
40  6, 7, 8, 9, 10, 11};
41 static const uint32_t kPlicTarget = kTopEarlgreyPlicTargetIbex0;
42 
43 /**
44  * Objects to access the peripherals used in this test via dif API.
45  */
46 static dif_flash_ctrl_state_t flash_ctrl;
47 static dif_rv_plic_t plic;
48 static dif_alert_handler_t alert_handler;
49 static dif_aon_timer_t aon_timer;
50 static dif_pwrmgr_t pwrmgr;
51 static dif_rstmgr_t rstmgr;
52 
53 static const dt_adc_ctrl_t kAdcCtrlDt = 0;
54 static_assert(kDtAdcCtrlCount == 1, "this test expects an adc_ctrl");
55 static const dt_rstmgr_t kRstmgrDt = 0;
56 static_assert(kDtRstmgrCount == 1, "this test expects a rstmgr");
57 static const dt_pwrmgr_t kPwrmgrDt = 0;
58 static_assert(kDtPwrmgrCount == 1, "this test expects a pwrmgr");
59 static const dt_aon_timer_t kAonTimerDt = 0;
60 static_assert(kDtAonTimerCount == 1, "this test expects an aon_timer");
61 static const dt_rv_plic_t kRvPlicDt = 0;
62 static_assert(kDtRvPlicCount >= 1, "this test expects at least one rv_plic");
63 static const dt_flash_ctrl_t kFlashCtrlDt = 0;
64 static_assert(kDtFlashCtrlCount >= 1,
65  "this test expects at least one flash_ctrl");
66 static const dt_alert_handler_t kAlertHandlerDt = 0;
67 static_assert(kDtAlertHandlerCount == 1,
68  "this library expects exactly one alert_handler");
69 
70 dif_pwrmgr_request_sources_t aon_timer_wakeup_sources;
71 dif_pwrmgr_request_sources_t adc_ctrl_wakeup_sources;
72 dif_pwrmgr_request_sources_t all_wakeup_sources;
73 dif_pwrmgr_request_sources_t wdog_reset_sources;
74 
75 /**
76  * Program the alert handler to escalate on alerts upto phase 2 (i.e. reset) but
77  * the phase 1 (i.e. wipe secrets) should occur and last during the time the
78  * wdog is programed to bark.
79  */
80 enum {
81  kWdogBarkMicros = 3 * 100, // 300 us
82  kWdogBiteMicros = 4 * 100, // 400 us
83  kEscalationPhase0Micros = 1 * 100, // 100 us
84  // The cpu value is slightly larger as the busy_spin_micros
85  // routine cycle count comes out slightly smaller due to the
86  // fact that it does not divide by exactly 1M
87  // see sw/device/lib/runtime/hart.c
88  kEscalationPhase0MicrosCpu = kEscalationPhase0Micros + 20, // 120 us
89  kEscalationPhase1Micros = 5 * 100, // 500 us
90  kEscalationPhase2Micros = 50, // 50 us
91 };
92 
93 static_assert(
94  kWdogBarkMicros < kWdogBiteMicros &&
95  kWdogBarkMicros > kEscalationPhase0Micros &&
96  kWdogBarkMicros < (kEscalationPhase0Micros + kEscalationPhase1Micros) &&
97  kWdogBiteMicros < (kEscalationPhase0Micros + kEscalationPhase1Micros),
98  "The wdog bark and bite shall happens during the escalation phase 1");
99 
100 /**
101  * External ISR.
102  *
103  * Handles all peripheral interrupts on Ibex. PLIC asserts an external interrupt
104  * line to the CPU, which results in a call to this OTTF ISR. This ISR
105  * overrides the default OTTF implementation.
106  */
107 void ottf_external_isr(uint32_t *exc_info) {
108  top_earlgrey_plic_peripheral_t peripheral;
109  dif_rv_plic_irq_id_t irq_id;
110  uint32_t irq = 0;
111  uint32_t alert = 0;
112 
113  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic, kPlicTarget, &irq_id));
114 
115  peripheral = (top_earlgrey_plic_peripheral_t)
116  top_earlgrey_plic_interrupt_for_peripheral[irq_id];
117 
118  if (peripheral == kTopEarlgreyPlicPeripheralAonTimerAon) {
119  irq =
120  (dif_aon_timer_irq_t)(irq_id -
121  (dif_rv_plic_irq_id_t)
122  kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired);
123 
124  // Stops escalation process.
125  CHECK_DIF_OK(dif_alert_handler_escalation_clear(&alert_handler,
126  kDifAlertHandlerClassA));
127  CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(&aon_timer, irq));
128 
129  CHECK(irq != kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark,
130  "AON Timer Wdog should not bark");
131 
132  } else if (peripheral == kTopEarlgreyPlicPeripheralAlertHandler) {
133  irq = (dif_rv_plic_irq_id_t)(irq_id -
134  (dif_rv_plic_irq_id_t)
135  kTopEarlgreyPlicIrqIdAlertHandlerClassa);
136 
137  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(&alert_handler, alert));
138 
139  dif_alert_handler_class_state_t state;
140  CHECK_DIF_OK(dif_alert_handler_get_class_state(
141  &alert_handler, kDifAlertHandlerClassA, &state));
142 
143  CHECK(state == kDifAlertHandlerClassStatePhase0, "Wrong phase %d", state);
144 
145  CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(&alert_handler, irq));
146  }
147 
148  // Complete the IRQ by writing the IRQ source to the Ibex specific CC
149  // register.
150  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic, kPlicTarget, irq_id));
151 }
152 
153 /**
154  * Initialize the peripherals used in this test.
155  */
156 void init_peripherals(void) {
157  // Initialize pwrmgr.
158  CHECK_DIF_OK(dif_pwrmgr_init_from_dt(kPwrmgrDt, &pwrmgr));
159 
160  // Initialize rstmgr to check the reset reason.
161  CHECK_DIF_OK(dif_rstmgr_init_from_dt(kRstmgrDt, &rstmgr));
162 
163  // Initialize aon timer to use the wdog.
164  CHECK_DIF_OK(dif_aon_timer_init_from_dt(kAonTimerDt, &aon_timer));
165  CHECK_DIF_OK(dif_pwrmgr_find_request_source(
166  &pwrmgr, kDifPwrmgrReqTypeWakeup, dt_aon_timer_instance_id(kAonTimerDt),
167  kDtAonTimerWakeupWkupReq, &aon_timer_wakeup_sources));
168 
169  // Initialize flash_ctrl
170  CHECK_DIF_OK(dif_flash_ctrl_init_state_from_dt(&flash_ctrl, kFlashCtrlDt));
171 
172  // Initialize plic.
173  CHECK_DIF_OK(dif_rv_plic_init_from_dt(kRvPlicDt, &plic));
174 
175  rv_plic_testutils_irq_range_enable(
176  &plic, kPlicTarget, kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired,
177  kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark);
178 
179  // Initialize alert handler.
180  CHECK_DIF_OK(dif_alert_handler_init_from_dt(kAlertHandlerDt, &alert_handler));
181 
182  // Other wakeups.
183  CHECK_DIF_OK(dif_pwrmgr_find_request_source(
184  &pwrmgr, kDifPwrmgrReqTypeWakeup, dt_adc_ctrl_instance_id(kAdcCtrlDt),
185  kDtAdcCtrlWakeupWkupReq, &adc_ctrl_wakeup_sources));
186  CHECK_DIF_OK(dif_pwrmgr_find_request_source(
187  &pwrmgr, kDifPwrmgrReqTypeReset, dt_aon_timer_instance_id(kDtAonTimerAon),
188  kDtAonTimerResetReqAonTimer, &wdog_reset_sources));
189  CHECK_DIF_OK(dif_pwrmgr_get_all_request_sources(
190  &pwrmgr, kDifPwrmgrReqTypeWakeup, &all_wakeup_sources));
191 }
192 
193 /**
194  * Program the alert handler to escalate on alerts upto phase 2 (i.e. reset) but
195  * the phase 1 (i.e. wipe secrets) should occur and last during the time the
196  * wdog is programed to bark.
197  */
198 static void alert_handler_config(void) {
199  dif_alert_handler_alert_t alerts[] = {kTopEarlgreyAlertIdPwrmgrAonFatalFault};
200  dif_alert_handler_class_t alert_classes[] = {kDifAlertHandlerClassA};
201 
202  uint32_t cycles[3] = {0};
203  CHECK_STATUS_OK(alert_handler_testutils_get_cycles_from_us(
204  kEscalationPhase0Micros, &cycles[0]));
205  CHECK_STATUS_OK(alert_handler_testutils_get_cycles_from_us(
206  kEscalationPhase1Micros, &cycles[1]));
207  CHECK_STATUS_OK(alert_handler_testutils_get_cycles_from_us(
208  kEscalationPhase2Micros, &cycles[2]));
209 
210  dif_alert_handler_escalation_phase_t esc_phases[] = {
211  {.phase = kDifAlertHandlerClassStatePhase0,
212  .signal = 0,
213  .duration_cycles =
214  cycles[0] * alert_handler_testutils_cycle_rescaling_factor()},
215  {.phase = kDifAlertHandlerClassStatePhase1,
216  .signal = 1,
217  .duration_cycles =
218  cycles[1] * alert_handler_testutils_cycle_rescaling_factor()},
219  {.phase = kDifAlertHandlerClassStatePhase2,
220  .signal = 3,
221  .duration_cycles =
222  cycles[2] * alert_handler_testutils_cycle_rescaling_factor()}};
223 
224  dif_alert_handler_class_config_t class_config[] = {{
225  .auto_lock_accumulation_counter = kDifToggleDisabled,
226  .accumulator_threshold = 0,
227  .irq_deadline_cycles =
228  cycles[0] * alert_handler_testutils_cycle_rescaling_factor(),
229  .escalation_phases = esc_phases,
230  .escalation_phases_len = ARRAYSIZE(esc_phases),
231  .crashdump_escalation_phase = kDifAlertHandlerClassStatePhase3,
232  }};
233 
234  dif_alert_handler_class_t classes[] = {kDifAlertHandlerClassA};
235  dif_alert_handler_config_t config = {
236  .alerts = alerts,
237  .alert_classes = alert_classes,
238  .alerts_len = ARRAYSIZE(alerts),
239  .classes = classes,
240  .class_configs = class_config,
241  .classes_len = ARRAYSIZE(class_config),
242  .ping_timeout = kAlertHandlerTestutilsDefaultPingTimeout,
243  };
244 
245  CHECK_STATUS_OK(alert_handler_testutils_configure_all(&alert_handler, config,
246  kDifToggleEnabled));
247  // Enables alert handler irq.
248  CHECK_DIF_OK(dif_alert_handler_irq_set_enabled(
249  &alert_handler, kDifAlertHandlerIrqClassa, kDifToggleEnabled));
250 }
251 
252 /**
253  * Execute the aon timer interrupt test.
254  */
255 static void config_escalate(dif_aon_timer_t *aon_timer,
256  const dif_pwrmgr_t *pwrmgr) {
257  uint32_t bark_cycles = 0;
258  CHECK_STATUS_OK(aon_timer_testutils_get_aon_cycles_32_from_us(kWdogBarkMicros,
259  &bark_cycles));
260  bark_cycles *= alert_handler_testutils_cycle_rescaling_factor();
261  uint32_t bite_cycles = 0;
262  CHECK_STATUS_OK(aon_timer_testutils_get_aon_cycles_32_from_us(kWdogBiteMicros,
263  &bite_cycles));
264  bite_cycles *= alert_handler_testutils_cycle_rescaling_factor();
265 
266  LOG_INFO(
267  "Wdog will bark after %u/%u us/cycles and bite after %u/%u us/cycles",
268  (uint32_t)kWdogBarkMicros, (uint32_t)bark_cycles,
269  (uint32_t)kWdogBiteMicros, (uint32_t)bite_cycles);
270 
271  // Setup the wdog bark and bite timeouts.
272  CHECK_STATUS_OK(aon_timer_testutils_watchdog_config(aon_timer, bark_cycles,
273  bite_cycles, false));
274 
275  // Trigger the alert handler to escalate.
276  dif_pwrmgr_alert_t alert = kDifPwrmgrAlertFatalFault;
277  CHECK_DIF_OK(dif_pwrmgr_alert_force(pwrmgr, alert));
278 }
279 
280 static void low_power_glitch_reset(const dif_pwrmgr_t *pwrmgr) {
281  // Program the pwrmgr to go to deep sleep state (clocks off).
282  CHECK_STATUS_OK(
283  pwrmgr_testutils_enable_low_power(pwrmgr, aon_timer_wakeup_sources, 0));
284  // Enter in low power mode.
285  wait_for_interrupt();
286 }
287 
288 static void normal_sleep_glitch_reset(const dif_pwrmgr_t *pwrmgr) {
289  // Place device into normal (shallow) power
290  dif_pwrmgr_domain_config_t config;
291  config = kDifPwrmgrDomainOptionUsbClockInLowPower |
292  kDifPwrmgrDomainOptionCoreClockInLowPower |
293  kDifPwrmgrDomainOptionIoClockInLowPower |
294  kDifPwrmgrDomainOptionMainPowerInLowPower;
295  CHECK_STATUS_OK(pwrmgr_testutils_enable_low_power(
296  pwrmgr, aon_timer_wakeup_sources, config));
297  // Enter in low power mode.
298  wait_for_interrupt();
299 }
300 
301 static void timer_on(uint32_t usec) {
302  busy_spin_micros(usec);
303  // If we arrive here the test must fail.
304  CHECK(false, "Timeout waiting for reset!");
305 }
306 
307 /**
308  * Configure the wdog.
309  */
310 static void config_wdog(const dif_aon_timer_t *aon_timer,
311  const dif_pwrmgr_t *pwrmgr, uint64_t bark_time_us,
312  uint64_t bite_time_us) {
313  uint32_t bark_cycles = 0;
314  CHECK_STATUS_OK(aon_timer_testutils_get_aon_cycles_32_from_us(bark_time_us,
315  &bark_cycles));
316  uint32_t bite_cycles = 0;
317  CHECK_STATUS_OK(aon_timer_testutils_get_aon_cycles_32_from_us(bite_time_us,
318  &bite_cycles));
319 
320  LOG_INFO("Wdog will bark after %u us and bite after %u us",
321  (uint32_t)bark_time_us, (uint32_t)bite_time_us);
322  // Setup the wdog bark and bite timeouts.
323 
324  CHECK_STATUS_OK(aon_timer_testutils_watchdog_config(aon_timer, bark_cycles,
325  bite_cycles, false));
326  // Set wdog as a reset source.
327  CHECK_DIF_OK(dif_pwrmgr_set_request_sources(
328  pwrmgr, kDifPwrmgrReqTypeReset, wdog_reset_sources, kDifToggleEnabled));
329 }
330 
331 /**
332  * Execute the aon timer wdog bite reset during sleep test.
333  */
334 static void sleep_wdog_bite_test(const dif_aon_timer_t *aon_timer,
335  const dif_pwrmgr_t *pwrmgr,
336  uint64_t bark_time_us) {
337  uint64_t bite_time_us = bark_time_us * 2;
338  config_wdog(aon_timer, pwrmgr, bark_time_us, bite_time_us);
339 }
340 
341 static void low_power_wdog(const dif_pwrmgr_t *pwrmgr) {
342  // Program the pwrmgr to go to deep sleep state (clocks off).
343  // Enter in low power mode.
344  CHECK_STATUS_OK(
345  pwrmgr_testutils_enable_low_power(pwrmgr, adc_ctrl_wakeup_sources, 0));
346  LOG_INFO("Low power set for watch dog");
347  wait_for_interrupt();
348  // If we arrive here the test must fail.
349  CHECK(false, "Fail to enter in low power mode!");
350 }
351 
352 static void normal_sleep_wdog(const dif_pwrmgr_t *pwrmgr) {
353  // Place device into low power and immediately wake.
354  dif_pwrmgr_domain_config_t config;
355  config = kDifPwrmgrDomainOptionUsbClockInLowPower |
356  kDifPwrmgrDomainOptionCoreClockInLowPower |
357  kDifPwrmgrDomainOptionIoClockInLowPower |
358  kDifPwrmgrDomainOptionMainPowerInLowPower;
359 
360  // Enter in low power mode.
361  CHECK_STATUS_OK(pwrmgr_testutils_enable_low_power(
362  pwrmgr, adc_ctrl_wakeup_sources, config));
363  LOG_INFO("Normal sleep set for watchdog");
364  wait_for_interrupt();
365 }
366 
367 static void low_power_por(const dif_pwrmgr_t *pwrmgr) {
368  // Set por as a reset source.
369  CHECK_DIF_OK(dif_pwrmgr_set_request_sources(
370  pwrmgr, kDifPwrmgrReqTypeReset, wdog_reset_sources, kDifToggleEnabled));
371 
372  // Program the pwrmgr to go to deep sleep state (clocks off).
373  CHECK_STATUS_OK(
374  pwrmgr_testutils_enable_low_power(pwrmgr, all_wakeup_sources, 0));
375  // Enter in low power mode.
376  wait_for_interrupt();
377  // If we arrive here the test must fail.
378  CHECK(false, "Fail to enter in low power mode!");
379 }
380 
381 static void normal_sleep_por(const dif_pwrmgr_t *pwrmgr) {
382  // Set por as a reset source.
383  CHECK_DIF_OK(dif_pwrmgr_set_request_sources(
384  pwrmgr, kDifPwrmgrReqTypeReset, wdog_reset_sources, kDifToggleEnabled));
385 
386  // Place device into low power and immediately wake.
387  dif_pwrmgr_domain_config_t config;
388  config = kDifPwrmgrDomainOptionUsbClockInLowPower |
389  kDifPwrmgrDomainOptionCoreClockInLowPower |
390  kDifPwrmgrDomainOptionIoClockInLowPower |
391  kDifPwrmgrDomainOptionMainPowerInLowPower;
392 
393  // Program the pwrmgr to go to swallow sleep state (clocks on).
394  CHECK_STATUS_OK(
395  pwrmgr_testutils_enable_low_power(pwrmgr, all_wakeup_sources, config));
396  // Enter in low power mode.
397  wait_for_interrupt();
398 }
399 
400 bool test_main(void) {
401  // Enable global and external IRQ at Ibex.
402  irq_global_ctrl(true);
403  irq_external_ctrl(true);
404 
405  init_peripherals();
406 
407  // Enable all the AON interrupts used in this test.
408  rv_plic_testutils_irq_range_enable(&plic, kPlicTarget,
409  kTopEarlgreyPlicIrqIdAlertHandlerClassa,
410  kTopEarlgreyPlicIrqIdAlertHandlerClassd);
411 
412  alert_handler_config();
413 
414  // First check the flash stored value
415  uint32_t event_idx = 0;
416  CHECK_STATUS_OK(flash_ctrl_testutils_counter_get(0, &event_idx));
417 
418  // Enable flash access
419  CHECK_STATUS_OK(
420  flash_ctrl_testutils_default_region_access(&flash_ctrl,
421  /*rd_en*/ true,
422  /*prog_en*/ true,
423  /*erase_en*/ true,
424  /*scramble_en*/ false,
425  /*ecc_en*/ false,
426  /*he_en*/ false));
427 
428  // Increment flash counter to know where we are
429  CHECK_STATUS_OK(flash_ctrl_testutils_counter_increment(&flash_ctrl, 0));
430 
431  LOG_INFO("Test round %d", event_idx);
432  LOG_INFO("RST_IDX[%d] = %d", event_idx, RST_IDX[event_idx]);
433 
434  // Check if there was a HW reset caused by expected cases
435  dif_rstmgr_reset_info_bitfield_t rst_info;
436  rst_info = rstmgr_testutils_reason_get();
437  rstmgr_testutils_reason_clear();
438  LOG_INFO("reset info = %02X", rst_info);
439 
440  CHECK(rst_info == kDifRstmgrResetInfoPor ||
441  rst_info == kDifRstmgrResetInfoSysRstCtrl ||
442  rst_info == kDifRstmgrResetInfoWatchdog ||
443  rst_info == kDifRstmgrResetInfoEscalation ||
444  rst_info == kDifRstmgrResetInfoLowPowerExit ||
445  rst_info == (kDifRstmgrResetInfoSysRstCtrl |
446  kDifRstmgrResetInfoLowPowerExit) ||
447  rst_info == (kDifRstmgrResetInfoPowerUnstable |
448  kDifRstmgrResetInfoLowPowerExit) ||
449  rst_info == (kDifRstmgrResetInfoPowerUnstable |
450  kDifRstmgrResetInfoWatchdog |
451  kDifRstmgrResetInfoLowPowerExit) ||
452  rst_info == (kDifRstmgrResetInfoPowerUnstable |
453  kDifRstmgrResetInfoWatchdog) ||
454  rst_info == kDifRstmgrResetInfoPowerUnstable ||
455  rst_info ==
456  (kDifRstmgrResetInfoPor | kDifRstmgrResetInfoLowPowerExit) ||
457  rst_info == (kDifRstmgrResetInfoWatchdog |
458  kDifRstmgrResetInfoLowPowerExit) ||
459  rst_info == (kDifRstmgrResetInfoEscalation |
460  kDifRstmgrResetInfoLowPowerExit) ||
461  rst_info == kDifRstmgrResetInfoSw,
462  "Wrong reset reason %02X", rst_info);
463 
464  switch (RST_IDX[event_idx] / 2) {
465  case 0:
466  if (RST_IDX[event_idx] % 2) {
467  LOG_INFO("Booting and setting normal sleep followed by glitch reset");
468  LOG_INFO("Let SV wait timer reset");
469  normal_sleep_glitch_reset(&pwrmgr);
470  timer_on(kWdogBiteMicros);
471  } else {
472  LOG_INFO("Booting and setting deep sleep followed by glitch reset");
473  LOG_INFO("Let SV wait timer reset");
474  low_power_glitch_reset(&pwrmgr);
475  }
476  break;
477  case 1:
478  if (RST_IDX[event_idx] % 2) {
479  LOG_INFO("Booting and setting normal sleep followed by hw por");
480  LOG_INFO("Let SV wait timer reset");
481  normal_sleep_por(&pwrmgr);
482  timer_on(kWdogBiteMicros);
483  } else {
484  LOG_INFO("Booting and setting deep sleep followed by hw por");
485  LOG_INFO("Let SV wait timer reset");
486  low_power_por(&pwrmgr);
487  }
488  break;
489  case 2:
490  if (RST_IDX[event_idx] % 2) {
491  LOG_INFO(
492  "Booting and setting normal sleep mode followed for low_power "
493  "entry reset");
494  LOG_INFO("Let SV wait timer reset");
495  // actually the same test as normal sleep + watchdog
496  CHECK_STATUS_OK(rstmgr_testutils_pre_reset(&rstmgr));
497  sleep_wdog_bite_test(&aon_timer, &pwrmgr, 200);
498  normal_sleep_wdog(&pwrmgr);
499  timer_on(kEscalationPhase0MicrosCpu);
500  } else {
501  LOG_INFO(
502  "Booting and setting deep sleep mode followed for low_power entry "
503  "reset");
504  LOG_INFO("Let SV wait timer reset");
505  // Executing the wdog bite reset during sleep test.
506  // actually the same test as deep sleep + watchdog
507  CHECK_STATUS_OK(rstmgr_testutils_pre_reset(&rstmgr));
508  sleep_wdog_bite_test(&aon_timer, &pwrmgr, 200);
509  low_power_wdog(&pwrmgr);
510  }
511  break;
512 
513  case 3:
514  if (RST_IDX[event_idx] % 2) {
515  LOG_INFO(
516  "Booting and setting normal sleep followed by watchdog reset "
517  "combined "
518  "with sw_req");
519  LOG_INFO("Let SV wait timer reset");
520  // Executing the wdog bite reset during sleep test.
521  CHECK_STATUS_OK(rstmgr_testutils_pre_reset(&rstmgr));
522  CHECK_DIF_OK(dif_rstmgr_software_device_reset(&rstmgr));
523  LOG_INFO("Device reset from sw");
524  sleep_wdog_bite_test(&aon_timer, &pwrmgr, 200);
525  normal_sleep_wdog(&pwrmgr);
526  timer_on(kEscalationPhase0MicrosCpu);
527  } else {
528  LOG_INFO(
529  "Booting and setting deep sleep followed by watchdog reset "
530  "combined "
531  "with sw_req");
532  LOG_INFO("Let SV wait timer reset");
533  // Executing the wdog bite reset during sleep test.
534  CHECK_STATUS_OK(rstmgr_testutils_pre_reset(&rstmgr));
535  CHECK_DIF_OK(dif_rstmgr_software_device_reset(&rstmgr));
536  LOG_INFO("Device reset from sw");
537  sleep_wdog_bite_test(&aon_timer, &pwrmgr, 200);
538  low_power_wdog(&pwrmgr);
539  }
540  break;
541  case 4:
542  if (RST_IDX[event_idx] % 2) {
543  LOG_INFO("Booting and setting normal sleep followed by watchdog reset");
544  LOG_INFO("Let SV wait timer reset");
545  // Executing the wdog bite reset during sleep test.
546  CHECK_STATUS_OK(rstmgr_testutils_pre_reset(&rstmgr));
547  sleep_wdog_bite_test(&aon_timer, &pwrmgr, 200);
548  normal_sleep_wdog(&pwrmgr);
549  timer_on(kEscalationPhase0MicrosCpu);
550  } else {
551  LOG_INFO("Booting and setting deep sleep followed by watchdog reset");
552  LOG_INFO("Let SV wait timer reset");
553  // Executing the wdog bite reset during sleep test.
554  CHECK_STATUS_OK(rstmgr_testutils_pre_reset(&rstmgr));
555  sleep_wdog_bite_test(&aon_timer, &pwrmgr, 200);
556  low_power_wdog(&pwrmgr);
557  }
558  break;
559  case 5:
560  if (RST_IDX[event_idx] % 2) {
561  LOG_INFO("Last Booting");
562 
563  return true;
564  } else {
565  LOG_INFO(
566  "Booting and running normal sleep followed by escalation reset");
567  config_escalate(&aon_timer, &pwrmgr);
568  timer_on(kEscalationPhase0MicrosCpu);
569  }
570  break;
571  default:
572  LOG_INFO("Booting for undefined case");
573  }
574 
575  return false;
576 }
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