dt_pwm.c

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
/**
 * @file
 * @brief Device Tables (DT) for IP pwm and top earlgrey.
 */
 
#include "hw/top/dt/dt_pwm.h"
 
 
 
 
 
/**
 * Description of instances.
 */
typedef struct dt_desc_pwm {
  dt_instance_id_t inst_id; /**< Instance ID */
  uint32_t reg_addr[kDtPwmRegBlockCount]; /**< Base address of each register block */
  uint32_t mem_addr[kDtPwmMemoryCount]; /**< Base address of each memory */
  uint32_t mem_size[kDtPwmMemoryCount]; /**< Size in bytes of each memory */
  /**
   * Alert ID of the first Alert of this instance.
   * 
   * This value is undefined if the block is not connected to the Alert Handler.
   */
  top_earlgrey_alert_id_t first_alert;
  dt_clock_t clock[kDtPwmClockCount]; /**< Clock signal connected to each clock port */
  dt_reset_t reset[kDtPwmResetCount]; /**< Reset signal connected to each reset port */
  dt_periph_io_t periph_io[kDtPwmPeriphIoCount]; /**< Description of each peripheral I/O */
  struct {
    uint8_t output_channel_count; /**< Number of output channels */
  } ipgen_ext; /**< Extension */
} dt_desc_pwm_t;
 
 
 
 
static const dt_desc_pwm_t pwm_desc[kDtPwmCount] = {
  [kDtPwmAon] = {
    .inst_id = kDtInstanceIdPwmAon,
    .reg_addr = {
      [kDtPwmRegBlockCore] = 0x40450000,
    },
    .mem_addr = {
    },
    .mem_size = {
    },
    .first_alert = kTopEarlgreyAlertIdPwmAonFatalFault,
    .clock = {
      [kDtPwmClockClk] = kDtClockIoDiv4,
      [kDtPwmClockCore] = kDtClockAon,
    },
    .reset = {
      [kDtPwmResetRst] = kDtResetLcIoDiv4,
      [kDtPwmResetCore] = kDtResetLcAon,
    },
    .periph_io = {
      [kDtPwmPeriphIoPwm0] = {
        .__internal = {
          .type = kDtPeriphIoTypeMio,
          .dir = kDtPeriphIoDirOut,
          .periph_input_or_direct_pad = 0,
          .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselPwmAonPwm0,
        },
      },
      [kDtPwmPeriphIoPwm1] = {
        .__internal = {
          .type = kDtPeriphIoTypeMio,
          .dir = kDtPeriphIoDirOut,
          .periph_input_or_direct_pad = 0,
          .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselPwmAonPwm1,
        },
      },
      [kDtPwmPeriphIoPwm2] = {
        .__internal = {
          .type = kDtPeriphIoTypeMio,
          .dir = kDtPeriphIoDirOut,
          .periph_input_or_direct_pad = 0,
          .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselPwmAonPwm2,
        },
      },
      [kDtPwmPeriphIoPwm3] = {
        .__internal = {
          .type = kDtPeriphIoTypeMio,
          .dir = kDtPeriphIoDirOut,
          .periph_input_or_direct_pad = 0,
          .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselPwmAonPwm3,
        },
      },
      [kDtPwmPeriphIoPwm4] = {
        .__internal = {
          .type = kDtPeriphIoTypeMio,
          .dir = kDtPeriphIoDirOut,
          .periph_input_or_direct_pad = 0,
          .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselPwmAonPwm4,
        },
      },
      [kDtPwmPeriphIoPwm5] = {
        .__internal = {
          .type = kDtPeriphIoTypeMio,
          .dir = kDtPeriphIoDirOut,
          .periph_input_or_direct_pad = 0,
          .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselPwmAonPwm5,
        },
      },
    },
    .ipgen_ext = {
      .output_channel_count = 6,
    },
  },
};
 
/**
 * Return a pointer to the `dt_pwm_desc_t` structure of the requested
 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
 * the function) with the provided default value.
 */
#define TRY_GET_DT(dt, default)   ({     if ((dt) < (dt_pwm_t)0 || (dt) >= kDtPwmCount)       return (default);     &pwm_desc[dt];   })
 
dt_pwm_t dt_pwm_from_instance_id(dt_instance_id_t inst_id) {
  if (inst_id >= kDtInstanceIdPwmAon && inst_id <= kDtInstanceIdPwmAon) {
    return (dt_pwm_t)(inst_id - kDtInstanceIdPwmAon);
  }
  return (dt_pwm_t)0;
}
 
dt_instance_id_t dt_pwm_instance_id(
    dt_pwm_t dt) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->inst_id;
}
 
uint32_t dt_pwm_reg_block(
    dt_pwm_t dt,
    dt_pwm_reg_block_t reg_block) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
}
 
uint32_t dt_pwm_memory_base(
    dt_pwm_t dt,
    dt_pwm_memory_t mem) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
}
 
uint32_t dt_pwm_memory_size(
    dt_pwm_t dt,
    dt_pwm_memory_t mem)  {
  // Return an empty size in case of wrong argument.
  return TRY_GET_DT(dt, 0)->mem_size[mem];
}
 
 
dt_alert_id_t dt_pwm_alert_to_alert_id(
    dt_pwm_t dt,
    dt_pwm_alert_t alert) {
  return (dt_alert_id_t)((uint32_t)pwm_desc[dt].first_alert + (uint32_t)alert);
}
 
dt_pwm_alert_t dt_pwm_alert_from_alert_id(
    dt_pwm_t dt,
    dt_alert_id_t alert) {
  dt_pwm_alert_t count = kDtPwmAlertCount;
  if (alert < pwm_desc[dt].first_alert || alert >= pwm_desc[dt].first_alert + (dt_alert_id_t)count) {
    return count;
  }
  return (dt_pwm_alert_t)(alert - pwm_desc[dt].first_alert);
}
 
 
dt_periph_io_t dt_pwm_periph_io(
    dt_pwm_t dt,
    dt_pwm_periph_io_t sig) {
  // Return a harmless value in case of wrong argument.
  return TRY_GET_DT(dt, kDtPeriphIoConstantHighZ)->periph_io[sig];
}
 
dt_clock_t dt_pwm_clock(
    dt_pwm_t dt,
    dt_pwm_clock_t clk) {
  // Return the first clock in case of invalid argument.
  return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
}
 
dt_reset_t dt_pwm_reset(
    dt_pwm_t dt,
    dt_pwm_reset_t rst) {
  const dt_pwm_reset_t count = kDtPwmResetCount;
  if (rst >= count) {
    return kDtResetUnknown;
  }
  return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
}
 
 
 
uint8_t dt_pwm_output_channel_count(dt_pwm_t dt) {
  return TRY_GET_DT(dt, 0)->ipgen_ext.output_channel_count;
}