dma_regs.h

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/**
 * @file
 * @brief Generated register defines for dma
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _DMA_REG_DEFS_
#define _DMA_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of interrupt clearing sources to process
#define DMA_PARAM_NUM_INT_CLEAR_SOURCES 11
 
// Number of alerts
#define DMA_PARAM_NUM_ALERTS 1
 
// Register width
#define DMA_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define DMA_INTR_COMMON_DMA_DONE_BIT 0
#define DMA_INTR_COMMON_DMA_CHUNK_DONE_BIT 1
#define DMA_INTR_COMMON_DMA_ERROR_BIT 2
 
// Interrupt State Register
#define DMA_INTR_STATE_REG_OFFSET 0x0
#define DMA_INTR_STATE_REG_RESVAL 0x0u
#define DMA_INTR_STATE_DMA_DONE_BIT 0
#define DMA_INTR_STATE_DMA_CHUNK_DONE_BIT 1
#define DMA_INTR_STATE_DMA_ERROR_BIT 2
 
// Interrupt Enable Register
#define DMA_INTR_ENABLE_REG_OFFSET 0x4
#define DMA_INTR_ENABLE_REG_RESVAL 0x0u
#define DMA_INTR_ENABLE_DMA_DONE_BIT 0
#define DMA_INTR_ENABLE_DMA_CHUNK_DONE_BIT 1
#define DMA_INTR_ENABLE_DMA_ERROR_BIT 2
 
// Interrupt Test Register
#define DMA_INTR_TEST_REG_OFFSET 0x8
#define DMA_INTR_TEST_REG_RESVAL 0x0u
#define DMA_INTR_TEST_DMA_DONE_BIT 0
#define DMA_INTR_TEST_DMA_CHUNK_DONE_BIT 1
#define DMA_INTR_TEST_DMA_ERROR_BIT 2
 
// Alert Test Register
#define DMA_ALERT_TEST_REG_OFFSET 0xc
#define DMA_ALERT_TEST_REG_RESVAL 0x0u
#define DMA_ALERT_TEST_FATAL_FAULT_BIT 0
 
// Lower 32 bits of the physical or virtual address of memory location within
// SoC memory address map or physical address within OT non-secure memory
// space.
#define DMA_SRC_ADDR_LO_REG_OFFSET 0x10
#define DMA_SRC_ADDR_LO_REG_RESVAL 0x0u
 
// Upper 32 bits of the source address.
#define DMA_SRC_ADDR_HI_REG_OFFSET 0x14
#define DMA_SRC_ADDR_HI_REG_RESVAL 0x0u
 
// Lower 32 bits of the physical or virtual address of memory location within
// SoC memory address map or physical address within OT non-secure memory
// space.
#define DMA_DST_ADDR_LO_REG_OFFSET 0x18
#define DMA_DST_ADDR_LO_REG_RESVAL 0x0u
 
// Upper 32 bits of the destination address.
#define DMA_DST_ADDR_HI_REG_OFFSET 0x1c
#define DMA_DST_ADDR_HI_REG_RESVAL 0x0u
 
// Address space that source and destination pointers refer to.
#define DMA_ADDR_SPACE_ID_REG_OFFSET 0x20
#define DMA_ADDR_SPACE_ID_REG_RESVAL 0x77u
#define DMA_ADDR_SPACE_ID_SRC_ASID_MASK 0xfu
#define DMA_ADDR_SPACE_ID_SRC_ASID_OFFSET 0
#define DMA_ADDR_SPACE_ID_SRC_ASID_FIELD \
  ((bitfield_field32_t) { .mask = DMA_ADDR_SPACE_ID_SRC_ASID_MASK, .index = DMA_ADDR_SPACE_ID_SRC_ASID_OFFSET })
#define DMA_ADDR_SPACE_ID_SRC_ASID_VALUE_OT_ADDR 0x7
#define DMA_ADDR_SPACE_ID_SRC_ASID_VALUE_SOC_ADDR 0xa
#define DMA_ADDR_SPACE_ID_SRC_ASID_VALUE_SYS_ADDR_ 0x9
#define DMA_ADDR_SPACE_ID_DST_ASID_MASK 0xfu
#define DMA_ADDR_SPACE_ID_DST_ASID_OFFSET 4
#define DMA_ADDR_SPACE_ID_DST_ASID_FIELD \
  ((bitfield_field32_t) { .mask = DMA_ADDR_SPACE_ID_DST_ASID_MASK, .index = DMA_ADDR_SPACE_ID_DST_ASID_OFFSET })
#define DMA_ADDR_SPACE_ID_DST_ASID_VALUE_OT_ADDR 0x7
#define DMA_ADDR_SPACE_ID_DST_ASID_VALUE_SOC_ADDR 0xa
#define DMA_ADDR_SPACE_ID_DST_ASID_VALUE_SYS_ADDR_ 0x9
 
// Base Address to mark the start of the DMA enabled memory range within the
// OT internal memory space.
#define DMA_ENABLED_MEMORY_RANGE_BASE_REG_OFFSET 0x24
#define DMA_ENABLED_MEMORY_RANGE_BASE_REG_RESVAL 0x0u
 
// Limit Address to mark the end of the DMA enabled memory range within the
// OT internal memory space.
#define DMA_ENABLED_MEMORY_RANGE_LIMIT_REG_OFFSET 0x28
#define DMA_ENABLED_MEMORY_RANGE_LIMIT_REG_RESVAL 0x0u
 
// Indicates that the ENABLED_MEMORY_RANGE_BASE and _LIMIT registers have
// been programmed to restrict DMA accesses within the OT internal address
// space.
#define DMA_RANGE_VALID_REG_OFFSET 0x2c
#define DMA_RANGE_VALID_REG_RESVAL 0x0u
#define DMA_RANGE_VALID_RANGE_VALID_BIT 0
 
// Used to lock the DMA enabled memory range configuration registers.
#define DMA_RANGE_REGWEN_REG_OFFSET 0x30
#define DMA_RANGE_REGWEN_REG_RESVAL 0x6u
#define DMA_RANGE_REGWEN_REGWEN_MASK 0xfu
#define DMA_RANGE_REGWEN_REGWEN_OFFSET 0
#define DMA_RANGE_REGWEN_REGWEN_FIELD \
  ((bitfield_field32_t) { .mask = DMA_RANGE_REGWEN_REGWEN_MASK, .index = DMA_RANGE_REGWEN_REGWEN_OFFSET })
 
// Indicates whether the configuration registers are locked because the DMA
// controller is operating.
#define DMA_CFG_REGWEN_REG_OFFSET 0x34
#define DMA_CFG_REGWEN_REG_RESVAL 0x6u
#define DMA_CFG_REGWEN_REGWEN_MASK 0xfu
#define DMA_CFG_REGWEN_REGWEN_OFFSET 0
#define DMA_CFG_REGWEN_REGWEN_FIELD \
  ((bitfield_field32_t) { .mask = DMA_CFG_REGWEN_REGWEN_MASK, .index = DMA_CFG_REGWEN_REGWEN_OFFSET })
 
// Total size of the data blob involved in DMA movement.
#define DMA_TOTAL_DATA_SIZE_REG_OFFSET 0x38
#define DMA_TOTAL_DATA_SIZE_REG_RESVAL 0x0u
 
// Number of bytes to be transferred in response to each interrupt/firmware
// request.
#define DMA_CHUNK_DATA_SIZE_REG_OFFSET 0x3c
#define DMA_CHUNK_DATA_SIZE_REG_RESVAL 0x0u
 
// Denotes the width of each transaction that the DMA shall issue.
#define DMA_TRANSFER_WIDTH_REG_OFFSET 0x40
#define DMA_TRANSFER_WIDTH_REG_RESVAL 0x2u
#define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_MASK 0x3u
#define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_OFFSET 0
#define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_FIELD \
  ((bitfield_field32_t) { .mask = DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_MASK, .index = DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_OFFSET })
#define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_VALUE_ONE_BYTE 0x0
#define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_VALUE_TWO_BYTE 0x1
#define DMA_TRANSFER_WIDTH_TRANSACTION_WIDTH_VALUE_FOUR_BYTE 0x2
 
// Control register for DMA data movement.
#define DMA_CONTROL_REG_OFFSET 0x44
#define DMA_CONTROL_REG_RESVAL 0x0u
#define DMA_CONTROL_OPCODE_MASK 0xfu
#define DMA_CONTROL_OPCODE_OFFSET 0
#define DMA_CONTROL_OPCODE_FIELD \
  ((bitfield_field32_t) { .mask = DMA_CONTROL_OPCODE_MASK, .index = DMA_CONTROL_OPCODE_OFFSET })
#define DMA_CONTROL_OPCODE_VALUE_COPY 0x0
#define DMA_CONTROL_OPCODE_VALUE_SHA256 0x1
#define DMA_CONTROL_OPCODE_VALUE_SHA384 0x2
#define DMA_CONTROL_OPCODE_VALUE_SHA512 0x3
#define DMA_CONTROL_HARDWARE_HANDSHAKE_ENABLE_BIT 4
#define DMA_CONTROL_DIGEST_SWAP_BIT 5
#define DMA_CONTROL_INITIAL_TRANSFER_BIT 8
#define DMA_CONTROL_ABORT_BIT 27
#define DMA_CONTROL_GO_BIT 31
 
// Defines the addressing behavior of the DMA for the source address.
#define DMA_SRC_CONFIG_REG_OFFSET 0x48
#define DMA_SRC_CONFIG_REG_RESVAL 0x0u
#define DMA_SRC_CONFIG_INCREMENT_BIT 0
#define DMA_SRC_CONFIG_WRAP_BIT 1
 
// Defines the addressing behavior of the DMA for the destination address.
#define DMA_DST_CONFIG_REG_OFFSET 0x4c
#define DMA_DST_CONFIG_REG_RESVAL 0x0u
#define DMA_DST_CONFIG_INCREMENT_BIT 0
#define DMA_DST_CONFIG_WRAP_BIT 1
 
// Status indication for DMA data movement.
#define DMA_STATUS_REG_OFFSET 0x50
#define DMA_STATUS_REG_RESVAL 0x0u
#define DMA_STATUS_BUSY_BIT 0
#define DMA_STATUS_DONE_BIT 1
#define DMA_STATUS_ABORTED_BIT 2
#define DMA_STATUS_ERROR_BIT 3
#define DMA_STATUS_SHA2_DIGEST_VALID_BIT 4
#define DMA_STATUS_CHUNK_DONE_BIT 5
 
// Denotes the source of the operational error.
#define DMA_ERROR_CODE_REG_OFFSET 0x54
#define DMA_ERROR_CODE_REG_RESVAL 0x0u
#define DMA_ERROR_CODE_SRC_ADDR_ERROR_BIT 0
#define DMA_ERROR_CODE_DST_ADDR_ERROR_BIT 1
#define DMA_ERROR_CODE_OPCODE_ERROR_BIT 2
#define DMA_ERROR_CODE_SIZE_ERROR_BIT 3
#define DMA_ERROR_CODE_BUS_ERROR_BIT 4
#define DMA_ERROR_CODE_BASE_LIMIT_ERROR_BIT 5
#define DMA_ERROR_CODE_RANGE_VALID_ERROR_BIT 6
#define DMA_ERROR_CODE_ASID_ERROR_BIT 7
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_DATA_FIELD_WIDTH 32
#define DMA_SHA2_DIGEST_MULTIREG_COUNT 16
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_0_REG_OFFSET 0x58
#define DMA_SHA2_DIGEST_0_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_1_REG_OFFSET 0x5c
#define DMA_SHA2_DIGEST_1_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_2_REG_OFFSET 0x60
#define DMA_SHA2_DIGEST_2_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_3_REG_OFFSET 0x64
#define DMA_SHA2_DIGEST_3_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_4_REG_OFFSET 0x68
#define DMA_SHA2_DIGEST_4_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_5_REG_OFFSET 0x6c
#define DMA_SHA2_DIGEST_5_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_6_REG_OFFSET 0x70
#define DMA_SHA2_DIGEST_6_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_7_REG_OFFSET 0x74
#define DMA_SHA2_DIGEST_7_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_8_REG_OFFSET 0x78
#define DMA_SHA2_DIGEST_8_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_9_REG_OFFSET 0x7c
#define DMA_SHA2_DIGEST_9_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_10_REG_OFFSET 0x80
#define DMA_SHA2_DIGEST_10_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_11_REG_OFFSET 0x84
#define DMA_SHA2_DIGEST_11_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_12_REG_OFFSET 0x88
#define DMA_SHA2_DIGEST_12_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_13_REG_OFFSET 0x8c
#define DMA_SHA2_DIGEST_13_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_14_REG_OFFSET 0x90
#define DMA_SHA2_DIGEST_14_REG_RESVAL 0x0u
 
// Digest register for the inline hashing operation.
#define DMA_SHA2_DIGEST_15_REG_OFFSET 0x94
#define DMA_SHA2_DIGEST_15_REG_RESVAL 0x0u
 
// Enable bits for incoming handshake interrupt wires.
#define DMA_HANDSHAKE_INTR_ENABLE_REG_OFFSET 0x98
#define DMA_HANDSHAKE_INTR_ENABLE_REG_RESVAL 0x7ffu
#define DMA_HANDSHAKE_INTR_ENABLE_MASK_MASK 0x7ffu
#define DMA_HANDSHAKE_INTR_ENABLE_MASK_OFFSET 0
#define DMA_HANDSHAKE_INTR_ENABLE_MASK_FIELD \
  ((bitfield_field32_t) { .mask = DMA_HANDSHAKE_INTR_ENABLE_MASK_MASK, .index = DMA_HANDSHAKE_INTR_ENABLE_MASK_OFFSET })
 
// Valid bits for which interrupt sources need clearing.
#define DMA_CLEAR_INTR_SRC_REG_OFFSET 0x9c
#define DMA_CLEAR_INTR_SRC_REG_RESVAL 0x0u
#define DMA_CLEAR_INTR_SRC_SOURCE_MASK 0x7ffu
#define DMA_CLEAR_INTR_SRC_SOURCE_OFFSET 0
#define DMA_CLEAR_INTR_SRC_SOURCE_FIELD \
  ((bitfield_field32_t) { .mask = DMA_CLEAR_INTR_SRC_SOURCE_MASK, .index = DMA_CLEAR_INTR_SRC_SOURCE_OFFSET })
 
// Bus selection bit where the clearing command should be performed."
#define DMA_CLEAR_INTR_BUS_REG_OFFSET 0xa0
#define DMA_CLEAR_INTR_BUS_REG_RESVAL 0x0u
#define DMA_CLEAR_INTR_BUS_BUS_MASK 0x7ffu
#define DMA_CLEAR_INTR_BUS_BUS_OFFSET 0
#define DMA_CLEAR_INTR_BUS_BUS_FIELD \
  ((bitfield_field32_t) { .mask = DMA_CLEAR_INTR_BUS_BUS_MASK, .index = DMA_CLEAR_INTR_BUS_BUS_OFFSET })
 
// Destination address for interrupt source clearing write. (common
// parameters)
#define DMA_INTR_SRC_ADDR_ADDR_FIELD_WIDTH 32
#define DMA_INTR_SRC_ADDR_MULTIREG_COUNT 11
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_0_REG_OFFSET 0xa4
#define DMA_INTR_SRC_ADDR_0_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_1_REG_OFFSET 0xa8
#define DMA_INTR_SRC_ADDR_1_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_2_REG_OFFSET 0xac
#define DMA_INTR_SRC_ADDR_2_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_3_REG_OFFSET 0xb0
#define DMA_INTR_SRC_ADDR_3_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_4_REG_OFFSET 0xb4
#define DMA_INTR_SRC_ADDR_4_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_5_REG_OFFSET 0xb8
#define DMA_INTR_SRC_ADDR_5_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_6_REG_OFFSET 0xbc
#define DMA_INTR_SRC_ADDR_6_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_7_REG_OFFSET 0xc0
#define DMA_INTR_SRC_ADDR_7_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_8_REG_OFFSET 0xc4
#define DMA_INTR_SRC_ADDR_8_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_9_REG_OFFSET 0xc8
#define DMA_INTR_SRC_ADDR_9_REG_RESVAL 0x0u
 
// Destination address for interrupt source clearing write.
#define DMA_INTR_SRC_ADDR_10_REG_OFFSET 0xcc
#define DMA_INTR_SRC_ADDR_10_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write. (common parameters)
#define DMA_INTR_SRC_WR_VAL_WR_VAL_FIELD_WIDTH 32
#define DMA_INTR_SRC_WR_VAL_MULTIREG_COUNT 11
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_0_REG_OFFSET 0x124
#define DMA_INTR_SRC_WR_VAL_0_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_1_REG_OFFSET 0x128
#define DMA_INTR_SRC_WR_VAL_1_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_2_REG_OFFSET 0x12c
#define DMA_INTR_SRC_WR_VAL_2_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_3_REG_OFFSET 0x130
#define DMA_INTR_SRC_WR_VAL_3_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_4_REG_OFFSET 0x134
#define DMA_INTR_SRC_WR_VAL_4_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_5_REG_OFFSET 0x138
#define DMA_INTR_SRC_WR_VAL_5_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_6_REG_OFFSET 0x13c
#define DMA_INTR_SRC_WR_VAL_6_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_7_REG_OFFSET 0x140
#define DMA_INTR_SRC_WR_VAL_7_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_8_REG_OFFSET 0x144
#define DMA_INTR_SRC_WR_VAL_8_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_9_REG_OFFSET 0x148
#define DMA_INTR_SRC_WR_VAL_9_REG_RESVAL 0x0u
 
// Write value for interrupt clearing write.
#define DMA_INTR_SRC_WR_VAL_10_REG_OFFSET 0x14c
#define DMA_INTR_SRC_WR_VAL_10_REG_RESVAL 0x0u
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _DMA_REG_DEFS_
// End generated register defines for dma