Software APIs
dif_rram_ctrl_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
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11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i hw/ip/rram_ctrl/data/rram_ctrl.hjson -o
13// bazel-out/k8-fastbuild/bin/sw/device/lib/dif/autogen
14
15
16#include <stdint.h>
17
18#include "sw/device/lib/dif/dif_base.h"
19#include "sw/device/lib/dif/autogen/dif_rram_ctrl_autogen.h"
20
21#include "hw/top/rram_ctrl_regs.h" // Generated.
22
23
24OT_WARN_UNUSED_RESULT
25dif_result_t dif_rram_ctrl_init(
26 mmio_region_t base_addr,
27 dif_rram_ctrl_t *rram_ctrl) {
28 if (rram_ctrl == NULL) {
29 return kDifBadArg;
30 }
31
32 rram_ctrl->dt = kDtRramCtrlCount;
33 rram_ctrl->base_addr = base_addr;
34
35 return kDifOk;
36}
37
38OT_WARN_UNUSED_RESULT
39dif_result_t dif_rram_ctrl_init_from_dt(
40 dt_rram_ctrl_t dt,
41 dif_rram_ctrl_t *rram_ctrl) {
42 if (rram_ctrl == NULL) {
43 return kDifBadArg;
44 }
45
46 rram_ctrl->dt = dt;
47 rram_ctrl->base_addr = mmio_region_from_addr(dt_rram_ctrl_primary_reg_block(dt));
48
49 return kDifOk;
50}
51
52dif_result_t dif_rram_ctrl_get_dt(
53 const dif_rram_ctrl_t *rram_ctrl,
54 dt_rram_ctrl_t *dt) {
55 if ((int)rram_ctrl->dt == kDtRramCtrlCount || dt == NULL) {
56 return kDifBadArg;
57 }
58 *dt = rram_ctrl->dt;
59 return kDifOk;
60}
61
62 dif_result_t dif_rram_ctrl_alert_force(
63 const dif_rram_ctrl_t *rram_ctrl,
64 dif_rram_ctrl_alert_t alert) {
65 if (rram_ctrl == NULL) {
66 return kDifBadArg;
67 }
68
69 bitfield_bit32_index_t alert_idx;
70 switch (alert) {
71 case kDifRramCtrlAlertRecovErr:
72 alert_idx = RRAM_CTRL_ALERT_TEST_RECOV_ERR_BIT;
73 break;
74 case kDifRramCtrlAlertFatalStdErr:
75 alert_idx = RRAM_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT;
76 break;
77 case kDifRramCtrlAlertFatalErr:
78 alert_idx = RRAM_CTRL_ALERT_TEST_FATAL_ERR_BIT;
79 break;
80 case kDifRramCtrlAlertFatalMacroErr:
81 alert_idx = RRAM_CTRL_ALERT_TEST_FATAL_MACRO_ERR_BIT;
82 break;
83 case kDifRramCtrlAlertRecovMacroErr:
84 alert_idx = RRAM_CTRL_ALERT_TEST_RECOV_MACRO_ERR_BIT;
85 break;
86 default:
87 return kDifBadArg;
88 }
89
90 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
91 // Keep the alert test enabled: writing 0 to the regwen bit locks the register.
92 alert_test_reg = bitfield_bit32_write(
93 alert_test_reg, RRAM_CTRL_ALERT_TEST_REGWEN_BIT, true);
94 mmio_region_write32(
95 rram_ctrl->base_addr,
96 (ptrdiff_t)RRAM_CTRL_ALERT_TEST_REG_OFFSET,
97 alert_test_reg);
98
99
100 return kDifOk;
101}
102
103
104 /**
105 * Get the corresponding interrupt register bit offset of the IRQ.
106 */
107 static bool rram_ctrl_get_irq_bit_index(
108 dif_rram_ctrl_irq_t irq,
109 bitfield_bit32_index_t *index_out) {
110
111 switch (irq) {
112 case kDtRramCtrlIrqWrEmpty:
113 *index_out = RRAM_CTRL_INTR_COMMON_WR_EMPTY_BIT;
114 break;
115 case kDtRramCtrlIrqWrLvl:
116 *index_out = RRAM_CTRL_INTR_COMMON_WR_LVL_BIT;
117 break;
118 case kDtRramCtrlIrqRdFull:
119 *index_out = RRAM_CTRL_INTR_COMMON_RD_FULL_BIT;
120 break;
121 case kDtRramCtrlIrqRdLvl:
122 *index_out = RRAM_CTRL_INTR_COMMON_RD_LVL_BIT;
123 break;
124 case kDtRramCtrlIrqOpDone:
125 *index_out = RRAM_CTRL_INTR_COMMON_OP_DONE_BIT;
126 break;
127 case kDtRramCtrlIrqCorr1Err:
128 *index_out = RRAM_CTRL_INTR_COMMON_CORR1_ERR_BIT;
129 break;
130 case kDtRramCtrlIrqCorr2Err:
131 *index_out = RRAM_CTRL_INTR_COMMON_CORR2_ERR_BIT;
132 break;
133 default:
134 return false;
135 }
136
137 return true;
138 }
139
140 static dif_irq_type_t irq_types[] = {
141 kDifIrqTypeStatus,
142 kDifIrqTypeStatus,
143 kDifIrqTypeStatus,
144 kDifIrqTypeStatus,
145 kDifIrqTypeEvent,
146 kDifIrqTypeEvent,
147 kDifIrqTypeEvent,
148 };
149
150 OT_WARN_UNUSED_RESULT
151 dif_result_t dif_rram_ctrl_irq_get_type(
152 const dif_rram_ctrl_t *rram_ctrl,
153 dif_rram_ctrl_irq_t irq,
154 dif_irq_type_t *type) {
155
156
157 if (rram_ctrl == NULL ||
158 type == NULL ||
159 irq < kDifRramCtrlIrqWrEmpty ||
160 irq > kDifRramCtrlIrqCorr2Err) {
161 return kDifBadArg;
162 }
163
164 *type = irq_types[irq];
165
166 return kDifOk;
167 }
168
169 OT_WARN_UNUSED_RESULT
170 dif_result_t dif_rram_ctrl_irq_get_state(
171 const dif_rram_ctrl_t *rram_ctrl,
172 dif_rram_ctrl_irq_state_snapshot_t *snapshot) {
173
174 if (rram_ctrl == NULL || snapshot == NULL) {
175 return kDifBadArg;
176 }
177
178 *snapshot = mmio_region_read32(
179 rram_ctrl->base_addr,
180 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET);
181
182
183 return kDifOk;
184 }
185
186 OT_WARN_UNUSED_RESULT
187 dif_result_t dif_rram_ctrl_irq_acknowledge_state(
188 const dif_rram_ctrl_t *rram_ctrl,
189 dif_rram_ctrl_irq_state_snapshot_t snapshot) {
190 if (rram_ctrl == NULL) {
191 return kDifBadArg;
192 }
193
194 mmio_region_write32(
195 rram_ctrl->base_addr,
196 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET,
197 snapshot);
198
199
200 return kDifOk;
201 }
202
203 OT_WARN_UNUSED_RESULT
204 dif_result_t dif_rram_ctrl_irq_is_pending(
205 const dif_rram_ctrl_t *rram_ctrl,
206 dif_rram_ctrl_irq_t irq,
207 bool *is_pending) {
208
209 if (rram_ctrl == NULL || is_pending == NULL) {
210 return kDifBadArg;
211 }
212
213 bitfield_bit32_index_t index;
214 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
215 return kDifBadArg;
216 }
217
218 uint32_t intr_state_reg = mmio_region_read32(
219 rram_ctrl->base_addr,
220 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET);
221
222
223 *is_pending = bitfield_bit32_read(intr_state_reg, index);
224
225 return kDifOk;
226 }
227
228 OT_WARN_UNUSED_RESULT
229 dif_result_t dif_rram_ctrl_irq_acknowledge_all(
230 const dif_rram_ctrl_t *rram_ctrl
231 ) {
232
233 if (rram_ctrl == NULL) {
234 return kDifBadArg;
235 }
236
237 // Writing to the register clears the corresponding bits (Write-one clear).
238 mmio_region_write32(
239 rram_ctrl->base_addr,
240 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET,
241 UINT32_MAX);
242
243
244 return kDifOk;
245 }
246
247 OT_WARN_UNUSED_RESULT
248 dif_result_t dif_rram_ctrl_irq_acknowledge(
249 const dif_rram_ctrl_t *rram_ctrl,
250 dif_rram_ctrl_irq_t irq) {
251
252 if (rram_ctrl == NULL) {
253 return kDifBadArg;
254 }
255
256 bitfield_bit32_index_t index;
257 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
258 return kDifBadArg;
259 }
260
261 // Writing to the register clears the corresponding bits (Write-one clear).
262 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
263 mmio_region_write32(
264 rram_ctrl->base_addr,
265 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET,
266 intr_state_reg);
267
268
269 return kDifOk;
270 }
271
272 OT_WARN_UNUSED_RESULT
273 dif_result_t dif_rram_ctrl_irq_force(
274 const dif_rram_ctrl_t *rram_ctrl,
275 dif_rram_ctrl_irq_t irq,
276 const bool val) {
277
278 if (rram_ctrl == NULL) {
279 return kDifBadArg;
280 }
281
282 bitfield_bit32_index_t index;
283 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
284 return kDifBadArg;
285 }
286
287 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
288 mmio_region_write32(
289 rram_ctrl->base_addr,
290 (ptrdiff_t)RRAM_CTRL_INTR_TEST_REG_OFFSET,
291 intr_test_reg);
292
293
294 return kDifOk;
295 }
296
297 OT_WARN_UNUSED_RESULT
298 dif_result_t dif_rram_ctrl_irq_get_enabled(
299 const dif_rram_ctrl_t *rram_ctrl,
300 dif_rram_ctrl_irq_t irq,
301 dif_toggle_t *state) {
302
303 if (rram_ctrl == NULL || state == NULL) {
304 return kDifBadArg;
305 }
306
307 bitfield_bit32_index_t index;
308 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
309 return kDifBadArg;
310 }
311
312 uint32_t intr_enable_reg = mmio_region_read32(
313 rram_ctrl->base_addr,
314 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET);
315
316
317 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
318 *state = is_enabled ?
319 kDifToggleEnabled : kDifToggleDisabled;
320
321 return kDifOk;
322 }
323
324 OT_WARN_UNUSED_RESULT
325 dif_result_t dif_rram_ctrl_irq_set_enabled(
326 const dif_rram_ctrl_t *rram_ctrl,
327 dif_rram_ctrl_irq_t irq,
328 dif_toggle_t state) {
329
330 if (rram_ctrl == NULL) {
331 return kDifBadArg;
332 }
333
334 bitfield_bit32_index_t index;
335 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
336 return kDifBadArg;
337 }
338
339 uint32_t intr_enable_reg = mmio_region_read32(
340 rram_ctrl->base_addr,
341 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET);
342
343
344 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
345 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
346 mmio_region_write32(
347 rram_ctrl->base_addr,
348 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET,
349 intr_enable_reg);
350
351
352 return kDifOk;
353 }
354
355 OT_WARN_UNUSED_RESULT
356 dif_result_t dif_rram_ctrl_irq_disable_all(
357 const dif_rram_ctrl_t *rram_ctrl,
358 dif_rram_ctrl_irq_enable_snapshot_t *snapshot) {
359
360 if (rram_ctrl == NULL) {
361 return kDifBadArg;
362 }
363
364 // Pass the current interrupt state to the caller, if requested.
365 if (snapshot != NULL) {
366 *snapshot = mmio_region_read32(
367 rram_ctrl->base_addr,
368 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET);
369
370 }
371
372 // Disable all interrupts.
373 mmio_region_write32(
374 rram_ctrl->base_addr,
375 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET,
376 0u);
377
378
379 return kDifOk;
380 }
381
382 OT_WARN_UNUSED_RESULT
383 dif_result_t dif_rram_ctrl_irq_restore_all(
384 const dif_rram_ctrl_t *rram_ctrl,
385 const dif_rram_ctrl_irq_enable_snapshot_t *snapshot) {
386
387 if (rram_ctrl == NULL || snapshot == NULL) {
388 return kDifBadArg;
389 }
390
391 mmio_region_write32(
392 rram_ctrl->base_addr,
393 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET,
394 *snapshot);
395
396
397 return kDifOk;
398 }
399