Software APIs
dif_rram_ctrl_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
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11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i hw/ip/rram_ctrl/data/rram_ctrl.hjson -o
13// bazel-out/k8-fastbuild/bin/sw/device/lib/dif/autogen
14
15
16#include <stdint.h>
17
18#include "sw/device/lib/dif/dif_base.h"
19#include "sw/device/lib/dif/autogen/dif_rram_ctrl_autogen.h"
20
21#include "hw/top/rram_ctrl_regs.h" // Generated.
22
23
24OT_WARN_UNUSED_RESULT
25dif_result_t dif_rram_ctrl_init(
26 mmio_region_t base_addr,
27 dif_rram_ctrl_t *rram_ctrl) {
28 if (rram_ctrl == NULL) {
29 return kDifBadArg;
30 }
31
32 rram_ctrl->dt = kDtRramCtrlCount;
33 rram_ctrl->base_addr = base_addr;
34
35 return kDifOk;
36}
37
38OT_WARN_UNUSED_RESULT
39dif_result_t dif_rram_ctrl_init_from_dt(
40 dt_rram_ctrl_t dt,
41 dif_rram_ctrl_t *rram_ctrl) {
42 if (rram_ctrl == NULL) {
43 return kDifBadArg;
44 }
45
46 rram_ctrl->dt = dt;
47 rram_ctrl->base_addr = mmio_region_from_addr(dt_rram_ctrl_primary_reg_block(dt));
48
49 return kDifOk;
50}
51
52dif_result_t dif_rram_ctrl_get_dt(
53 const dif_rram_ctrl_t *rram_ctrl,
54 dt_rram_ctrl_t *dt) {
55 if ((int)rram_ctrl->dt == kDtRramCtrlCount || dt == NULL) {
56 return kDifBadArg;
57 }
58 *dt = rram_ctrl->dt;
59 return kDifOk;
60}
61
62 dif_result_t dif_rram_ctrl_alert_force(
63 const dif_rram_ctrl_t *rram_ctrl,
64 dif_rram_ctrl_alert_t alert) {
65 if (rram_ctrl == NULL) {
66 return kDifBadArg;
67 }
68
69 bitfield_bit32_index_t alert_idx;
70 switch (alert) {
71 case kDifRramCtrlAlertRecovErr:
72 alert_idx = RRAM_CTRL_ALERT_TEST_RECOV_ERR_BIT;
73 break;
74 case kDifRramCtrlAlertFatalStdErr:
75 alert_idx = RRAM_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT;
76 break;
77 case kDifRramCtrlAlertFatalErr:
78 alert_idx = RRAM_CTRL_ALERT_TEST_FATAL_ERR_BIT;
79 break;
80 case kDifRramCtrlAlertFatalMacroErr:
81 alert_idx = RRAM_CTRL_ALERT_TEST_FATAL_MACRO_ERR_BIT;
82 break;
83 case kDifRramCtrlAlertRecovMacroErr:
84 alert_idx = RRAM_CTRL_ALERT_TEST_RECOV_MACRO_ERR_BIT;
85 break;
86 default:
87 return kDifBadArg;
88 }
89
90 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
91 mmio_region_write32(
92 rram_ctrl->base_addr,
93 (ptrdiff_t)RRAM_CTRL_ALERT_TEST_REG_OFFSET,
94 alert_test_reg);
95
96
97 return kDifOk;
98}
99
100
101 /**
102 * Get the corresponding interrupt register bit offset of the IRQ.
103 */
104 static bool rram_ctrl_get_irq_bit_index(
105 dif_rram_ctrl_irq_t irq,
106 bitfield_bit32_index_t *index_out) {
107
108 switch (irq) {
109 case kDtRramCtrlIrqWrEmpty:
110 *index_out = RRAM_CTRL_INTR_COMMON_WR_EMPTY_BIT;
111 break;
112 case kDtRramCtrlIrqWrLvl:
113 *index_out = RRAM_CTRL_INTR_COMMON_WR_LVL_BIT;
114 break;
115 case kDtRramCtrlIrqRdFull:
116 *index_out = RRAM_CTRL_INTR_COMMON_RD_FULL_BIT;
117 break;
118 case kDtRramCtrlIrqRdLvl:
119 *index_out = RRAM_CTRL_INTR_COMMON_RD_LVL_BIT;
120 break;
121 case kDtRramCtrlIrqOpDone:
122 *index_out = RRAM_CTRL_INTR_COMMON_OP_DONE_BIT;
123 break;
124 case kDtRramCtrlIrqCorrErr:
125 *index_out = RRAM_CTRL_INTR_COMMON_CORR_ERR_BIT;
126 break;
127 default:
128 return false;
129 }
130
131 return true;
132 }
133
134 static dif_irq_type_t irq_types[] = {
135 kDifIrqTypeStatus,
136 kDifIrqTypeStatus,
137 kDifIrqTypeStatus,
138 kDifIrqTypeStatus,
139 kDifIrqTypeEvent,
140 kDifIrqTypeEvent,
141 };
142
143 OT_WARN_UNUSED_RESULT
144 dif_result_t dif_rram_ctrl_irq_get_type(
145 const dif_rram_ctrl_t *rram_ctrl,
146 dif_rram_ctrl_irq_t irq,
147 dif_irq_type_t *type) {
148
149
150 if (rram_ctrl == NULL ||
151 type == NULL ||
152 irq < kDifRramCtrlIrqWrEmpty ||
153 irq > kDifRramCtrlIrqCorrErr) {
154 return kDifBadArg;
155 }
156
157 *type = irq_types[irq];
158
159 return kDifOk;
160 }
161
162 OT_WARN_UNUSED_RESULT
163 dif_result_t dif_rram_ctrl_irq_get_state(
164 const dif_rram_ctrl_t *rram_ctrl,
165 dif_rram_ctrl_irq_state_snapshot_t *snapshot) {
166
167 if (rram_ctrl == NULL || snapshot == NULL) {
168 return kDifBadArg;
169 }
170
171 *snapshot = mmio_region_read32(
172 rram_ctrl->base_addr,
173 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET);
174
175
176 return kDifOk;
177 }
178
179 OT_WARN_UNUSED_RESULT
180 dif_result_t dif_rram_ctrl_irq_acknowledge_state(
181 const dif_rram_ctrl_t *rram_ctrl,
182 dif_rram_ctrl_irq_state_snapshot_t snapshot) {
183 if (rram_ctrl == NULL) {
184 return kDifBadArg;
185 }
186
187 mmio_region_write32(
188 rram_ctrl->base_addr,
189 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET,
190 snapshot);
191
192
193 return kDifOk;
194 }
195
196 OT_WARN_UNUSED_RESULT
197 dif_result_t dif_rram_ctrl_irq_is_pending(
198 const dif_rram_ctrl_t *rram_ctrl,
199 dif_rram_ctrl_irq_t irq,
200 bool *is_pending) {
201
202 if (rram_ctrl == NULL || is_pending == NULL) {
203 return kDifBadArg;
204 }
205
206 bitfield_bit32_index_t index;
207 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
208 return kDifBadArg;
209 }
210
211 uint32_t intr_state_reg = mmio_region_read32(
212 rram_ctrl->base_addr,
213 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET);
214
215
216 *is_pending = bitfield_bit32_read(intr_state_reg, index);
217
218 return kDifOk;
219 }
220
221 OT_WARN_UNUSED_RESULT
222 dif_result_t dif_rram_ctrl_irq_acknowledge_all(
223 const dif_rram_ctrl_t *rram_ctrl
224 ) {
225
226 if (rram_ctrl == NULL) {
227 return kDifBadArg;
228 }
229
230 // Writing to the register clears the corresponding bits (Write-one clear).
231 mmio_region_write32(
232 rram_ctrl->base_addr,
233 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET,
234 UINT32_MAX);
235
236
237 return kDifOk;
238 }
239
240 OT_WARN_UNUSED_RESULT
241 dif_result_t dif_rram_ctrl_irq_acknowledge(
242 const dif_rram_ctrl_t *rram_ctrl,
243 dif_rram_ctrl_irq_t irq) {
244
245 if (rram_ctrl == NULL) {
246 return kDifBadArg;
247 }
248
249 bitfield_bit32_index_t index;
250 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
251 return kDifBadArg;
252 }
253
254 // Writing to the register clears the corresponding bits (Write-one clear).
255 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
256 mmio_region_write32(
257 rram_ctrl->base_addr,
258 (ptrdiff_t)RRAM_CTRL_INTR_STATE_REG_OFFSET,
259 intr_state_reg);
260
261
262 return kDifOk;
263 }
264
265 OT_WARN_UNUSED_RESULT
266 dif_result_t dif_rram_ctrl_irq_force(
267 const dif_rram_ctrl_t *rram_ctrl,
268 dif_rram_ctrl_irq_t irq,
269 const bool val) {
270
271 if (rram_ctrl == NULL) {
272 return kDifBadArg;
273 }
274
275 bitfield_bit32_index_t index;
276 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
277 return kDifBadArg;
278 }
279
280 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
281 mmio_region_write32(
282 rram_ctrl->base_addr,
283 (ptrdiff_t)RRAM_CTRL_INTR_TEST_REG_OFFSET,
284 intr_test_reg);
285
286
287 return kDifOk;
288 }
289
290 OT_WARN_UNUSED_RESULT
291 dif_result_t dif_rram_ctrl_irq_get_enabled(
292 const dif_rram_ctrl_t *rram_ctrl,
293 dif_rram_ctrl_irq_t irq,
294 dif_toggle_t *state) {
295
296 if (rram_ctrl == NULL || state == NULL) {
297 return kDifBadArg;
298 }
299
300 bitfield_bit32_index_t index;
301 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
302 return kDifBadArg;
303 }
304
305 uint32_t intr_enable_reg = mmio_region_read32(
306 rram_ctrl->base_addr,
307 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET);
308
309
310 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
311 *state = is_enabled ?
312 kDifToggleEnabled : kDifToggleDisabled;
313
314 return kDifOk;
315 }
316
317 OT_WARN_UNUSED_RESULT
318 dif_result_t dif_rram_ctrl_irq_set_enabled(
319 const dif_rram_ctrl_t *rram_ctrl,
320 dif_rram_ctrl_irq_t irq,
321 dif_toggle_t state) {
322
323 if (rram_ctrl == NULL) {
324 return kDifBadArg;
325 }
326
327 bitfield_bit32_index_t index;
328 if (!rram_ctrl_get_irq_bit_index(irq, &index)) {
329 return kDifBadArg;
330 }
331
332 uint32_t intr_enable_reg = mmio_region_read32(
333 rram_ctrl->base_addr,
334 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET);
335
336
337 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
338 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
339 mmio_region_write32(
340 rram_ctrl->base_addr,
341 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET,
342 intr_enable_reg);
343
344
345 return kDifOk;
346 }
347
348 OT_WARN_UNUSED_RESULT
349 dif_result_t dif_rram_ctrl_irq_disable_all(
350 const dif_rram_ctrl_t *rram_ctrl,
351 dif_rram_ctrl_irq_enable_snapshot_t *snapshot) {
352
353 if (rram_ctrl == NULL) {
354 return kDifBadArg;
355 }
356
357 // Pass the current interrupt state to the caller, if requested.
358 if (snapshot != NULL) {
359 *snapshot = mmio_region_read32(
360 rram_ctrl->base_addr,
361 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET);
362
363 }
364
365 // Disable all interrupts.
366 mmio_region_write32(
367 rram_ctrl->base_addr,
368 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET,
369 0u);
370
371
372 return kDifOk;
373 }
374
375 OT_WARN_UNUSED_RESULT
376 dif_result_t dif_rram_ctrl_irq_restore_all(
377 const dif_rram_ctrl_t *rram_ctrl,
378 const dif_rram_ctrl_irq_enable_snapshot_t *snapshot) {
379
380 if (rram_ctrl == NULL || snapshot == NULL) {
381 return kDifBadArg;
382 }
383
384 mmio_region_write32(
385 rram_ctrl->base_addr,
386 (ptrdiff_t)RRAM_CTRL_INTR_ENABLE_REG_OFFSET,
387 *snapshot);
388
389
390 return kDifOk;
391 }
392