14 static_assert(PWM_PARAM_N_OUTPUTS == 6,
15 "Expected six PWM channels. May need to update `dif_pwm.h`.");
16 static_assert(PWM_CFG_DC_RESN_MASK == 0xf,
17 "Expected duty cycle configuration register to be 4 bits.");
20 if (pwm == NULL || config.
clock_divisor > PWM_CFG_CLK_DIV_MASK ||
26 if (!mmio_region_read32(pwm->
base_addr, PWM_REGWEN_REG_OFFSET)) {
33 uint32_t config_reg = mmio_region_read32(pwm->
base_addr, PWM_CFG_REG_OFFSET);
50 mmio_region_write32(pwm->
base_addr, PWM_CFG_REG_OFFSET, 0);
51 mmio_region_write32(pwm->
base_addr, PWM_CFG_REG_OFFSET, config_reg);
64 if (!mmio_region_read32(pwm->
base_addr, PWM_REGWEN_REG_OFFSET)) {
73 mmio_region_read32(pwm->
base_addr, PWM_CFG_REG_OFFSET),
74 PWM_CFG_DC_RESN_FIELD);
75 uint32_t beats_per_pulse_cycle = 1U << (duty_cycle_resolution + 1);
86 uint16_t phase_cntr_ticks_per_beat =
87 (uint16_t)(1 << (16 - duty_cycle_resolution - 1));
88 uint32_t duty_cycle_reg =
108 uint32_t invert_reg =
109 mmio_region_read32(pwm->
base_addr, PWM_INVERT_REG_OFFSET);
112 uint32_t blink_param_reg = 0;
123 blink_param_reg, PWM_BLINK_PARAM_0_Y_0_FIELD,
134 #define DIF_PWM_CHANNEL_CONFIG_CASE_(channel_) \
135 case kDifPwmChannel##channel_: \
136 invert_reg = bitfield_bit32_write( \
137 invert_reg, PWM_INVERT_INVERT_##channel_##_BIT, config.polarity); \
138 mmio_region_write32(pwm->base_addr, \
139 PWM_DUTY_CYCLE_##channel_##_REG_OFFSET, \
141 mmio_region_write32(pwm->base_addr, PWM_PWM_PARAM_##channel_##_REG_OFFSET, \
143 if (config.mode == kDifPwmModeHeartbeat || \
144 config.mode == kDifPwmModeBlink) { \
145 mmio_region_write32(pwm->base_addr, \
146 PWM_BLINK_PARAM_##channel_##_REG_OFFSET, \
156 #undef DIF_PWM_CHANNEL_CONFIG_CASE_
158 mmio_region_write32(pwm->
base_addr, PWM_INVERT_REG_OFFSET, invert_reg);
169 if (!mmio_region_read32(pwm->
base_addr, PWM_REGWEN_REG_OFFSET)) {
173 uint32_t config_reg = mmio_region_read32(pwm->
base_addr, PWM_CFG_REG_OFFSET);
176 mmio_region_write32(pwm->
base_addr, PWM_CFG_REG_OFFSET, config_reg);
183 if (pwm == NULL || is_enabled == NULL) {
187 uint32_t config_reg = mmio_region_read32(pwm->
base_addr, PWM_CFG_REG_OFFSET);
197 if (pwm == NULL || channels >= (1U << PWM_PARAM_N_OUTPUTS) ||
202 if (!mmio_region_read32(pwm->
base_addr, PWM_REGWEN_REG_OFFSET)) {
206 uint32_t enable_reg =
207 mmio_region_read32(pwm->
base_addr, PWM_PWM_EN_REG_OFFSET);
210 enable_reg |= channels;
212 enable_reg &= ~channels;
215 mmio_region_write32(pwm->
base_addr, PWM_PWM_EN_REG_OFFSET, enable_reg);
223 if (pwm == NULL || is_enabled == NULL) {
229 if (channel_bit >= PWM_PARAM_N_OUTPUTS) {
233 uint32_t enable_reg =
234 mmio_region_read32(pwm->
base_addr, PWM_PWM_EN_REG_OFFSET);
246 mmio_region_write32(pwm->
base_addr, PWM_REGWEN_REG_OFFSET, 0);
252 if (pwm == NULL || is_locked == NULL) {
257 mmio_region_read32(pwm->
base_addr, PWM_REGWEN_REG_OFFSET) ? false :
true;