Software APIs
dif_keymgr_dpe_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_keymgr_dpe_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "keymgr_dpe_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_keymgr_dpe_init(mmio_region_t base_addr,
18  dif_keymgr_dpe_t *keymgr_dpe) {
19  if (keymgr_dpe == NULL) {
20  return kDifBadArg;
21  }
22 
23  keymgr_dpe->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_keymgr_dpe_alert_force(const dif_keymgr_dpe_t *keymgr_dpe,
29  dif_keymgr_dpe_alert_t alert) {
30  if (keymgr_dpe == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifKeymgrDpeAlertRecovOperationErr:
37  alert_idx = KEYMGR_DPE_ALERT_TEST_RECOV_OPERATION_ERR_BIT;
38  break;
39  case kDifKeymgrDpeAlertFatalFaultErr:
40  alert_idx = KEYMGR_DPE_ALERT_TEST_FATAL_FAULT_ERR_BIT;
41  break;
42  default:
43  return kDifBadArg;
44  }
45 
46  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
47  mmio_region_write32(keymgr_dpe->base_addr,
48  (ptrdiff_t)KEYMGR_DPE_ALERT_TEST_REG_OFFSET,
49  alert_test_reg);
50 
51  return kDifOk;
52 }
53 
54 /**
55  * Get the corresponding interrupt register bit offset of the IRQ.
56  */
57 static bool keymgr_dpe_get_irq_bit_index(dif_keymgr_dpe_irq_t irq,
58  bitfield_bit32_index_t *index_out) {
59  switch (irq) {
60  case kDifKeymgrDpeIrqOpDone:
61  *index_out = KEYMGR_DPE_INTR_COMMON_OP_DONE_BIT;
62  break;
63  default:
64  return false;
65  }
66 
67  return true;
68 }
69 
70 static dif_irq_type_t irq_types[] = {
71  kDifIrqTypeEvent,
72 };
73 
74 OT_WARN_UNUSED_RESULT
75 dif_result_t dif_keymgr_dpe_irq_get_type(const dif_keymgr_dpe_t *keymgr_dpe,
76  dif_keymgr_dpe_irq_t irq,
77  dif_irq_type_t *type) {
78  if (keymgr_dpe == NULL || type == NULL || irq == kDifKeymgrDpeIrqOpDone + 1) {
79  return kDifBadArg;
80  }
81 
82  *type = irq_types[irq];
83 
84  return kDifOk;
85 }
86 
87 OT_WARN_UNUSED_RESULT
88 dif_result_t dif_keymgr_dpe_irq_get_state(
89  const dif_keymgr_dpe_t *keymgr_dpe,
90  dif_keymgr_dpe_irq_state_snapshot_t *snapshot) {
91  if (keymgr_dpe == NULL || snapshot == NULL) {
92  return kDifBadArg;
93  }
94 
95  *snapshot = mmio_region_read32(keymgr_dpe->base_addr,
96  (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET);
97 
98  return kDifOk;
99 }
100 
101 OT_WARN_UNUSED_RESULT
102 dif_result_t dif_keymgr_dpe_irq_acknowledge_state(
103  const dif_keymgr_dpe_t *keymgr_dpe,
104  dif_keymgr_dpe_irq_state_snapshot_t snapshot) {
105  if (keymgr_dpe == NULL) {
106  return kDifBadArg;
107  }
108 
109  mmio_region_write32(keymgr_dpe->base_addr,
110  (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET, snapshot);
111 
112  return kDifOk;
113 }
114 
115 OT_WARN_UNUSED_RESULT
116 dif_result_t dif_keymgr_dpe_irq_is_pending(const dif_keymgr_dpe_t *keymgr_dpe,
117  dif_keymgr_dpe_irq_t irq,
118  bool *is_pending) {
119  if (keymgr_dpe == NULL || is_pending == NULL) {
120  return kDifBadArg;
121  }
122 
123  bitfield_bit32_index_t index;
124  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
125  return kDifBadArg;
126  }
127 
128  uint32_t intr_state_reg = mmio_region_read32(
129  keymgr_dpe->base_addr, (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET);
130 
131  *is_pending = bitfield_bit32_read(intr_state_reg, index);
132 
133  return kDifOk;
134 }
135 
136 OT_WARN_UNUSED_RESULT
137 dif_result_t dif_keymgr_dpe_irq_acknowledge_all(
138  const dif_keymgr_dpe_t *keymgr_dpe) {
139  if (keymgr_dpe == NULL) {
140  return kDifBadArg;
141  }
142 
143  // Writing to the register clears the corresponding bits (Write-one clear).
144  mmio_region_write32(keymgr_dpe->base_addr,
145  (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET, UINT32_MAX);
146 
147  return kDifOk;
148 }
149 
150 OT_WARN_UNUSED_RESULT
151 dif_result_t dif_keymgr_dpe_irq_acknowledge(const dif_keymgr_dpe_t *keymgr_dpe,
152  dif_keymgr_dpe_irq_t irq) {
153  if (keymgr_dpe == NULL) {
154  return kDifBadArg;
155  }
156 
157  bitfield_bit32_index_t index;
158  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
159  return kDifBadArg;
160  }
161 
162  // Writing to the register clears the corresponding bits (Write-one clear).
163  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
164  mmio_region_write32(keymgr_dpe->base_addr,
165  (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET,
166  intr_state_reg);
167 
168  return kDifOk;
169 }
170 
171 OT_WARN_UNUSED_RESULT
172 dif_result_t dif_keymgr_dpe_irq_force(const dif_keymgr_dpe_t *keymgr_dpe,
173  dif_keymgr_dpe_irq_t irq,
174  const bool val) {
175  if (keymgr_dpe == NULL) {
176  return kDifBadArg;
177  }
178 
179  bitfield_bit32_index_t index;
180  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
181  return kDifBadArg;
182  }
183 
184  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
185  mmio_region_write32(keymgr_dpe->base_addr,
186  (ptrdiff_t)KEYMGR_DPE_INTR_TEST_REG_OFFSET,
187  intr_test_reg);
188 
189  return kDifOk;
190 }
191 
192 OT_WARN_UNUSED_RESULT
193 dif_result_t dif_keymgr_dpe_irq_get_enabled(const dif_keymgr_dpe_t *keymgr_dpe,
194  dif_keymgr_dpe_irq_t irq,
195  dif_toggle_t *state) {
196  if (keymgr_dpe == NULL || state == NULL) {
197  return kDifBadArg;
198  }
199 
200  bitfield_bit32_index_t index;
201  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
202  return kDifBadArg;
203  }
204 
205  uint32_t intr_enable_reg = mmio_region_read32(
206  keymgr_dpe->base_addr, (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET);
207 
208  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
209  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
210 
211  return kDifOk;
212 }
213 
214 OT_WARN_UNUSED_RESULT
215 dif_result_t dif_keymgr_dpe_irq_set_enabled(const dif_keymgr_dpe_t *keymgr_dpe,
216  dif_keymgr_dpe_irq_t irq,
217  dif_toggle_t state) {
218  if (keymgr_dpe == NULL) {
219  return kDifBadArg;
220  }
221 
222  bitfield_bit32_index_t index;
223  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
224  return kDifBadArg;
225  }
226 
227  uint32_t intr_enable_reg = mmio_region_read32(
228  keymgr_dpe->base_addr, (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET);
229 
230  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
231  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
232  mmio_region_write32(keymgr_dpe->base_addr,
233  (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET,
234  intr_enable_reg);
235 
236  return kDifOk;
237 }
238 
239 OT_WARN_UNUSED_RESULT
240 dif_result_t dif_keymgr_dpe_irq_disable_all(
241  const dif_keymgr_dpe_t *keymgr_dpe,
242  dif_keymgr_dpe_irq_enable_snapshot_t *snapshot) {
243  if (keymgr_dpe == NULL) {
244  return kDifBadArg;
245  }
246 
247  // Pass the current interrupt state to the caller, if requested.
248  if (snapshot != NULL) {
249  *snapshot = mmio_region_read32(
250  keymgr_dpe->base_addr, (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET);
251  }
252 
253  // Disable all interrupts.
254  mmio_region_write32(keymgr_dpe->base_addr,
255  (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET, 0u);
256 
257  return kDifOk;
258 }
259 
260 OT_WARN_UNUSED_RESULT
261 dif_result_t dif_keymgr_dpe_irq_restore_all(
262  const dif_keymgr_dpe_t *keymgr_dpe,
263  const dif_keymgr_dpe_irq_enable_snapshot_t *snapshot) {
264  if (keymgr_dpe == NULL || snapshot == NULL) {
265  return kDifBadArg;
266  }
267 
268  mmio_region_write32(keymgr_dpe->base_addr,
269  (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET, *snapshot);
270 
271  return kDifOk;
272 }
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