Software APIs
dif_keymgr_dpe_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_keymgr_dpe_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "keymgr_dpe_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_keymgr_dpe_init(mmio_region_t base_addr,
18  dif_keymgr_dpe_t *keymgr_dpe) {
19  if (keymgr_dpe == NULL) {
20  return kDifBadArg;
21  }
22 
23  keymgr_dpe->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_keymgr_dpe_alert_force(const dif_keymgr_dpe_t *keymgr_dpe,
29  dif_keymgr_dpe_alert_t alert) {
30  if (keymgr_dpe == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifKeymgrDpeAlertRecovOperationErr:
37  alert_idx = KEYMGR_DPE_ALERT_TEST_RECOV_OPERATION_ERR_BIT;
38  break;
39  case kDifKeymgrDpeAlertFatalFaultErr:
40  alert_idx = KEYMGR_DPE_ALERT_TEST_FATAL_FAULT_ERR_BIT;
41  break;
42  default:
43  return kDifBadArg;
44  }
45 
46  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
47  mmio_region_write32(keymgr_dpe->base_addr,
48  (ptrdiff_t)KEYMGR_DPE_ALERT_TEST_REG_OFFSET,
49  alert_test_reg);
50 
51  return kDifOk;
52 }
53 
54 /**
55  * Get the corresponding interrupt register bit offset of the IRQ.
56  */
57 static bool keymgr_dpe_get_irq_bit_index(dif_keymgr_dpe_irq_t irq,
58  bitfield_bit32_index_t *index_out) {
59  switch (irq) {
60  case kDifKeymgrDpeIrqOpDone:
61  *index_out = KEYMGR_DPE_INTR_COMMON_OP_DONE_BIT;
62  break;
63  default:
64  return false;
65  }
66 
67  return true;
68 }
69 
70 static dif_irq_type_t irq_types[] = {
71  kDifIrqTypeEvent,
72 };
73 
74 OT_WARN_UNUSED_RESULT
75 dif_result_t dif_keymgr_dpe_irq_get_type(const dif_keymgr_dpe_t *keymgr_dpe,
76  dif_keymgr_dpe_irq_t irq,
77  dif_irq_type_t *type) {
78  if (keymgr_dpe == NULL || type == NULL || irq < 0 ||
79  irq > kDifKeymgrDpeIrqOpDone) {
80  return kDifBadArg;
81  }
82 
83  *type = irq_types[irq];
84 
85  return kDifOk;
86 }
87 
88 OT_WARN_UNUSED_RESULT
89 dif_result_t dif_keymgr_dpe_irq_get_state(
90  const dif_keymgr_dpe_t *keymgr_dpe,
91  dif_keymgr_dpe_irq_state_snapshot_t *snapshot) {
92  if (keymgr_dpe == NULL || snapshot == NULL) {
93  return kDifBadArg;
94  }
95 
96  *snapshot = mmio_region_read32(keymgr_dpe->base_addr,
97  (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET);
98 
99  return kDifOk;
100 }
101 
102 OT_WARN_UNUSED_RESULT
103 dif_result_t dif_keymgr_dpe_irq_acknowledge_state(
104  const dif_keymgr_dpe_t *keymgr_dpe,
105  dif_keymgr_dpe_irq_state_snapshot_t snapshot) {
106  if (keymgr_dpe == NULL) {
107  return kDifBadArg;
108  }
109 
110  mmio_region_write32(keymgr_dpe->base_addr,
111  (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET, snapshot);
112 
113  return kDifOk;
114 }
115 
116 OT_WARN_UNUSED_RESULT
117 dif_result_t dif_keymgr_dpe_irq_is_pending(const dif_keymgr_dpe_t *keymgr_dpe,
118  dif_keymgr_dpe_irq_t irq,
119  bool *is_pending) {
120  if (keymgr_dpe == NULL || is_pending == NULL) {
121  return kDifBadArg;
122  }
123 
124  bitfield_bit32_index_t index;
125  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
126  return kDifBadArg;
127  }
128 
129  uint32_t intr_state_reg = mmio_region_read32(
130  keymgr_dpe->base_addr, (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET);
131 
132  *is_pending = bitfield_bit32_read(intr_state_reg, index);
133 
134  return kDifOk;
135 }
136 
137 OT_WARN_UNUSED_RESULT
138 dif_result_t dif_keymgr_dpe_irq_acknowledge_all(
139  const dif_keymgr_dpe_t *keymgr_dpe) {
140  if (keymgr_dpe == NULL) {
141  return kDifBadArg;
142  }
143 
144  // Writing to the register clears the corresponding bits (Write-one clear).
145  mmio_region_write32(keymgr_dpe->base_addr,
146  (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET, UINT32_MAX);
147 
148  return kDifOk;
149 }
150 
151 OT_WARN_UNUSED_RESULT
152 dif_result_t dif_keymgr_dpe_irq_acknowledge(const dif_keymgr_dpe_t *keymgr_dpe,
153  dif_keymgr_dpe_irq_t irq) {
154  if (keymgr_dpe == NULL) {
155  return kDifBadArg;
156  }
157 
158  bitfield_bit32_index_t index;
159  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
160  return kDifBadArg;
161  }
162 
163  // Writing to the register clears the corresponding bits (Write-one clear).
164  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
165  mmio_region_write32(keymgr_dpe->base_addr,
166  (ptrdiff_t)KEYMGR_DPE_INTR_STATE_REG_OFFSET,
167  intr_state_reg);
168 
169  return kDifOk;
170 }
171 
172 OT_WARN_UNUSED_RESULT
173 dif_result_t dif_keymgr_dpe_irq_force(const dif_keymgr_dpe_t *keymgr_dpe,
174  dif_keymgr_dpe_irq_t irq,
175  const bool val) {
176  if (keymgr_dpe == NULL) {
177  return kDifBadArg;
178  }
179 
180  bitfield_bit32_index_t index;
181  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
182  return kDifBadArg;
183  }
184 
185  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
186  mmio_region_write32(keymgr_dpe->base_addr,
187  (ptrdiff_t)KEYMGR_DPE_INTR_TEST_REG_OFFSET,
188  intr_test_reg);
189 
190  return kDifOk;
191 }
192 
193 OT_WARN_UNUSED_RESULT
194 dif_result_t dif_keymgr_dpe_irq_get_enabled(const dif_keymgr_dpe_t *keymgr_dpe,
195  dif_keymgr_dpe_irq_t irq,
196  dif_toggle_t *state) {
197  if (keymgr_dpe == NULL || state == NULL) {
198  return kDifBadArg;
199  }
200 
201  bitfield_bit32_index_t index;
202  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
203  return kDifBadArg;
204  }
205 
206  uint32_t intr_enable_reg = mmio_region_read32(
207  keymgr_dpe->base_addr, (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET);
208 
209  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
210  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
211 
212  return kDifOk;
213 }
214 
215 OT_WARN_UNUSED_RESULT
216 dif_result_t dif_keymgr_dpe_irq_set_enabled(const dif_keymgr_dpe_t *keymgr_dpe,
217  dif_keymgr_dpe_irq_t irq,
218  dif_toggle_t state) {
219  if (keymgr_dpe == NULL) {
220  return kDifBadArg;
221  }
222 
223  bitfield_bit32_index_t index;
224  if (!keymgr_dpe_get_irq_bit_index(irq, &index)) {
225  return kDifBadArg;
226  }
227 
228  uint32_t intr_enable_reg = mmio_region_read32(
229  keymgr_dpe->base_addr, (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET);
230 
231  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
232  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
233  mmio_region_write32(keymgr_dpe->base_addr,
234  (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET,
235  intr_enable_reg);
236 
237  return kDifOk;
238 }
239 
240 OT_WARN_UNUSED_RESULT
241 dif_result_t dif_keymgr_dpe_irq_disable_all(
242  const dif_keymgr_dpe_t *keymgr_dpe,
243  dif_keymgr_dpe_irq_enable_snapshot_t *snapshot) {
244  if (keymgr_dpe == NULL) {
245  return kDifBadArg;
246  }
247 
248  // Pass the current interrupt state to the caller, if requested.
249  if (snapshot != NULL) {
250  *snapshot = mmio_region_read32(
251  keymgr_dpe->base_addr, (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET);
252  }
253 
254  // Disable all interrupts.
255  mmio_region_write32(keymgr_dpe->base_addr,
256  (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET, 0u);
257 
258  return kDifOk;
259 }
260 
261 OT_WARN_UNUSED_RESULT
262 dif_result_t dif_keymgr_dpe_irq_restore_all(
263  const dif_keymgr_dpe_t *keymgr_dpe,
264  const dif_keymgr_dpe_irq_enable_snapshot_t *snapshot) {
265  if (keymgr_dpe == NULL || snapshot == NULL) {
266  return kDifBadArg;
267  }
268 
269  mmio_region_write32(keymgr_dpe->base_addr,
270  (ptrdiff_t)KEYMGR_DPE_INTR_ENABLE_REG_OFFSET, *snapshot);
271 
272  return kDifOk;
273 }
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