Software APIs
dif_keymgr_dpe.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
5#include "sw/device/lib/dif/dif_keymgr_dpe.h"
6
7#include <assert.h>
8
9#include "sw/device/lib/dif/dif_base.h"
10
11#include "hw/top/keymgr_dpe_regs.h" // Generated.
12#include "sw/device/lib/dif/autogen/dif_keymgr_dpe_autogen.h"
13
14/**
15 * Address spaces of SW_BINDING_N, SALT_N, SW_SHARE0_OUTPUT_N, and
16 * SW_SHARE1_OUTPUT_N registers must be contiguous to be able to use
17 * `mmio_region_memcpy_to/from_mmio32()`.
18 */
19static_assert(KEYMGR_DPE_SW_BINDING_1_REG_OFFSET ==
20 KEYMGR_DPE_SW_BINDING_0_REG_OFFSET + 4,
21 "SW_BINDING_N registers must be contiguous.");
22static_assert(KEYMGR_DPE_SW_BINDING_2_REG_OFFSET ==
23 KEYMGR_DPE_SW_BINDING_0_REG_OFFSET + 8,
24 "SW_BINDING_N registers must be contiguous.");
25static_assert(KEYMGR_DPE_SW_BINDING_3_REG_OFFSET ==
26 KEYMGR_DPE_SW_BINDING_0_REG_OFFSET + 12,
27 "SW_BINDING_N registers must be contiguous.");
28static_assert(KEYMGR_DPE_SW_BINDING_4_REG_OFFSET ==
29 KEYMGR_DPE_SW_BINDING_0_REG_OFFSET + 16,
30 "SW_BINDING_N registers must be contiguous.");
31static_assert(KEYMGR_DPE_SW_BINDING_5_REG_OFFSET ==
32 KEYMGR_DPE_SW_BINDING_0_REG_OFFSET + 20,
33 "SW_BINDING_N registers must be contiguous.");
34static_assert(KEYMGR_DPE_SW_BINDING_6_REG_OFFSET ==
35 KEYMGR_DPE_SW_BINDING_0_REG_OFFSET + 24,
36 "SW_BINDING_N registers must be contiguous.");
37static_assert(KEYMGR_DPE_SW_BINDING_7_REG_OFFSET ==
38 KEYMGR_DPE_SW_BINDING_0_REG_OFFSET + 28,
39 "SW_BINDING_N registers must be contiguous.");
40
41static_assert(KEYMGR_DPE_SALT_1_REG_OFFSET == KEYMGR_DPE_SALT_0_REG_OFFSET + 4,
42 "SALT_N registers must be contiguous.");
43static_assert(KEYMGR_DPE_SALT_2_REG_OFFSET == KEYMGR_DPE_SALT_0_REG_OFFSET + 8,
44 "SALT_N registers must be contiguous.");
45static_assert(KEYMGR_DPE_SALT_3_REG_OFFSET == KEYMGR_DPE_SALT_0_REG_OFFSET + 12,
46 "SALT_N registers must be contiguous.");
47static_assert(KEYMGR_DPE_SALT_4_REG_OFFSET == KEYMGR_DPE_SALT_0_REG_OFFSET + 16,
48 "SALT_N registers must be contiguous.");
49static_assert(KEYMGR_DPE_SALT_5_REG_OFFSET == KEYMGR_DPE_SALT_0_REG_OFFSET + 20,
50 "SALT_N registers must be contiguous.");
51static_assert(KEYMGR_DPE_SALT_6_REG_OFFSET == KEYMGR_DPE_SALT_0_REG_OFFSET + 24,
52 "SALT_N registers must be contiguous.");
53static_assert(KEYMGR_DPE_SALT_7_REG_OFFSET == KEYMGR_DPE_SALT_0_REG_OFFSET + 28,
54 "SALT_N registers must be contiguous.");
55
56static_assert(KEYMGR_DPE_SW_SHARE0_OUTPUT_1_REG_OFFSET ==
57 KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_OFFSET + 4,
58 "SW_SHARE0_OUTPUT_N registers must be contiguous.");
59static_assert(KEYMGR_DPE_SW_SHARE0_OUTPUT_2_REG_OFFSET ==
60 KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_OFFSET + 8,
61 "SW_SHARE0_OUTPUT_N registers must be contiguous.");
62static_assert(KEYMGR_DPE_SW_SHARE0_OUTPUT_3_REG_OFFSET ==
63 KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_OFFSET + 12,
64 "SW_SHARE0_OUTPUT_N registers must be contiguous.");
65static_assert(KEYMGR_DPE_SW_SHARE0_OUTPUT_4_REG_OFFSET ==
66 KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_OFFSET + 16,
67 "SW_SHARE0_OUTPUT_N registers must be contiguous.");
68static_assert(KEYMGR_DPE_SW_SHARE0_OUTPUT_5_REG_OFFSET ==
69 KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_OFFSET + 20,
70 "SW_SHARE0_OUTPUT_N registers must be contiguous.");
71static_assert(KEYMGR_DPE_SW_SHARE0_OUTPUT_6_REG_OFFSET ==
72 KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_OFFSET + 24,
73 "SW_SHARE0_OUTPUT_N registers must be contiguous.");
74static_assert(KEYMGR_DPE_SW_SHARE0_OUTPUT_7_REG_OFFSET ==
75 KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_OFFSET + 28,
76 "SW_SHARE0_OUTPUT_N registers must be contiguous.");
77
78static_assert(KEYMGR_DPE_SW_SHARE1_OUTPUT_1_REG_OFFSET ==
79 KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_OFFSET + 4,
80 "SW_SHARE1_OUTPUT_N registers must be contiguous.");
81static_assert(KEYMGR_DPE_SW_SHARE1_OUTPUT_2_REG_OFFSET ==
82 KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_OFFSET + 8,
83 "SW_SHARE1_OUTPUT_N registers must be contiguous.");
84static_assert(KEYMGR_DPE_SW_SHARE1_OUTPUT_3_REG_OFFSET ==
85 KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_OFFSET + 12,
86 "SW_SHARE1_OUTPUT_N registers must be contiguous.");
87static_assert(KEYMGR_DPE_SW_SHARE1_OUTPUT_4_REG_OFFSET ==
88 KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_OFFSET + 16,
89 "SW_SHARE1_OUTPUT_N registers must be contiguous.");
90static_assert(KEYMGR_DPE_SW_SHARE1_OUTPUT_5_REG_OFFSET ==
91 KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_OFFSET + 20,
92 "SW_SHARE1_OUTPUT_N registers must be contiguous.");
93static_assert(KEYMGR_DPE_SW_SHARE1_OUTPUT_6_REG_OFFSET ==
94 KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_OFFSET + 24,
95 "SW_SHARE1_OUTPUT_N registers must be contiguous.");
96static_assert(KEYMGR_DPE_SW_SHARE1_OUTPUT_7_REG_OFFSET ==
97 KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_OFFSET + 28,
98 "SW_SHARE1_OUTPUT_N registers must be contiguous.");
99
100/**
101 * Error code constants of `dif_keymgr_dpe_status_code_t` are masks for the bits
102 * of ERR_CODE register shifted left by 1.
103 */
104static_assert(kDifKeymgrDpeStatusCodeInvalidOperation >> 1 ==
105 1 << KEYMGR_DPE_ERR_CODE_INVALID_OP_BIT,
106 "Layout of ERR_CODE register changed.");
107static_assert(kDifKeymgrDpeStatusCodeInvalidKmacInput >> 1 ==
108 1 << KEYMGR_DPE_ERR_CODE_INVALID_KMAC_INPUT_BIT,
109 "Layout of ERR_CODE register changed.");
110
111/**
112 * Ensure that enum values for versioned key generation match the parameters
113 * generated by HW.
114 */
115static_assert(kDifKeymgrDpeKeyDestAes ==
116 KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_AES,
117 "Key destination macros must match the values from its enum.");
118static_assert(kDifKeymgrDpeKeyDestKmac ==
119 KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_KMAC,
120 "Key destination macros must match the values from its enum.");
121static_assert(kDifKeymgrDpeKeyDestOtbn ==
122 KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_OTBN,
123 "Key destination macros must match the values from its enum.");
124
125/**
126 * Ensure that SW-visible FSM values match the one defined as SW enum.
127 */
128static_assert(kDifKeymgrDpeStateReset ==
129 KEYMGR_DPE_WORKING_STATE_STATE_VALUE_RESET,
130 "Keymgr_DPE reported FSM state and SW enums must match.");
131static_assert(kDifKeymgrDpeStateAvailable ==
132 KEYMGR_DPE_WORKING_STATE_STATE_VALUE_AVAILABLE,
133 "Keymgr_DPE reported FSM state and SW enums must match.");
134static_assert(kDifKeymgrDpeStateDisabled ==
135 KEYMGR_DPE_WORKING_STATE_STATE_VALUE_DISABLED,
136 "Keymgr_DPE reported FSM state and SW enums must match.");
137static_assert(kDifKeymgrDpeStateInvalid ==
138 KEYMGR_DPE_WORKING_STATE_STATE_VALUE_INVALID,
139 "Keymgr_DPE reported FSM state and SW enums must match.");
140
141/**
142 * Checks if the key manager is ready for a new operation, i.e. it is idle and
143 * the CONFIG register is unlocked.
144 */
145OT_WARN_UNUSED_RESULT
146static bool is_ready(const dif_keymgr_dpe_t *keymgr_dpe) {
147 // KeymgrDPE must be idle and the CONTROL register must be writable.
148 uint32_t reg_op_status = mmio_region_read32(keymgr_dpe->base_addr,
149 KEYMGR_DPE_OP_STATUS_REG_OFFSET);
150 if (bitfield_field32_read(reg_op_status, KEYMGR_DPE_OP_STATUS_STATUS_FIELD) !=
151 KEYMGR_DPE_OP_STATUS_STATUS_VALUE_IDLE) {
152 return false;
153 }
154 uint32_t reg_cfg_regwen = mmio_region_read32(
155 keymgr_dpe->base_addr, KEYMGR_DPE_CFG_REGWEN_REG_OFFSET);
156 return bitfield_bit32_read(reg_cfg_regwen, KEYMGR_DPE_CFG_REGWEN_EN_BIT);
157}
158
159dif_result_t dif_keymgr_dpe_initialize(const dif_keymgr_dpe_t *keymgr_dpe,
160 uint32_t slot_dst_sel) {
161 if (keymgr_dpe == NULL) {
162 return kDifBadArg;
163 }
164
165 if (!is_ready(keymgr_dpe)) {
166 return kDifLocked;
167 }
168
169 // TODO(#30667): Verify if the max key version needs to be written here too!
170 // When loading the UDS the RTL fetches the max key version from
171 // the SW register. Verify that the lock is released when the
172 // version register is locked.
173 uint32_t reg_control = bitfield_field32_write(
174 KEYMGR_DPE_CONTROL_SHADOWED_REG_RESVAL,
175 KEYMGR_DPE_CONTROL_SHADOWED_SLOT_DST_SEL_FIELD, slot_dst_sel);
176 reg_control = bitfield_field32_write(
177 reg_control, KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_FIELD,
178 KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_ADVANCE);
179 mmio_region_write32_shadowed(keymgr_dpe->base_addr,
180 KEYMGR_DPE_CONTROL_SHADOWED_REG_OFFSET,
181 reg_control);
182
183 mmio_region_write32(keymgr_dpe->base_addr, KEYMGR_DPE_START_REG_OFFSET,
184 1 << KEYMGR_DPE_START_EN_BIT);
185
186 return kDifOk;
187}
188
189dif_result_t dif_keymgr_dpe_advance_state(
190 const dif_keymgr_dpe_t *keymgr_dpe,
191 const dif_keymgr_dpe_advance_params_t *params) {
192 if (keymgr_dpe == NULL || params == NULL) {
193 return kDifBadArg;
194 }
195
196 if (!is_ready(keymgr_dpe)) {
197 return kDifLocked;
198 }
199
200 // If either of SLOT_POLICY_REGWEN, MAX_KEY_VER_REGWEN or SW_BINDING_REGWEN is
201 // locked, return error.
202 uint32_t slot_policy_regwen = mmio_region_read32(
203 keymgr_dpe->base_addr, KEYMGR_DPE_SLOT_POLICY_REGWEN_REG_OFFSET);
204 if (!bitfield_bit32_read(slot_policy_regwen,
205 KEYMGR_DPE_SLOT_POLICY_REGWEN_EN_BIT)) {
206 return kDifLocked;
207 }
208
209 uint32_t reg_max_key_ver_wen = mmio_region_read32(
210 keymgr_dpe->base_addr, KEYMGR_DPE_MAX_KEY_VER_REGWEN_REG_OFFSET);
211 if (!bitfield_bit32_read(reg_max_key_ver_wen,
212 KEYMGR_DPE_MAX_KEY_VER_REGWEN_EN_BIT)) {
213 return kDifLocked;
214 }
215
216 uint32_t sw_binding_regwen = mmio_region_read32(
217 keymgr_dpe->base_addr, KEYMGR_DPE_SW_BINDING_REGWEN_REG_OFFSET);
218 if (!bitfield_bit32_read(sw_binding_regwen,
219 KEYMGR_DPE_SW_BINDING_REGWEN_EN_BIT)) {
220 return kDifLocked;
221 }
222
223 // Now that we know REGWEN registers are enabled, we can write each value and
224 // then lock REGWEN registers (rw0c).
225 mmio_region_write32(keymgr_dpe->base_addr, KEYMGR_DPE_SLOT_POLICY_REG_OFFSET,
226 params->slot_policy);
227 mmio_region_write32(keymgr_dpe->base_addr,
228 KEYMGR_DPE_SLOT_POLICY_REGWEN_REG_OFFSET, 0);
229
230 mmio_region_write32_shadowed(keymgr_dpe->base_addr,
231 KEYMGR_DPE_MAX_KEY_VER_SHADOWED_REG_OFFSET,
232 params->max_key_version);
233 mmio_region_write32(keymgr_dpe->base_addr,
234 KEYMGR_DPE_MAX_KEY_VER_REGWEN_REG_OFFSET, 0);
235
236 mmio_region_memcpy_to_mmio32(
237 keymgr_dpe->base_addr, KEYMGR_DPE_SW_BINDING_0_REG_OFFSET,
238 params->binding_value, sizeof(params->binding_value));
239 mmio_region_write32(keymgr_dpe->base_addr,
240 KEYMGR_DPE_SW_BINDING_REGWEN_REG_OFFSET, 0);
241
242 uint32_t reg_control = bitfield_field32_write(
243 KEYMGR_DPE_CONTROL_SHADOWED_REG_RESVAL,
244 KEYMGR_DPE_CONTROL_SHADOWED_SLOT_SRC_SEL_FIELD, params->slot_src_sel);
245 reg_control = bitfield_field32_write(
246 reg_control, KEYMGR_DPE_CONTROL_SHADOWED_SLOT_DST_SEL_FIELD,
247 params->slot_dst_sel);
248 reg_control = bitfield_field32_write(
249 reg_control, KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_FIELD,
250 KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_ADVANCE);
251 mmio_region_write32_shadowed(keymgr_dpe->base_addr,
252 KEYMGR_DPE_CONTROL_SHADOWED_REG_OFFSET,
253 reg_control);
254 mmio_region_write32(keymgr_dpe->base_addr, KEYMGR_DPE_START_REG_OFFSET,
255 1 << KEYMGR_DPE_START_EN_BIT);
256
257 return kDifOk;
258}
259
260dif_result_t dif_keymgr_dpe_erase_slot(
261 const dif_keymgr_dpe_t *keymgr_dpe,
262 const dif_keymgr_dpe_erase_params_t *params) {
263 if (keymgr_dpe == NULL) {
264 return kDifBadArg;
265 }
266
267 if (!is_ready(keymgr_dpe)) {
268 return kDifLocked;
269 }
270
271 uint32_t reg_control = bitfield_field32_write(
272 KEYMGR_DPE_CONTROL_SHADOWED_REG_RESVAL,
273 KEYMGR_DPE_CONTROL_SHADOWED_SLOT_DST_SEL_FIELD, params->slot_dst_sel);
274 reg_control = bitfield_field32_write(
275 reg_control, KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_FIELD,
276 KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_ERASE_SLOT);
277 mmio_region_write32_shadowed(keymgr_dpe->base_addr,
278 KEYMGR_DPE_CONTROL_SHADOWED_REG_OFFSET,
279 reg_control);
280 mmio_region_write32(keymgr_dpe->base_addr, KEYMGR_DPE_START_REG_OFFSET,
281 1 << KEYMGR_DPE_START_EN_BIT);
282
283 return kDifOk;
284}
285
286dif_result_t dif_keymgr_dpe_disable(const dif_keymgr_dpe_t *keymgr_dpe) {
287 if (keymgr_dpe == NULL) {
288 return kDifBadArg;
289 }
290
291 if (!is_ready(keymgr_dpe)) {
292 return kDifLocked;
293 }
294
295 uint32_t reg_control = bitfield_field32_write(
296 KEYMGR_DPE_CONTROL_SHADOWED_REG_RESVAL,
297 KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_FIELD,
298 KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_DISABLE);
299 mmio_region_write32_shadowed(keymgr_dpe->base_addr,
300 KEYMGR_DPE_CONTROL_SHADOWED_REG_OFFSET,
301 reg_control);
302 mmio_region_write32(keymgr_dpe->base_addr, KEYMGR_DPE_START_REG_OFFSET,
303 1 << KEYMGR_DPE_START_EN_BIT);
304
305 return kDifOk;
306}
307
308dif_result_t dif_keymgr_dpe_generate(
309 const dif_keymgr_dpe_t *keymgr_dpe,
310 const dif_keymgr_dpe_generate_params_t *params) {
311 if (keymgr_dpe == NULL || params == NULL) {
312 return kDifBadArg;
313 }
314
315 if (!is_ready(keymgr_dpe)) {
316 return kDifLocked;
317 }
318
319 uint32_t reg_control = bitfield_field32_write(
320 KEYMGR_DPE_CONTROL_SHADOWED_REG_RESVAL,
321 KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_FIELD, params->key_dest);
322 reg_control = bitfield_field32_write(
323 reg_control, KEYMGR_DPE_CONTROL_SHADOWED_SLOT_SRC_SEL_FIELD,
324 params->slot_src_sel);
325
326 if (params->sideload_key) {
327 reg_control = bitfield_field32_write(
328 reg_control, KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_FIELD,
329 KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT);
330 } else {
331 reg_control = bitfield_field32_write(
332 reg_control, KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_FIELD,
333 KEYMGR_DPE_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_SW_OUTPUT);
334 }
335 mmio_region_write32_shadowed(keymgr_dpe->base_addr,
336 KEYMGR_DPE_CONTROL_SHADOWED_REG_OFFSET,
337 reg_control);
338
339 // Write SALT and VERSION.
340 mmio_region_memcpy_to_mmio32(keymgr_dpe->base_addr,
341 KEYMGR_DPE_SALT_0_REG_OFFSET, params->salt,
342 sizeof(params->salt));
343 mmio_region_write32(keymgr_dpe->base_addr, KEYMGR_DPE_KEY_VERSION_REG_OFFSET,
344 params->version);
345
346 // Start the operation
347 mmio_region_write32(keymgr_dpe->base_addr, KEYMGR_DPE_START_REG_OFFSET,
348 1 << KEYMGR_DPE_START_EN_BIT);
349
350 return kDifOk;
351}
352
353dif_result_t dif_keymgr_dpe_read_output(const dif_keymgr_dpe_t *keymgr_dpe,
354 dif_keymgr_dpe_output_t *output) {
355 if (keymgr_dpe == NULL || output == NULL) {
356 return kDifBadArg;
357 }
358
359 mmio_region_memcpy_from_mmio32(keymgr_dpe->base_addr,
360 KEYMGR_DPE_SW_SHARE0_OUTPUT_0_REG_OFFSET,
361 output->value[0], sizeof(output->value[0]));
362 mmio_region_memcpy_from_mmio32(keymgr_dpe->base_addr,
363 KEYMGR_DPE_SW_SHARE1_OUTPUT_0_REG_OFFSET,
364 output->value[1], sizeof(output->value[1]));
365
366 return kDifOk;
367}
368
369dif_result_t dif_keymgr_dpe_get_status_codes(
370 const dif_keymgr_dpe_t *keymgr_dpe,
371 dif_keymgr_dpe_status_codes_t *status_codes) {
372 if (keymgr_dpe == NULL || status_codes == NULL) {
373 return kDifBadArg;
374 }
375
376 // Read and clear OP_STATUS register (rw1c).
377 uint32_t reg_op_status = mmio_region_read32(keymgr_dpe->base_addr,
378 KEYMGR_DPE_OP_STATUS_REG_OFFSET);
379
380 bool is_idle = false;
381 bool has_error = false;
382 switch (reg_op_status) {
383 case KEYMGR_DPE_OP_STATUS_STATUS_VALUE_IDLE:
384 is_idle = true;
385 break;
386 case KEYMGR_DPE_OP_STATUS_STATUS_VALUE_DONE_SUCCESS:
387 is_idle = true;
388 mmio_region_write32(keymgr_dpe->base_addr,
389 KEYMGR_DPE_OP_STATUS_REG_OFFSET, reg_op_status);
390 break;
391 case KEYMGR_DPE_OP_STATUS_STATUS_VALUE_DONE_ERROR:
392 is_idle = true;
393 has_error = true;
394 mmio_region_write32(keymgr_dpe->base_addr,
395 KEYMGR_DPE_OP_STATUS_REG_OFFSET, reg_op_status);
396 break;
397 case KEYMGR_DPE_OP_STATUS_STATUS_VALUE_WIP:
398 break;
399 default:
400 return kDifError;
401 }
402
403 // `kIdleBitfield` defines the idle field within
404 // `dif_keymgr_dpe_status_codes_t`.
405 *status_codes = (dif_keymgr_dpe_status_codes_t)bitfield_field32_write(
406 0, kIdleBitfield, is_idle);
407
408 if (has_error) {
409 // Read and clear ERR_CODE register (rw1c).
410 uint32_t reg_err_code = mmio_region_read32(keymgr_dpe->base_addr,
411 KEYMGR_DPE_ERR_CODE_REG_OFFSET);
412 mmio_region_write32(keymgr_dpe->base_addr, KEYMGR_DPE_ERR_CODE_REG_OFFSET,
413 reg_err_code);
414 *status_codes = (dif_keymgr_dpe_status_codes_t)bitfield_field32_write(
415 *status_codes, kErrorBitfield, reg_err_code);
416 }
417
418 return kDifOk;
419}
420
421dif_result_t dif_keymgr_dpe_get_state(const dif_keymgr_dpe_t *keymgr_dpe,
422 dif_keymgr_dpe_state_t *state) {
423 if (keymgr_dpe == NULL || state == NULL) {
424 return kDifBadArg;
425 }
426
427 uint32_t reg_state = mmio_region_read32(keymgr_dpe->base_addr,
428 KEYMGR_DPE_WORKING_STATE_REG_OFFSET);
429
430 *state =
431 bitfield_field32_read(reg_state, KEYMGR_DPE_WORKING_STATE_STATE_FIELD);
432 return kDifOk;
433}
434
435dif_result_t dif_keymgr_dpe_clear_sideload_key(
436 const dif_keymgr_dpe_t *keymgr_dpe,
437 dif_keymgr_dpe_sideload_clr_t clear_dest) {
438 if (keymgr_dpe == NULL) {
439 return kDifBadArg;
440 }
441
442 mmio_region_write32(keymgr_dpe->base_addr,
443 KEYMGR_DPE_SIDELOAD_CLEAR_REG_OFFSET, clear_dest);
444
445 return kDifOk;
446}
447
448dif_result_t dif_keymgr_dpe_configure(const dif_keymgr_dpe_t *keymgr_dpe,
449 dif_keymgr_dpe_config_t config) {
450 if (keymgr_dpe == NULL) {
451 return kDifBadArg;
452 }
453
454 // Verify if the register is unlocked
455 uint32_t reseed_regwen = mmio_region_read32(
456 keymgr_dpe->base_addr, KEYMGR_DPE_RESEED_INTERVAL_REGWEN_REG_OFFSET);
457 if (!bitfield_bit32_read(reseed_regwen,
458 KEYMGR_DPE_RESEED_INTERVAL_REGWEN_EN_BIT)) {
459 return kDifLocked;
460 }
461
462 uint32_t reg_val =
463 bitfield_field32_write(0, KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_VAL_FIELD,
464 config.entropy_reseed_interval);
465 mmio_region_write32_shadowed(keymgr_dpe->base_addr,
466 KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_REG_OFFSET,
467 reg_val);
468
469 return kDifOk;
470}