Software APIs
dif_i2c_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_i2c.h"
6 
7 #include <cstring>
8 #include <limits>
9 #include <ostream>
10 
11 #include "gtest/gtest.h"
12 #include "sw/device/lib/base/mmio.h"
13 #include "sw/device/lib/base/mock_mmio.h"
14 #include "sw/device/lib/dif/dif_test_base.h"
15 
16 #include "i2c_regs.h" // Generated.
17 
18 // We define global namespace == and << to make `dif_i2c_timing_params_t` work
19 // nicely with EXPECT_EQ.
20 bool operator==(dif_i2c_config_t a, dif_i2c_config_t b) {
21  // We just do a dumb memcmp. The config params struct is essentially an array
22  // of half-words, so we won't run into padding issues.
23  return std::memcmp(&a, &b, sizeof(dif_i2c_config_t)) == 0;
24 }
25 
26 std::ostream &operator<<(std::ostream &os, const dif_i2c_config_t &params) {
27  return os << "{\n"
28  << " .scl_time_high_cycles = " << params.scl_time_high_cycles
29  << ",\n"
30  << " .scl_time_low_cycles = " << params.scl_time_low_cycles
31  << ",\n"
32  << " .rise_cycles = " << params.rise_cycles << ",\n"
33  << " .fall_cycles = " << params.fall_cycles << ",\n"
34  << " .start_signal_setup_cycles = "
35  << params.start_signal_setup_cycles << ",\n"
36  << " .start_signal_hold_cycles = "
37  << params.start_signal_hold_cycles << ",\n"
38  << " .data_signal_setup_cycles = "
39  << params.data_signal_setup_cycles << ",\n"
40  << " .data_signal_hold_cycles = " << params.data_signal_hold_cycles
41  << ",\n"
42  << " .stop_signal_setup_cycles = "
43  << params.stop_signal_setup_cycles << ",\n"
44  << " .stop_signal_hold_cycles = " << params.stop_signal_hold_cycles
45  << ",\n"
46  << "}";
47 }
48 
49 // We define global namespace == and << to make `dif_i2c_status_t` work
50 // nicely with EXPECT_EQ.
51 bool operator==(dif_i2c_status_t a, dif_i2c_status_t b) {
52  return a.enable_host == b.enable_host && a.enable_target == b.enable_target &&
53  a.line_loopback == b.line_loopback &&
54  a.fmt_fifo_full == b.fmt_fifo_full &&
55  a.rx_fifo_full == b.rx_fifo_full &&
56  a.fmt_fifo_empty == b.fmt_fifo_empty &&
57  a.rx_fifo_empty == b.rx_fifo_empty && a.host_idle == b.host_idle &&
58  a.target_idle == b.target_idle && a.tx_fifo_full == b.tx_fifo_full &&
59  a.acq_fifo_full == b.acq_fifo_full &&
60  a.tx_fifo_empty == b.tx_fifo_empty &&
61  a.acq_fifo_empty == b.acq_fifo_empty;
62 }
63 
64 std::ostream &operator<<(std::ostream &os, const dif_i2c_status_t &params) {
65  return os << "{\n"
66  << " .enable_host = " << params.enable_host << ",\n"
67  << " .enable_target = " << params.enable_target << ",\n"
68  << " .line_loopback = " << params.line_loopback << ",\n"
69  << " .fmt_fifo_full = " << params.fmt_fifo_full << ",\n"
70  << " .rx_fifo_full = " << params.rx_fifo_full << ",\n"
71  << " .fmt_fifo_empty = " << params.fmt_fifo_empty << ",\n"
72  << " .rx_fifo_empty = " << params.rx_fifo_empty << ",\n"
73  << " .host_idle = " << params.host_idle << ",\n"
74  << " .target_idle = " << params.target_idle << ",\n"
75  << " .tx_fifo_full = " << params.tx_fifo_full << ",\n"
76  << " .acq_fifo_full = " << params.acq_fifo_full << ",\n"
77  << " .tx_fifo_empty = " << params.tx_fifo_empty << ",\n"
78  << " .acq_fifo_empty = " << params.acq_fifo_empty << ",\n"
79  << "}";
80 }
81 
82 namespace dif_i2c_unittest {
83 namespace {
84 using ::mock_mmio::LeInt;
85 using ::mock_mmio::MmioTest;
86 using ::mock_mmio::MockDevice;
87 
88 class I2cTest : public testing::Test, public MmioTest {
89  protected:
90  dif_i2c_t i2c_ = {.base_addr = dev().region()};
91 };
92 
93 // "Base" configs consisting of harware timings, in "slow" and "fast" variants.
94 constexpr dif_i2c_timing_config_t kBaseConfigSlow = {
95  .lowest_target_device_speed =
96  kDifI2cSpeedStandard, // Remove once we upgrade the host compiler.
97  .clock_period_nanos = 90,
98  .sda_rise_nanos = 250,
99  .sda_fall_nanos = 220,
100 };
101 
102 constexpr dif_i2c_timing_config_t kBaseConfigFast = {
103  .lowest_target_device_speed =
104  kDifI2cSpeedStandard, // Remove once we upgrade the host compiler.
105  .clock_period_nanos = 20,
106  .sda_rise_nanos = 120,
107  .sda_fall_nanos = 130,
108 };
109 
110 TEST(ComputeTimingTest, StandardSpeed) {
111  dif_i2c_timing_config_t config;
112  dif_i2c_config_t params, expected;
113 
114  config = kBaseConfigSlow;
115  config.lowest_target_device_speed = kDifI2cSpeedStandard;
116  expected = {
117  .scl_time_high_cycles = 53,
118  .scl_time_low_cycles = 53,
119  .rise_cycles = 3,
120  .fall_cycles = 3,
121  .start_signal_setup_cycles = 53,
122  .start_signal_hold_cycles = 45,
123  .data_signal_setup_cycles = 3,
124  .data_signal_hold_cycles = 1,
125  .stop_signal_setup_cycles = 45,
126  .stop_signal_hold_cycles = 53,
127  };
128  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
129  EXPECT_EQ(params, expected);
130 
131  config = kBaseConfigFast;
132  config.lowest_target_device_speed = kDifI2cSpeedStandard;
133  expected = {
134  .scl_time_high_cycles = 252,
135  .scl_time_low_cycles = 235,
136  .rise_cycles = 6,
137  .fall_cycles = 7,
138  .start_signal_setup_cycles = 235,
139  .start_signal_hold_cycles = 200,
140  .data_signal_setup_cycles = 13,
141  .data_signal_hold_cycles = 1,
142  .stop_signal_setup_cycles = 200,
143  .stop_signal_hold_cycles = 235,
144  };
145  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
146  EXPECT_EQ(params, expected);
147 
148  config = kBaseConfigSlow;
149  config.lowest_target_device_speed = kDifI2cSpeedStandard;
150  config.scl_period_nanos = 11000;
151  expected = {
152  .scl_time_high_cycles = 64,
153  .scl_time_low_cycles = 53,
154  .rise_cycles = 3,
155  .fall_cycles = 3,
156  .start_signal_setup_cycles = 53,
157  .start_signal_hold_cycles = 45,
158  .data_signal_setup_cycles = 3,
159  .data_signal_hold_cycles = 1,
160  .stop_signal_setup_cycles = 45,
161  .stop_signal_hold_cycles = 53,
162  };
163  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
164  EXPECT_EQ(params, expected);
165 
166  // Test that the SCL high and low times are bounded at a minimum
167  // of 4 cycles. for these branches to execute we need to have
168  // scl_time_high_cycles < 4 and scl_time_low_cycles < 4
169  // and lengthened_high_cycles (calculated in the DIF) < 4.
170  // Based on our config and the DIFs calculations we choose the
171  // smallest valid multiple of 100, which is 1600.
172  static_assert(kDifI2cInputDelayCycles == 4,
173  "I2C DIF unit tests are hardcoded for 4 input delay cycles.");
174  config = kBaseConfigSlow;
175  config.lowest_target_device_speed = kDifI2cSpeedStandard;
176  config.clock_period_nanos = 1600;
177  expected = {
178  .scl_time_high_cycles = 4,
179  .scl_time_low_cycles = 4,
180  .rise_cycles = 1,
181  .fall_cycles = 1,
182  .start_signal_setup_cycles = 3,
183  .start_signal_hold_cycles = 3,
184  .data_signal_setup_cycles = 1,
185  .data_signal_hold_cycles = 1,
186  .stop_signal_setup_cycles = 3,
187  .stop_signal_hold_cycles = 3,
188  };
189  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
190  EXPECT_EQ(params, expected);
191 }
192 
193 TEST(ComputeTimingTest, FastSpeed) {
194  dif_i2c_timing_config_t config;
195  dif_i2c_config_t params, expected;
196 
197  config = kBaseConfigSlow;
198  config.lowest_target_device_speed = kDifI2cSpeedFast;
199  expected = {
200  .scl_time_high_cycles = 7,
201  .scl_time_low_cycles = 15,
202  .rise_cycles = 3,
203  .fall_cycles = 3,
204  .start_signal_setup_cycles = 7,
205  .start_signal_hold_cycles = 7,
206  .data_signal_setup_cycles = 2,
207  .data_signal_hold_cycles = 1,
208  .stop_signal_setup_cycles = 7,
209  .stop_signal_hold_cycles = 15,
210  };
211  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
212  EXPECT_EQ(params, expected);
213 
214  config = kBaseConfigFast;
215  config.lowest_target_device_speed = kDifI2cSpeedFast;
216  expected = {
217  .scl_time_high_cycles = 47,
218  .scl_time_low_cycles = 65,
219  .rise_cycles = 6,
220  .fall_cycles = 7,
221  .start_signal_setup_cycles = 30,
222  .start_signal_hold_cycles = 30,
223  .data_signal_setup_cycles = 5,
224  .data_signal_hold_cycles = 1,
225  .stop_signal_setup_cycles = 30,
226  .stop_signal_hold_cycles = 65,
227  };
228  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
229  EXPECT_EQ(params, expected);
230 
231  config = kBaseConfigSlow;
232  config.lowest_target_device_speed = kDifI2cSpeedFast;
233  config.scl_period_nanos = 8000;
234  expected = {
235  .scl_time_high_cycles = 68,
236  .scl_time_low_cycles = 15,
237  .rise_cycles = 3,
238  .fall_cycles = 3,
239  .start_signal_setup_cycles = 7,
240  .start_signal_hold_cycles = 7,
241  .data_signal_setup_cycles = 2,
242  .data_signal_hold_cycles = 1,
243  .stop_signal_setup_cycles = 7,
244  .stop_signal_hold_cycles = 15,
245  };
246  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
247  EXPECT_EQ(params, expected);
248 
249  // Test that the SCL high and low times are bounded at a minimum
250  // of 4 cycles. for these branches to execute we need to have
251  // scl_time_high_cycles < 4 and scl_time_low_cycles < 4
252  // and lengthened_high_cycles (calculated in the DIF) < 4.
253  // Based on our config and the DIFs calculations we choose the
254  // smallest valid multiple of 100, which is 500.
255  static_assert(kDifI2cInputDelayCycles == 4,
256  "I2C DIF unit tests are hardcoded for 4 input delay cycles.");
257  config = kBaseConfigSlow;
258  config.lowest_target_device_speed = kDifI2cSpeedFast;
259  config.clock_period_nanos = 500;
260  expected = {
261  .scl_time_high_cycles = 4,
262  .scl_time_low_cycles = 4,
263  .rise_cycles = 1,
264  .fall_cycles = 1,
265  .start_signal_setup_cycles = 2,
266  .start_signal_hold_cycles = 2,
267  .data_signal_setup_cycles = 1,
268  .data_signal_hold_cycles = 1,
269  .stop_signal_setup_cycles = 2,
270  .stop_signal_hold_cycles = 3,
271  };
272  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
273  EXPECT_EQ(params, expected);
274 }
275 
276 TEST(ComputeTimingTest, FastPlusSpeed) {
277  dif_i2c_timing_config_t config;
278  dif_i2c_config_t params, expected;
279 
280  config = kBaseConfigFast;
281  config.lowest_target_device_speed = kDifI2cSpeedFastPlus;
282  expected = {
283  .scl_time_high_cycles = 13,
284  .scl_time_low_cycles = 25,
285  .rise_cycles = 6,
286  .fall_cycles = 7,
287  .start_signal_setup_cycles = 13,
288  .start_signal_hold_cycles = 13,
289  .data_signal_setup_cycles = 3,
290  .data_signal_hold_cycles = 1,
291  .stop_signal_setup_cycles = 13,
292  .stop_signal_hold_cycles = 25,
293  };
294  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
295  EXPECT_EQ(params, expected);
296 
297  config = kBaseConfigFast;
298  config.lowest_target_device_speed = kDifI2cSpeedFastPlus;
299  config.scl_period_nanos = 1500;
300  expected = {
301  .scl_time_high_cycles = 37,
302  .scl_time_low_cycles = 25,
303  .rise_cycles = 6,
304  .fall_cycles = 7,
305  .start_signal_setup_cycles = 13,
306  .start_signal_hold_cycles = 13,
307  .data_signal_setup_cycles = 3,
308  .data_signal_hold_cycles = 1,
309  .stop_signal_setup_cycles = 13,
310  .stop_signal_hold_cycles = 25,
311  };
312  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
313  EXPECT_EQ(params, expected);
314 
315  // Test that the SCL high and low times are bounded at a minimum
316  // of 4 cycles. for these branches to execute we need to have
317  // scl_time_high_cycles < 4 and scl_time_low_cycles < 4
318  // and lengthened_high_cycles (calculated in the DIF) < 4.
319  // Based on our config and the DIFs calculations we choose the
320  // smallest valid multiple of 100, which is 200.
321  static_assert(kDifI2cInputDelayCycles == 4,
322  "I2C DIF unit tests are hardcoded for 4 input delay cycles.");
323  config = kBaseConfigFast;
324  config.lowest_target_device_speed = kDifI2cSpeedFastPlus;
325  config.clock_period_nanos = 200;
326  expected = {
327  .scl_time_high_cycles = 4,
328  .scl_time_low_cycles = 4,
329  .rise_cycles = 1,
330  .fall_cycles = 1,
331  .start_signal_setup_cycles = 2,
332  .start_signal_hold_cycles = 2,
333  .data_signal_setup_cycles = 1,
334  .data_signal_hold_cycles = 1,
335  .stop_signal_setup_cycles = 2,
336  .stop_signal_hold_cycles = 3,
337  };
338  EXPECT_DIF_OK(dif_i2c_compute_timing(config, &params));
339  EXPECT_EQ(params, expected);
340 }
341 
342 TEST(ComputeTimingTest, NullArgs) {
343  EXPECT_DIF_BADARG(dif_i2c_compute_timing(kBaseConfigFast, nullptr));
344 }
345 
346 class ConfigTest : public I2cTest {};
347 
348 TEST_F(ConfigTest, NormalInit) {
349  dif_i2c_config_t config = {
350  .scl_time_high_cycles = 252,
351  .scl_time_low_cycles = 235,
352  .rise_cycles = 6,
353  .fall_cycles = 7,
354  .start_signal_setup_cycles = 235,
355  .start_signal_hold_cycles = 200,
356  .data_signal_setup_cycles = 13,
357  .data_signal_hold_cycles = 1,
358  .stop_signal_setup_cycles = 200,
359  .stop_signal_hold_cycles = 235,
360  };
361 
362  EXPECT_WRITE32(I2C_TIMING0_REG_OFFSET,
363  {
364  {I2C_TIMING0_THIGH_OFFSET, config.scl_time_high_cycles},
365  {I2C_TIMING0_TLOW_OFFSET, config.scl_time_low_cycles},
366  });
367  EXPECT_WRITE32(I2C_TIMING1_REG_OFFSET,
368  {
369  {I2C_TIMING1_T_R_OFFSET, config.rise_cycles},
370  {I2C_TIMING1_T_F_OFFSET, config.fall_cycles},
371  });
372  EXPECT_WRITE32(
373  I2C_TIMING2_REG_OFFSET,
374  {
375  {I2C_TIMING2_TSU_STA_OFFSET, config.start_signal_setup_cycles},
376  {I2C_TIMING2_THD_STA_OFFSET, config.start_signal_hold_cycles},
377  });
378  EXPECT_WRITE32(
379  I2C_TIMING3_REG_OFFSET,
380  {
381  {I2C_TIMING3_TSU_DAT_OFFSET, config.data_signal_setup_cycles},
382  {I2C_TIMING3_THD_DAT_OFFSET, config.data_signal_hold_cycles},
383  });
384  EXPECT_WRITE32(
385  I2C_TIMING4_REG_OFFSET,
386  {
387  {I2C_TIMING4_TSU_STO_OFFSET, config.stop_signal_setup_cycles},
388  {I2C_TIMING4_T_BUF_OFFSET, config.stop_signal_hold_cycles},
389  });
390 
391  EXPECT_DIF_OK(dif_i2c_configure(&i2c_, config));
392 
393  dif_i2c_status status, expectedStatus;
394  EXPECT_READ32(I2C_CTRL_REG_OFFSET, 0x0000000b); // Host and Target active
395  EXPECT_READ32(I2C_STATUS_REG_OFFSET, 0x0000073c); // All empty and idle
396  EXPECT_DIF_OK(dif_i2c_get_status(&i2c_, &status));
397  expectedStatus = {
398  .enable_host = true,
399  .enable_target = true,
400  .ack_control_en = true,
401  .fmt_fifo_empty = true,
402  .rx_fifo_empty = true,
403  .host_idle = true,
404  .target_idle = true,
405  .tx_fifo_empty = true,
406  .acq_fifo_empty = true,
407  .ack_ctrl_stretch = true,
408  };
409  EXPECT_EQ(status, expectedStatus);
410 }
411 
412 TEST_F(ConfigTest, NullArgs) {
413  dif_i2c_status status;
414  EXPECT_DIF_BADARG(dif_i2c_get_status(nullptr, &status));
415  EXPECT_DIF_BADARG(dif_i2c_get_status(&i2c_, nullptr));
416  EXPECT_DIF_BADARG(dif_i2c_configure(nullptr, {}));
417 }
418 
419 class FifoCtrlTest : public I2cTest {};
420 
421 TEST_F(FifoCtrlTest, RxReset) {
422  EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
423  {{I2C_FIFO_CTRL_RXRST_BIT, 0x1, 0x1}});
424  EXPECT_DIF_OK(dif_i2c_reset_rx_fifo(&i2c_));
425 }
426 
427 TEST_F(FifoCtrlTest, RxNullArgs) {
428  EXPECT_DIF_BADARG(dif_i2c_reset_rx_fifo(nullptr));
429 }
430 
431 TEST_F(FifoCtrlTest, FmtReset) {
432  EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
433  {{I2C_FIFO_CTRL_FMTRST_BIT, 0x1, 0x1}});
434  EXPECT_DIF_OK(dif_i2c_reset_fmt_fifo(&i2c_));
435 }
436 
437 TEST_F(FifoCtrlTest, FmtNullArgs) {
438  EXPECT_DIF_BADARG(dif_i2c_reset_fmt_fifo(nullptr));
439 }
440 
441 TEST_F(FifoCtrlTest, AcqReset) {
442  EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
443  {{I2C_FIFO_CTRL_ACQRST_BIT, 0x1, 0x1}});
444  EXPECT_DIF_OK(dif_i2c_reset_acq_fifo(&i2c_));
445 }
446 
447 TEST_F(FifoCtrlTest, AcqNullArgs) {
448  EXPECT_DIF_BADARG(dif_i2c_reset_acq_fifo(nullptr));
449 }
450 
451 TEST_F(FifoCtrlTest, TxReset) {
452  EXPECT_MASK32(I2C_FIFO_CTRL_REG_OFFSET,
453  {{I2C_FIFO_CTRL_TXRST_BIT, 0x1, 0x1}});
454  EXPECT_DIF_OK(dif_i2c_reset_tx_fifo(&i2c_));
455 }
456 
457 TEST_F(FifoCtrlTest, TxNullArgs) {
458  EXPECT_DIF_BADARG(dif_i2c_reset_tx_fifo(nullptr));
459 }
460 
461 class HostFifoConfigTest : public I2cTest {};
462 
463 TEST_F(HostFifoConfigTest, SetLevels) {
464  EXPECT_MASK32(I2C_HOST_FIFO_CONFIG_REG_OFFSET,
465  {
466  {
467  I2C_HOST_FIFO_CONFIG_RX_THRESH_OFFSET,
468  I2C_HOST_FIFO_CONFIG_RX_THRESH_MASK,
469  0u,
470  },
471  {
472  I2C_HOST_FIFO_CONFIG_FMT_THRESH_OFFSET,
473  I2C_HOST_FIFO_CONFIG_FMT_THRESH_MASK,
474  2u,
475  },
476  });
477  EXPECT_DIF_OK(dif_i2c_set_host_watermarks(&i2c_, /*rx_level > */ 0u,
478  /*fmt_level < */ 2u));
479 
480  EXPECT_MASK32(I2C_HOST_FIFO_CONFIG_REG_OFFSET,
481  {
482  {
483  I2C_HOST_FIFO_CONFIG_RX_THRESH_OFFSET,
484  I2C_HOST_FIFO_CONFIG_RX_THRESH_MASK,
485  3u,
486  },
487  {
488  I2C_HOST_FIFO_CONFIG_FMT_THRESH_OFFSET,
489  I2C_HOST_FIFO_CONFIG_FMT_THRESH_MASK,
490  17u,
491  },
492  });
493  EXPECT_DIF_OK(dif_i2c_set_host_watermarks(&i2c_, /*rx_level > */ 3u,
494  /*fmt_level < */ 17u));
495 
496  EXPECT_MASK32(I2C_HOST_FIFO_CONFIG_REG_OFFSET,
497  {
498  {
499  I2C_HOST_FIFO_CONFIG_RX_THRESH_OFFSET,
500  I2C_HOST_FIFO_CONFIG_RX_THRESH_MASK,
501  29u,
502  },
503  {
504  I2C_HOST_FIFO_CONFIG_FMT_THRESH_OFFSET,
505  I2C_HOST_FIFO_CONFIG_FMT_THRESH_MASK,
506  9u,
507  },
508  });
509  EXPECT_DIF_OK(dif_i2c_set_host_watermarks(&i2c_, /*rx_level > */ 29u,
510  /*fmt_level < */ 9u));
511 }
512 
513 TEST_F(HostFifoConfigTest, SetLevelsNullArgs) {
514  EXPECT_DIF_BADARG(dif_i2c_set_host_watermarks(nullptr, /*rx_level > */ 3u,
515  /*fmt_level < */ 17u));
516 }
517 
518 class TargetFifoConfigTest : public I2cTest {};
519 
520 TEST_F(TargetFifoConfigTest, SetLevels) {
521  EXPECT_MASK32(I2C_TARGET_FIFO_CONFIG_REG_OFFSET,
522  {
523  {
524  I2C_TARGET_FIFO_CONFIG_TX_THRESH_OFFSET,
525  I2C_TARGET_FIFO_CONFIG_TX_THRESH_MASK,
526  2u,
527  },
528  {
529  I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_OFFSET,
530  I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_MASK,
531  0u,
532  },
533  });
534  EXPECT_DIF_OK(dif_i2c_set_target_watermarks(&i2c_, /*tx_level < */ 2u,
535  /*acq_level > */ 0u));
536 
537  EXPECT_MASK32(I2C_TARGET_FIFO_CONFIG_REG_OFFSET,
538  {
539  {
540  I2C_TARGET_FIFO_CONFIG_TX_THRESH_OFFSET,
541  I2C_TARGET_FIFO_CONFIG_TX_THRESH_MASK,
542  17u,
543  },
544  {
545  I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_OFFSET,
546  I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_MASK,
547  3u,
548  },
549  });
550  EXPECT_DIF_OK(dif_i2c_set_target_watermarks(&i2c_, /*tx_level < */ 17u,
551  /*acq_level > */ 3u));
552 
553  EXPECT_MASK32(I2C_TARGET_FIFO_CONFIG_REG_OFFSET,
554  {
555  {
556  I2C_TARGET_FIFO_CONFIG_TX_THRESH_OFFSET,
557  I2C_TARGET_FIFO_CONFIG_TX_THRESH_MASK,
558  29u,
559  },
560  {
561  I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_OFFSET,
562  I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_MASK,
563  9u,
564  },
565  });
566  EXPECT_DIF_OK(dif_i2c_set_target_watermarks(&i2c_, /*tx_level < */ 29u,
567  /*acq_level > */ 9u));
568 }
569 
570 TEST_F(TargetFifoConfigTest, SetLevelsNullArgs) {
571  EXPECT_DIF_BADARG(dif_i2c_set_target_watermarks(nullptr, /*tx_level < */ 17u,
572  /*acq_level > */ 3u));
573 }
574 
575 class ControlTest : public I2cTest {};
576 
577 TEST_F(ControlTest, HostEnable) {
578  EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ENABLEHOST_BIT, 0x1, 0x1}});
579  EXPECT_DIF_OK(dif_i2c_host_set_enabled(&i2c_, kDifToggleEnabled));
580 
581  EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ENABLEHOST_BIT, 0x1, 0x0}});
582  EXPECT_DIF_OK(dif_i2c_host_set_enabled(&i2c_, kDifToggleDisabled));
583 
584  EXPECT_MASK32(I2C_CTRL_REG_OFFSET,
585  {{I2C_CTRL_MULTI_CONTROLLER_MONITOR_EN_BIT, 0x1, 0x1}});
586  EXPECT_DIF_OK(
587  dif_i2c_multi_controller_monitor_set_enabled(&i2c_, kDifToggleEnabled));
588 
589  EXPECT_MASK32(I2C_CTRL_REG_OFFSET,
590  {{I2C_CTRL_MULTI_CONTROLLER_MONITOR_EN_BIT, 0x1, 0x0}});
591  EXPECT_DIF_OK(
592  dif_i2c_multi_controller_monitor_set_enabled(&i2c_, kDifToggleDisabled));
593 }
594 
595 TEST_F(ControlTest, HostEnableNullArgs) {
596  EXPECT_DIF_BADARG(dif_i2c_host_set_enabled(nullptr, kDifToggleEnabled));
597  EXPECT_DIF_BADARG(
598  dif_i2c_multi_controller_monitor_set_enabled(nullptr, kDifToggleEnabled));
599 
600  dif_i2c_controller_halt_events_t events_arg = {0};
601  EXPECT_DIF_BADARG(dif_i2c_get_controller_halt_events(nullptr, &events_arg));
602  EXPECT_DIF_BADARG(dif_i2c_get_controller_halt_events(&i2c_, nullptr));
603  EXPECT_DIF_BADARG(dif_i2c_clear_controller_halt_events(nullptr, events_arg));
604 }
605 
606 TEST_F(ControlTest, ControllerHaltEvents) {
607  dif_i2c_controller_halt_events_t events_arg = {0};
608  EXPECT_READ32(I2C_CONTROLLER_EVENTS_REG_OFFSET,
609  {
610  {I2C_CONTROLLER_EVENTS_NACK_BIT, 1},
611  {I2C_CONTROLLER_EVENTS_ARBITRATION_LOST_BIT, 1},
612  });
613  EXPECT_DIF_OK(dif_i2c_get_controller_halt_events(&i2c_, &events_arg));
614  EXPECT_TRUE(events_arg.nack_received);
615  EXPECT_FALSE(events_arg.unhandled_nack_timeout);
616  EXPECT_FALSE(events_arg.bus_timeout);
617  EXPECT_TRUE(events_arg.arbitration_lost);
618 
619  EXPECT_READ32(I2C_CONTROLLER_EVENTS_REG_OFFSET,
620  {
621  {I2C_CONTROLLER_EVENTS_UNHANDLED_NACK_TIMEOUT_BIT, 1},
622  {I2C_CONTROLLER_EVENTS_BUS_TIMEOUT_BIT, 1},
623  });
624  EXPECT_DIF_OK(dif_i2c_get_controller_halt_events(&i2c_, &events_arg));
625  EXPECT_FALSE(events_arg.nack_received);
626  EXPECT_TRUE(events_arg.unhandled_nack_timeout);
627  EXPECT_TRUE(events_arg.bus_timeout);
628  EXPECT_FALSE(events_arg.arbitration_lost);
629 
630  events_arg.nack_received = false;
631  events_arg.unhandled_nack_timeout = true;
632  events_arg.bus_timeout = false;
633  EXPECT_WRITE32(I2C_CONTROLLER_EVENTS_REG_OFFSET,
634  {
635  {I2C_CONTROLLER_EVENTS_NACK_BIT, 0},
636  {I2C_CONTROLLER_EVENTS_UNHANDLED_NACK_TIMEOUT_BIT, 1},
637  {I2C_CONTROLLER_EVENTS_BUS_TIMEOUT_BIT, 0},
638  });
639  EXPECT_DIF_OK(dif_i2c_clear_controller_halt_events(&i2c_, events_arg));
640 
641  events_arg.nack_received = true;
642  events_arg.unhandled_nack_timeout = false;
643  events_arg.bus_timeout = true;
644  events_arg.arbitration_lost = false;
645  EXPECT_WRITE32(I2C_CONTROLLER_EVENTS_REG_OFFSET,
646  {
647  {I2C_CONTROLLER_EVENTS_NACK_BIT, 1},
648  {I2C_CONTROLLER_EVENTS_UNHANDLED_NACK_TIMEOUT_BIT, 0},
649  {I2C_CONTROLLER_EVENTS_BUS_TIMEOUT_BIT, 1},
650  {I2C_CONTROLLER_EVENTS_ARBITRATION_LOST_BIT, 0},
651  });
652  EXPECT_DIF_OK(dif_i2c_clear_controller_halt_events(&i2c_, events_arg));
653 }
654 
655 TEST_F(ControlTest, DeviceEnable) {
656  EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ENABLETARGET_BIT, 0x1, 0x1}});
657  EXPECT_DIF_OK(dif_i2c_device_set_enabled(&i2c_, kDifToggleEnabled));
658 
659  EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ENABLETARGET_BIT, 0x1, 0x0}});
660  EXPECT_DIF_OK(dif_i2c_device_set_enabled(&i2c_, kDifToggleDisabled));
661 
662  EXPECT_MASK32(I2C_CTRL_REG_OFFSET,
663  {{I2C_CTRL_NACK_ADDR_AFTER_TIMEOUT_BIT, 0x1, 0x1}});
664  EXPECT_DIF_OK(dif_i2c_addr_nack_set_enabled(&i2c_, kDifToggleEnabled));
665 
666  EXPECT_MASK32(I2C_CTRL_REG_OFFSET,
667  {{I2C_CTRL_NACK_ADDR_AFTER_TIMEOUT_BIT, 0x1, 0x0}});
668  EXPECT_DIF_OK(dif_i2c_addr_nack_set_enabled(&i2c_, kDifToggleDisabled));
669 
670  EXPECT_MASK32(I2C_CTRL_REG_OFFSET,
671  {{I2C_CTRL_TX_STRETCH_CTRL_EN_BIT, 0x1, 0x1}});
672  EXPECT_DIF_OK(
673  dif_i2c_target_tx_stretch_ctrl_set_enabled(&i2c_, kDifToggleEnabled));
674 
675  EXPECT_MASK32(I2C_CTRL_REG_OFFSET,
676  {{I2C_CTRL_TX_STRETCH_CTRL_EN_BIT, 0x1, 0x0}});
677  EXPECT_DIF_OK(
678  dif_i2c_target_tx_stretch_ctrl_set_enabled(&i2c_, kDifToggleDisabled));
679 }
680 
681 TEST_F(ControlTest, DeviceEnableNullArgs) {
682  EXPECT_DIF_BADARG(dif_i2c_device_set_enabled(nullptr, kDifToggleEnabled));
683  EXPECT_DIF_BADARG(dif_i2c_addr_nack_set_enabled(nullptr, kDifToggleEnabled));
684  EXPECT_DIF_BADARG(
685  dif_i2c_target_tx_stretch_ctrl_set_enabled(nullptr, kDifToggleEnabled));
686 
687  dif_i2c_target_tx_halt_events_t events_arg = {0};
688  EXPECT_DIF_BADARG(dif_i2c_get_target_tx_halt_events(nullptr, &events_arg));
689  EXPECT_DIF_BADARG(dif_i2c_get_target_tx_halt_events(&i2c_, nullptr));
690  EXPECT_DIF_BADARG(dif_i2c_clear_target_tx_halt_events(nullptr, events_arg));
691 }
692 
693 TEST_F(ControlTest, DeviceHaltEvents) {
694  dif_i2c_target_tx_halt_events_t events_arg = {0};
695  EXPECT_READ32(I2C_TARGET_EVENTS_REG_OFFSET,
696  {
697  {I2C_TARGET_EVENTS_TX_PENDING_BIT, 1},
698  });
699  EXPECT_DIF_OK(dif_i2c_get_target_tx_halt_events(&i2c_, &events_arg));
700  EXPECT_TRUE(events_arg.tx_pending);
701  EXPECT_FALSE(events_arg.bus_timeout);
702  EXPECT_FALSE(events_arg.arbitration_lost);
703 
704  EXPECT_READ32(I2C_TARGET_EVENTS_REG_OFFSET,
705  {
706  {I2C_TARGET_EVENTS_BUS_TIMEOUT_BIT, 1},
707  {I2C_TARGET_EVENTS_ARBITRATION_LOST_BIT, 1},
708  });
709  EXPECT_DIF_OK(dif_i2c_get_target_tx_halt_events(&i2c_, &events_arg));
710  EXPECT_FALSE(events_arg.tx_pending);
711  EXPECT_TRUE(events_arg.bus_timeout);
712  EXPECT_TRUE(events_arg.arbitration_lost);
713 
714  events_arg.tx_pending = false;
715  events_arg.bus_timeout = true;
716  events_arg.arbitration_lost = false;
717  EXPECT_WRITE32(I2C_TARGET_EVENTS_REG_OFFSET,
718  {
719  {I2C_TARGET_EVENTS_TX_PENDING_BIT, 0},
720  {I2C_TARGET_EVENTS_BUS_TIMEOUT_BIT, 1},
721  {I2C_TARGET_EVENTS_ARBITRATION_LOST_BIT, 0},
722  });
723  EXPECT_DIF_OK(dif_i2c_clear_target_tx_halt_events(&i2c_, events_arg));
724 
725  events_arg.tx_pending = true;
726  events_arg.bus_timeout = false;
727  events_arg.arbitration_lost = true;
728  EXPECT_WRITE32(I2C_TARGET_EVENTS_REG_OFFSET,
729  {
730  {I2C_TARGET_EVENTS_TX_PENDING_BIT, 1},
731  {I2C_TARGET_EVENTS_BUS_TIMEOUT_BIT, 0},
732  {I2C_TARGET_EVENTS_ARBITRATION_LOST_BIT, 1},
733  });
734  EXPECT_DIF_OK(dif_i2c_clear_target_tx_halt_events(&i2c_, events_arg));
735 }
736 
737 TEST_F(ControlTest, LLPBK) {
738  EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_LLPBK_BIT, 0x1, 0x1}});
739  EXPECT_DIF_OK(dif_i2c_line_loopback_set_enabled(&i2c_, kDifToggleEnabled));
740 
741  EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_LLPBK_BIT, 0x1, 0x0}});
742  EXPECT_DIF_OK(dif_i2c_line_loopback_set_enabled(&i2c_, kDifToggleDisabled));
743 }
744 
745 TEST_F(ControlTest, LLPBKNullArgs) {
746  EXPECT_DIF_BADARG(
747  dif_i2c_line_loopback_set_enabled(nullptr, kDifToggleEnabled));
748 }
749 
750 TEST_F(ControlTest, AddrNack) {
751  EXPECT_MASK32(I2C_CTRL_REG_OFFSET,
752  {{I2C_CTRL_NACK_ADDR_AFTER_TIMEOUT_BIT, 0x1, 0x1}});
753  EXPECT_DIF_OK(dif_i2c_addr_nack_set_enabled(&i2c_, kDifToggleEnabled));
754 
755  EXPECT_MASK32(I2C_CTRL_REG_OFFSET,
756  {{I2C_CTRL_NACK_ADDR_AFTER_TIMEOUT_BIT, 0x1, 0x0}});
757  EXPECT_DIF_OK(dif_i2c_addr_nack_set_enabled(&i2c_, kDifToggleDisabled));
758 }
759 
760 TEST_F(ControlTest, AddrNackNullArgs) {
761  EXPECT_DIF_BADARG(dif_i2c_addr_nack_set_enabled(nullptr, kDifToggleEnabled));
762 }
763 
764 TEST_F(ControlTest, AckControl) {
765  EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ACK_CTRL_EN_BIT, 0x1, 0x1}});
766  EXPECT_DIF_OK(dif_i2c_ack_ctrl_set_enabled(&i2c_, kDifToggleEnabled));
767 
768  EXPECT_MASK32(I2C_CTRL_REG_OFFSET, {{I2C_CTRL_ACK_CTRL_EN_BIT, 0x1, 0x0}});
769  EXPECT_DIF_OK(dif_i2c_ack_ctrl_set_enabled(&i2c_, kDifToggleDisabled));
770 
771  uint16_t auto_ack_count = 0;
772  EXPECT_READ32(I2C_TARGET_ACK_CTRL_REG_OFFSET,
773  {
774  {I2C_TARGET_ACK_CTRL_NBYTES_OFFSET, 0xa5},
775  });
776  EXPECT_DIF_OK(dif_i2c_get_auto_ack_count(&i2c_, &auto_ack_count));
777  EXPECT_EQ(auto_ack_count, 0xa5);
778 
779  EXPECT_WRITE32(I2C_TARGET_ACK_CTRL_REG_OFFSET,
780  {
781  {I2C_TARGET_ACK_CTRL_NBYTES_OFFSET, 256},
782  });
783  EXPECT_DIF_OK(dif_i2c_set_auto_ack_count(&i2c_, 256));
784 
785  EXPECT_WRITE32(I2C_TARGET_ACK_CTRL_REG_OFFSET,
786  {
787  {I2C_TARGET_ACK_CTRL_NACK_BIT, 1},
788  });
789  EXPECT_DIF_OK(dif_i2c_nack_transaction(&i2c_));
790 
791  uint8_t pending_data;
792  EXPECT_READ32(I2C_ACQ_FIFO_NEXT_DATA_REG_OFFSET, 0x76);
793  EXPECT_DIF_OK(dif_i2c_get_pending_acq_byte(&i2c_, &pending_data));
794  EXPECT_EQ(pending_data, 0x76);
795 }
796 
797 TEST_F(ControlTest, AckControlNullArgs) {
798  EXPECT_DIF_BADARG(dif_i2c_ack_ctrl_set_enabled(nullptr, kDifToggleEnabled));
799 
800  uint16_t count_arg = 0;
801  EXPECT_DIF_BADARG(dif_i2c_get_auto_ack_count(nullptr, &count_arg));
802  EXPECT_DIF_BADARG(dif_i2c_get_auto_ack_count(&i2c_, nullptr));
803 
804  EXPECT_DIF_BADARG(dif_i2c_set_auto_ack_count(nullptr, /*count=*/0));
805  // Check BadArgument for count larger than CSR.
806  count_arg = I2C_TARGET_ACK_CTRL_NBYTES_MASK + 1;
807  EXPECT_DIF_BADARG(dif_i2c_set_auto_ack_count(&i2c_, count_arg));
808  EXPECT_DIF_BADARG(dif_i2c_nack_transaction(nullptr));
809 
810  uint8_t data_arg = 0;
811  EXPECT_DIF_BADARG(dif_i2c_get_pending_acq_byte(nullptr, &data_arg));
812  EXPECT_DIF_BADARG(dif_i2c_get_pending_acq_byte(&i2c_, nullptr));
813 }
814 
815 class OverrideTest : public I2cTest {};
816 
817 TEST_F(OverrideTest, Enable) {
818  EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {{I2C_OVRD_TXOVRDEN_BIT, 0x1, 0x1}});
819  EXPECT_DIF_OK(dif_i2c_override_set_enabled(&i2c_, kDifToggleEnabled));
820 
821  EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {{I2C_OVRD_TXOVRDEN_BIT, 0x1, 0x0}});
822  EXPECT_DIF_OK(dif_i2c_override_set_enabled(&i2c_, kDifToggleDisabled));
823 }
824 
825 TEST_F(OverrideTest, EnableNullArgs) {
826  EXPECT_DIF_BADARG(dif_i2c_override_set_enabled(nullptr, kDifToggleEnabled));
827 }
828 
829 TEST_F(OverrideTest, Drive) {
830  EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {
831  {I2C_OVRD_SCLVAL_BIT, 0x1, 0x0},
832  {I2C_OVRD_SDAVAL_BIT, 0x1, 0x0},
833  });
834  EXPECT_DIF_OK(dif_i2c_override_drive_pins(&i2c_, false, false));
835 
836  EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {
837  {I2C_OVRD_SCLVAL_BIT, 0x1, 0x0},
838  {I2C_OVRD_SDAVAL_BIT, 0x1, 0x1},
839  });
840  EXPECT_DIF_OK(dif_i2c_override_drive_pins(&i2c_, false, true));
841 
842  EXPECT_MASK32(I2C_OVRD_REG_OFFSET, {
843  {I2C_OVRD_SCLVAL_BIT, 0x1, 0x1},
844  {I2C_OVRD_SDAVAL_BIT, 0x1, 0x1},
845  });
846  EXPECT_DIF_OK(dif_i2c_override_drive_pins(&i2c_, true, true));
847 }
848 
849 TEST_F(OverrideTest, DriveNullArgs) {
850  EXPECT_DIF_BADARG(dif_i2c_override_drive_pins(nullptr, false, false));
851 }
852 
853 TEST_F(OverrideTest, Sample) {
854  uint16_t scl, sda;
855  EXPECT_READ32(I2C_VAL_REG_OFFSET, 0x10293847);
856  EXPECT_DIF_OK(dif_i2c_override_sample_pins(&i2c_, &scl, &sda));
857  EXPECT_EQ(scl, 0x3847);
858  EXPECT_EQ(sda, 0x1029);
859 
860  scl = 0, sda = 0;
861  EXPECT_READ32(I2C_VAL_REG_OFFSET, 0x10293847);
862  EXPECT_DIF_OK(dif_i2c_override_sample_pins(&i2c_, nullptr, &sda));
863  EXPECT_EQ(scl, 0x0);
864  EXPECT_EQ(sda, 0x1029);
865 
866  scl = 0, sda = 0;
867  EXPECT_READ32(I2C_VAL_REG_OFFSET, 0x10293847);
868  EXPECT_DIF_OK(dif_i2c_override_sample_pins(&i2c_, &scl, nullptr));
869  EXPECT_EQ(scl, 0x3847);
870  EXPECT_EQ(sda, 0x0);
871 }
872 
873 TEST_F(OverrideTest, SampleNullArgs) {
874  uint16_t scl, sda;
875  EXPECT_DIF_BADARG(dif_i2c_override_sample_pins(nullptr, &scl, &sda));
876 }
877 
878 class FifoTest : public I2cTest {};
879 
880 TEST_F(FifoTest, GetLevels) {
881  dif_i2c_level_t rx, fmt, tx, acq;
882  EXPECT_READ32(I2C_HOST_FIFO_STATUS_REG_OFFSET, 0x00290047);
883  EXPECT_READ32(I2C_TARGET_FIFO_STATUS_REG_OFFSET, 0x00100038);
884  EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, &fmt, &rx, &tx, &acq));
885  EXPECT_EQ(fmt, 0x47);
886  EXPECT_EQ(rx, 0x29);
887  EXPECT_EQ(tx, 0x38);
888  EXPECT_EQ(acq, 0x10);
889 
890  rx = 0, fmt = 0, tx = 0, acq = 0;
891  EXPECT_READ32(I2C_HOST_FIFO_STATUS_REG_OFFSET, 0x00290047);
892  EXPECT_READ32(I2C_TARGET_FIFO_STATUS_REG_OFFSET, 0x00100038);
893  EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, &fmt, &rx, nullptr, nullptr));
894  EXPECT_EQ(fmt, 0x47);
895  EXPECT_EQ(rx, 0x29);
896  EXPECT_EQ(tx, 0x0);
897  EXPECT_EQ(acq, 0x0);
898 
899  rx = 0, fmt = 0, tx = 0, acq = 0;
900  EXPECT_READ32(I2C_HOST_FIFO_STATUS_REG_OFFSET, 0x00290047);
901  EXPECT_READ32(I2C_TARGET_FIFO_STATUS_REG_OFFSET, 0x00100038);
902  EXPECT_DIF_OK(
903  dif_i2c_get_fifo_levels(&i2c_, &fmt, nullptr, nullptr, nullptr));
904  EXPECT_EQ(rx, 0x0);
905  EXPECT_EQ(fmt, 0x47);
906  EXPECT_EQ(tx, 0x0);
907  EXPECT_EQ(acq, 0x0);
908 
909  rx = 0, fmt = 0, tx = 0, acq = 0;
910  EXPECT_READ32(I2C_HOST_FIFO_STATUS_REG_OFFSET, 0x00290047);
911  EXPECT_READ32(I2C_TARGET_FIFO_STATUS_REG_OFFSET, 0x00100038);
912  EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, nullptr, &rx, nullptr, nullptr));
913  EXPECT_EQ(rx, 0x29);
914  EXPECT_EQ(fmt, 0x0);
915  EXPECT_EQ(tx, 0x0);
916  EXPECT_EQ(acq, 0x0);
917 
918  rx = 0, fmt = 0, tx = 0, acq = 0;
919  EXPECT_READ32(I2C_HOST_FIFO_STATUS_REG_OFFSET, 0x00290047);
920  EXPECT_READ32(I2C_TARGET_FIFO_STATUS_REG_OFFSET, 0x00100038);
921  EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, nullptr, nullptr, &tx, &acq));
922  EXPECT_EQ(fmt, 0x0);
923  EXPECT_EQ(rx, 0x0);
924  EXPECT_EQ(tx, 0x38);
925  EXPECT_EQ(acq, 0x10);
926 
927  rx = 0, fmt = 0, tx = 0, acq = 0;
928  EXPECT_READ32(I2C_HOST_FIFO_STATUS_REG_OFFSET, 0x00290047);
929  EXPECT_READ32(I2C_TARGET_FIFO_STATUS_REG_OFFSET, 0x00100038);
930  EXPECT_DIF_OK(dif_i2c_get_fifo_levels(&i2c_, nullptr, nullptr, &tx, nullptr));
931  EXPECT_EQ(rx, 0x0);
932  EXPECT_EQ(fmt, 0x0);
933  EXPECT_EQ(tx, 0x38);
934  EXPECT_EQ(acq, 0x0);
935 
936  rx = 0, fmt = 0, tx = 0, acq = 0;
937  EXPECT_READ32(I2C_HOST_FIFO_STATUS_REG_OFFSET, 0x00290047);
938  EXPECT_READ32(I2C_TARGET_FIFO_STATUS_REG_OFFSET, 0x00100038);
939  EXPECT_DIF_OK(
940  dif_i2c_get_fifo_levels(&i2c_, nullptr, nullptr, nullptr, &acq));
941  EXPECT_EQ(rx, 0x0);
942  EXPECT_EQ(fmt, 0x0);
943  EXPECT_EQ(tx, 0x0);
944  EXPECT_EQ(acq, 0x10);
945 }
946 
947 TEST_F(FifoTest, GetLevelsNullArgs) {
948  dif_i2c_level_t rx, fmt;
949  EXPECT_DIF_BADARG(
950  dif_i2c_get_fifo_levels(nullptr, &rx, &fmt, nullptr, nullptr));
951 }
952 
953 TEST_F(FifoTest, Read) {
954  uint8_t val;
955 
956  EXPECT_READ32(I2C_RDATA_REG_OFFSET, 0xab);
957  EXPECT_READ32(I2C_RDATA_REG_OFFSET, 0xcd);
958  EXPECT_READ32(I2C_RDATA_REG_OFFSET, 0xef);
959 
960  EXPECT_DIF_OK(dif_i2c_read_byte(&i2c_, &val));
961  EXPECT_EQ(val, 0xab);
962  EXPECT_DIF_OK(dif_i2c_read_byte(&i2c_, &val));
963  EXPECT_EQ(val, 0xcd);
964  EXPECT_DIF_OK(dif_i2c_read_byte(&i2c_, nullptr));
965  EXPECT_EQ(val, 0xcd);
966 }
967 
968 TEST_F(FifoTest, ReadNullArgs) {
969  uint8_t val;
970  EXPECT_DIF_BADARG(dif_i2c_read_byte(nullptr, &val));
971 }
972 
973 TEST_F(FifoTest, Acquire) {
974  uint8_t val;
975  dif_i2c_signal_t signal;
976 
977  EXPECT_READ32(I2C_ACQDATA_REG_OFFSET, 0x0ab);
978  EXPECT_READ32(I2C_ACQDATA_REG_OFFSET, 0x3cd);
979  EXPECT_READ32(I2C_ACQDATA_REG_OFFSET, 0x2ef);
980  EXPECT_READ32(I2C_ACQDATA_REG_OFFSET, 0x101);
981 
982  EXPECT_DIF_OK(dif_i2c_acquire_byte(&i2c_, &val, &signal));
983  EXPECT_EQ(val, 0xab);
984  EXPECT_EQ(signal, kDifI2cSignalNone);
985  EXPECT_DIF_OK(dif_i2c_acquire_byte(&i2c_, &val, &signal));
986  EXPECT_EQ(val, 0xcd);
987  EXPECT_EQ(signal, kDifI2cSignalRepeat);
988  EXPECT_DIF_OK(dif_i2c_acquire_byte(&i2c_, nullptr, &signal));
989  EXPECT_EQ(val, 0xcd);
990  EXPECT_EQ(signal, kDifI2cSignalStop);
991  EXPECT_DIF_OK(dif_i2c_acquire_byte(&i2c_, &val, nullptr));
992  EXPECT_EQ(val, 0x01);
993  EXPECT_EQ(signal, kDifI2cSignalStop);
994 }
995 
996 TEST_F(FifoTest, AcqNullArgs) {
997  uint8_t val;
998  dif_i2c_signal_t signal;
999 
1000  EXPECT_DIF_BADARG(dif_i2c_acquire_byte(nullptr, &val, &signal));
1001 }
1002 
1003 TEST_F(FifoTest, WriteRaw) {
1004  EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
1005  {I2C_FDATA_FBYTE_OFFSET, 0x44},
1006  {I2C_FDATA_START_BIT, 0x1},
1007  });
1008  EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x44,
1009  {
1010  .start = true,
1011  }));
1012 
1013  EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
1014  {I2C_FDATA_FBYTE_OFFSET, 0x55},
1015  });
1016  EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x55, {}));
1017 
1018  EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
1019  {I2C_FDATA_FBYTE_OFFSET, 0x66},
1020  {I2C_FDATA_STOP_BIT, 0x1},
1021  {I2C_FDATA_NAKOK_BIT, 0x1},
1022  });
1023  EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x66,
1024  {
1025  .stop = true,
1026  .suppress_nak_irq = true,
1027  }));
1028 
1029  EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
1030  {I2C_FDATA_FBYTE_OFFSET, 0x00},
1031  {I2C_FDATA_READB_BIT, 0x1},
1032  {I2C_FDATA_RCONT_BIT, 0x1},
1033  });
1034  EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x00,
1035  {
1036  .read = true,
1037  .read_cont = true,
1038  }));
1039 
1040  EXPECT_WRITE32(I2C_FDATA_REG_OFFSET, {
1041  {I2C_FDATA_FBYTE_OFFSET, 0x77},
1042  {I2C_FDATA_READB_BIT, 0x1},
1043  });
1044  EXPECT_DIF_OK(dif_i2c_write_byte_raw(&i2c_, 0x77,
1045  {
1046  .read = true,
1047  }));
1048 }
1049 
1050 TEST_F(FifoTest, WriteRawBadArgs) {
1051  EXPECT_DIF_BADARG(dif_i2c_write_byte_raw(nullptr, 0xff, {}));
1052  EXPECT_DIF_BADARG(dif_i2c_write_byte_raw(&i2c_, 0xff,
1053  {
1054  .start = true,
1055  .read = true,
1056  }));
1057  EXPECT_DIF_BADARG(dif_i2c_write_byte_raw(&i2c_, 0xff,
1058  {
1059  .read_cont = true,
1060  .suppress_nak_irq = true,
1061  }));
1062 }
1063 
1064 TEST_F(FifoTest, TransmitByte) {
1065  EXPECT_WRITE32(I2C_TXDATA_REG_OFFSET, 0x00000044);
1066  EXPECT_DIF_OK(dif_i2c_transmit_byte(&i2c_, 0x44));
1067 }
1068 
1069 TEST_F(FifoTest, TransmitBadArgs) {
1070  EXPECT_DIF_BADARG(dif_i2c_transmit_byte(nullptr, 0xff));
1071 }
1072 
1073 class StretchTest : public I2cTest {};
1074 
1075 TEST_F(StretchTest, ConfigTimeouts) {
1076  EXPECT_WRITE32(I2C_TIMEOUT_CTRL_REG_OFFSET,
1077  {{I2C_TIMEOUT_CTRL_EN_BIT, 1},
1078  {I2C_TIMEOUT_CTRL_MODE_BIT, 0},
1079  {I2C_TIMEOUT_CTRL_VAL_OFFSET, 0x01234567}});
1080  EXPECT_DIF_OK(dif_i2c_enable_clock_timeout(&i2c_, kDifI2cSclTimeoutStretch,
1081  0x01234567));
1082  EXPECT_WRITE32(I2C_TIMEOUT_CTRL_REG_OFFSET,
1083  {{I2C_TIMEOUT_CTRL_EN_BIT, 1},
1084  {I2C_TIMEOUT_CTRL_MODE_BIT, 1},
1085  {I2C_TIMEOUT_CTRL_VAL_OFFSET, 0x07654321}});
1086  EXPECT_DIF_OK(
1087  dif_i2c_enable_clock_timeout(&i2c_, kDifI2cSclTimeoutBus, 0x07654321));
1088  EXPECT_WRITE32(I2C_HOST_TIMEOUT_CTRL_REG_OFFSET, 0x81234567);
1089  EXPECT_DIF_OK(dif_i2c_set_host_timeout(&i2c_, 0x81234567));
1090 }
1091 
1092 TEST_F(StretchTest, ConfigTimeoutsBadArgs) {
1093  EXPECT_DIF_BADARG(dif_i2c_enable_clock_timeout(
1094  nullptr, kDifI2cSclTimeoutStretch, 0x01234567));
1095  EXPECT_DIF_BADARG(dif_i2c_set_host_timeout(nullptr, 0x81234567));
1096 }
1097 
1098 // Assemble 2 Ids to the byte to form the expections checked in the address test
1099 uint32_t assemble_address(dif_i2c_id_t *id0, dif_i2c_id_t *id1) {
1100  uint32_t config = 0x00000000;
1101  if (id0 == NULL) {
1102  config = bitfield_field32_write(config, I2C_TARGET_ID_ADDRESS0_FIELD, 0x7f);
1103  } else {
1104  config = bitfield_field32_write(config, I2C_TARGET_ID_ADDRESS0_FIELD,
1105  id0->address);
1106  config =
1107  bitfield_field32_write(config, I2C_TARGET_ID_MASK0_FIELD, id0->mask);
1108  }
1109 
1110  if (id1 == NULL) {
1111  config = bitfield_field32_write(config, I2C_TARGET_ID_ADDRESS1_FIELD, 0x7f);
1112  } else {
1113  config = bitfield_field32_write(config, I2C_TARGET_ID_ADDRESS1_FIELD,
1114  id1->address);
1115  config =
1116  bitfield_field32_write(config, I2C_TARGET_ID_MASK1_FIELD, id1->mask);
1117  }
1118  return config;
1119 }
1120 
1121 class AddressTest : public I2cTest {};
1122 TEST_F(AddressTest, SetDeviceAddress) {
1123  // dif_i2c_id_t id0 = NULL, id1 = NULL;
1124  EXPECT_WRITE32(I2C_TARGET_ID_REG_OFFSET, assemble_address(nullptr, nullptr));
1125  EXPECT_DIF_OK(dif_i2c_set_device_id(&i2c_, nullptr, nullptr));
1126 
1127  dif_i2c_id_t id0 = {.mask = 0x12, .address = 0x34};
1128  EXPECT_WRITE32(I2C_TARGET_ID_REG_OFFSET, assemble_address(&id0, nullptr));
1129  EXPECT_DIF_OK(dif_i2c_set_device_id(&i2c_, &id0, nullptr));
1130 
1131  dif_i2c_id_t id1 = {.mask = 0x56, .address = 0x78};
1132  EXPECT_WRITE32(I2C_TARGET_ID_REG_OFFSET, assemble_address(nullptr, &id1));
1133  EXPECT_DIF_OK(dif_i2c_set_device_id(&i2c_, nullptr, &id1));
1134 
1135  EXPECT_WRITE32(I2C_TARGET_ID_REG_OFFSET, assemble_address(&id0, &id1));
1136  EXPECT_DIF_OK(dif_i2c_set_device_id(&i2c_, &id0, &id1));
1137 }
1138 
1139 TEST_F(AddressTest, SetAddressBadArgs) {
1140  dif_i2c_id_t id0 = {}, id1 = {};
1141  EXPECT_DIF_BADARG(dif_i2c_set_device_id(nullptr, &id0, &id1));
1142 }
1143 
1144 } // namespace
1145 } // namespace dif_i2c_unittest
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