5 #ifndef OPENTITAN_SW_DEVICE_LIB_DIF_DIF_DMA_H_
6 #define OPENTITAN_SW_DEVICE_LIB_DIF_DIF_DMA_H_
24 typedef enum dif_dma_address_space_id {
26 kDifDmaOpentitanInternalBus = 0x07,
30 kDifDmaSoCControlRegisterBus = 0x0a,
33 kDifDmaSoCSystemBus = 0x09,
34 } dif_dma_address_space_id_t;
37 typedef enum dif_dma_transaction_width {
39 kDifDmaTransWidth1Byte = 0x00,
41 kDifDmaTransWidth2Bytes = 0x01,
43 kDifDmaTransWidth4Bytes = 0x02,
44 } dif_dma_transaction_width_t;
47 typedef enum dif_dma_transaction_opcode {
49 kDifDmaCopyOpcode = 0x00,
51 kDifDmaSha256Opcode = 0x01,
53 kDifDmaSha384Opcode = 0x02,
55 kDifDmaSha512Opcode = 0x03,
56 } dif_dma_transaction_opcode_t;
63 dif_dma_address_space_id_t asid;
77 dif_dma_transaction_width_t width;
99 bool memory_auto_increment;
104 bool fifo_auto_increment;
108 bool direction_from_mem_to_fifo;
149 dif_dma_transaction_opcode_t opcode);
217 typedef enum dif_dma_status_code {
219 kDifDmaStatusBusy = 0x01 << DMA_STATUS_BUSY_BIT,
221 kDifDmaStatusDone = 0x01 << DMA_STATUS_DONE_BIT,
223 kDifDmaStatusAborted = 0x01 << DMA_STATUS_ABORTED_BIT,
226 kDifDmaStatusError = 0x01 << DMA_STATUS_ERROR_BIT,
228 kDifDmaStatusSha2DigestValid = 0x01 << DMA_STATUS_SHA2_DIGEST_VALID_BIT,
229 } dif_dma_status_code_t;
274 dif_dma_status_code_t flag);
276 typedef enum dif_dma_error_code {
278 kDifDmaErrorNone = 0x00,
280 kDifDmaErrorSourceAddress = 0x01 << 0,
282 kDifDmaErrorDestinationAddress = 0x01 << 1,
284 kDifDmaErrorOpcode = 0x01 << 2,
286 kDifDmaErrorSize = 0x01 << 3,
288 kDifDmaErrorBus = 0x01 << 4,
290 kDifDmaErrorEnableMemoryConfig = 0x01 << 5,
292 kDifDmaErrorRangeValid = 0x01 << 6,
294 kDifDmaErrorInvalidAsid = 0x01 << 7,
295 } dif_dma_error_code_t;
306 dif_dma_error_code_t *error);
316 uint32_t *digest_len);
327 dif_dma_transaction_opcode_t opcode,
340 uint32_t enable_state);
352 uint32_t clear_state);
366 uint32_t clear_irq_bus);
373 kDifDmaIntrClearIdx0 = 0x0,
374 kDifDmaIntrClearIdx1 = 0x4,
375 kDifDmaIntrClearIdx2 = 0x8,
376 kDifDmaIntrClearIdx3 = 0xC,
377 kDifDmaIntrClearIdx4 = 0x10,
378 kDifDmaIntrClearIdx5 = 0x14,
379 kDifDmaIntrClearIdx6 = 0x18,
380 kDifDmaIntrClearIdx7 = 0x1C,
381 kDifDmaIntrClearIdx8 = 0x20,
382 kDifDmaIntrClearIdx9 = 0x24,
383 kDifDmaIntrClearIdx10 = 0x28,
396 uint32_t intr_src_addr);
409 uint32_t intr_src_value);
413 #endif // __cplusplus
415 #endif // OPENTITAN_SW_DEVICE_LIB_DIF_DIF_DMA_H_