Software APIs
dif_adc_ctrl_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_adc_ctrl_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "adc_ctrl_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_adc_ctrl_init(mmio_region_t base_addr,
18  dif_adc_ctrl_t *adc_ctrl) {
19  if (adc_ctrl == NULL) {
20  return kDifBadArg;
21  }
22 
23  adc_ctrl->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_adc_ctrl_alert_force(const dif_adc_ctrl_t *adc_ctrl,
29  dif_adc_ctrl_alert_t alert) {
30  if (adc_ctrl == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifAdcCtrlAlertFatalFault:
37  alert_idx = ADC_CTRL_ALERT_TEST_FATAL_FAULT_BIT;
38  break;
39  default:
40  return kDifBadArg;
41  }
42 
43  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
44  mmio_region_write32(adc_ctrl->base_addr,
45  (ptrdiff_t)ADC_CTRL_ALERT_TEST_REG_OFFSET,
46  alert_test_reg);
47 
48  return kDifOk;
49 }
50 
51 /**
52  * Get the corresponding interrupt register bit offset of the IRQ.
53  */
54 static bool adc_ctrl_get_irq_bit_index(dif_adc_ctrl_irq_t irq,
55  bitfield_bit32_index_t *index_out) {
56  switch (irq) {
57  case kDifAdcCtrlIrqMatchPending:
58  *index_out = ADC_CTRL_INTR_COMMON_MATCH_PENDING_BIT;
59  break;
60  default:
61  return false;
62  }
63 
64  return true;
65 }
66 
67 static dif_irq_type_t irq_types[] = {
68  kDifIrqTypeStatus,
69 };
70 
71 OT_WARN_UNUSED_RESULT
72 dif_result_t dif_adc_ctrl_irq_get_type(const dif_adc_ctrl_t *adc_ctrl,
73  dif_adc_ctrl_irq_t irq,
74  dif_irq_type_t *type) {
75  if (adc_ctrl == NULL || type == NULL ||
76  irq == kDifAdcCtrlIrqMatchPending + 1) {
77  return kDifBadArg;
78  }
79 
80  *type = irq_types[irq];
81 
82  return kDifOk;
83 }
84 
85 OT_WARN_UNUSED_RESULT
86 dif_result_t dif_adc_ctrl_irq_get_state(
87  const dif_adc_ctrl_t *adc_ctrl,
88  dif_adc_ctrl_irq_state_snapshot_t *snapshot) {
89  if (adc_ctrl == NULL || snapshot == NULL) {
90  return kDifBadArg;
91  }
92 
93  *snapshot = mmio_region_read32(adc_ctrl->base_addr,
94  (ptrdiff_t)ADC_CTRL_INTR_STATE_REG_OFFSET);
95 
96  return kDifOk;
97 }
98 
99 OT_WARN_UNUSED_RESULT
100 dif_result_t dif_adc_ctrl_irq_acknowledge_state(
101  const dif_adc_ctrl_t *adc_ctrl,
102  dif_adc_ctrl_irq_state_snapshot_t snapshot) {
103  if (adc_ctrl == NULL) {
104  return kDifBadArg;
105  }
106 
107  mmio_region_write32(adc_ctrl->base_addr,
108  (ptrdiff_t)ADC_CTRL_INTR_STATE_REG_OFFSET, snapshot);
109 
110  return kDifOk;
111 }
112 
113 OT_WARN_UNUSED_RESULT
114 dif_result_t dif_adc_ctrl_irq_is_pending(const dif_adc_ctrl_t *adc_ctrl,
115  dif_adc_ctrl_irq_t irq,
116  bool *is_pending) {
117  if (adc_ctrl == NULL || is_pending == NULL) {
118  return kDifBadArg;
119  }
120 
121  bitfield_bit32_index_t index;
122  if (!adc_ctrl_get_irq_bit_index(irq, &index)) {
123  return kDifBadArg;
124  }
125 
126  uint32_t intr_state_reg = mmio_region_read32(
127  adc_ctrl->base_addr, (ptrdiff_t)ADC_CTRL_INTR_STATE_REG_OFFSET);
128 
129  *is_pending = bitfield_bit32_read(intr_state_reg, index);
130 
131  return kDifOk;
132 }
133 
134 OT_WARN_UNUSED_RESULT
135 dif_result_t dif_adc_ctrl_irq_acknowledge_all(const dif_adc_ctrl_t *adc_ctrl) {
136  if (adc_ctrl == NULL) {
137  return kDifBadArg;
138  }
139 
140  // Writing to the register clears the corresponding bits (Write-one clear).
141  mmio_region_write32(adc_ctrl->base_addr,
142  (ptrdiff_t)ADC_CTRL_INTR_STATE_REG_OFFSET, UINT32_MAX);
143 
144  return kDifOk;
145 }
146 
147 OT_WARN_UNUSED_RESULT
148 dif_result_t dif_adc_ctrl_irq_acknowledge(const dif_adc_ctrl_t *adc_ctrl,
149  dif_adc_ctrl_irq_t irq) {
150  if (adc_ctrl == NULL) {
151  return kDifBadArg;
152  }
153 
154  bitfield_bit32_index_t index;
155  if (!adc_ctrl_get_irq_bit_index(irq, &index)) {
156  return kDifBadArg;
157  }
158 
159  // Writing to the register clears the corresponding bits (Write-one clear).
160  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
161  mmio_region_write32(adc_ctrl->base_addr,
162  (ptrdiff_t)ADC_CTRL_INTR_STATE_REG_OFFSET,
163  intr_state_reg);
164 
165  return kDifOk;
166 }
167 
168 OT_WARN_UNUSED_RESULT
169 dif_result_t dif_adc_ctrl_irq_force(const dif_adc_ctrl_t *adc_ctrl,
170  dif_adc_ctrl_irq_t irq, const bool val) {
171  if (adc_ctrl == NULL) {
172  return kDifBadArg;
173  }
174 
175  bitfield_bit32_index_t index;
176  if (!adc_ctrl_get_irq_bit_index(irq, &index)) {
177  return kDifBadArg;
178  }
179 
180  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
181  mmio_region_write32(adc_ctrl->base_addr,
182  (ptrdiff_t)ADC_CTRL_INTR_TEST_REG_OFFSET, intr_test_reg);
183 
184  return kDifOk;
185 }
186 
187 OT_WARN_UNUSED_RESULT
188 dif_result_t dif_adc_ctrl_irq_get_enabled(const dif_adc_ctrl_t *adc_ctrl,
189  dif_adc_ctrl_irq_t irq,
190  dif_toggle_t *state) {
191  if (adc_ctrl == NULL || state == NULL) {
192  return kDifBadArg;
193  }
194 
195  bitfield_bit32_index_t index;
196  if (!adc_ctrl_get_irq_bit_index(irq, &index)) {
197  return kDifBadArg;
198  }
199 
200  uint32_t intr_enable_reg = mmio_region_read32(
201  adc_ctrl->base_addr, (ptrdiff_t)ADC_CTRL_INTR_ENABLE_REG_OFFSET);
202 
203  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
204  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
205 
206  return kDifOk;
207 }
208 
209 OT_WARN_UNUSED_RESULT
210 dif_result_t dif_adc_ctrl_irq_set_enabled(const dif_adc_ctrl_t *adc_ctrl,
211  dif_adc_ctrl_irq_t irq,
212  dif_toggle_t state) {
213  if (adc_ctrl == NULL) {
214  return kDifBadArg;
215  }
216 
217  bitfield_bit32_index_t index;
218  if (!adc_ctrl_get_irq_bit_index(irq, &index)) {
219  return kDifBadArg;
220  }
221 
222  uint32_t intr_enable_reg = mmio_region_read32(
223  adc_ctrl->base_addr, (ptrdiff_t)ADC_CTRL_INTR_ENABLE_REG_OFFSET);
224 
225  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
226  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
227  mmio_region_write32(adc_ctrl->base_addr,
228  (ptrdiff_t)ADC_CTRL_INTR_ENABLE_REG_OFFSET,
229  intr_enable_reg);
230 
231  return kDifOk;
232 }
233 
234 OT_WARN_UNUSED_RESULT
235 dif_result_t dif_adc_ctrl_irq_disable_all(
236  const dif_adc_ctrl_t *adc_ctrl,
237  dif_adc_ctrl_irq_enable_snapshot_t *snapshot) {
238  if (adc_ctrl == NULL) {
239  return kDifBadArg;
240  }
241 
242  // Pass the current interrupt state to the caller, if requested.
243  if (snapshot != NULL) {
244  *snapshot = mmio_region_read32(adc_ctrl->base_addr,
245  (ptrdiff_t)ADC_CTRL_INTR_ENABLE_REG_OFFSET);
246  }
247 
248  // Disable all interrupts.
249  mmio_region_write32(adc_ctrl->base_addr,
250  (ptrdiff_t)ADC_CTRL_INTR_ENABLE_REG_OFFSET, 0u);
251 
252  return kDifOk;
253 }
254 
255 OT_WARN_UNUSED_RESULT
256 dif_result_t dif_adc_ctrl_irq_restore_all(
257  const dif_adc_ctrl_t *adc_ctrl,
258  const dif_adc_ctrl_irq_enable_snapshot_t *snapshot) {
259  if (adc_ctrl == NULL || snapshot == NULL) {
260  return kDifBadArg;
261  }
262 
263  mmio_region_write32(adc_ctrl->base_addr,
264  (ptrdiff_t)ADC_CTRL_INTR_ENABLE_REG_OFFSET, *snapshot);
265 
266  return kDifOk;
267 }
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