Software APIs
alert_test.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 // clang-format off
5 
6 //
7 // ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
8 // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
9 // util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson
10 // -o hw/top_earlgrey
11 #include "sw/device/lib/arch/boot_stage.h"
12 #include "sw/device/lib/base/mmio.h"
13 #include "sw/device/lib/dif/autogen/dif_adc_ctrl_autogen.h"
14 #include "sw/device/lib/dif/autogen/dif_aes_autogen.h"
15 #include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h"
16 #include "sw/device/lib/dif/autogen/dif_aon_timer_autogen.h"
17 #include "sw/device/lib/dif/autogen/dif_clkmgr_autogen.h"
18 #include "sw/device/lib/dif/autogen/dif_csrng_autogen.h"
19 #include "sw/device/lib/dif/autogen/dif_edn_autogen.h"
20 #include "sw/device/lib/dif/autogen/dif_entropy_src_autogen.h"
21 #include "sw/device/lib/dif/autogen/dif_flash_ctrl_autogen.h"
22 #include "sw/device/lib/dif/autogen/dif_gpio_autogen.h"
23 #include "sw/device/lib/dif/autogen/dif_hmac_autogen.h"
24 #include "sw/device/lib/dif/autogen/dif_i2c_autogen.h"
25 #include "sw/device/lib/dif/autogen/dif_keymgr_autogen.h"
26 #include "sw/device/lib/dif/autogen/dif_kmac_autogen.h"
27 #include "sw/device/lib/dif/autogen/dif_lc_ctrl_autogen.h"
28 #include "sw/device/lib/dif/autogen/dif_otbn_autogen.h"
29 #include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h"
30 #include "sw/device/lib/dif/autogen/dif_pattgen_autogen.h"
31 #include "sw/device/lib/dif/autogen/dif_pinmux_autogen.h"
32 #include "sw/device/lib/dif/autogen/dif_pwm_autogen.h"
33 #include "sw/device/lib/dif/autogen/dif_pwrmgr_autogen.h"
34 #include "sw/device/lib/dif/autogen/dif_rom_ctrl_autogen.h"
35 #include "sw/device/lib/dif/autogen/dif_rstmgr_autogen.h"
36 #include "sw/device/lib/dif/autogen/dif_rv_core_ibex_autogen.h"
37 #include "sw/device/lib/dif/autogen/dif_rv_plic_autogen.h"
38 #include "sw/device/lib/dif/autogen/dif_rv_timer_autogen.h"
39 #include "sw/device/lib/dif/autogen/dif_sensor_ctrl_autogen.h"
40 #include "sw/device/lib/dif/autogen/dif_spi_device_autogen.h"
41 #include "sw/device/lib/dif/autogen/dif_spi_host_autogen.h"
42 #include "sw/device/lib/dif/autogen/dif_sram_ctrl_autogen.h"
43 #include "sw/device/lib/dif/autogen/dif_sysrst_ctrl_autogen.h"
44 #include "sw/device/lib/dif/autogen/dif_uart_autogen.h"
45 #include "sw/device/lib/dif/autogen/dif_usbdev_autogen.h"
46 #include "sw/device/lib/testing/alert_handler_testutils.h"
47 #include "sw/device/lib/testing/test_framework/FreeRTOSConfig.h"
48 #include "sw/device/lib/testing/test_framework/check.h"
49 #include "sw/device/lib/testing/test_framework/ottf_test_config.h"
50 
51 #include "alert_handler_regs.h" // Generated.
52 #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
53 
54 OTTF_DEFINE_TEST_CONFIG();
55 
56 static dif_alert_handler_t alert_handler;
57 static dif_adc_ctrl_t adc_ctrl_aon;
58 static dif_aes_t aes;
59 static dif_aon_timer_t aon_timer_aon;
60 static dif_clkmgr_t clkmgr_aon;
61 static dif_csrng_t csrng;
62 static dif_edn_t edn0;
63 static dif_edn_t edn1;
64 static dif_entropy_src_t entropy_src;
65 static dif_flash_ctrl_t flash_ctrl;
66 static dif_gpio_t gpio;
67 static dif_hmac_t hmac;
68 static dif_i2c_t i2c0;
69 static dif_i2c_t i2c1;
70 static dif_i2c_t i2c2;
71 static dif_keymgr_t keymgr;
72 static dif_kmac_t kmac;
73 static dif_lc_ctrl_t lc_ctrl;
74 static dif_otbn_t otbn;
75 static dif_otp_ctrl_t otp_ctrl;
76 static dif_pattgen_t pattgen;
77 static dif_pinmux_t pinmux_aon;
78 static dif_pwm_t pwm_aon;
79 static dif_pwrmgr_t pwrmgr_aon;
80 static dif_rom_ctrl_t rom_ctrl;
81 static dif_rstmgr_t rstmgr_aon;
82 static dif_rv_core_ibex_t rv_core_ibex;
83 static dif_rv_plic_t rv_plic;
84 static dif_rv_timer_t rv_timer;
85 static dif_sensor_ctrl_t sensor_ctrl_aon;
86 static dif_spi_device_t spi_device;
87 static dif_spi_host_t spi_host0;
88 static dif_spi_host_t spi_host1;
89 static dif_sram_ctrl_t sram_ctrl_main;
90 static dif_sram_ctrl_t sram_ctrl_ret_aon;
91 static dif_sysrst_ctrl_t sysrst_ctrl_aon;
92 static dif_uart_t uart0;
93 static dif_uart_t uart1;
94 static dif_uart_t uart2;
95 static dif_uart_t uart3;
96 static dif_usbdev_t usbdev;
97 
98 /**
99  * Initialize the peripherals used in this test.
100  */
101 static void init_peripherals(void) {
102  mmio_region_t base_addr;
103  base_addr = mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR);
104  CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler));
105 
106  base_addr = mmio_region_from_addr(TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR);
107  CHECK_DIF_OK(dif_adc_ctrl_init(base_addr, &adc_ctrl_aon));
108 
109  base_addr = mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR);
110  CHECK_DIF_OK(dif_aes_init(base_addr, &aes));
111 
112  base_addr = mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR);
113  CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon));
114 
115  base_addr = mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR);
116  CHECK_DIF_OK(dif_clkmgr_init(base_addr, &clkmgr_aon));
117 
118  base_addr = mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR);
119  CHECK_DIF_OK(dif_csrng_init(base_addr, &csrng));
120 
121  base_addr = mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR);
122  CHECK_DIF_OK(dif_edn_init(base_addr, &edn0));
123 
124  base_addr = mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR);
125  CHECK_DIF_OK(dif_edn_init(base_addr, &edn1));
126 
127  base_addr = mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR);
128  CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src));
129 
130  base_addr = mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR);
131  CHECK_DIF_OK(dif_flash_ctrl_init(base_addr, &flash_ctrl));
132 
133  base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR);
134  CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio));
135 
136  base_addr = mmio_region_from_addr(TOP_EARLGREY_HMAC_BASE_ADDR);
137  CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac));
138 
139  base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C0_BASE_ADDR);
140  CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0));
141 
142  base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C1_BASE_ADDR);
143  CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c1));
144 
145  base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C2_BASE_ADDR);
146  CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c2));
147 
148  base_addr = mmio_region_from_addr(TOP_EARLGREY_KEYMGR_BASE_ADDR);
149  CHECK_DIF_OK(dif_keymgr_init(base_addr, &keymgr));
150 
151  base_addr = mmio_region_from_addr(TOP_EARLGREY_KMAC_BASE_ADDR);
152  CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac));
153 
154  base_addr = mmio_region_from_addr(TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR);
155  CHECK_DIF_OK(dif_lc_ctrl_init(base_addr, &lc_ctrl));
156 
157  base_addr = mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR);
158  CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn));
159 
160  base_addr = mmio_region_from_addr(TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR);
161  CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl));
162 
163  base_addr = mmio_region_from_addr(TOP_EARLGREY_PATTGEN_BASE_ADDR);
164  CHECK_DIF_OK(dif_pattgen_init(base_addr, &pattgen));
165 
166  base_addr = mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR);
167  CHECK_DIF_OK(dif_pinmux_init(base_addr, &pinmux_aon));
168 
169  base_addr = mmio_region_from_addr(TOP_EARLGREY_PWM_AON_BASE_ADDR);
170  CHECK_DIF_OK(dif_pwm_init(base_addr, &pwm_aon));
171 
172  base_addr = mmio_region_from_addr(TOP_EARLGREY_PWRMGR_AON_BASE_ADDR);
173  CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr_aon));
174 
175  base_addr = mmio_region_from_addr(TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR);
176  CHECK_DIF_OK(dif_rom_ctrl_init(base_addr, &rom_ctrl));
177 
178  base_addr = mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR);
179  CHECK_DIF_OK(dif_rstmgr_init(base_addr, &rstmgr_aon));
180 
181  base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR);
182  CHECK_DIF_OK(dif_rv_core_ibex_init(base_addr, &rv_core_ibex));
183 
184  base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR);
185  CHECK_DIF_OK(dif_rv_plic_init(base_addr, &rv_plic));
186 
187  base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR);
188  CHECK_DIF_OK(dif_rv_timer_init(base_addr, &rv_timer));
189 
190  base_addr = mmio_region_from_addr(TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR);
191  CHECK_DIF_OK(dif_sensor_ctrl_init(base_addr, &sensor_ctrl_aon));
192 
193  base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_DEVICE_BASE_ADDR);
194  CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device));
195 
196  base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST0_BASE_ADDR);
197  CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0));
198 
199  base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST1_BASE_ADDR);
200  CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host1));
201 
202  base_addr = mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR);
203  CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_main));
204 
205  base_addr = mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR);
206  CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_ret_aon));
207 
208  base_addr = mmio_region_from_addr(TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR);
209  CHECK_DIF_OK(dif_sysrst_ctrl_init(base_addr, &sysrst_ctrl_aon));
210 
211  base_addr = mmio_region_from_addr(TOP_EARLGREY_UART0_BASE_ADDR);
212  CHECK_DIF_OK(dif_uart_init(base_addr, &uart0));
213 
214  base_addr = mmio_region_from_addr(TOP_EARLGREY_UART1_BASE_ADDR);
215  CHECK_DIF_OK(dif_uart_init(base_addr, &uart1));
216 
217  base_addr = mmio_region_from_addr(TOP_EARLGREY_UART2_BASE_ADDR);
218  CHECK_DIF_OK(dif_uart_init(base_addr, &uart2));
219 
220  base_addr = mmio_region_from_addr(TOP_EARLGREY_UART3_BASE_ADDR);
221  CHECK_DIF_OK(dif_uart_init(base_addr, &uart3));
222 
223  base_addr = mmio_region_from_addr(TOP_EARLGREY_USBDEV_BASE_ADDR);
224  CHECK_DIF_OK(dif_usbdev_init(base_addr, &usbdev));
225 
226 }
227 
228 /**
229  * Configure the alert handler to escalate on alerts upto phase 1 (i.e. wipe
230  * secret) but not trigger reset. Then CPU can check if alert_handler triggers the correct
231  * alert_cause register.
232  */
233 static void alert_handler_config(void) {
234  dif_alert_handler_alert_t alerts[ALERT_HANDLER_PARAM_N_ALERTS];
235  dif_alert_handler_class_t alert_classes[ALERT_HANDLER_PARAM_N_ALERTS];
236 
237  // Enable all incoming alerts and configure them to classa.
238  // This alert should never fire because we do not expect any incoming alerts.
239  for (dif_alert_handler_alert_t i = 0; i < ALERT_HANDLER_PARAM_N_ALERTS; ++i) {
240  alerts[i] = i;
241  alert_classes[i] = kDifAlertHandlerClassA;
242  }
243 
244  dif_alert_handler_escalation_phase_t esc_phases[] = {
245  {.phase = kDifAlertHandlerClassStatePhase0,
246  .signal = 0,
247  .duration_cycles = 2000}};
248 
249  dif_alert_handler_class_config_t class_config = {
250  .auto_lock_accumulation_counter = kDifToggleDisabled,
251  .accumulator_threshold = 0,
252  .irq_deadline_cycles = 10000,
253  .escalation_phases = esc_phases,
254  .escalation_phases_len = ARRAYSIZE(esc_phases),
255  .crashdump_escalation_phase = kDifAlertHandlerClassStatePhase1,
256  };
257 
258  dif_alert_handler_class_config_t class_configs[] = {class_config,
259  class_config};
260 
261  dif_alert_handler_class_t classes[] = {kDifAlertHandlerClassA,
262  kDifAlertHandlerClassB};
263  dif_alert_handler_config_t config = {
264  .alerts = alerts,
265  .alert_classes = alert_classes,
266  .alerts_len = ARRAYSIZE(alerts),
267  .classes = classes,
268  .class_configs = class_configs,
269  .classes_len = ARRAYSIZE(class_configs),
270  .ping_timeout = 1000,
271  };
272 
273  CHECK_STATUS_OK(alert_handler_testutils_configure_all(&alert_handler, config,
274  kDifToggleEnabled));
275 }
276 
277 // Trigger alert for each module by writing one to `alert_test` register.
278 // Then check alert_handler's alert_cause register to make sure the correct alert reaches
279 // alert_handler.
280 static void trigger_alert_test(void) {
281  bool is_cause;
282  dif_alert_handler_alert_t exp_alert;
283 
284  // Write adc_ctrl's alert_test reg and check alert_cause.
285  for (dif_adc_ctrl_alert_t i = 0; i < 1; ++i) {
286  CHECK_DIF_OK(dif_adc_ctrl_alert_force(&adc_ctrl_aon, kDifAdcCtrlAlertFatalFault + i));
287 
288  // Verify that alert handler received it.
289  exp_alert = kTopEarlgreyAlertIdAdcCtrlAonFatalFault + i;
290  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
291  &alert_handler, exp_alert, &is_cause));
292  CHECK(is_cause, "Expect alert %d!", exp_alert);
293 
294  // Clear alert cause register
295  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
296  &alert_handler, exp_alert));
297  }
298 
299  // Write aes's alert_test reg and check alert_cause.
300  for (dif_aes_alert_t i = 0; i < 2; ++i) {
301  CHECK_DIF_OK(dif_aes_alert_force(&aes, kDifAesAlertRecovCtrlUpdateErr + i));
302 
303  // Verify that alert handler received it.
304  exp_alert = kTopEarlgreyAlertIdAesRecovCtrlUpdateErr + i;
305  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
306  &alert_handler, exp_alert, &is_cause));
307  CHECK(is_cause, "Expect alert %d!", exp_alert);
308 
309  // Clear alert cause register
310  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
311  &alert_handler, exp_alert));
312  }
313 
314  // Write aon_timer's alert_test reg and check alert_cause.
315  for (dif_aon_timer_alert_t i = 0; i < 1; ++i) {
316  CHECK_DIF_OK(dif_aon_timer_alert_force(&aon_timer_aon, kDifAonTimerAlertFatalFault + i));
317 
318  // Verify that alert handler received it.
319  exp_alert = kTopEarlgreyAlertIdAonTimerAonFatalFault + i;
320  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
321  &alert_handler, exp_alert, &is_cause));
322  CHECK(is_cause, "Expect alert %d!", exp_alert);
323 
324  // Clear alert cause register
325  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
326  &alert_handler, exp_alert));
327  }
328 
329  // Write clkmgr's alert_test reg and check alert_cause.
330  for (dif_clkmgr_alert_t i = 0; i < 2; ++i) {
331  CHECK_DIF_OK(dif_clkmgr_alert_force(&clkmgr_aon, kDifClkmgrAlertRecovFault + i));
332 
333  // Verify that alert handler received it.
334  exp_alert = kTopEarlgreyAlertIdClkmgrAonRecovFault + i;
335  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
336  &alert_handler, exp_alert, &is_cause));
337  CHECK(is_cause, "Expect alert %d!", exp_alert);
338 
339  // Clear alert cause register
340  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
341  &alert_handler, exp_alert));
342  }
343 
344  // Write csrng's alert_test reg and check alert_cause.
345  for (dif_csrng_alert_t i = 0; i < 2; ++i) {
346  CHECK_DIF_OK(dif_csrng_alert_force(&csrng, kDifCsrngAlertRecovAlert + i));
347 
348  // Verify that alert handler received it.
349  exp_alert = kTopEarlgreyAlertIdCsrngRecovAlert + i;
350  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
351  &alert_handler, exp_alert, &is_cause));
352  CHECK(is_cause, "Expect alert %d!", exp_alert);
353 
354  // Clear alert cause register
355  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
356  &alert_handler, exp_alert));
357  }
358 
359  // Write edn's alert_test reg and check alert_cause.
360  for (dif_edn_alert_t i = 0; i < 2; ++i) {
361  CHECK_DIF_OK(dif_edn_alert_force(&edn0, kDifEdnAlertRecovAlert + i));
362 
363  // Verify that alert handler received it.
364  exp_alert = kTopEarlgreyAlertIdEdn0RecovAlert + i;
365  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
366  &alert_handler, exp_alert, &is_cause));
367  CHECK(is_cause, "Expect alert %d!", exp_alert);
368 
369  // Clear alert cause register
370  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
371  &alert_handler, exp_alert));
372  }
373 
374  // Write edn's alert_test reg and check alert_cause.
375  for (dif_edn_alert_t i = 0; i < 2; ++i) {
376  CHECK_DIF_OK(dif_edn_alert_force(&edn1, kDifEdnAlertRecovAlert + i));
377 
378  // Verify that alert handler received it.
379  exp_alert = kTopEarlgreyAlertIdEdn1RecovAlert + i;
380  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
381  &alert_handler, exp_alert, &is_cause));
382  CHECK(is_cause, "Expect alert %d!", exp_alert);
383 
384  // Clear alert cause register
385  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
386  &alert_handler, exp_alert));
387  }
388 
389  // Write entropy_src's alert_test reg and check alert_cause.
390  for (dif_entropy_src_alert_t i = 0; i < 2; ++i) {
391  CHECK_DIF_OK(dif_entropy_src_alert_force(&entropy_src, kDifEntropySrcAlertRecovAlert + i));
392 
393  // Verify that alert handler received it.
394  exp_alert = kTopEarlgreyAlertIdEntropySrcRecovAlert + i;
395  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
396  &alert_handler, exp_alert, &is_cause));
397  CHECK(is_cause, "Expect alert %d!", exp_alert);
398 
399  // Clear alert cause register
400  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
401  &alert_handler, exp_alert));
402  }
403 
404  // Write flash_ctrl's alert_test reg and check alert_cause.
405  for (dif_flash_ctrl_alert_t i = 0; i < 5; ++i) {
406  CHECK_DIF_OK(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertRecovErr + i));
407 
408  // Verify that alert handler received it.
409  exp_alert = kTopEarlgreyAlertIdFlashCtrlRecovErr + i;
410  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
411  &alert_handler, exp_alert, &is_cause));
412  CHECK(is_cause, "Expect alert %d!", exp_alert);
413 
414  // Clear alert cause register
415  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
416  &alert_handler, exp_alert));
417  }
418 
419  // Write gpio's alert_test reg and check alert_cause.
420  for (dif_gpio_alert_t i = 0; i < 1; ++i) {
421  CHECK_DIF_OK(dif_gpio_alert_force(&gpio, kDifGpioAlertFatalFault + i));
422 
423  // Verify that alert handler received it.
424  exp_alert = kTopEarlgreyAlertIdGpioFatalFault + i;
425  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
426  &alert_handler, exp_alert, &is_cause));
427  CHECK(is_cause, "Expect alert %d!", exp_alert);
428 
429  // Clear alert cause register
430  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
431  &alert_handler, exp_alert));
432  }
433 
434  // Write hmac's alert_test reg and check alert_cause.
435  for (dif_hmac_alert_t i = 0; i < 1; ++i) {
436  CHECK_DIF_OK(dif_hmac_alert_force(&hmac, kDifHmacAlertFatalFault + i));
437 
438  // Verify that alert handler received it.
439  exp_alert = kTopEarlgreyAlertIdHmacFatalFault + i;
440  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
441  &alert_handler, exp_alert, &is_cause));
442  CHECK(is_cause, "Expect alert %d!", exp_alert);
443 
444  // Clear alert cause register
445  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
446  &alert_handler, exp_alert));
447  }
448 
449  // Write i2c's alert_test reg and check alert_cause.
450  for (dif_i2c_alert_t i = 0; i < 1; ++i) {
451  CHECK_DIF_OK(dif_i2c_alert_force(&i2c0, kDifI2cAlertFatalFault + i));
452 
453  // Verify that alert handler received it.
454  exp_alert = kTopEarlgreyAlertIdI2c0FatalFault + i;
455  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
456  &alert_handler, exp_alert, &is_cause));
457  CHECK(is_cause, "Expect alert %d!", exp_alert);
458 
459  // Clear alert cause register
460  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
461  &alert_handler, exp_alert));
462  }
463 
464  // Write i2c's alert_test reg and check alert_cause.
465  for (dif_i2c_alert_t i = 0; i < 1; ++i) {
466  CHECK_DIF_OK(dif_i2c_alert_force(&i2c1, kDifI2cAlertFatalFault + i));
467 
468  // Verify that alert handler received it.
469  exp_alert = kTopEarlgreyAlertIdI2c1FatalFault + i;
470  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
471  &alert_handler, exp_alert, &is_cause));
472  CHECK(is_cause, "Expect alert %d!", exp_alert);
473 
474  // Clear alert cause register
475  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
476  &alert_handler, exp_alert));
477  }
478 
479  // Write i2c's alert_test reg and check alert_cause.
480  for (dif_i2c_alert_t i = 0; i < 1; ++i) {
481  CHECK_DIF_OK(dif_i2c_alert_force(&i2c2, kDifI2cAlertFatalFault + i));
482 
483  // Verify that alert handler received it.
484  exp_alert = kTopEarlgreyAlertIdI2c2FatalFault + i;
485  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
486  &alert_handler, exp_alert, &is_cause));
487  CHECK(is_cause, "Expect alert %d!", exp_alert);
488 
489  // Clear alert cause register
490  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
491  &alert_handler, exp_alert));
492  }
493 
494  // Write keymgr's alert_test reg and check alert_cause.
495  for (dif_keymgr_alert_t i = 0; i < 2; ++i) {
496  CHECK_DIF_OK(dif_keymgr_alert_force(&keymgr, kDifKeymgrAlertRecovOperationErr + i));
497 
498  // Verify that alert handler received it.
499  exp_alert = kTopEarlgreyAlertIdKeymgrRecovOperationErr + i;
500  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
501  &alert_handler, exp_alert, &is_cause));
502  CHECK(is_cause, "Expect alert %d!", exp_alert);
503 
504  // Clear alert cause register
505  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
506  &alert_handler, exp_alert));
507  }
508 
509  // Write kmac's alert_test reg and check alert_cause.
510  for (dif_kmac_alert_t i = 0; i < 2; ++i) {
511  CHECK_DIF_OK(dif_kmac_alert_force(&kmac, kDifKmacAlertRecovOperationErr + i));
512 
513  // Verify that alert handler received it.
514  exp_alert = kTopEarlgreyAlertIdKmacRecovOperationErr + i;
515  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
516  &alert_handler, exp_alert, &is_cause));
517  CHECK(is_cause, "Expect alert %d!", exp_alert);
518 
519  // Clear alert cause register
520  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
521  &alert_handler, exp_alert));
522  }
523 
524  // Write lc_ctrl's alert_test reg and check alert_cause.
525  for (dif_lc_ctrl_alert_t i = 0; i < 3; ++i) {
526  CHECK_DIF_OK(dif_lc_ctrl_alert_force(&lc_ctrl, kDifLcCtrlAlertFatalProgError + i));
527 
528  // Verify that alert handler received it.
529  exp_alert = kTopEarlgreyAlertIdLcCtrlFatalProgError + i;
530  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
531  &alert_handler, exp_alert, &is_cause));
532  CHECK(is_cause, "Expect alert %d!", exp_alert);
533 
534  // Clear alert cause register
535  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
536  &alert_handler, exp_alert));
537  }
538 
539  // Write otbn's alert_test reg and check alert_cause.
540  for (dif_otbn_alert_t i = 0; i < 2; ++i) {
541  CHECK_DIF_OK(dif_otbn_alert_force(&otbn, kDifOtbnAlertFatal + i));
542 
543  // Verify that alert handler received it.
544  exp_alert = kTopEarlgreyAlertIdOtbnFatal + i;
545  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
546  &alert_handler, exp_alert, &is_cause));
547  CHECK(is_cause, "Expect alert %d!", exp_alert);
548 
549  // Clear alert cause register
550  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
551  &alert_handler, exp_alert));
552  }
553 
554  // TODO(lowrisc/opentitan#20348): Enable otp_ctrl when this is fixed.
555  if (kBootStage != kBootStageOwner) {
556  // Write otp_ctrl's alert_test reg and check alert_cause.
557  for (dif_otp_ctrl_alert_t i = 0; i < 5; ++i) {
558  CHECK_DIF_OK(dif_otp_ctrl_alert_force(&otp_ctrl, kDifOtpCtrlAlertFatalMacroError + i));
559 
560  // Verify that alert handler received it.
561  exp_alert = kTopEarlgreyAlertIdOtpCtrlFatalMacroError + i;
562  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
563  &alert_handler, exp_alert, &is_cause));
564  CHECK(is_cause, "Expect alert %d!", exp_alert);
565 
566  // Clear alert cause register
567  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
568  &alert_handler, exp_alert));
569  }
570  }
571 
572  // Write pattgen's alert_test reg and check alert_cause.
573  for (dif_pattgen_alert_t i = 0; i < 1; ++i) {
574  CHECK_DIF_OK(dif_pattgen_alert_force(&pattgen, kDifPattgenAlertFatalFault + i));
575 
576  // Verify that alert handler received it.
577  exp_alert = kTopEarlgreyAlertIdPattgenFatalFault + i;
578  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
579  &alert_handler, exp_alert, &is_cause));
580  CHECK(is_cause, "Expect alert %d!", exp_alert);
581 
582  // Clear alert cause register
583  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
584  &alert_handler, exp_alert));
585  }
586 
587  // Write pinmux's alert_test reg and check alert_cause.
588  for (dif_pinmux_alert_t i = 0; i < 1; ++i) {
589  CHECK_DIF_OK(dif_pinmux_alert_force(&pinmux_aon, kDifPinmuxAlertFatalFault + i));
590 
591  // Verify that alert handler received it.
592  exp_alert = kTopEarlgreyAlertIdPinmuxAonFatalFault + i;
593  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
594  &alert_handler, exp_alert, &is_cause));
595  CHECK(is_cause, "Expect alert %d!", exp_alert);
596 
597  // Clear alert cause register
598  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
599  &alert_handler, exp_alert));
600  }
601 
602  // Write pwm's alert_test reg and check alert_cause.
603  for (dif_pwm_alert_t i = 0; i < 1; ++i) {
604  CHECK_DIF_OK(dif_pwm_alert_force(&pwm_aon, kDifPwmAlertFatalFault + i));
605 
606  // Verify that alert handler received it.
607  exp_alert = kTopEarlgreyAlertIdPwmAonFatalFault + i;
608  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
609  &alert_handler, exp_alert, &is_cause));
610  CHECK(is_cause, "Expect alert %d!", exp_alert);
611 
612  // Clear alert cause register
613  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
614  &alert_handler, exp_alert));
615  }
616 
617  // Write pwrmgr's alert_test reg and check alert_cause.
618  for (dif_pwrmgr_alert_t i = 0; i < 1; ++i) {
619  CHECK_DIF_OK(dif_pwrmgr_alert_force(&pwrmgr_aon, kDifPwrmgrAlertFatalFault + i));
620 
621  // Verify that alert handler received it.
622  exp_alert = kTopEarlgreyAlertIdPwrmgrAonFatalFault + i;
623  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
624  &alert_handler, exp_alert, &is_cause));
625  CHECK(is_cause, "Expect alert %d!", exp_alert);
626 
627  // Clear alert cause register
628  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
629  &alert_handler, exp_alert));
630  }
631 
632  // Write rom_ctrl's alert_test reg and check alert_cause.
633  for (dif_rom_ctrl_alert_t i = 0; i < 1; ++i) {
634  CHECK_DIF_OK(dif_rom_ctrl_alert_force(&rom_ctrl, kDifRomCtrlAlertFatal + i));
635 
636  // Verify that alert handler received it.
637  exp_alert = kTopEarlgreyAlertIdRomCtrlFatal + i;
638  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
639  &alert_handler, exp_alert, &is_cause));
640  CHECK(is_cause, "Expect alert %d!", exp_alert);
641 
642  // Clear alert cause register
643  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
644  &alert_handler, exp_alert));
645  }
646 
647  // Write rstmgr's alert_test reg and check alert_cause.
648  for (dif_rstmgr_alert_t i = 0; i < 2; ++i) {
649  CHECK_DIF_OK(dif_rstmgr_alert_force(&rstmgr_aon, kDifRstmgrAlertFatalFault + i));
650 
651  // Verify that alert handler received it.
652  exp_alert = kTopEarlgreyAlertIdRstmgrAonFatalFault + i;
653  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
654  &alert_handler, exp_alert, &is_cause));
655  CHECK(is_cause, "Expect alert %d!", exp_alert);
656 
657  // Clear alert cause register
658  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
659  &alert_handler, exp_alert));
660  }
661 
662  // Write rv_core_ibex's alert_test reg and check alert_cause.
663  for (dif_rv_core_ibex_alert_t i = 0; i < 4; ++i) {
664  CHECK_DIF_OK(dif_rv_core_ibex_alert_force(&rv_core_ibex, kDifRvCoreIbexAlertFatalSwErr + i));
665 
666  // Verify that alert handler received it.
667  exp_alert = kTopEarlgreyAlertIdRvCoreIbexFatalSwErr + i;
668  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
669  &alert_handler, exp_alert, &is_cause));
670  CHECK(is_cause, "Expect alert %d!", exp_alert);
671 
672  // Clear alert cause register
673  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
674  &alert_handler, exp_alert));
675  }
676 
677  // Write rv_plic's alert_test reg and check alert_cause.
678  for (dif_rv_plic_alert_t i = 0; i < 1; ++i) {
679  CHECK_DIF_OK(dif_rv_plic_alert_force(&rv_plic, kDifRvPlicAlertFatalFault + i));
680 
681  // Verify that alert handler received it.
682  exp_alert = kTopEarlgreyAlertIdRvPlicFatalFault + i;
683  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
684  &alert_handler, exp_alert, &is_cause));
685  CHECK(is_cause, "Expect alert %d!", exp_alert);
686 
687  // Clear alert cause register
688  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
689  &alert_handler, exp_alert));
690  }
691 
692  // Write rv_timer's alert_test reg and check alert_cause.
693  for (dif_rv_timer_alert_t i = 0; i < 1; ++i) {
694  CHECK_DIF_OK(dif_rv_timer_alert_force(&rv_timer, kDifRvTimerAlertFatalFault + i));
695 
696  // Verify that alert handler received it.
697  exp_alert = kTopEarlgreyAlertIdRvTimerFatalFault + i;
698  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
699  &alert_handler, exp_alert, &is_cause));
700  CHECK(is_cause, "Expect alert %d!", exp_alert);
701 
702  // Clear alert cause register
703  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
704  &alert_handler, exp_alert));
705  }
706 
707  // Write sensor_ctrl's alert_test reg and check alert_cause.
708  for (dif_sensor_ctrl_alert_t i = 0; i < 2; ++i) {
709  CHECK_DIF_OK(dif_sensor_ctrl_alert_force(&sensor_ctrl_aon, kDifSensorCtrlAlertRecovAlert + i));
710 
711  // Verify that alert handler received it.
712  exp_alert = kTopEarlgreyAlertIdSensorCtrlAonRecovAlert + i;
713  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
714  &alert_handler, exp_alert, &is_cause));
715  CHECK(is_cause, "Expect alert %d!", exp_alert);
716 
717  // Clear alert cause register
718  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
719  &alert_handler, exp_alert));
720  }
721 
722  // Write spi_device's alert_test reg and check alert_cause.
723  for (dif_spi_device_alert_t i = 0; i < 1; ++i) {
724  CHECK_DIF_OK(dif_spi_device_alert_force(&spi_device, kDifSpiDeviceAlertFatalFault + i));
725 
726  // Verify that alert handler received it.
727  exp_alert = kTopEarlgreyAlertIdSpiDeviceFatalFault + i;
728  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
729  &alert_handler, exp_alert, &is_cause));
730  CHECK(is_cause, "Expect alert %d!", exp_alert);
731 
732  // Clear alert cause register
733  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
734  &alert_handler, exp_alert));
735  }
736 
737  // Write spi_host's alert_test reg and check alert_cause.
738  for (dif_spi_host_alert_t i = 0; i < 1; ++i) {
739  CHECK_DIF_OK(dif_spi_host_alert_force(&spi_host0, kDifSpiHostAlertFatalFault + i));
740 
741  // Verify that alert handler received it.
742  exp_alert = kTopEarlgreyAlertIdSpiHost0FatalFault + i;
743  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
744  &alert_handler, exp_alert, &is_cause));
745  CHECK(is_cause, "Expect alert %d!", exp_alert);
746 
747  // Clear alert cause register
748  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
749  &alert_handler, exp_alert));
750  }
751 
752  // Write spi_host's alert_test reg and check alert_cause.
753  for (dif_spi_host_alert_t i = 0; i < 1; ++i) {
754  CHECK_DIF_OK(dif_spi_host_alert_force(&spi_host1, kDifSpiHostAlertFatalFault + i));
755 
756  // Verify that alert handler received it.
757  exp_alert = kTopEarlgreyAlertIdSpiHost1FatalFault + i;
758  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
759  &alert_handler, exp_alert, &is_cause));
760  CHECK(is_cause, "Expect alert %d!", exp_alert);
761 
762  // Clear alert cause register
763  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
764  &alert_handler, exp_alert));
765  }
766 
767  // Write sram_ctrl's alert_test reg and check alert_cause.
768  for (dif_sram_ctrl_alert_t i = 0; i < 1; ++i) {
769  CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_main, kDifSramCtrlAlertFatalError + i));
770 
771  // Verify that alert handler received it.
772  exp_alert = kTopEarlgreyAlertIdSramCtrlMainFatalError + i;
773  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
774  &alert_handler, exp_alert, &is_cause));
775  CHECK(is_cause, "Expect alert %d!", exp_alert);
776 
777  // Clear alert cause register
778  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
779  &alert_handler, exp_alert));
780  }
781 
782  // Write sram_ctrl's alert_test reg and check alert_cause.
783  for (dif_sram_ctrl_alert_t i = 0; i < 1; ++i) {
784  CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_ret_aon, kDifSramCtrlAlertFatalError + i));
785 
786  // Verify that alert handler received it.
787  exp_alert = kTopEarlgreyAlertIdSramCtrlRetAonFatalError + i;
788  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
789  &alert_handler, exp_alert, &is_cause));
790  CHECK(is_cause, "Expect alert %d!", exp_alert);
791 
792  // Clear alert cause register
793  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
794  &alert_handler, exp_alert));
795  }
796 
797  // Write sysrst_ctrl's alert_test reg and check alert_cause.
798  for (dif_sysrst_ctrl_alert_t i = 0; i < 1; ++i) {
799  CHECK_DIF_OK(dif_sysrst_ctrl_alert_force(&sysrst_ctrl_aon, kDifSysrstCtrlAlertFatalFault + i));
800 
801  // Verify that alert handler received it.
802  exp_alert = kTopEarlgreyAlertIdSysrstCtrlAonFatalFault + i;
803  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
804  &alert_handler, exp_alert, &is_cause));
805  CHECK(is_cause, "Expect alert %d!", exp_alert);
806 
807  // Clear alert cause register
808  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
809  &alert_handler, exp_alert));
810  }
811 
812  // Write uart's alert_test reg and check alert_cause.
813  for (dif_uart_alert_t i = 0; i < 1; ++i) {
814  CHECK_DIF_OK(dif_uart_alert_force(&uart0, kDifUartAlertFatalFault + i));
815 
816  // Verify that alert handler received it.
817  exp_alert = kTopEarlgreyAlertIdUart0FatalFault + i;
818  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
819  &alert_handler, exp_alert, &is_cause));
820  CHECK(is_cause, "Expect alert %d!", exp_alert);
821 
822  // Clear alert cause register
823  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
824  &alert_handler, exp_alert));
825  }
826 
827  // Write uart's alert_test reg and check alert_cause.
828  for (dif_uart_alert_t i = 0; i < 1; ++i) {
829  CHECK_DIF_OK(dif_uart_alert_force(&uart1, kDifUartAlertFatalFault + i));
830 
831  // Verify that alert handler received it.
832  exp_alert = kTopEarlgreyAlertIdUart1FatalFault + i;
833  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
834  &alert_handler, exp_alert, &is_cause));
835  CHECK(is_cause, "Expect alert %d!", exp_alert);
836 
837  // Clear alert cause register
838  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
839  &alert_handler, exp_alert));
840  }
841 
842  // Write uart's alert_test reg and check alert_cause.
843  for (dif_uart_alert_t i = 0; i < 1; ++i) {
844  CHECK_DIF_OK(dif_uart_alert_force(&uart2, kDifUartAlertFatalFault + i));
845 
846  // Verify that alert handler received it.
847  exp_alert = kTopEarlgreyAlertIdUart2FatalFault + i;
848  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
849  &alert_handler, exp_alert, &is_cause));
850  CHECK(is_cause, "Expect alert %d!", exp_alert);
851 
852  // Clear alert cause register
853  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
854  &alert_handler, exp_alert));
855  }
856 
857  // Write uart's alert_test reg and check alert_cause.
858  for (dif_uart_alert_t i = 0; i < 1; ++i) {
859  CHECK_DIF_OK(dif_uart_alert_force(&uart3, kDifUartAlertFatalFault + i));
860 
861  // Verify that alert handler received it.
862  exp_alert = kTopEarlgreyAlertIdUart3FatalFault + i;
863  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
864  &alert_handler, exp_alert, &is_cause));
865  CHECK(is_cause, "Expect alert %d!", exp_alert);
866 
867  // Clear alert cause register
868  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
869  &alert_handler, exp_alert));
870  }
871 
872  // Write usbdev's alert_test reg and check alert_cause.
873  for (dif_usbdev_alert_t i = 0; i < 1; ++i) {
874  CHECK_DIF_OK(dif_usbdev_alert_force(&usbdev, kDifUsbdevAlertFatalFault + i));
875 
876  // Verify that alert handler received it.
877  exp_alert = kTopEarlgreyAlertIdUsbdevFatalFault + i;
878  CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
879  &alert_handler, exp_alert, &is_cause));
880  CHECK(is_cause, "Expect alert %d!", exp_alert);
881 
882  // Clear alert cause register
883  CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
884  &alert_handler, exp_alert));
885  }
886 }
887 
888 bool test_main(void) {
889  init_peripherals();
890  alert_handler_config();
891  trigger_alert_test();
892  return true;
893 }
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