14void isr_testutils_aon_timer_isr(
17 dif_aon_timer_irq_t *irq_serviced) {
22 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
26 top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id];
29 dif_aon_timer_irq_t irq =
30 (dif_aon_timer_irq_t)(plic_irq_id -
38 dif_aon_timer_irq_get_state(aon_timer_ctx.
aon_timer, &snapshot));
40 "Only aon_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
46 CHECK_DIF_OK(dif_aon_timer_irq_get_type(aon_timer_ctx.
aon_timer, irq, &type));
48 CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(aon_timer_ctx.
aon_timer, irq));
52 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
56void isr_testutils_flash_ctrl_isr(
60 dif_flash_ctrl_irq_t *irq_serviced) {
65 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
69 top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id];
72 dif_flash_ctrl_irq_t irq =
73 (dif_flash_ctrl_irq_t)(plic_irq_id -
81 dif_flash_ctrl_irq_get_state(flash_ctrl_ctx.
flash_ctrl, &snapshot));
83 "Only flash_ctrl IRQ %d expected to fire. Actual IRQ state = %x", irq,
90 dif_flash_ctrl_irq_get_type(flash_ctrl_ctx.
flash_ctrl, irq, &type));
93 dif_flash_ctrl_irq_acknowledge(flash_ctrl_ctx.
flash_ctrl, irq));
94 }
else if (mute_status_irq) {
95 CHECK_DIF_OK(dif_flash_ctrl_irq_set_enabled(flash_ctrl_ctx.
flash_ctrl, irq,
100 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
104void isr_testutils_gpio_isr(
107 dif_gpio_irq_t *irq_serviced) {
112 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
116 top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id];
126 CHECK_DIF_OK(dif_gpio_irq_get_state(gpio_ctx.
gpio, &snapshot));
128 "Only gpio IRQ %d expected to fire. Actual IRQ state = %x", irq,
134 CHECK_DIF_OK(dif_gpio_irq_get_type(gpio_ctx.
gpio, irq, &type));
136 CHECK_DIF_OK(dif_gpio_irq_acknowledge(gpio_ctx.
gpio, irq));
140 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
144void isr_testutils_pwrmgr_isr(
147 dif_pwrmgr_irq_t *irq_serviced) {
152 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
156 top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id];
159 dif_pwrmgr_irq_t irq =
166 CHECK_DIF_OK(dif_pwrmgr_irq_get_state(pwrmgr_ctx.
pwrmgr, &snapshot));
168 "Only pwrmgr IRQ %d expected to fire. Actual IRQ state = %x", irq,
174 CHECK_DIF_OK(dif_pwrmgr_irq_get_type(pwrmgr_ctx.
pwrmgr, irq, &type));
176 CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(pwrmgr_ctx.
pwrmgr, irq));
180 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
184void isr_testutils_rv_timer_isr(
187 dif_rv_timer_irq_t *irq_serviced) {
192 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
196 top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id];
199 dif_rv_timer_irq_t irq =
200 (dif_rv_timer_irq_t)(plic_irq_id -
207 CHECK_DIF_OK(dif_rv_timer_irq_get_state(rv_timer_ctx.
rv_timer,
210 "Only rv_timer IRQ %d expected to fire. Actual IRQ state = %x", irq,
216 CHECK_DIF_OK(dif_rv_timer_irq_get_type(rv_timer_ctx.
rv_timer, irq, &type));
218 CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(rv_timer_ctx.
rv_timer, irq));
222 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
226void isr_testutils_spi_device_isr(
228 bool mute_status_irq,
230 dif_spi_device_irq_t *irq_serviced) {
235 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
239 top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id];
242 dif_spi_device_irq_t irq =
243 (dif_spi_device_irq_t)(plic_irq_id -
251 dif_spi_device_irq_get_state(spi_device_ctx.
spi_device, &snapshot));
253 "Only spi_device IRQ %d expected to fire. Actual IRQ state = %x", irq,
260 dif_spi_device_irq_get_type(spi_device_ctx.
spi_device, irq, &type));
263 dif_spi_device_irq_acknowledge(spi_device_ctx.
spi_device, irq));
264 }
else if (mute_status_irq) {
265 CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device_ctx.
spi_device, irq,
270 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
274void isr_testutils_spi_host_isr(
276 bool mute_status_irq,
278 dif_spi_host_irq_t *irq_serviced) {
283 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
287 top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id];
290 dif_spi_host_irq_t irq =
291 (dif_spi_host_irq_t)(plic_irq_id -
298 CHECK_DIF_OK(dif_spi_host_irq_get_state(spi_host_ctx.
spi_host, &snapshot));
300 "Only spi_host IRQ %d expected to fire. Actual IRQ state = %x", irq,
306 CHECK_DIF_OK(dif_spi_host_irq_get_type(spi_host_ctx.
spi_host, irq, &type));
308 CHECK_DIF_OK(dif_spi_host_irq_acknowledge(spi_host_ctx.
spi_host, irq));
309 }
else if (mute_status_irq) {
310 CHECK_DIF_OK(dif_spi_host_irq_set_enabled(spi_host_ctx.
spi_host, irq,
315 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
319void isr_testutils_uart_isr(
322 dif_uart_irq_t *irq_serviced) {
327 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
331 top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id];
341 CHECK_DIF_OK(dif_uart_irq_get_state(uart_ctx.
uart, &snapshot));
343 "Only uart IRQ %d expected to fire. Actual IRQ state = %x", irq,
349 CHECK_DIF_OK(dif_uart_irq_get_type(uart_ctx.
uart, irq, &type));
351 CHECK_DIF_OK(dif_uart_irq_acknowledge(uart_ctx.
uart, irq));
352 }
else if (mute_status_irq) {
358 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,
362void isr_testutils_usbdev_isr(
365 dif_usbdev_irq_t *irq_serviced) {
370 dif_rv_plic_irq_claim(plic_ctx.
rv_plic, plic_ctx.
hart_id, &plic_irq_id));
374 top_englishbreakfast_plic_interrupt_for_peripheral[plic_irq_id];
377 dif_usbdev_irq_t irq =
384 CHECK_DIF_OK(dif_usbdev_irq_get_state(usbdev_ctx.
usbdev, &snapshot));
386 "Only usbdev IRQ %d expected to fire. Actual IRQ state = %x", irq,
392 CHECK_DIF_OK(dif_usbdev_irq_get_type(usbdev_ctx.
usbdev, irq, &type));
394 CHECK_DIF_OK(dif_usbdev_irq_acknowledge(usbdev_ctx.
usbdev, irq));
395 }
else if (mute_status_irq) {
401 CHECK_DIF_OK(dif_rv_plic_irq_complete(plic_ctx.
rv_plic, plic_ctx.
hart_id,