Generated register defines for rstmgr. More...

Macros
#define	RSTMGR_PARAM_RD_WIDTH 32

#define	RSTMGR_PARAM_IDX_WIDTH 4

#define	RSTMGR_PARAM_NUM_HW_RESETS 4

#define	RSTMGR_PARAM_NUM_SW_RESETS 3

#define	RSTMGR_PARAM_NUM_TOTAL_RESETS 7

#define	RSTMGR_PARAM_NUM_ALERTS 2

#define	RSTMGR_PARAM_REG_WIDTH 32

#define	RSTMGR_ALERT_TEST_REG_OFFSET 0x0

#define	RSTMGR_ALERT_TEST_REG_RESVAL 0x0u

#define	RSTMGR_ALERT_TEST_FATAL_FAULT_BIT 0

#define	RSTMGR_ALERT_TEST_FATAL_CNSTY_FAULT_BIT 1

#define	RSTMGR_RESET_REQ_REG_OFFSET 0x4

#define	RSTMGR_RESET_REQ_REG_RESVAL 0x9u

#define	RSTMGR_RESET_REQ_VAL_MASK 0xfu

#define	RSTMGR_RESET_REQ_VAL_OFFSET 0

#define	RSTMGR_RESET_REQ_VAL_FIELD ((bitfield_field32_t) { .mask = RSTMGR_RESET_REQ_VAL_MASK, .index = RSTMGR_RESET_REQ_VAL_OFFSET })

#define	RSTMGR_RESET_INFO_REG_OFFSET 0x8

#define	RSTMGR_RESET_INFO_REG_RESVAL 0x1u

#define	RSTMGR_RESET_INFO_POR_BIT 0

#define	RSTMGR_RESET_INFO_LOW_POWER_EXIT_BIT 1

#define	RSTMGR_RESET_INFO_SW_RESET_BIT 2

#define	RSTMGR_RESET_INFO_HW_REQ_MASK 0xfu

#define	RSTMGR_RESET_INFO_HW_REQ_OFFSET 3

#define	RSTMGR_RESET_INFO_HW_REQ_FIELD ((bitfield_field32_t) { .mask = RSTMGR_RESET_INFO_HW_REQ_MASK, .index = RSTMGR_RESET_INFO_HW_REQ_OFFSET })

#define	RSTMGR_ALERT_REGWEN_REG_OFFSET 0xc

#define	RSTMGR_ALERT_REGWEN_REG_RESVAL 0x1u

#define	RSTMGR_ALERT_REGWEN_EN_BIT 0

#define	RSTMGR_ALERT_INFO_CTRL_REG_OFFSET 0x10

#define	RSTMGR_ALERT_INFO_CTRL_REG_RESVAL 0x0u

#define	RSTMGR_ALERT_INFO_CTRL_EN_BIT 0

#define	RSTMGR_ALERT_INFO_CTRL_INDEX_MASK 0xfu

#define	RSTMGR_ALERT_INFO_CTRL_INDEX_OFFSET 4

#define	RSTMGR_ALERT_INFO_CTRL_INDEX_FIELD ((bitfield_field32_t) { .mask = RSTMGR_ALERT_INFO_CTRL_INDEX_MASK, .index = RSTMGR_ALERT_INFO_CTRL_INDEX_OFFSET })

#define	RSTMGR_ALERT_INFO_ATTR_REG_OFFSET 0x14

#define	RSTMGR_ALERT_INFO_ATTR_REG_RESVAL 0x0u

#define	RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_MASK 0xfu

#define	RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_OFFSET 0

#define	RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_FIELD ((bitfield_field32_t) { .mask = RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_MASK, .index = RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_OFFSET })

#define	RSTMGR_ALERT_INFO_REG_OFFSET 0x18

#define	RSTMGR_ALERT_INFO_REG_RESVAL 0x0u

#define	RSTMGR_CPU_REGWEN_REG_OFFSET 0x1c

#define	RSTMGR_CPU_REGWEN_REG_RESVAL 0x1u

#define	RSTMGR_CPU_REGWEN_EN_BIT 0

#define	RSTMGR_CPU_INFO_CTRL_REG_OFFSET 0x20

#define	RSTMGR_CPU_INFO_CTRL_REG_RESVAL 0x0u

#define	RSTMGR_CPU_INFO_CTRL_EN_BIT 0

#define	RSTMGR_CPU_INFO_CTRL_INDEX_MASK 0xfu

#define	RSTMGR_CPU_INFO_CTRL_INDEX_OFFSET 4

#define	RSTMGR_CPU_INFO_CTRL_INDEX_FIELD ((bitfield_field32_t) { .mask = RSTMGR_CPU_INFO_CTRL_INDEX_MASK, .index = RSTMGR_CPU_INFO_CTRL_INDEX_OFFSET })

#define	RSTMGR_CPU_INFO_ATTR_REG_OFFSET 0x24

#define	RSTMGR_CPU_INFO_ATTR_REG_RESVAL 0x0u

#define	RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_MASK 0xfu

#define	RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_OFFSET 0

#define	RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_FIELD ((bitfield_field32_t) { .mask = RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_MASK, .index = RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_OFFSET })

#define	RSTMGR_CPU_INFO_REG_OFFSET 0x28

#define	RSTMGR_CPU_INFO_REG_RESVAL 0x0u

#define	RSTMGR_SW_RST_REGWEN_EN_FIELD_WIDTH 1

#define	RSTMGR_SW_RST_REGWEN_MULTIREG_COUNT 3

#define	RSTMGR_SW_RST_REGWEN_0_REG_OFFSET 0x2c

#define	RSTMGR_SW_RST_REGWEN_0_REG_RESVAL 0x1u

#define	RSTMGR_SW_RST_REGWEN_0_EN_0_BIT 0

#define	RSTMGR_SW_RST_REGWEN_1_REG_OFFSET 0x30

#define	RSTMGR_SW_RST_REGWEN_1_REG_RESVAL 0x1u

#define	RSTMGR_SW_RST_REGWEN_1_EN_1_BIT 0

#define	RSTMGR_SW_RST_REGWEN_2_REG_OFFSET 0x34

#define	RSTMGR_SW_RST_REGWEN_2_REG_RESVAL 0x1u

#define	RSTMGR_SW_RST_REGWEN_2_EN_2_BIT 0

#define	RSTMGR_SW_RST_CTRL_N_VAL_FIELD_WIDTH 1

#define	RSTMGR_SW_RST_CTRL_N_MULTIREG_COUNT 3

#define	RSTMGR_SW_RST_CTRL_N_0_REG_OFFSET 0x38

#define	RSTMGR_SW_RST_CTRL_N_0_REG_RESVAL 0x1u

#define	RSTMGR_SW_RST_CTRL_N_0_VAL_0_BIT 0

#define	RSTMGR_SW_RST_CTRL_N_1_REG_OFFSET 0x3c

#define	RSTMGR_SW_RST_CTRL_N_1_REG_RESVAL 0x1u

#define	RSTMGR_SW_RST_CTRL_N_1_VAL_1_BIT 0

#define	RSTMGR_SW_RST_CTRL_N_2_REG_OFFSET 0x40

#define	RSTMGR_SW_RST_CTRL_N_2_REG_RESVAL 0x1u

#define	RSTMGR_SW_RST_CTRL_N_2_VAL_2_BIT 0

#define	RSTMGR_ERR_CODE_REG_OFFSET 0x44

#define	RSTMGR_ERR_CODE_REG_RESVAL 0x0u

#define	RSTMGR_ERR_CODE_REG_INTG_ERR_BIT 0

#define	RSTMGR_ERR_CODE_RESET_CONSISTENCY_ERR_BIT 1

#define	RSTMGR_ERR_CODE_FSM_ERR_BIT 2

Detailed Description

Generated register defines for rstmgr.

Definition in file rstmgr_regs.h.

Macro Definition Documentation

◆ RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_FIELD

#define RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_FIELD ((bitfield_field32_t) { .mask = RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_MASK, .index = RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_OFFSET })

Definition at line 85 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_MASK

#define RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_MASK 0xfu

Definition at line 83 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_OFFSET

#define RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_OFFSET 0

Definition at line 84 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_ATTR_REG_OFFSET

#define RSTMGR_ALERT_INFO_ATTR_REG_OFFSET 0x14

Definition at line 81 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_ATTR_REG_RESVAL

#define RSTMGR_ALERT_INFO_ATTR_REG_RESVAL 0x0u

Definition at line 82 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_CTRL_EN_BIT

#define RSTMGR_ALERT_INFO_CTRL_EN_BIT 0

Definition at line 74 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_CTRL_INDEX_FIELD

#define RSTMGR_ALERT_INFO_CTRL_INDEX_FIELD ((bitfield_field32_t) { .mask = RSTMGR_ALERT_INFO_CTRL_INDEX_MASK, .index = RSTMGR_ALERT_INFO_CTRL_INDEX_OFFSET })

Definition at line 77 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_CTRL_INDEX_MASK

#define RSTMGR_ALERT_INFO_CTRL_INDEX_MASK 0xfu

Definition at line 75 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_CTRL_INDEX_OFFSET

#define RSTMGR_ALERT_INFO_CTRL_INDEX_OFFSET 4

Definition at line 76 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_CTRL_REG_OFFSET

#define RSTMGR_ALERT_INFO_CTRL_REG_OFFSET 0x10

Definition at line 72 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_CTRL_REG_RESVAL

#define RSTMGR_ALERT_INFO_CTRL_REG_RESVAL 0x0u

Definition at line 73 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_REG_OFFSET

#define RSTMGR_ALERT_INFO_REG_OFFSET 0x18

Definition at line 89 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_INFO_REG_RESVAL

#define RSTMGR_ALERT_INFO_REG_RESVAL 0x0u

Definition at line 90 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_REGWEN_EN_BIT

#define RSTMGR_ALERT_REGWEN_EN_BIT 0

Definition at line 69 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_REGWEN_REG_OFFSET

#define RSTMGR_ALERT_REGWEN_REG_OFFSET 0xc

Definition at line 67 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_REGWEN_REG_RESVAL

#define RSTMGR_ALERT_REGWEN_REG_RESVAL 0x1u

Definition at line 68 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_TEST_FATAL_CNSTY_FAULT_BIT

#define RSTMGR_ALERT_TEST_FATAL_CNSTY_FAULT_BIT 1

Definition at line 45 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_TEST_FATAL_FAULT_BIT

#define RSTMGR_ALERT_TEST_FATAL_FAULT_BIT 0

Definition at line 44 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_TEST_REG_OFFSET

#define RSTMGR_ALERT_TEST_REG_OFFSET 0x0

Definition at line 42 of file rstmgr_regs.h.

◆ RSTMGR_ALERT_TEST_REG_RESVAL

#define RSTMGR_ALERT_TEST_REG_RESVAL 0x0u

Definition at line 43 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_FIELD

#define RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_FIELD ((bitfield_field32_t) { .mask = RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_MASK, .index = RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_OFFSET })

Definition at line 111 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_MASK

#define RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_MASK 0xfu

Definition at line 109 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_OFFSET

#define RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_OFFSET 0

Definition at line 110 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_ATTR_REG_OFFSET

#define RSTMGR_CPU_INFO_ATTR_REG_OFFSET 0x24

Definition at line 107 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_ATTR_REG_RESVAL

#define RSTMGR_CPU_INFO_ATTR_REG_RESVAL 0x0u

Definition at line 108 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_CTRL_EN_BIT

#define RSTMGR_CPU_INFO_CTRL_EN_BIT 0

Definition at line 100 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_CTRL_INDEX_FIELD

#define RSTMGR_CPU_INFO_CTRL_INDEX_FIELD ((bitfield_field32_t) { .mask = RSTMGR_CPU_INFO_CTRL_INDEX_MASK, .index = RSTMGR_CPU_INFO_CTRL_INDEX_OFFSET })

Definition at line 103 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_CTRL_INDEX_MASK

#define RSTMGR_CPU_INFO_CTRL_INDEX_MASK 0xfu

Definition at line 101 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_CTRL_INDEX_OFFSET

#define RSTMGR_CPU_INFO_CTRL_INDEX_OFFSET 4

Definition at line 102 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_CTRL_REG_OFFSET

#define RSTMGR_CPU_INFO_CTRL_REG_OFFSET 0x20

Definition at line 98 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_CTRL_REG_RESVAL

#define RSTMGR_CPU_INFO_CTRL_REG_RESVAL 0x0u

Definition at line 99 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_REG_OFFSET

#define RSTMGR_CPU_INFO_REG_OFFSET 0x28

Definition at line 115 of file rstmgr_regs.h.

◆ RSTMGR_CPU_INFO_REG_RESVAL

#define RSTMGR_CPU_INFO_REG_RESVAL 0x0u

Definition at line 116 of file rstmgr_regs.h.

◆ RSTMGR_CPU_REGWEN_EN_BIT

#define RSTMGR_CPU_REGWEN_EN_BIT 0

Definition at line 95 of file rstmgr_regs.h.

◆ RSTMGR_CPU_REGWEN_REG_OFFSET

#define RSTMGR_CPU_REGWEN_REG_OFFSET 0x1c

Definition at line 93 of file rstmgr_regs.h.

◆ RSTMGR_CPU_REGWEN_REG_RESVAL

#define RSTMGR_CPU_REGWEN_REG_RESVAL 0x1u

Definition at line 94 of file rstmgr_regs.h.

◆ RSTMGR_ERR_CODE_FSM_ERR_BIT

#define RSTMGR_ERR_CODE_FSM_ERR_BIT 2

Definition at line 161 of file rstmgr_regs.h.

◆ RSTMGR_ERR_CODE_REG_INTG_ERR_BIT

#define RSTMGR_ERR_CODE_REG_INTG_ERR_BIT 0

Definition at line 159 of file rstmgr_regs.h.

◆ RSTMGR_ERR_CODE_REG_OFFSET

#define RSTMGR_ERR_CODE_REG_OFFSET 0x44

Definition at line 157 of file rstmgr_regs.h.

◆ RSTMGR_ERR_CODE_REG_RESVAL

#define RSTMGR_ERR_CODE_REG_RESVAL 0x0u

Definition at line 158 of file rstmgr_regs.h.

◆ RSTMGR_ERR_CODE_RESET_CONSISTENCY_ERR_BIT

#define RSTMGR_ERR_CODE_RESET_CONSISTENCY_ERR_BIT 1

Definition at line 160 of file rstmgr_regs.h.

◆ RSTMGR_PARAM_IDX_WIDTH

#define RSTMGR_PARAM_IDX_WIDTH 4

Definition at line 23 of file rstmgr_regs.h.

◆ RSTMGR_PARAM_NUM_ALERTS

#define RSTMGR_PARAM_NUM_ALERTS 2

Definition at line 36 of file rstmgr_regs.h.

◆ RSTMGR_PARAM_NUM_HW_RESETS

#define RSTMGR_PARAM_NUM_HW_RESETS 4

Definition at line 27 of file rstmgr_regs.h.

◆ RSTMGR_PARAM_NUM_SW_RESETS

#define RSTMGR_PARAM_NUM_SW_RESETS 3

Definition at line 30 of file rstmgr_regs.h.

◆ RSTMGR_PARAM_NUM_TOTAL_RESETS

#define RSTMGR_PARAM_NUM_TOTAL_RESETS 7

Definition at line 33 of file rstmgr_regs.h.

◆ RSTMGR_PARAM_RD_WIDTH

#define RSTMGR_PARAM_RD_WIDTH 32

Definition at line 20 of file rstmgr_regs.h.

◆ RSTMGR_PARAM_REG_WIDTH

#define RSTMGR_PARAM_REG_WIDTH 32

Definition at line 39 of file rstmgr_regs.h.

◆ RSTMGR_RESET_INFO_HW_REQ_FIELD

#define RSTMGR_RESET_INFO_HW_REQ_FIELD ((bitfield_field32_t) { .mask = RSTMGR_RESET_INFO_HW_REQ_MASK, .index = RSTMGR_RESET_INFO_HW_REQ_OFFSET })

Definition at line 63 of file rstmgr_regs.h.

◆ RSTMGR_RESET_INFO_HW_REQ_MASK

#define RSTMGR_RESET_INFO_HW_REQ_MASK 0xfu

Definition at line 61 of file rstmgr_regs.h.

◆ RSTMGR_RESET_INFO_HW_REQ_OFFSET

#define RSTMGR_RESET_INFO_HW_REQ_OFFSET 3

Definition at line 62 of file rstmgr_regs.h.

◆ RSTMGR_RESET_INFO_LOW_POWER_EXIT_BIT

#define RSTMGR_RESET_INFO_LOW_POWER_EXIT_BIT 1

Definition at line 59 of file rstmgr_regs.h.

◆ RSTMGR_RESET_INFO_POR_BIT

#define RSTMGR_RESET_INFO_POR_BIT 0

Definition at line 58 of file rstmgr_regs.h.

◆ RSTMGR_RESET_INFO_REG_OFFSET

#define RSTMGR_RESET_INFO_REG_OFFSET 0x8

Definition at line 56 of file rstmgr_regs.h.

◆ RSTMGR_RESET_INFO_REG_RESVAL

#define RSTMGR_RESET_INFO_REG_RESVAL 0x1u

Definition at line 57 of file rstmgr_regs.h.

◆ RSTMGR_RESET_INFO_SW_RESET_BIT

#define RSTMGR_RESET_INFO_SW_RESET_BIT 2

Definition at line 60 of file rstmgr_regs.h.

◆ RSTMGR_RESET_REQ_REG_OFFSET

#define RSTMGR_RESET_REQ_REG_OFFSET 0x4

Definition at line 48 of file rstmgr_regs.h.

◆ RSTMGR_RESET_REQ_REG_RESVAL

#define RSTMGR_RESET_REQ_REG_RESVAL 0x9u

Definition at line 49 of file rstmgr_regs.h.

◆ RSTMGR_RESET_REQ_VAL_FIELD

#define RSTMGR_RESET_REQ_VAL_FIELD ((bitfield_field32_t) { .mask = RSTMGR_RESET_REQ_VAL_MASK, .index = RSTMGR_RESET_REQ_VAL_OFFSET })

Definition at line 52 of file rstmgr_regs.h.

◆ RSTMGR_RESET_REQ_VAL_MASK

#define RSTMGR_RESET_REQ_VAL_MASK 0xfu

Definition at line 50 of file rstmgr_regs.h.

◆ RSTMGR_RESET_REQ_VAL_OFFSET

#define RSTMGR_RESET_REQ_VAL_OFFSET 0

Definition at line 51 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_0_REG_OFFSET

#define RSTMGR_SW_RST_CTRL_N_0_REG_OFFSET 0x38

Definition at line 142 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_0_REG_RESVAL

#define RSTMGR_SW_RST_CTRL_N_0_REG_RESVAL 0x1u

Definition at line 143 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_0_VAL_0_BIT

#define RSTMGR_SW_RST_CTRL_N_0_VAL_0_BIT 0

Definition at line 144 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_1_REG_OFFSET

#define RSTMGR_SW_RST_CTRL_N_1_REG_OFFSET 0x3c

Definition at line 147 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_1_REG_RESVAL

#define RSTMGR_SW_RST_CTRL_N_1_REG_RESVAL 0x1u

Definition at line 148 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_1_VAL_1_BIT

#define RSTMGR_SW_RST_CTRL_N_1_VAL_1_BIT 0

Definition at line 149 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_2_REG_OFFSET

#define RSTMGR_SW_RST_CTRL_N_2_REG_OFFSET 0x40

Definition at line 152 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_2_REG_RESVAL

#define RSTMGR_SW_RST_CTRL_N_2_REG_RESVAL 0x1u

Definition at line 153 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_2_VAL_2_BIT

#define RSTMGR_SW_RST_CTRL_N_2_VAL_2_BIT 0

Definition at line 154 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_MULTIREG_COUNT

#define RSTMGR_SW_RST_CTRL_N_MULTIREG_COUNT 3

Definition at line 139 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_CTRL_N_VAL_FIELD_WIDTH

#define RSTMGR_SW_RST_CTRL_N_VAL_FIELD_WIDTH 1

Definition at line 138 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_0_EN_0_BIT

#define RSTMGR_SW_RST_REGWEN_0_EN_0_BIT 0

Definition at line 125 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_0_REG_OFFSET

#define RSTMGR_SW_RST_REGWEN_0_REG_OFFSET 0x2c

Definition at line 123 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_0_REG_RESVAL

#define RSTMGR_SW_RST_REGWEN_0_REG_RESVAL 0x1u

Definition at line 124 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_1_EN_1_BIT

#define RSTMGR_SW_RST_REGWEN_1_EN_1_BIT 0

Definition at line 130 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_1_REG_OFFSET

#define RSTMGR_SW_RST_REGWEN_1_REG_OFFSET 0x30

Definition at line 128 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_1_REG_RESVAL

#define RSTMGR_SW_RST_REGWEN_1_REG_RESVAL 0x1u

Definition at line 129 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_2_EN_2_BIT

#define RSTMGR_SW_RST_REGWEN_2_EN_2_BIT 0

Definition at line 135 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_2_REG_OFFSET

#define RSTMGR_SW_RST_REGWEN_2_REG_OFFSET 0x34

Definition at line 133 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_2_REG_RESVAL

#define RSTMGR_SW_RST_REGWEN_2_REG_RESVAL 0x1u

Definition at line 134 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_EN_FIELD_WIDTH

#define RSTMGR_SW_RST_REGWEN_EN_FIELD_WIDTH 1

Definition at line 119 of file rstmgr_regs.h.

◆ RSTMGR_SW_RST_REGWEN_MULTIREG_COUNT

#define RSTMGR_SW_RST_REGWEN_MULTIREG_COUNT 3

Definition at line 120 of file rstmgr_regs.h.

Macros