Software APIs
dt_sram_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_SRAM_CTRL_H_
8#define OPENTITAN_DT_SRAM_CTRL_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP sram_ctrl and top englishbreakfast.
13 *
14 * This file contains the type definitions and global functions of the sram_ctrl.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20
21
22/**
23 * List of instances.
24 */
25typedef enum dt_sram_ctrl {
26 kDtSramCtrlMain = 0, /**< sram_ctrl_main */
27 kDtSramCtrlFirst = 0, /**< \internal First instance */
28 kDtSramCtrlCount = 1, /**< \internal Number of instances */
30
31/**
32 * List of register blocks.
33 *
34 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
35 */
37 kDtSramCtrlRegBlockRegs = 0, /**< */
38 kDtSramCtrlRegBlockRam = 1, /**< */
39 kDtSramCtrlRegBlockCount = 2, /**< \internal Number of register blocks */
41
42/** Primary register block (associated with the "primary" set of registers that control the IP). */
43static const dt_sram_ctrl_reg_block_t kDtSramCtrlRegBlockPrimary = kDtSramCtrlRegBlockRegs;
44
45/**
46 * List of clock ports.
47 *
48 * Clock ports are guaranteed to be numbered consecutively from 0.
49 */
50typedef enum dt_sram_ctrl_clock {
51 kDtSramCtrlClockClk = 0, /**< Clock port clk_i */
52 kDtSramCtrlClockOtp = 1, /**< Clock port clk_otp_i */
53 kDtSramCtrlClockCount = 2, /**< \internal Number of clock ports */
55
56/**
57 * List of reset ports.
58 *
59 * Reset ports are guaranteed to be numbered consecutively from 0.
60 */
61typedef enum dt_sram_ctrl_reset {
62 kDtSramCtrlResetRst = 0, /**< Reset port rst_ni */
63 kDtSramCtrlResetOtp = 1, /**< Reset port rst_otp_ni */
64 kDtSramCtrlResetCount = 2, /**< \internal Number of reset ports */
66
67/**
68 * List of supported hardware features.
69 */
70#define OPENTITAN_SRAM_CTRL_HAS_INTEGRITY 1
71#define OPENTITAN_SRAM_CTRL_HAS_SCRAMBLED 1
72#define OPENTITAN_SRAM_CTRL_HAS_LOCK_ON_ERROR 1
73#define OPENTITAN_SRAM_CTRL_HAS_MEMSET 1
74#define OPENTITAN_SRAM_CTRL_HAS_FETCH_ALLOW 1
75#define OPENTITAN_SRAM_CTRL_HAS_SUBWORD_ACCESS 1
76#define OPENTITAN_SRAM_CTRL_HAS_REGWEN 1
77
78
79
80/**
81 * Get the sram_ctrl instance from an instance ID
82 *
83 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
84 *
85 * @param inst_id Instance ID.
86 * @return A sram_ctrl instance.
87 *
88 * **Note:** This function only makes sense if the instance ID has device type sram_ctrl,
89 * otherwise the returned value is unspecified.
90 */
92
93/**
94 * Get the instance ID of an instance.
95 *
96 * @param dt Instance of sram_ctrl.
97 * @return The instance ID of that instance.
98 */
100
101/**
102 * Get the register base address of an instance.
103 *
104 * @param dt Instance of sram_ctrl.
105 * @param reg_block The register block requested.
106 * @return The register base address of the requested block.
107 */
110 dt_sram_ctrl_reg_block_t reg_block);
111
112/**
113 * Get the primary register base address of an instance.
114 *
115 * This is just a convenience function, equivalent to
116 * `dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs)`
117 *
118 * @param dt Instance of sram_ctrl.
119 * @return The register base address of the primary register block.
120 */
121static inline uint32_t dt_sram_ctrl_primary_reg_block(
122 dt_sram_ctrl_t dt) {
123 return dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs);
124}
125
126
127
128
129/**
130 * Get the clock signal connected to a clock port of an instance.
131 *
132 * @param dt Instance of sram_ctrl.
133 * @param clk Clock port.
134 * @return Clock signal.
135 */
139
140/**
141 * Get the reset signal connected to a reset port of an instance.
142 *
143 * @param dt Instance of sram_ctrl.
144 * @param rst Reset port.
145 * @return Reset signal.
146 */
150
151
152
153#endif // OPENTITAN_DT_SRAM_CTRL_H_