dt_sram_ctrl.h

Go to the documentation of this file.

// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_SRAM_CTRL_H_
#define OPENTITAN_DT_SRAM_CTRL_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP sram_ctrl and top englishbreakfast.
 *
 * This file contains the type definitions and global functions of the sram_ctrl.
 */
 
#include "hw/top/dt/dt_api.h"
#include <stdint.h>
 
 
 
/**
 * List of instances.
 */
typedef enum dt_sram_ctrl {
  kDtSramCtrlMain = 0, /**< sram_ctrl_main */
  kDtSramCtrlFirst = 0, /**< \internal First instance */
  kDtSramCtrlCount = 1, /**< \internal Number of instances */
} dt_sram_ctrl_t;
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_sram_ctrl_reg_block {
  kDtSramCtrlRegBlockRegs = 0, /**<  */
  kDtSramCtrlRegBlockCount = 1, /**< \internal Number of register blocks */
} dt_sram_ctrl_reg_block_t;
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_sram_ctrl_reg_block_t kDtSramCtrlRegBlockPrimary = kDtSramCtrlRegBlockRegs;
 
/**
 * List of memories.
 *
 * Memories are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_sram_ctrl_memory {
  kDtSramCtrlMemoryRam = 0, /**<  */
  kDtSramCtrlMemoryCount = 1, /**< \internal Number of memories */
} dt_sram_ctrl_memory_t;
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_sram_ctrl_clock {
  kDtSramCtrlClockClk = 0, /**< Clock port clk_i */
  kDtSramCtrlClockOtp = 1, /**< Clock port clk_otp_i */
  kDtSramCtrlClockCount = 2, /**< \internal Number of clock ports */
} dt_sram_ctrl_clock_t;
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_sram_ctrl_reset {
  kDtSramCtrlResetRst = 0, /**< Reset port rst_ni */
  kDtSramCtrlResetOtp = 1, /**< Reset port rst_otp_ni */
  kDtSramCtrlResetCount = 2, /**< \internal Number of reset ports */
} dt_sram_ctrl_reset_t;
 
/**
 * List of supported hardware features.
 */
#define OPENTITAN_SRAM_CTRL_HAS_INTEGRITY 1
#define OPENTITAN_SRAM_CTRL_HAS_SCRAMBLED 1
#define OPENTITAN_SRAM_CTRL_HAS_LOCK_ON_ERROR 1
#define OPENTITAN_SRAM_CTRL_HAS_MEMSET 1
#define OPENTITAN_SRAM_CTRL_HAS_FETCH_ALLOW 1
#define OPENTITAN_SRAM_CTRL_HAS_SUBWORD_ACCESS 1
#define OPENTITAN_SRAM_CTRL_HAS_REGWEN 1
 
 
 
/**
 * Get the sram_ctrl instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A sram_ctrl instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type sram_ctrl,
 * otherwise the returned value is unspecified.
 */
dt_sram_ctrl_t dt_sram_ctrl_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of sram_ctrl.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_sram_ctrl_instance_id(dt_sram_ctrl_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of sram_ctrl.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_sram_ctrl_reg_block(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs)`
 *
 * @param dt Instance of sram_ctrl.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_sram_ctrl_primary_reg_block(
    dt_sram_ctrl_t dt) {
  return dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs);
}
 
/**
 * Get the base address of a memory.
 *
 * @param dt Instance of sram_ctrl.
 * @param mem The memory requested.
 * @return The base address of the requested memory.
 */
uint32_t dt_sram_ctrl_memory_base(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_memory_t mem);
 
/**
 * Get the size of a memory.
 *
 * @param dt Instance of sram_ctrl.
 * @param mem The memory requested.
 * @return The size of the requested memory.
 */
uint32_t dt_sram_ctrl_memory_size(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_memory_t mem);
 
 
 
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of sram_ctrl.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_sram_ctrl_clock(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of sram_ctrl.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_sram_ctrl_reset(
    dt_sram_ctrl_t dt,
    dt_sram_ctrl_reset_t rst);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_SRAM_CTRL_H_