Software APIs
dt_sram_ctrl.h
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// Copyright lowRISC contributors (OpenTitan project).
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Device table API auto-generated by `dtgen`
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#ifndef OPENTITAN_DT_SRAM_CTRL_H_
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#define OPENTITAN_DT_SRAM_CTRL_H_
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/**
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* @file
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* @brief Device Tables (DT) for IP sram_ctrl and top englishbreakfast.
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*
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* This file contains the type definitions and global functions of the sram_ctrl.
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*/
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#include "
dt_api.h
"
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#include <stdint.h>
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/**
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* List of instances.
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*/
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typedef
enum
dt_sram_ctrl
{
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kDtSramCtrlMain
= 0,
/**< sram_ctrl_main */
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kDtSramCtrlFirst = 0,
/**< \internal First instance */
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kDtSramCtrlCount = 1,
/**< \internal Number of instances */
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}
dt_sram_ctrl_t
;
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/**
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* List of register blocks.
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*
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* Register blocks are guaranteed to start at 0 and to be consecutively numbered.
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*/
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typedef
enum
dt_sram_ctrl_reg_block
{
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kDtSramCtrlRegBlockRegs = 0,
/**< */
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kDtSramCtrlRegBlockRam = 1,
/**< */
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kDtSramCtrlRegBlockCount = 2,
/**< \internal Number of register blocks */
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}
dt_sram_ctrl_reg_block_t
;
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/** Primary register block (associated with the "primary" set of registers that control the IP). */
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static
const
dt_sram_ctrl_reg_block_t
kDtSramCtrlRegBlockPrimary = kDtSramCtrlRegBlockRegs;
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/**
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* List of clock ports.
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*
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* Clock ports are guaranteed to be numbered consecutively from 0.
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*/
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typedef
enum
dt_sram_ctrl_clock
{
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kDtSramCtrlClockClk
= 0,
/**< Clock port clk_i */
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kDtSramCtrlClockOtp
= 1,
/**< Clock port clk_otp_i */
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kDtSramCtrlClockCount = 2,
/**< \internal Number of clock ports */
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}
dt_sram_ctrl_clock_t
;
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/**
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* List of reset ports.
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*
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* Reset ports are guaranteed to be numbered consecutively from 0.
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*/
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typedef
enum
dt_sram_ctrl_reset
{
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kDtSramCtrlResetRst
= 0,
/**< Reset port rst_ni */
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kDtSramCtrlResetOtp
= 1,
/**< Reset port rst_otp_ni */
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kDtSramCtrlResetCount = 2,
/**< \internal Number of reset ports */
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}
dt_sram_ctrl_reset_t
;
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/**
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* List of supported hardware features.
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*/
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#define OPENTITAN_SRAM_CTRL_HAS_INTEGRITY 1
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#define OPENTITAN_SRAM_CTRL_HAS_SCRAMBLED 1
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#define OPENTITAN_SRAM_CTRL_HAS_LOCK_ON_ERROR 1
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#define OPENTITAN_SRAM_CTRL_HAS_MEMSET 1
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#define OPENTITAN_SRAM_CTRL_HAS_FETCH_ALLOW 1
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#define OPENTITAN_SRAM_CTRL_HAS_SUBWORD_ACCESS 1
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#define OPENTITAN_SRAM_CTRL_HAS_REGWEN 1
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/**
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* Get the sram_ctrl instance from an instance ID
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*
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* For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
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*
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* @param inst_id Instance ID.
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* @return A sram_ctrl instance.
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*
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* **Note:** This function only makes sense if the instance ID has device type sram_ctrl,
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* otherwise the returned value is unspecified.
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*/
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dt_sram_ctrl_t
dt_sram_ctrl_from_instance_id
(
dt_instance_id_t
inst_id);
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/**
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* Get the instance ID of an instance.
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*
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* @param dt Instance of sram_ctrl.
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* @return The instance ID of that instance.
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*/
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dt_instance_id_t
dt_sram_ctrl_instance_id
(
dt_sram_ctrl_t
dt);
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/**
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* Get the register base address of an instance.
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*
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* @param dt Instance of sram_ctrl.
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* @param reg_block The register block requested.
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* @return The register base address of the requested block.
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*/
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uint32_t
dt_sram_ctrl_reg_block
(
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dt_sram_ctrl_t
dt,
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dt_sram_ctrl_reg_block_t
reg_block);
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/**
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* Get the primary register base address of an instance.
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*
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* This is just a convenience function, equivalent to
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* `dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs)`
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*
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* @param dt Instance of sram_ctrl.
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* @return The register base address of the primary register block.
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*/
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static
inline
uint32_t dt_sram_ctrl_primary_reg_block(
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dt_sram_ctrl_t
dt) {
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return
dt_sram_ctrl_reg_block
(dt, kDtSramCtrlRegBlockRegs);
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}
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/**
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* Get the clock signal connected to a clock port of an instance.
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*
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* @param dt Instance of sram_ctrl.
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* @param clk Clock port.
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* @return Clock signal.
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*/
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dt_clock_t
dt_sram_ctrl_clock
(
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dt_sram_ctrl_t
dt,
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dt_sram_ctrl_clock_t
clk);
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/**
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* Get the reset signal connected to a reset port of an instance.
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*
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* @param dt Instance of sram_ctrl.
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* @param rst Reset port.
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* @return Reset signal.
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*/
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dt_reset_t
dt_sram_ctrl_reset
(
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dt_sram_ctrl_t
dt,
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dt_sram_ctrl_reset_t
rst);
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#endif
// OPENTITAN_DT_SRAM_CTRL_H_
(englishbreakfast)
hw
top
dt
dt_sram_ctrl.h
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