Software APIs
dt_sram_ctrl.h
Go to the documentation of this file.
1
// Copyright lowRISC contributors (OpenTitan project).
2
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3
// SPDX-License-Identifier: Apache-2.0
4
//
5
// Device table API auto-generated by `dtgen`
6
7
#ifndef OPENTITAN_DT_SRAM_CTRL_H_
8
#define OPENTITAN_DT_SRAM_CTRL_H_
9
10
#ifdef __cplusplus
11
extern
"C"
{
12
#endif
// __cplusplus
13
14
/**
15
* @file
16
* @brief Device Tables (DT) for IP sram_ctrl and top englishbreakfast.
17
*
18
* This file contains the type definitions and global functions of the sram_ctrl.
19
*/
20
21
#include "
dt_api.h
"
22
#include <stdint.h>
23
24
25
26
/**
27
* List of instances.
28
*/
29
typedef
enum
dt_sram_ctrl
{
30
kDtSramCtrlMain
= 0,
/**< sram_ctrl_main */
31
kDtSramCtrlFirst = 0,
/**< \internal First instance */
32
kDtSramCtrlCount = 1,
/**< \internal Number of instances */
33
}
dt_sram_ctrl_t
;
34
35
/**
36
* List of register blocks.
37
*
38
* Register blocks are guaranteed to start at 0 and to be consecutively numbered.
39
*/
40
typedef
enum
dt_sram_ctrl_reg_block
{
41
kDtSramCtrlRegBlockRegs = 0,
/**< */
42
kDtSramCtrlRegBlockRam = 1,
/**< */
43
kDtSramCtrlRegBlockCount = 2,
/**< \internal Number of register blocks */
44
}
dt_sram_ctrl_reg_block_t
;
45
46
/** Primary register block (associated with the "primary" set of registers that control the IP). */
47
static
const
dt_sram_ctrl_reg_block_t
kDtSramCtrlRegBlockPrimary = kDtSramCtrlRegBlockRegs;
48
49
/**
50
* List of clock ports.
51
*
52
* Clock ports are guaranteed to be numbered consecutively from 0.
53
*/
54
typedef
enum
dt_sram_ctrl_clock
{
55
kDtSramCtrlClockClk
= 0,
/**< Clock port clk_i */
56
kDtSramCtrlClockOtp
= 1,
/**< Clock port clk_otp_i */
57
kDtSramCtrlClockCount = 2,
/**< \internal Number of clock ports */
58
}
dt_sram_ctrl_clock_t
;
59
60
/**
61
* List of reset ports.
62
*
63
* Reset ports are guaranteed to be numbered consecutively from 0.
64
*/
65
typedef
enum
dt_sram_ctrl_reset
{
66
kDtSramCtrlResetRst
= 0,
/**< Reset port rst_ni */
67
kDtSramCtrlResetOtp
= 1,
/**< Reset port rst_otp_ni */
68
kDtSramCtrlResetCount = 2,
/**< \internal Number of reset ports */
69
}
dt_sram_ctrl_reset_t
;
70
71
/**
72
* List of supported hardware features.
73
*/
74
#define OPENTITAN_SRAM_CTRL_HAS_INTEGRITY 1
75
#define OPENTITAN_SRAM_CTRL_HAS_SCRAMBLED 1
76
#define OPENTITAN_SRAM_CTRL_HAS_LOCK_ON_ERROR 1
77
#define OPENTITAN_SRAM_CTRL_HAS_MEMSET 1
78
#define OPENTITAN_SRAM_CTRL_HAS_FETCH_ALLOW 1
79
#define OPENTITAN_SRAM_CTRL_HAS_SUBWORD_ACCESS 1
80
#define OPENTITAN_SRAM_CTRL_HAS_REGWEN 1
81
82
83
84
/**
85
* Get the sram_ctrl instance from an instance ID
86
*
87
* For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
88
*
89
* @param inst_id Instance ID.
90
* @return A sram_ctrl instance.
91
*
92
* **Note:** This function only makes sense if the instance ID has device type sram_ctrl,
93
* otherwise the returned value is unspecified.
94
*/
95
dt_sram_ctrl_t
dt_sram_ctrl_from_instance_id
(
dt_instance_id_t
inst_id);
96
97
/**
98
* Get the instance ID of an instance.
99
*
100
* @param dt Instance of sram_ctrl.
101
* @return The instance ID of that instance.
102
*/
103
dt_instance_id_t
dt_sram_ctrl_instance_id
(
dt_sram_ctrl_t
dt);
104
105
/**
106
* Get the register base address of an instance.
107
*
108
* @param dt Instance of sram_ctrl.
109
* @param reg_block The register block requested.
110
* @return The register base address of the requested block.
111
*/
112
uint32_t
dt_sram_ctrl_reg_block
(
113
dt_sram_ctrl_t
dt,
114
dt_sram_ctrl_reg_block_t
reg_block);
115
116
/**
117
* Get the primary register base address of an instance.
118
*
119
* This is just a convenience function, equivalent to
120
* `dt_sram_ctrl_reg_block(dt, kDtSramCtrlRegBlockRegs)`
121
*
122
* @param dt Instance of sram_ctrl.
123
* @return The register base address of the primary register block.
124
*/
125
static
inline
uint32_t dt_sram_ctrl_primary_reg_block(
126
dt_sram_ctrl_t
dt) {
127
return
dt_sram_ctrl_reg_block
(dt, kDtSramCtrlRegBlockRegs);
128
}
129
130
131
132
133
/**
134
* Get the clock signal connected to a clock port of an instance.
135
*
136
* @param dt Instance of sram_ctrl.
137
* @param clk Clock port.
138
* @return Clock signal.
139
*/
140
dt_clock_t
dt_sram_ctrl_clock
(
141
dt_sram_ctrl_t
dt,
142
dt_sram_ctrl_clock_t
clk);
143
144
/**
145
* Get the reset signal connected to a reset port of an instance.
146
*
147
* @param dt Instance of sram_ctrl.
148
* @param rst Reset port.
149
* @return Reset signal.
150
*/
151
dt_reset_t
dt_sram_ctrl_reset
(
152
dt_sram_ctrl_t
dt,
153
dt_sram_ctrl_reset_t
rst);
154
155
156
157
#ifdef __cplusplus
158
}
// extern "C"
159
#endif
// __cplusplus
160
161
#endif
// OPENTITAN_DT_SRAM_CTRL_H_
(englishbreakfast)
hw
top
dt
dt_sram_ctrl.h
Return to
OpenTitan Documentation