Software APIs
dt_pwrmgr.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP pwrmgr and top englishbreakfast.
10 */
11
12#include "dt/dt_pwrmgr.h"
13
14
15#include "dt_pinmux.h"
16#include "dt_aon_timer.h"
17
18
19
20/**
21 * Description of instances.
22 */
23typedef struct dt_desc_pwrmgr {
24 dt_instance_id_t inst_id; /**< Instance ID */
25 uint32_t base_addr[kDtPwrmgrRegBlockCount]; /**< Base address of each register block */
26 /**
27 * PLIC ID of the first IRQ of this instance
28 *
29 * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
30 */
32 dt_clock_t clock[kDtPwrmgrClockCount]; /**< Clock signal connected to each clock port */
33 dt_reset_t reset[kDtPwrmgrResetCount]; /**< Reset signal connected to each reset port */
34 struct {
35 dt_pwrmgr_wakeup_src_t wakeup_src[3]; /**< List of wakeup sources, in the order of the register fields */
36 dt_pwrmgr_reset_req_src_t rst_reqs[1]; /**< List of reset requests, in the order of the register fields */
37 } pwrmgr_ext; /**< Extension */
39
40
41
42
43static const dt_desc_pwrmgr_t pwrmgr_desc[kDtPwrmgrCount] = {
44 [kDtPwrmgrAon] = {
45 .inst_id = kDtInstanceIdPwrmgrAon,
46 .base_addr = {
47 [kDtPwrmgrRegBlockCore] = 0x40400000,
48 },
50 .clock = {
55 },
56 .reset = {
62 },
63 .pwrmgr_ext = {
64 .wakeup_src = {
65 [0] = {
66 .inst_id = kDtInstanceIdPinmuxAon,
68 },
69 [1] = {
70 .inst_id = kDtInstanceIdPinmuxAon,
72 },
73 [2] = {
74 .inst_id = kDtInstanceIdAonTimerAon,
76 },
77 },
78 .rst_reqs = {
79 [0] = {
80 .inst_id = kDtInstanceIdAonTimerAon,
81 .reset_req = kDtAonTimerResetReqAonTimer,
82 },
83 },
84 },
85 },
86};
87
88/**
89 * Return a pointer to the `dt_pwrmgr_desc_t` structure of the requested
90 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
91 * the function) with the provided default value.
92 */
93#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_pwrmgr_t)0 || (dt) >= kDtPwrmgrCount) return (default); &pwrmgr_desc[dt]; })
94
96 if (inst_id >= kDtInstanceIdPwrmgrAon && inst_id <= kDtInstanceIdPwrmgrAon) {
97 return (dt_pwrmgr_t)(inst_id - kDtInstanceIdPwrmgrAon);
98 }
99 return (dt_pwrmgr_t)0;
100}
101
106
108 dt_pwrmgr_t dt,
109 dt_pwrmgr_reg_block_t reg_block) {
110 // Return a recognizable address in case of wrong argument.
111 return TRY_GET_DT(dt, 0xdeadbeef)->base_addr[reg_block];
112}
113
115 dt_pwrmgr_t dt,
116 dt_pwrmgr_irq_t irq) {
117 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
118 if (first_irq == kDtPlicIrqIdNone) {
119 return kDtPlicIrqIdNone;
120 }
121 return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
122}
123
125 dt_pwrmgr_t dt,
126 dt_plic_irq_id_t irq) {
127 dt_pwrmgr_irq_t count = kDtPwrmgrIrqCount;
128 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
129 if (first_irq == kDtPlicIrqIdNone) {
130 return count;
131 }
132 if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
133 return count;
134 }
135 return (dt_pwrmgr_irq_t)(irq - first_irq);
136}
137
138
139
140
142 dt_pwrmgr_t dt,
143 dt_pwrmgr_clock_t clk) {
144 // Return the first clock in case of invalid argument.
145 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
146}
147
149 dt_pwrmgr_t dt,
150 dt_pwrmgr_reset_t rst) {
151 const dt_pwrmgr_reset_t count = kDtPwrmgrResetCount;
152 if (rst >= count) {
153 return kDtResetUnknown;
154 }
155 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
156}
157
158
159
161 return 3;
162}
163
165 dt_pwrmgr_wakeup_src_t invalid = {.inst_id = kDtInstanceIdUnknown, .wakeup = 0};
166 return TRY_GET_DT(dt, invalid)->pwrmgr_ext.wakeup_src[idx];
167}
168
170 return 1;
171}
172
174 dt_pwrmgr_reset_req_src_t invalid = {.inst_id = kDtInstanceIdUnknown, .reset_req = 0};
175 return TRY_GET_DT(dt, invalid)->pwrmgr_ext.rst_reqs[idx];
176}
177
178