sram_ctrl_regs.h

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/**
 * @file
 * @brief Generated register defines for sram_ctrl
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _SRAM_CTRL_REG_DEFS_
#define _SRAM_CTRL_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of alerts
#define SRAM_CTRL_PARAM_NUM_ALERTS 1
 
// Register width
#define SRAM_CTRL_PARAM_REG_WIDTH 32
 
// Alert Test Register
#define SRAM_CTRL_ALERT_TEST_REG_OFFSET 0x0
#define SRAM_CTRL_ALERT_TEST_REG_RESVAL 0x80000000u
#define SRAM_CTRL_ALERT_TEST_FATAL_ERROR_BIT 0
#define SRAM_CTRL_ALERT_TEST_REGWEN_BIT 31
 
// SRAM status register.
#define SRAM_CTRL_STATUS_REG_OFFSET 0x4
#define SRAM_CTRL_STATUS_REG_RESVAL 0x0u
#define SRAM_CTRL_STATUS_BUS_INTEG_ERROR_BIT 0
#define SRAM_CTRL_STATUS_INIT_ERROR_BIT 1
#define SRAM_CTRL_STATUS_ESCALATED_BIT 2
#define SRAM_CTRL_STATUS_SCR_KEY_VALID_BIT 3
#define SRAM_CTRL_STATUS_SCR_KEY_SEED_VALID_BIT 4
#define SRAM_CTRL_STATUS_INIT_DONE_BIT 5
#define SRAM_CTRL_STATUS_READBACK_ERROR_BIT 6
#define SRAM_CTRL_STATUS_SRAM_ALERT_BIT 7
 
// Lock register for execution enable register.
#define SRAM_CTRL_EXEC_REGWEN_REG_OFFSET 0x8
#define SRAM_CTRL_EXEC_REGWEN_REG_RESVAL 0x1u
#define SRAM_CTRL_EXEC_REGWEN_EXEC_REGWEN_BIT 0
 
// Sram execution enable.
#define SRAM_CTRL_EXEC_REG_OFFSET 0xc
#define SRAM_CTRL_EXEC_REG_RESVAL 0x9u
#define SRAM_CTRL_EXEC_EN_MASK 0xfu
#define SRAM_CTRL_EXEC_EN_OFFSET 0
#define SRAM_CTRL_EXEC_EN_FIELD \
  ((bitfield_field32_t) { .mask = SRAM_CTRL_EXEC_EN_MASK, .index = SRAM_CTRL_EXEC_EN_OFFSET })
 
// Lock register for control register.
#define SRAM_CTRL_CTRL_REGWEN_REG_OFFSET 0x10
#define SRAM_CTRL_CTRL_REGWEN_REG_RESVAL 0x1u
#define SRAM_CTRL_CTRL_REGWEN_CTRL_REGWEN_BIT 0
 
// SRAM ctrl register.
#define SRAM_CTRL_CTRL_REG_OFFSET 0x14
#define SRAM_CTRL_CTRL_REG_RESVAL 0x0u
#define SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT 0
#define SRAM_CTRL_CTRL_INIT_BIT 1
 
// Clearable SRAM key request status.
#define SRAM_CTRL_SCR_KEY_ROTATED_REG_OFFSET 0x18
#define SRAM_CTRL_SCR_KEY_ROTATED_REG_RESVAL 0x9u
#define SRAM_CTRL_SCR_KEY_ROTATED_SUCCESS_MASK 0xfu
#define SRAM_CTRL_SCR_KEY_ROTATED_SUCCESS_OFFSET 0
#define SRAM_CTRL_SCR_KEY_ROTATED_SUCCESS_FIELD \
  ((bitfield_field32_t) { .mask = SRAM_CTRL_SCR_KEY_ROTATED_SUCCESS_MASK, .index = SRAM_CTRL_SCR_KEY_ROTATED_SUCCESS_OFFSET })
 
// Lock register for readback enable register.
#define SRAM_CTRL_READBACK_REGWEN_REG_OFFSET 0x1c
#define SRAM_CTRL_READBACK_REGWEN_REG_RESVAL 0x1u
#define SRAM_CTRL_READBACK_REGWEN_READBACK_REGWEN_BIT 0
 
// readback enable.
#define SRAM_CTRL_READBACK_REG_OFFSET 0x20
#define SRAM_CTRL_READBACK_REG_RESVAL 0x9u
#define SRAM_CTRL_READBACK_EN_MASK 0xfu
#define SRAM_CTRL_READBACK_EN_OFFSET 0
#define SRAM_CTRL_READBACK_EN_FIELD \
  ((bitfield_field32_t) { .mask = SRAM_CTRL_READBACK_EN_MASK, .index = SRAM_CTRL_READBACK_EN_OFFSET })
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _SRAM_CTRL_REG_DEFS_
// End generated register defines for sram_ctrl