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Software APIs
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Software APIs
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Generated register defines for spi_host. More...
Go to the source code of this file.
Generated register defines for spi_host.
Definition in file spi_host_regs.h.
| #define SPI_HOST_ALERT_TEST_FATAL_FAULT_BIT 0 |
Definition at line 59 of file spi_host_regs.h.
| #define SPI_HOST_ALERT_TEST_REG_OFFSET 0xc |
Definition at line 57 of file spi_host_regs.h.
| #define SPI_HOST_ALERT_TEST_REG_RESVAL 0x0u |
Definition at line 58 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_CSAAT_BIT 0 |
Definition at line 133 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_DIRECTION_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_COMMAND_DIRECTION_MASK, .index = SPI_HOST_COMMAND_DIRECTION_OFFSET }) |
Definition at line 140 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_DIRECTION_MASK 0x3u |
Definition at line 138 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_DIRECTION_OFFSET 3 |
Definition at line 139 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_LEN_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_COMMAND_LEN_MASK, .index = SPI_HOST_COMMAND_LEN_OFFSET }) |
Definition at line 144 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_LEN_MASK 0xfffffu |
Definition at line 142 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_LEN_OFFSET 5 |
Definition at line 143 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_REG_OFFSET 0x20 |
Definition at line 131 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_REG_RESVAL 0x0u |
Definition at line 132 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_SPEED_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_COMMAND_SPEED_MASK, .index = SPI_HOST_COMMAND_SPEED_OFFSET }) |
Definition at line 136 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_SPEED_MASK 0x3u |
Definition at line 134 of file spi_host_regs.h.
| #define SPI_HOST_COMMAND_SPEED_OFFSET 1 |
Definition at line 135 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CLKDIV_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_CONFIGOPTS_CLKDIV_MASK, .index = SPI_HOST_CONFIGOPTS_CLKDIV_OFFSET }) |
Definition at line 108 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CLKDIV_MASK 0xffffu |
Definition at line 106 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CLKDIV_OFFSET 0 |
Definition at line 107 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CPHA_BIT 30 |
Definition at line 123 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CPOL_BIT 31 |
Definition at line 124 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CSNIDLE_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_CONFIGOPTS_CSNIDLE_MASK, .index = SPI_HOST_CONFIGOPTS_CSNIDLE_OFFSET }) |
Definition at line 112 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CSNIDLE_MASK 0xfu |
Definition at line 110 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CSNIDLE_OFFSET 16 |
Definition at line 111 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CSNLEAD_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_CONFIGOPTS_CSNLEAD_MASK, .index = SPI_HOST_CONFIGOPTS_CSNLEAD_OFFSET }) |
Definition at line 120 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CSNLEAD_MASK 0xfu |
Definition at line 118 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CSNLEAD_OFFSET 24 |
Definition at line 119 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CSNTRAIL_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_CONFIGOPTS_CSNTRAIL_MASK, .index = SPI_HOST_CONFIGOPTS_CSNTRAIL_OFFSET }) |
Definition at line 116 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CSNTRAIL_MASK 0xfu |
Definition at line 114 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_CSNTRAIL_OFFSET 20 |
Definition at line 115 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_FULLCYC_BIT 29 |
Definition at line 122 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_REG_OFFSET 0x18 |
Definition at line 104 of file spi_host_regs.h.
| #define SPI_HOST_CONFIGOPTS_REG_RESVAL 0x0u |
Definition at line 105 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_OUTPUT_EN_BIT 29 |
Definition at line 72 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_REG_OFFSET 0x10 |
Definition at line 62 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_REG_RESVAL 0x7fu |
Definition at line 63 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_RX_WATERMARK_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_CONTROL_RX_WATERMARK_MASK, .index = SPI_HOST_CONTROL_RX_WATERMARK_OFFSET }) |
Definition at line 66 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_RX_WATERMARK_MASK 0xffu |
Definition at line 64 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_RX_WATERMARK_OFFSET 0 |
Definition at line 65 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_SPIEN_BIT 31 |
Definition at line 74 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_SW_RST_BIT 30 |
Definition at line 73 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_TX_WATERMARK_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_CONTROL_TX_WATERMARK_MASK, .index = SPI_HOST_CONTROL_TX_WATERMARK_OFFSET }) |
Definition at line 70 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_TX_WATERMARK_MASK 0xffu |
Definition at line 68 of file spi_host_regs.h.
| #define SPI_HOST_CONTROL_TX_WATERMARK_OFFSET 8 |
Definition at line 69 of file spi_host_regs.h.
| #define SPI_HOST_CSID_REG_OFFSET 0x1c |
Definition at line 127 of file spi_host_regs.h.
| #define SPI_HOST_CSID_REG_RESVAL 0x0u |
Definition at line 128 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_ENABLE_CMDBUSY_BIT 0 |
Definition at line 158 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_ENABLE_CMDINVAL_BIT 3 |
Definition at line 161 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_ENABLE_CSIDINVAL_BIT 4 |
Definition at line 162 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_ENABLE_OVERFLOW_BIT 1 |
Definition at line 159 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_ENABLE_REG_OFFSET 0x2c |
Definition at line 156 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_ENABLE_REG_RESVAL 0x1fu |
Definition at line 157 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_ENABLE_UNDERFLOW_BIT 2 |
Definition at line 160 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_STATUS_ACCESSINVAL_BIT 5 |
Definition at line 172 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_STATUS_CMDBUSY_BIT 0 |
Definition at line 167 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_STATUS_CMDINVAL_BIT 3 |
Definition at line 170 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_STATUS_CSIDINVAL_BIT 4 |
Definition at line 171 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_STATUS_OVERFLOW_BIT 1 |
Definition at line 168 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_STATUS_REG_OFFSET 0x30 |
Definition at line 165 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_STATUS_REG_RESVAL 0x0u |
Definition at line 166 of file spi_host_regs.h.
| #define SPI_HOST_ERROR_STATUS_UNDERFLOW_BIT 2 |
Definition at line 169 of file spi_host_regs.h.
| #define SPI_HOST_EVENT_ENABLE_IDLE_BIT 5 |
Definition at line 182 of file spi_host_regs.h.
| #define SPI_HOST_EVENT_ENABLE_READY_BIT 4 |
Definition at line 181 of file spi_host_regs.h.
| #define SPI_HOST_EVENT_ENABLE_REG_OFFSET 0x34 |
Definition at line 175 of file spi_host_regs.h.
| #define SPI_HOST_EVENT_ENABLE_REG_RESVAL 0x0u |
Definition at line 176 of file spi_host_regs.h.
| #define SPI_HOST_EVENT_ENABLE_RXFULL_BIT 0 |
Definition at line 177 of file spi_host_regs.h.
| #define SPI_HOST_EVENT_ENABLE_RXWM_BIT 2 |
Definition at line 179 of file spi_host_regs.h.
| #define SPI_HOST_EVENT_ENABLE_TXEMPTY_BIT 1 |
Definition at line 178 of file spi_host_regs.h.
| #define SPI_HOST_EVENT_ENABLE_TXWM_BIT 3 |
Definition at line 180 of file spi_host_regs.h.
| #define SPI_HOST_INTR_COMMON_ERROR_BIT 0 |
Definition at line 35 of file spi_host_regs.h.
| #define SPI_HOST_INTR_COMMON_SPI_EVENT_BIT 1 |
Definition at line 36 of file spi_host_regs.h.
| #define SPI_HOST_INTR_ENABLE_ERROR_BIT 0 |
Definition at line 47 of file spi_host_regs.h.
| #define SPI_HOST_INTR_ENABLE_REG_OFFSET 0x4 |
Definition at line 45 of file spi_host_regs.h.
| #define SPI_HOST_INTR_ENABLE_REG_RESVAL 0x0u |
Definition at line 46 of file spi_host_regs.h.
| #define SPI_HOST_INTR_ENABLE_SPI_EVENT_BIT 1 |
Definition at line 48 of file spi_host_regs.h.
| #define SPI_HOST_INTR_STATE_ERROR_BIT 0 |
Definition at line 41 of file spi_host_regs.h.
| #define SPI_HOST_INTR_STATE_REG_OFFSET 0x0 |
Definition at line 39 of file spi_host_regs.h.
| #define SPI_HOST_INTR_STATE_REG_RESVAL 0x0u |
Definition at line 40 of file spi_host_regs.h.
| #define SPI_HOST_INTR_STATE_SPI_EVENT_BIT 1 |
Definition at line 42 of file spi_host_regs.h.
| #define SPI_HOST_INTR_TEST_ERROR_BIT 0 |
Definition at line 53 of file spi_host_regs.h.
| #define SPI_HOST_INTR_TEST_REG_OFFSET 0x8 |
Definition at line 51 of file spi_host_regs.h.
| #define SPI_HOST_INTR_TEST_REG_RESVAL 0x0u |
Definition at line 52 of file spi_host_regs.h.
| #define SPI_HOST_INTR_TEST_SPI_EVENT_BIT 1 |
Definition at line 54 of file spi_host_regs.h.
| #define SPI_HOST_PARAM_CMD_DEPTH 4 |
Definition at line 26 of file spi_host_regs.h.
| #define SPI_HOST_PARAM_NUM_ALERTS 1 |
Definition at line 29 of file spi_host_regs.h.
| #define SPI_HOST_PARAM_REG_WIDTH 32 |
Definition at line 32 of file spi_host_regs.h.
| #define SPI_HOST_PARAM_RX_DEPTH 64 |
Definition at line 23 of file spi_host_regs.h.
| #define SPI_HOST_PARAM_TX_DEPTH 72 |
Definition at line 20 of file spi_host_regs.h.
| #define SPI_HOST_RXDATA_REG_OFFSET 0x24 |
Definition at line 148 of file spi_host_regs.h.
| #define SPI_HOST_RXDATA_SIZE_BYTES 4 |
Definition at line 150 of file spi_host_regs.h.
| #define SPI_HOST_RXDATA_SIZE_WORDS 1 |
Definition at line 149 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_ACTIVE_BIT 30 |
Definition at line 100 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_BYTEORDER_BIT 22 |
Definition at line 92 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_CMDQD_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_STATUS_CMDQD_MASK, .index = SPI_HOST_STATUS_CMDQD_OFFSET }) |
Definition at line 89 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_CMDQD_MASK 0xfu |
Definition at line 87 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_CMDQD_OFFSET 16 |
Definition at line 88 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_READY_BIT 31 |
Definition at line 101 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_REG_OFFSET 0x14 |
Definition at line 77 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_REG_RESVAL 0x0u |
Definition at line 78 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_RXEMPTY_BIT 24 |
Definition at line 94 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_RXFULL_BIT 25 |
Definition at line 95 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_RXQD_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_STATUS_RXQD_MASK, .index = SPI_HOST_STATUS_RXQD_OFFSET }) |
Definition at line 85 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_RXQD_MASK 0xffu |
Definition at line 83 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_RXQD_OFFSET 8 |
Definition at line 84 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_RXSTALL_BIT 23 |
Definition at line 93 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_RXWM_BIT 20 |
Definition at line 91 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_TXEMPTY_BIT 28 |
Definition at line 98 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_TXFULL_BIT 29 |
Definition at line 99 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_TXQD_FIELD ((bitfield_field32_t) { .mask = SPI_HOST_STATUS_TXQD_MASK, .index = SPI_HOST_STATUS_TXQD_OFFSET }) |
Definition at line 81 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_TXQD_MASK 0xffu |
Definition at line 79 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_TXQD_OFFSET 0 |
Definition at line 80 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_TXSTALL_BIT 27 |
Definition at line 97 of file spi_host_regs.h.
| #define SPI_HOST_STATUS_TXWM_BIT 26 |
Definition at line 96 of file spi_host_regs.h.
| #define SPI_HOST_TXDATA_REG_OFFSET 0x28 |
Definition at line 152 of file spi_host_regs.h.
| #define SPI_HOST_TXDATA_SIZE_BYTES 4 |
Definition at line 154 of file spi_host_regs.h.
| #define SPI_HOST_TXDATA_SIZE_WORDS 1 |
Definition at line 153 of file spi_host_regs.h.